1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2021 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### How to use this driver #####
27 ==============================================================================
28 [..]
29 The I2C HAL driver can be used as follows:
30
31 (#) Declare a I2C_HandleTypeDef handle structure, for example:
32 I2C_HandleTypeDef hi2c;
33
34 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
35 (##) Enable the I2Cx interface clock
36 (##) I2C pins configuration
37 (+++) Enable the clock for the I2C GPIOs
38 (+++) Configure I2C pins as alternate function open-drain
39 (##) NVIC configuration if you need to use interrupt process
40 (+++) Configure the I2Cx interrupt priority
41 (+++) Enable the NVIC I2C IRQ Channel
42 (##) DMA Configuration if you need to use DMA process
43 (+++) Declare a DMA_HandleTypeDef handle structure for
44 the transmit or receive channel
45 (+++) Enable the DMAx interface clock using
46 (+++) Configure the DMA handle parameters
47 (+++) Configure the DMA Tx or Rx channel
48 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
49 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
50 the DMA Tx or Rx channel
51
52 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
53 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
54
55 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
56 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
57
58 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
59
60 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
61
62 *** Polling mode IO operation ***
63 =================================
64 [..]
65 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
66 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
67 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
68 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
69
70 *** Polling mode IO MEM operation ***
71 =====================================
72 [..]
73 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
74 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
75
76
77 *** Interrupt mode IO operation ***
78 ===================================
79 [..]
80 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
81 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
82 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
83 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
84 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
85 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
86 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
87 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
88 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
89 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
90 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
91 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
92 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
93 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
94 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
95 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
96 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
97 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
98 This action will inform Master to generate a Stop condition to discard the communication.
99
100
101 *** Interrupt mode or DMA mode IO sequential operation ***
102 ==========================================================
103 [..]
104 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
105 when a direction change during transfer
106 [..]
107 (+) A specific option field manage the different steps of a sequential transfer
108 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
109 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
110 no sequential mode
111 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
112 and data to transfer without a final stop condition
113 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
114 start condition, address and data to transfer without a final stop condition,
115 an then permit a call the same master sequential interface several times
116 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
117 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
118 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
119 and with new data to transfer if the direction change or manage only the new data to
120 transfer
121 if no direction change and without a final stop condition in both cases
122 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
123 and with new data to transfer if the direction change or manage only the new data to
124 transfer
125 if no direction change and with a final stop condition in both cases
126 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
127 after several call of the same master sequential interface several times
128 (link with option I2C_FIRST_AND_NEXT_FRAME).
129 Usage can, transfer several bytes one by one using
130 HAL_I2C_Master_Seq_Transmit_IT
131 or HAL_I2C_Master_Seq_Receive_IT
132 or HAL_I2C_Master_Seq_Transmit_DMA
133 or HAL_I2C_Master_Seq_Receive_DMA
134 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
135 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
136 Receive sequence permit to call the opposite interface Receive or Transmit
137 without stopping the communication and so generate a restart condition.
138 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
139 each call of the same master sequential
140 interface.
141 Usage can, transfer several bytes one by one with a restart with slave address between
142 each bytes using
143 HAL_I2C_Master_Seq_Transmit_IT
144 or HAL_I2C_Master_Seq_Receive_IT
145 or HAL_I2C_Master_Seq_Transmit_DMA
146 or HAL_I2C_Master_Seq_Receive_DMA
147 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
148 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
149 generation of STOP condition.
150
151 (+) Different sequential I2C interfaces are listed below:
152 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
153 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
154 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
155 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
156 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
157 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
158 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
159 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
160 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
161 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
162 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
163 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
164 HAL_I2C_DisableListen_IT()
165 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
166 add their own code to check the Address Match Code and the transmission direction request by master
167 (Write/Read).
168 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
169 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
170 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
171 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
172 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
173 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
174 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
175 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
176 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
177 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
178 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
179 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
180 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
181 This action will inform Master to generate a Stop condition to discard the communication.
182
183 *** Interrupt mode IO MEM operation ***
184 =======================================
185 [..]
186 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
187 HAL_I2C_Mem_Write_IT()
188 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
189 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
190 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
191 HAL_I2C_Mem_Read_IT()
192 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
193 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
194 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
195 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
196
197 *** DMA mode IO operation ***
198 ==============================
199 [..]
200 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
201 HAL_I2C_Master_Transmit_DMA()
202 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
203 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
204 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
205 HAL_I2C_Master_Receive_DMA()
206 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
207 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
208 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
209 HAL_I2C_Slave_Transmit_DMA()
210 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
211 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
212 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
213 HAL_I2C_Slave_Receive_DMA()
214 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
215 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
216 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
217 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
218 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
219 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
220 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
221 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
222 This action will inform Master to generate a Stop condition to discard the communication.
223
224 *** DMA mode IO MEM operation ***
225 =================================
226 [..]
227 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
228 HAL_I2C_Mem_Write_DMA()
229 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
230 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
231 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
232 HAL_I2C_Mem_Read_DMA()
233 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
234 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
235 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
236 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
237
238
239 *** I2C HAL driver macros list ***
240 ==================================
241 [..]
242 Below the list of most used macros in I2C HAL driver.
243
244 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
245 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
246 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
247 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
248 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
249 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
250 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
251
252 *** Callback registration ***
253 =============================================
254 [..]
255 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
256 allows the user to configure dynamically the driver callbacks.
257 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
258 to register an interrupt callback.
259 [..]
260 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
261 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
262 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
263 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
264 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
265 (+) ListenCpltCallback : callback for end of listen mode.
266 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
267 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
268 (+) ErrorCallback : callback for error detection.
269 (+) AbortCpltCallback : callback for abort completion process.
270 (+) MspInitCallback : callback for Msp Init.
271 (+) MspDeInitCallback : callback for Msp DeInit.
272 This function takes as parameters the HAL peripheral handle, the Callback ID
273 and a pointer to the user callback function.
274 [..]
275 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
276 [..]
277 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
278 weak function.
279 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
280 and the Callback ID.
281 This function allows to reset following callbacks:
282 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
283 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
284 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
285 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
286 (+) ListenCpltCallback : callback for end of listen mode.
287 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
288 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
289 (+) ErrorCallback : callback for error detection.
290 (+) AbortCpltCallback : callback for abort completion process.
291 (+) MspInitCallback : callback for Msp Init.
292 (+) MspDeInitCallback : callback for Msp DeInit.
293 [..]
294 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
295 [..]
296 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
297 all callbacks are set to the corresponding weak functions:
298 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
299 Exception done for MspInit and MspDeInit functions that are
300 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
301 these callbacks are null (not registered beforehand).
302 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
303 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
304 [..]
305 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
306 Exception done MspInit/MspDeInit functions that can be registered/unregistered
307 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
308 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
309 Then, the user first registers the MspInit/MspDeInit user callbacks
310 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
311 or HAL_I2C_Init() function.
312 [..]
313 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
314 not defined, the callback registration feature is not available and all callbacks
315 are set to the corresponding weak functions.
316
317 [..]
318 (@) You can refer to the I2C HAL driver header file for more useful macros
319
320 @endverbatim
321 */
322
323 /* Includes ------------------------------------------------------------------*/
324 #include "stm32u5xx_hal.h"
325
326 /** @addtogroup STM32U5xx_HAL_Driver
327 * @{
328 */
329
330 /** @defgroup I2C I2C
331 * @brief I2C HAL module driver
332 * @{
333 */
334
335 #ifdef HAL_I2C_MODULE_ENABLED
336
337 /* Private typedef -----------------------------------------------------------*/
338 /* Private define ------------------------------------------------------------*/
339
340 /** @defgroup I2C_Private_Define I2C Private Define
341 * @{
342 */
343 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
344 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
345 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
352 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
353
354 #define MAX_NBYTE_SIZE 255U
355 #define SLAVE_ADDR_SHIFT 7U
356 #define SLAVE_ADDR_MSK 0x06U
357
358 /* Private define for @ref PreviousState usage */
359 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
360 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
361 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
362 /*!< Mask State define, keep only RX and TX bits */
363 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
364 /*!< Default Value */
365 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
366 (uint32_t)HAL_I2C_MODE_MASTER))
367 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
368 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
369 (uint32_t)HAL_I2C_MODE_MASTER))
370 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
371 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
372 (uint32_t)HAL_I2C_MODE_SLAVE))
373 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
374 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
375 (uint32_t)HAL_I2C_MODE_SLAVE))
376 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
377 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
378 (uint32_t)HAL_I2C_MODE_MEM))
379 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
380 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
381 (uint32_t)HAL_I2C_MODE_MEM))
382 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
383
384
385 /* Private define to centralize the enable/disable of Interrupts */
386 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
387 @ref I2C_XFER_LISTEN_IT */
388 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
389 @ref I2C_XFER_LISTEN_IT */
390 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
391 and @ref I2C_XFER_RX_IT */
392
393 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
394 and NACK treatment */
395 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
396 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
397
398 /* Private define Sequential Transfer Options default/reset value */
399 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
400 /**
401 * @}
402 */
403
404 /* Private macros ------------------------------------------------------------*/
405 /** @addtogroup I2C_Private_Macro
406 * @{
407 */
408 #if defined(HAL_DMA_MODULE_ENABLED)
409 /* Macro to get remaining data to transfer on DMA side */
410 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__))
411 #endif /* HAL_DMA_MODULE_ENABLED */
412 /**
413 * @}
414 */
415
416 /* Private variables ---------------------------------------------------------*/
417 /* Private function prototypes -----------------------------------------------*/
418
419 /** @defgroup I2C_Private_Functions I2C Private Functions
420 * @{
421 */
422 #if defined(HAL_DMA_MODULE_ENABLED)
423 /* Private functions to handle DMA transfer */
424 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
425 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
426 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
427 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
428 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
429 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
430
431 #endif /* HAL_DMA_MODULE_ENABLED */
432
433 /* Private functions to handle IT transfer */
434 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
435 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
436 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
437 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
438 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
439 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
440 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
441
442 /* Private functions to handle IT transfer */
443 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
444 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
445 uint32_t Tickstart);
446 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
447 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
448 uint32_t Tickstart);
449
450 /* Private functions for I2C transfer IRQ handler */
451 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
452 uint32_t ITSources);
453 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
454 uint32_t ITSources);
455 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
456 uint32_t ITSources);
457 #if defined(HAL_DMA_MODULE_ENABLED)
458 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
459 uint32_t ITSources);
460 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
461 uint32_t ITSources);
462 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
463 uint32_t ITSources);
464 #endif /* HAL_DMA_MODULE_ENABLED */
465
466 /* Private functions to handle flags during polling transfer */
467 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
468 uint32_t Timeout, uint32_t Tickstart);
469 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
470 uint32_t Tickstart);
471 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
472 uint32_t Tickstart);
473 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
474 uint32_t Tickstart);
475 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
476 uint32_t Tickstart);
477
478 /* Private functions to centralize the enable/disable of Interrupts */
479 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
480 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
481
482 /* Private function to treat different error callback */
483 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
484
485 /* Private function to flush TXDR register */
486 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
487
488 /* Private function to handle start, restart or stop a transfer */
489 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
490 uint32_t Request);
491
492 /* Private function to Convert Specific options */
493 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
494 /**
495 * @}
496 */
497
498 /* Exported functions --------------------------------------------------------*/
499
500 /** @defgroup I2C_Exported_Functions I2C Exported Functions
501 * @{
502 */
503
504 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
505 * @brief Initialization and Configuration functions
506 *
507 @verbatim
508 ===============================================================================
509 ##### Initialization and de-initialization functions #####
510 ===============================================================================
511 [..] This subsection provides a set of functions allowing to initialize and
512 deinitialize the I2Cx peripheral:
513
514 (+) User must Implement HAL_I2C_MspInit() function in which he configures
515 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
516
517 (+) Call the function HAL_I2C_Init() to configure the selected device with
518 the selected configuration:
519 (++) Clock Timing
520 (++) Own Address 1
521 (++) Addressing mode (Master, Slave)
522 (++) Dual Addressing mode
523 (++) Own Address 2
524 (++) Own Address 2 Mask
525 (++) General call mode
526 (++) Nostretch mode
527
528 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
529 of the selected I2Cx peripheral.
530
531 @endverbatim
532 * @{
533 */
534
535 /**
536 * @brief Initializes the I2C according to the specified parameters
537 * in the I2C_InitTypeDef and initialize the associated handle.
538 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
539 * the configuration information for the specified I2C.
540 * @retval HAL status
541 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)542 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
543 {
544 /* Check the I2C handle allocation */
545 if (hi2c == NULL)
546 {
547 return HAL_ERROR;
548 }
549
550 /* Check the parameters */
551 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
552 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
553 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
554 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
555 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
556 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
557 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
558 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
559
560 if (hi2c->State == HAL_I2C_STATE_RESET)
561 {
562 /* Allocate lock resource and initialize it */
563 hi2c->Lock = HAL_UNLOCKED;
564
565 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
566 /* Init the I2C Callback settings */
567 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
568 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
569 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
570 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
571 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
572 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
573 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
574 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
575 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
576 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
577
578 if (hi2c->MspInitCallback == NULL)
579 {
580 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
581 }
582
583 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
584 hi2c->MspInitCallback(hi2c);
585 #else
586 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
587 HAL_I2C_MspInit(hi2c);
588 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
589 }
590
591 hi2c->State = HAL_I2C_STATE_BUSY;
592
593 /* Disable the selected I2C peripheral */
594 __HAL_I2C_DISABLE(hi2c);
595
596 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
597 /* Configure I2Cx: Frequency range */
598 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
599
600 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
601 /* Disable Own Address1 before set the Own Address1 configuration */
602 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
603
604 /* Configure I2Cx: Own Address1 and ack own address1 mode */
605 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
606 {
607 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
608 }
609 else /* I2C_ADDRESSINGMODE_10BIT */
610 {
611 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
612 }
613
614 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
615 /* Configure I2Cx: Addressing Master mode */
616 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
617 {
618 hi2c->Instance->CR2 = (I2C_CR2_ADD10);
619 }
620 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
621 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
622
623 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
624 /* Disable Own Address2 before set the Own Address2 configuration */
625 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
626
627 /* Configure I2Cx: Dual mode and Own Address2 */
628 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
629 (hi2c->Init.OwnAddress2Masks << 8));
630
631 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
632 /* Configure I2Cx: Generalcall and NoStretch mode */
633 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
634
635 /* Enable the selected I2C peripheral */
636 __HAL_I2C_ENABLE(hi2c);
637
638 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
639 hi2c->State = HAL_I2C_STATE_READY;
640 hi2c->PreviousState = I2C_STATE_NONE;
641 hi2c->Mode = HAL_I2C_MODE_NONE;
642
643 return HAL_OK;
644 }
645
646 /**
647 * @brief DeInitialize the I2C peripheral.
648 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
649 * the configuration information for the specified I2C.
650 * @retval HAL status
651 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)652 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
653 {
654 /* Check the I2C handle allocation */
655 if (hi2c == NULL)
656 {
657 return HAL_ERROR;
658 }
659
660 /* Check the parameters */
661 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
662
663 hi2c->State = HAL_I2C_STATE_BUSY;
664
665 /* Disable the I2C Peripheral Clock */
666 __HAL_I2C_DISABLE(hi2c);
667
668 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
669 if (hi2c->MspDeInitCallback == NULL)
670 {
671 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
672 }
673
674 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
675 hi2c->MspDeInitCallback(hi2c);
676 #else
677 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
678 HAL_I2C_MspDeInit(hi2c);
679 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
680
681 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
682 hi2c->State = HAL_I2C_STATE_RESET;
683 hi2c->PreviousState = I2C_STATE_NONE;
684 hi2c->Mode = HAL_I2C_MODE_NONE;
685
686 /* Release Lock */
687 __HAL_UNLOCK(hi2c);
688
689 return HAL_OK;
690 }
691
692 /**
693 * @brief Initialize the I2C MSP.
694 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
695 * the configuration information for the specified I2C.
696 * @retval None
697 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)698 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
699 {
700 /* Prevent unused argument(s) compilation warning */
701 UNUSED(hi2c);
702
703 /* NOTE : This function should not be modified, when the callback is needed,
704 the HAL_I2C_MspInit could be implemented in the user file
705 */
706 }
707
708 /**
709 * @brief DeInitialize the I2C MSP.
710 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
711 * the configuration information for the specified I2C.
712 * @retval None
713 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)714 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
715 {
716 /* Prevent unused argument(s) compilation warning */
717 UNUSED(hi2c);
718
719 /* NOTE : This function should not be modified, when the callback is needed,
720 the HAL_I2C_MspDeInit could be implemented in the user file
721 */
722 }
723
724 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
725 /**
726 * @brief Register a User I2C Callback
727 * To be used instead of the weak predefined callback
728 * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
729 * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
730 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
731 * the configuration information for the specified I2C.
732 * @param CallbackID ID of the callback to be registered
733 * This parameter can be one of the following values:
734 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
735 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
736 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
737 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
738 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
739 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
740 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
741 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
742 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
743 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
744 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
745 * @param pCallback pointer to the Callback function
746 * @retval HAL status
747 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)748 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
749 pI2C_CallbackTypeDef pCallback)
750 {
751 HAL_StatusTypeDef status = HAL_OK;
752
753 if (pCallback == NULL)
754 {
755 /* Update the error code */
756 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
757
758 return HAL_ERROR;
759 }
760
761 if (HAL_I2C_STATE_READY == hi2c->State)
762 {
763 switch (CallbackID)
764 {
765 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
766 hi2c->MasterTxCpltCallback = pCallback;
767 break;
768
769 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
770 hi2c->MasterRxCpltCallback = pCallback;
771 break;
772
773 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
774 hi2c->SlaveTxCpltCallback = pCallback;
775 break;
776
777 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
778 hi2c->SlaveRxCpltCallback = pCallback;
779 break;
780
781 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
782 hi2c->ListenCpltCallback = pCallback;
783 break;
784
785 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
786 hi2c->MemTxCpltCallback = pCallback;
787 break;
788
789 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
790 hi2c->MemRxCpltCallback = pCallback;
791 break;
792
793 case HAL_I2C_ERROR_CB_ID :
794 hi2c->ErrorCallback = pCallback;
795 break;
796
797 case HAL_I2C_ABORT_CB_ID :
798 hi2c->AbortCpltCallback = pCallback;
799 break;
800
801 case HAL_I2C_MSPINIT_CB_ID :
802 hi2c->MspInitCallback = pCallback;
803 break;
804
805 case HAL_I2C_MSPDEINIT_CB_ID :
806 hi2c->MspDeInitCallback = pCallback;
807 break;
808
809 default :
810 /* Update the error code */
811 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
812
813 /* Return error status */
814 status = HAL_ERROR;
815 break;
816 }
817 }
818 else if (HAL_I2C_STATE_RESET == hi2c->State)
819 {
820 switch (CallbackID)
821 {
822 case HAL_I2C_MSPINIT_CB_ID :
823 hi2c->MspInitCallback = pCallback;
824 break;
825
826 case HAL_I2C_MSPDEINIT_CB_ID :
827 hi2c->MspDeInitCallback = pCallback;
828 break;
829
830 default :
831 /* Update the error code */
832 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
833
834 /* Return error status */
835 status = HAL_ERROR;
836 break;
837 }
838 }
839 else
840 {
841 /* Update the error code */
842 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
843
844 /* Return error status */
845 status = HAL_ERROR;
846 }
847
848 return status;
849 }
850
851 /**
852 * @brief Unregister an I2C Callback
853 * I2C callback is redirected to the weak predefined callback
854 * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
855 * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
856 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
857 * the configuration information for the specified I2C.
858 * @param CallbackID ID of the callback to be unregistered
859 * This parameter can be one of the following values:
860 * This parameter can be one of the following values:
861 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
862 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
863 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
864 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
865 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
866 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
867 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
868 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
869 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
870 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
871 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
872 * @retval HAL status
873 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)874 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
875 {
876 HAL_StatusTypeDef status = HAL_OK;
877
878 if (HAL_I2C_STATE_READY == hi2c->State)
879 {
880 switch (CallbackID)
881 {
882 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
883 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
884 break;
885
886 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
887 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
888 break;
889
890 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
891 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
892 break;
893
894 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
895 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
896 break;
897
898 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
899 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
900 break;
901
902 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
903 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
904 break;
905
906 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
907 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
908 break;
909
910 case HAL_I2C_ERROR_CB_ID :
911 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
912 break;
913
914 case HAL_I2C_ABORT_CB_ID :
915 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
916 break;
917
918 case HAL_I2C_MSPINIT_CB_ID :
919 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
920 break;
921
922 case HAL_I2C_MSPDEINIT_CB_ID :
923 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
924 break;
925
926 default :
927 /* Update the error code */
928 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
929
930 /* Return error status */
931 status = HAL_ERROR;
932 break;
933 }
934 }
935 else if (HAL_I2C_STATE_RESET == hi2c->State)
936 {
937 switch (CallbackID)
938 {
939 case HAL_I2C_MSPINIT_CB_ID :
940 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
941 break;
942
943 case HAL_I2C_MSPDEINIT_CB_ID :
944 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
945 break;
946
947 default :
948 /* Update the error code */
949 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
950
951 /* Return error status */
952 status = HAL_ERROR;
953 break;
954 }
955 }
956 else
957 {
958 /* Update the error code */
959 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
960
961 /* Return error status */
962 status = HAL_ERROR;
963 }
964
965 return status;
966 }
967
968 /**
969 * @brief Register the Slave Address Match I2C Callback
970 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
971 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
972 * the configuration information for the specified I2C.
973 * @param pCallback pointer to the Address Match Callback function
974 * @retval HAL status
975 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)976 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
977 {
978 HAL_StatusTypeDef status = HAL_OK;
979
980 if (pCallback == NULL)
981 {
982 /* Update the error code */
983 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
984
985 return HAL_ERROR;
986 }
987
988 if (HAL_I2C_STATE_READY == hi2c->State)
989 {
990 hi2c->AddrCallback = pCallback;
991 }
992 else
993 {
994 /* Update the error code */
995 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
996
997 /* Return error status */
998 status = HAL_ERROR;
999 }
1000
1001 return status;
1002 }
1003
1004 /**
1005 * @brief UnRegister the Slave Address Match I2C Callback
1006 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
1007 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1008 * the configuration information for the specified I2C.
1009 * @retval HAL status
1010 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)1011 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
1012 {
1013 HAL_StatusTypeDef status = HAL_OK;
1014
1015 if (HAL_I2C_STATE_READY == hi2c->State)
1016 {
1017 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1018 }
1019 else
1020 {
1021 /* Update the error code */
1022 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1023
1024 /* Return error status */
1025 status = HAL_ERROR;
1026 }
1027
1028 return status;
1029 }
1030
1031 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1032
1033 /**
1034 * @}
1035 */
1036
1037 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1038 * @brief Data transfers functions
1039 *
1040 @verbatim
1041 ===============================================================================
1042 ##### IO operation functions #####
1043 ===============================================================================
1044 [..]
1045 This subsection provides a set of functions allowing to manage the I2C data
1046 transfers.
1047
1048 (#) There are two modes of transfer:
1049 (++) Blocking mode : The communication is performed in the polling mode.
1050 The status of all data processing is returned by the same function
1051 after finishing transfer.
1052 (++) No-Blocking mode : The communication is performed using Interrupts
1053 or DMA. These functions return the status of the transfer startup.
1054 The end of the data processing will be indicated through the
1055 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1056 using DMA mode.
1057
1058 (#) Blocking mode functions are :
1059 (++) HAL_I2C_Master_Transmit()
1060 (++) HAL_I2C_Master_Receive()
1061 (++) HAL_I2C_Slave_Transmit()
1062 (++) HAL_I2C_Slave_Receive()
1063 (++) HAL_I2C_Mem_Write()
1064 (++) HAL_I2C_Mem_Read()
1065 (++) HAL_I2C_IsDeviceReady()
1066
1067 (#) No-Blocking mode functions with Interrupt are :
1068 (++) HAL_I2C_Master_Transmit_IT()
1069 (++) HAL_I2C_Master_Receive_IT()
1070 (++) HAL_I2C_Slave_Transmit_IT()
1071 (++) HAL_I2C_Slave_Receive_IT()
1072 (++) HAL_I2C_Mem_Write_IT()
1073 (++) HAL_I2C_Mem_Read_IT()
1074 (++) HAL_I2C_Master_Seq_Transmit_IT()
1075 (++) HAL_I2C_Master_Seq_Receive_IT()
1076 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1077 (++) HAL_I2C_Slave_Seq_Receive_IT()
1078 (++) HAL_I2C_EnableListen_IT()
1079 (++) HAL_I2C_DisableListen_IT()
1080 (++) HAL_I2C_Master_Abort_IT()
1081
1082 (#) No-Blocking mode functions with DMA are :
1083 (++) HAL_I2C_Master_Transmit_DMA()
1084 (++) HAL_I2C_Master_Receive_DMA()
1085 (++) HAL_I2C_Slave_Transmit_DMA()
1086 (++) HAL_I2C_Slave_Receive_DMA()
1087 (++) HAL_I2C_Mem_Write_DMA()
1088 (++) HAL_I2C_Mem_Read_DMA()
1089 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1090 (++) HAL_I2C_Master_Seq_Receive_DMA()
1091 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1092 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1093
1094 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1095 (++) HAL_I2C_MasterTxCpltCallback()
1096 (++) HAL_I2C_MasterRxCpltCallback()
1097 (++) HAL_I2C_SlaveTxCpltCallback()
1098 (++) HAL_I2C_SlaveRxCpltCallback()
1099 (++) HAL_I2C_MemTxCpltCallback()
1100 (++) HAL_I2C_MemRxCpltCallback()
1101 (++) HAL_I2C_AddrCallback()
1102 (++) HAL_I2C_ListenCpltCallback()
1103 (++) HAL_I2C_ErrorCallback()
1104 (++) HAL_I2C_AbortCpltCallback()
1105
1106 @endverbatim
1107 * @{
1108 */
1109
1110 /**
1111 * @brief Transmits in master mode an amount of data in blocking mode.
1112 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1113 * the configuration information for the specified I2C.
1114 * @param DevAddress Target device address: The device 7 bits address value
1115 * in datasheet must be shifted to the left before calling the interface
1116 * @param pData Pointer to data buffer
1117 * @param Size Amount of data to be sent
1118 * @param Timeout Timeout duration
1119 * @retval HAL status
1120 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1121 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1122 uint16_t Size, uint32_t Timeout)
1123 {
1124 uint32_t tickstart;
1125
1126 if (hi2c->State == HAL_I2C_STATE_READY)
1127 {
1128 /* Process Locked */
1129 __HAL_LOCK(hi2c);
1130
1131 /* Init tickstart for timeout management*/
1132 tickstart = HAL_GetTick();
1133
1134 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1135 {
1136 return HAL_ERROR;
1137 }
1138
1139 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1140 hi2c->Mode = HAL_I2C_MODE_MASTER;
1141 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1142
1143 /* Prepare transfer parameters */
1144 hi2c->pBuffPtr = pData;
1145 hi2c->XferCount = Size;
1146 hi2c->XferISR = NULL;
1147
1148 /* Send Slave Address */
1149 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1150 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1151 {
1152 hi2c->XferSize = MAX_NBYTE_SIZE;
1153 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1154 I2C_GENERATE_START_WRITE);
1155 }
1156 else
1157 {
1158 hi2c->XferSize = hi2c->XferCount;
1159 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1160 I2C_GENERATE_START_WRITE);
1161 }
1162
1163 while (hi2c->XferCount > 0U)
1164 {
1165 /* Wait until TXIS flag is set */
1166 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1167 {
1168 return HAL_ERROR;
1169 }
1170 /* Write data to TXDR */
1171 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1172
1173 /* Increment Buffer pointer */
1174 hi2c->pBuffPtr++;
1175
1176 hi2c->XferCount--;
1177 hi2c->XferSize--;
1178
1179 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1180 {
1181 /* Wait until TCR flag is set */
1182 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1183 {
1184 return HAL_ERROR;
1185 }
1186
1187 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1188 {
1189 hi2c->XferSize = MAX_NBYTE_SIZE;
1190 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1191 I2C_NO_STARTSTOP);
1192 }
1193 else
1194 {
1195 hi2c->XferSize = hi2c->XferCount;
1196 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1197 I2C_NO_STARTSTOP);
1198 }
1199 }
1200 }
1201
1202 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1203 /* Wait until STOPF flag is set */
1204 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1205 {
1206 return HAL_ERROR;
1207 }
1208
1209 /* Clear STOP Flag */
1210 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1211
1212 /* Clear Configuration Register 2 */
1213 I2C_RESET_CR2(hi2c);
1214
1215 hi2c->State = HAL_I2C_STATE_READY;
1216 hi2c->Mode = HAL_I2C_MODE_NONE;
1217
1218 /* Process Unlocked */
1219 __HAL_UNLOCK(hi2c);
1220
1221 return HAL_OK;
1222 }
1223 else
1224 {
1225 return HAL_BUSY;
1226 }
1227 }
1228
1229 /**
1230 * @brief Receives in master mode an amount of data in blocking mode.
1231 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1232 * the configuration information for the specified I2C.
1233 * @param DevAddress Target device address: The device 7 bits address value
1234 * in datasheet must be shifted to the left before calling the interface
1235 * @param pData Pointer to data buffer
1236 * @param Size Amount of data to be sent
1237 * @param Timeout Timeout duration
1238 * @retval HAL status
1239 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1240 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1241 uint16_t Size, uint32_t Timeout)
1242 {
1243 uint32_t tickstart;
1244
1245 if (hi2c->State == HAL_I2C_STATE_READY)
1246 {
1247 /* Process Locked */
1248 __HAL_LOCK(hi2c);
1249
1250 /* Init tickstart for timeout management*/
1251 tickstart = HAL_GetTick();
1252
1253 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1254 {
1255 return HAL_ERROR;
1256 }
1257
1258 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1259 hi2c->Mode = HAL_I2C_MODE_MASTER;
1260 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1261
1262 /* Prepare transfer parameters */
1263 hi2c->pBuffPtr = pData;
1264 hi2c->XferCount = Size;
1265 hi2c->XferISR = NULL;
1266
1267 /* Send Slave Address */
1268 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1269 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1270 {
1271 hi2c->XferSize = MAX_NBYTE_SIZE;
1272 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1273 I2C_GENERATE_START_READ);
1274 }
1275 else
1276 {
1277 hi2c->XferSize = hi2c->XferCount;
1278 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1279 I2C_GENERATE_START_READ);
1280 }
1281
1282 while (hi2c->XferCount > 0U)
1283 {
1284 /* Wait until RXNE flag is set */
1285 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1286 {
1287 return HAL_ERROR;
1288 }
1289
1290 /* Read data from RXDR */
1291 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1292
1293 /* Increment Buffer pointer */
1294 hi2c->pBuffPtr++;
1295
1296 hi2c->XferSize--;
1297 hi2c->XferCount--;
1298
1299 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1300 {
1301 /* Wait until TCR flag is set */
1302 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1303 {
1304 return HAL_ERROR;
1305 }
1306
1307 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1308 {
1309 hi2c->XferSize = MAX_NBYTE_SIZE;
1310 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1311 I2C_NO_STARTSTOP);
1312 }
1313 else
1314 {
1315 hi2c->XferSize = hi2c->XferCount;
1316 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1317 I2C_NO_STARTSTOP);
1318 }
1319 }
1320 }
1321
1322 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1323 /* Wait until STOPF flag is set */
1324 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1325 {
1326 return HAL_ERROR;
1327 }
1328
1329 /* Clear STOP Flag */
1330 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1331
1332 /* Clear Configuration Register 2 */
1333 I2C_RESET_CR2(hi2c);
1334
1335 hi2c->State = HAL_I2C_STATE_READY;
1336 hi2c->Mode = HAL_I2C_MODE_NONE;
1337
1338 /* Process Unlocked */
1339 __HAL_UNLOCK(hi2c);
1340
1341 return HAL_OK;
1342 }
1343 else
1344 {
1345 return HAL_BUSY;
1346 }
1347 }
1348
1349 /**
1350 * @brief Transmits in slave mode an amount of data in blocking mode.
1351 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1352 * the configuration information for the specified I2C.
1353 * @param pData Pointer to data buffer
1354 * @param Size Amount of data to be sent
1355 * @param Timeout Timeout duration
1356 * @retval HAL status
1357 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1358 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1359 uint32_t Timeout)
1360 {
1361 uint32_t tickstart;
1362
1363 if (hi2c->State == HAL_I2C_STATE_READY)
1364 {
1365 if ((pData == NULL) || (Size == 0U))
1366 {
1367 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1368 return HAL_ERROR;
1369 }
1370 /* Process Locked */
1371 __HAL_LOCK(hi2c);
1372
1373 /* Init tickstart for timeout management*/
1374 tickstart = HAL_GetTick();
1375
1376 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1377 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1378 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1379
1380 /* Prepare transfer parameters */
1381 hi2c->pBuffPtr = pData;
1382 hi2c->XferCount = Size;
1383 hi2c->XferISR = NULL;
1384
1385 /* Enable Address Acknowledge */
1386 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1387
1388 /* Wait until ADDR flag is set */
1389 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1390 {
1391 /* Disable Address Acknowledge */
1392 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1393 return HAL_ERROR;
1394 }
1395
1396 /* Preload TX data if no stretch enable */
1397 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1398 {
1399 /* Preload TX register */
1400 /* Write data to TXDR */
1401 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1402
1403 /* Increment Buffer pointer */
1404 hi2c->pBuffPtr++;
1405
1406 hi2c->XferCount--;
1407 }
1408
1409 /* Clear ADDR flag */
1410 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1411
1412 /* If 10bit addressing mode is selected */
1413 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1414 {
1415 /* Wait until ADDR flag is set */
1416 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1417 {
1418 /* Disable Address Acknowledge */
1419 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1420 return HAL_ERROR;
1421 }
1422
1423 /* Clear ADDR flag */
1424 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1425 }
1426
1427 /* Wait until DIR flag is set Transmitter mode */
1428 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1429 {
1430 /* Disable Address Acknowledge */
1431 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1432 return HAL_ERROR;
1433 }
1434
1435 while (hi2c->XferCount > 0U)
1436 {
1437 /* Wait until TXIS flag is set */
1438 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1439 {
1440 /* Disable Address Acknowledge */
1441 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1442 return HAL_ERROR;
1443 }
1444
1445 /* Write data to TXDR */
1446 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1447
1448 /* Increment Buffer pointer */
1449 hi2c->pBuffPtr++;
1450
1451 hi2c->XferCount--;
1452 }
1453
1454 /* Wait until AF flag is set */
1455 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1456 {
1457 /* Disable Address Acknowledge */
1458 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1459 return HAL_ERROR;
1460 }
1461
1462 /* Flush TX register */
1463 I2C_Flush_TXDR(hi2c);
1464
1465 /* Clear AF flag */
1466 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1467
1468 /* Wait until STOP flag is set */
1469 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1470 {
1471 /* Disable Address Acknowledge */
1472 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1473
1474 return HAL_ERROR;
1475 }
1476
1477 /* Clear STOP flag */
1478 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1479
1480 /* Wait until BUSY flag is reset */
1481 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1482 {
1483 /* Disable Address Acknowledge */
1484 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1485 return HAL_ERROR;
1486 }
1487
1488 /* Disable Address Acknowledge */
1489 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1490
1491 hi2c->State = HAL_I2C_STATE_READY;
1492 hi2c->Mode = HAL_I2C_MODE_NONE;
1493
1494 /* Process Unlocked */
1495 __HAL_UNLOCK(hi2c);
1496
1497 return HAL_OK;
1498 }
1499 else
1500 {
1501 return HAL_BUSY;
1502 }
1503 }
1504
1505 /**
1506 * @brief Receive in slave mode an amount of data in blocking mode
1507 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1508 * the configuration information for the specified I2C.
1509 * @param pData Pointer to data buffer
1510 * @param Size Amount of data to be sent
1511 * @param Timeout Timeout duration
1512 * @retval HAL status
1513 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1514 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1515 uint32_t Timeout)
1516 {
1517 uint32_t tickstart;
1518
1519 if (hi2c->State == HAL_I2C_STATE_READY)
1520 {
1521 if ((pData == NULL) || (Size == 0U))
1522 {
1523 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1524 return HAL_ERROR;
1525 }
1526 /* Process Locked */
1527 __HAL_LOCK(hi2c);
1528
1529 /* Init tickstart for timeout management*/
1530 tickstart = HAL_GetTick();
1531
1532 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1533 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1534 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1535
1536 /* Prepare transfer parameters */
1537 hi2c->pBuffPtr = pData;
1538 hi2c->XferCount = Size;
1539 hi2c->XferSize = hi2c->XferCount;
1540 hi2c->XferISR = NULL;
1541
1542 /* Enable Address Acknowledge */
1543 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1544
1545 /* Wait until ADDR flag is set */
1546 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1547 {
1548 /* Disable Address Acknowledge */
1549 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1550 return HAL_ERROR;
1551 }
1552
1553 /* Clear ADDR flag */
1554 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1555
1556 /* Wait until DIR flag is reset Receiver mode */
1557 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1558 {
1559 /* Disable Address Acknowledge */
1560 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1561 return HAL_ERROR;
1562 }
1563
1564 while (hi2c->XferCount > 0U)
1565 {
1566 /* Wait until RXNE flag is set */
1567 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1568 {
1569 /* Disable Address Acknowledge */
1570 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1571
1572 /* Store Last receive data if any */
1573 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1574 {
1575 /* Read data from RXDR */
1576 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1577
1578 /* Increment Buffer pointer */
1579 hi2c->pBuffPtr++;
1580
1581 hi2c->XferCount--;
1582 hi2c->XferSize--;
1583 }
1584
1585 return HAL_ERROR;
1586 }
1587
1588 /* Read data from RXDR */
1589 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1590
1591 /* Increment Buffer pointer */
1592 hi2c->pBuffPtr++;
1593
1594 hi2c->XferCount--;
1595 hi2c->XferSize--;
1596 }
1597
1598 /* Wait until STOP flag is set */
1599 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1600 {
1601 /* Disable Address Acknowledge */
1602 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1603 return HAL_ERROR;
1604 }
1605
1606 /* Clear STOP flag */
1607 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1608
1609 /* Wait until BUSY flag is reset */
1610 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1611 {
1612 /* Disable Address Acknowledge */
1613 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1614 return HAL_ERROR;
1615 }
1616
1617 /* Disable Address Acknowledge */
1618 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1619
1620 hi2c->State = HAL_I2C_STATE_READY;
1621 hi2c->Mode = HAL_I2C_MODE_NONE;
1622
1623 /* Process Unlocked */
1624 __HAL_UNLOCK(hi2c);
1625
1626 return HAL_OK;
1627 }
1628 else
1629 {
1630 return HAL_BUSY;
1631 }
1632 }
1633
1634 /**
1635 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1636 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1637 * the configuration information for the specified I2C.
1638 * @param DevAddress Target device address: The device 7 bits address value
1639 * in datasheet must be shifted to the left before calling the interface
1640 * @param pData Pointer to data buffer
1641 * @param Size Amount of data to be sent
1642 * @retval HAL status
1643 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1644 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1645 uint16_t Size)
1646 {
1647 uint32_t xfermode;
1648
1649 if (hi2c->State == HAL_I2C_STATE_READY)
1650 {
1651 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1652 {
1653 return HAL_BUSY;
1654 }
1655
1656 /* Process Locked */
1657 __HAL_LOCK(hi2c);
1658
1659 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1660 hi2c->Mode = HAL_I2C_MODE_MASTER;
1661 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1662
1663 /* Prepare transfer parameters */
1664 hi2c->pBuffPtr = pData;
1665 hi2c->XferCount = Size;
1666 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1667 hi2c->XferISR = I2C_Master_ISR_IT;
1668
1669 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1670 {
1671 hi2c->XferSize = MAX_NBYTE_SIZE;
1672 xfermode = I2C_RELOAD_MODE;
1673 }
1674 else
1675 {
1676 hi2c->XferSize = hi2c->XferCount;
1677 xfermode = I2C_AUTOEND_MODE;
1678 }
1679
1680 /* Send Slave Address */
1681 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1682 /* Check if the Autonomous mode is enabled */
1683 if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
1684 {
1685 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_WRITE);
1686 }
1687 else
1688 {
1689 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1690 }
1691
1692 /* Process Unlocked */
1693 __HAL_UNLOCK(hi2c);
1694
1695 /* Note : The I2C interrupts must be enabled after unlocking current process
1696 to avoid the risk of I2C interrupt handle execution before current
1697 process unlock */
1698
1699 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1700 /* possible to enable all of these */
1701 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1702 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1703 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1704
1705 return HAL_OK;
1706 }
1707 else
1708 {
1709 return HAL_BUSY;
1710 }
1711 }
1712
1713 /**
1714 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1715 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1716 * the configuration information for the specified I2C.
1717 * @param DevAddress Target device address: The device 7 bits address value
1718 * in datasheet must be shifted to the left before calling the interface
1719 * @param pData Pointer to data buffer
1720 * @param Size Amount of data to be sent
1721 * @retval HAL status
1722 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1723 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1724 uint16_t Size)
1725 {
1726 uint32_t xfermode;
1727
1728 if (hi2c->State == HAL_I2C_STATE_READY)
1729 {
1730 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1731 {
1732 return HAL_BUSY;
1733 }
1734
1735 /* Process Locked */
1736 __HAL_LOCK(hi2c);
1737
1738 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1739 hi2c->Mode = HAL_I2C_MODE_MASTER;
1740 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1741
1742 /* Prepare transfer parameters */
1743 hi2c->pBuffPtr = pData;
1744 hi2c->XferCount = Size;
1745 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1746 hi2c->XferISR = I2C_Master_ISR_IT;
1747
1748 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1749 {
1750 hi2c->XferSize = MAX_NBYTE_SIZE;
1751 xfermode = I2C_RELOAD_MODE;
1752 }
1753 else
1754 {
1755 hi2c->XferSize = hi2c->XferCount;
1756 xfermode = I2C_AUTOEND_MODE;
1757 }
1758
1759 /* Send Slave Address */
1760 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1761 /* Check if the Autonomous mode is enabled */
1762 if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
1763 {
1764 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_READ);
1765 }
1766 else
1767 {
1768 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1769 }
1770
1771 /* Process Unlocked */
1772 __HAL_UNLOCK(hi2c);
1773
1774 /* Note : The I2C interrupts must be enabled after unlocking current process
1775 to avoid the risk of I2C interrupt handle execution before current
1776 process unlock */
1777
1778 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1779 /* possible to enable all of these */
1780 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1781 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1782 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1783
1784 return HAL_OK;
1785 }
1786 else
1787 {
1788 return HAL_BUSY;
1789 }
1790 }
1791
1792 /**
1793 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1794 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1795 * the configuration information for the specified I2C.
1796 * @param pData Pointer to data buffer
1797 * @param Size Amount of data to be sent
1798 * @retval HAL status
1799 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1800 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1801 {
1802 if (hi2c->State == HAL_I2C_STATE_READY)
1803 {
1804 /* Process Locked */
1805 __HAL_LOCK(hi2c);
1806
1807 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1808 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1809 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1810
1811 /* Enable Address Acknowledge */
1812 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1813
1814 /* Prepare transfer parameters */
1815 hi2c->pBuffPtr = pData;
1816 hi2c->XferCount = Size;
1817 hi2c->XferSize = hi2c->XferCount;
1818 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1819 hi2c->XferISR = I2C_Slave_ISR_IT;
1820
1821 /* Preload TX data if no stretch enable */
1822 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1823 {
1824 /* Preload TX register */
1825 /* Write data to TXDR */
1826 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1827
1828 /* Increment Buffer pointer */
1829 hi2c->pBuffPtr++;
1830
1831 hi2c->XferCount--;
1832 hi2c->XferSize--;
1833 }
1834
1835 /* Process Unlocked */
1836 __HAL_UNLOCK(hi2c);
1837
1838 /* Note : The I2C interrupts must be enabled after unlocking current process
1839 to avoid the risk of I2C interrupt handle execution before current
1840 process unlock */
1841
1842 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1843 /* possible to enable all of these */
1844 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1845 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1846 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1847
1848 return HAL_OK;
1849 }
1850 else
1851 {
1852 return HAL_BUSY;
1853 }
1854 }
1855
1856 /**
1857 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1858 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1859 * the configuration information for the specified I2C.
1860 * @param pData Pointer to data buffer
1861 * @param Size Amount of data to be sent
1862 * @retval HAL status
1863 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1864 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1865 {
1866 if (hi2c->State == HAL_I2C_STATE_READY)
1867 {
1868 /* Process Locked */
1869 __HAL_LOCK(hi2c);
1870
1871 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1872 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1873 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1874
1875 /* Enable Address Acknowledge */
1876 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1877
1878 /* Prepare transfer parameters */
1879 hi2c->pBuffPtr = pData;
1880 hi2c->XferCount = Size;
1881 hi2c->XferSize = hi2c->XferCount;
1882 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1883 hi2c->XferISR = I2C_Slave_ISR_IT;
1884
1885 /* Process Unlocked */
1886 __HAL_UNLOCK(hi2c);
1887
1888 /* Note : The I2C interrupts must be enabled after unlocking current process
1889 to avoid the risk of I2C interrupt handle execution before current
1890 process unlock */
1891
1892 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1893 /* possible to enable all of these */
1894 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1895 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1896 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1897
1898 return HAL_OK;
1899 }
1900 else
1901 {
1902 return HAL_BUSY;
1903 }
1904 }
1905
1906 #if defined(HAL_DMA_MODULE_ENABLED)
1907 /**
1908 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1909 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1910 * the configuration information for the specified I2C.
1911 * @param DevAddress Target device address: The device 7 bits address value
1912 * in datasheet must be shifted to the left before calling the interface
1913 * @param pData Pointer to data buffer
1914 * @param Size Amount of data to be sent
1915 * @retval HAL status
1916 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1917 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1918 uint16_t Size)
1919 {
1920 uint32_t xfermode;
1921 HAL_StatusTypeDef dmaxferstatus;
1922
1923 if (hi2c->State == HAL_I2C_STATE_READY)
1924 {
1925 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1926 {
1927 return HAL_BUSY;
1928 }
1929
1930 /* Process Locked */
1931 __HAL_LOCK(hi2c);
1932
1933 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1934 hi2c->Mode = HAL_I2C_MODE_MASTER;
1935 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1936
1937 /* Prepare transfer parameters */
1938 hi2c->pBuffPtr = pData;
1939 hi2c->XferCount = Size;
1940 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1941 hi2c->XferISR = I2C_Master_ISR_DMA;
1942
1943 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1944 {
1945 hi2c->XferSize = MAX_NBYTE_SIZE;
1946 xfermode = I2C_RELOAD_MODE;
1947 }
1948 else
1949 {
1950 hi2c->XferSize = hi2c->XferCount;
1951 xfermode = I2C_AUTOEND_MODE;
1952 }
1953
1954 if (hi2c->XferSize > 0U)
1955 {
1956 if (hi2c->hdmatx != NULL)
1957 {
1958 /* Set the I2C DMA transfer complete callback */
1959 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1960
1961 /* Set the DMA error callback */
1962 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1963
1964 /* Set the unused DMA callbacks to NULL */
1965 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1966 hi2c->hdmatx->XferAbortCallback = NULL;
1967
1968 /* Enable the DMA channel */
1969 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1970 {
1971 if (hi2c->hdmatx->LinkedListQueue != NULL)
1972 {
1973 /* Set DMA data size */
1974 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
1975
1976 /* Set DMA source address */
1977 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
1978
1979 /* Set DMA destination address */
1980 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
1981 = (uint32_t)&hi2c->Instance->TXDR;
1982
1983 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
1984 }
1985 else
1986 {
1987 /* Update I2C state */
1988 hi2c->State = HAL_I2C_STATE_READY;
1989 hi2c->Mode = HAL_I2C_MODE_NONE;
1990
1991 /* Update I2C error code */
1992 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
1993
1994 /* Process Unlocked */
1995 __HAL_UNLOCK(hi2c);
1996
1997 return HAL_ERROR;
1998 }
1999 }
2000 else
2001 {
2002 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2003 hi2c->XferSize);
2004 }
2005 }
2006 else
2007 {
2008 /* Update I2C state */
2009 hi2c->State = HAL_I2C_STATE_READY;
2010 hi2c->Mode = HAL_I2C_MODE_NONE;
2011
2012 /* Update I2C error code */
2013 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2014
2015 /* Process Unlocked */
2016 __HAL_UNLOCK(hi2c);
2017
2018 return HAL_ERROR;
2019 }
2020
2021 if (dmaxferstatus == HAL_OK)
2022 {
2023 /* Send Slave Address */
2024 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2025 /* Check if the Autonomous mode is enabled */
2026 if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
2027 {
2028 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
2029 I2C_GENERATE_NO_START_WRITE);
2030 }
2031 else
2032 {
2033 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
2034 }
2035
2036 /* Update XferCount value */
2037 hi2c->XferCount -= hi2c->XferSize;
2038
2039 /* Process Unlocked */
2040 __HAL_UNLOCK(hi2c);
2041
2042 /* Note : The I2C interrupts must be enabled after unlocking current process
2043 to avoid the risk of I2C interrupt handle execution before current
2044 process unlock */
2045 /* Enable ERR and NACK interrupts */
2046 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2047
2048 /* Enable DMA Request */
2049 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2050 }
2051 else
2052 {
2053 /* Update I2C state */
2054 hi2c->State = HAL_I2C_STATE_READY;
2055 hi2c->Mode = HAL_I2C_MODE_NONE;
2056
2057 /* Update I2C error code */
2058 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2059
2060 /* Process Unlocked */
2061 __HAL_UNLOCK(hi2c);
2062
2063 return HAL_ERROR;
2064 }
2065 }
2066 else
2067 {
2068 /* Update Transfer ISR function pointer */
2069 hi2c->XferISR = I2C_Master_ISR_IT;
2070
2071 /* Send Slave Address */
2072 /* Set NBYTES to write and generate START condition */
2073 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2074 I2C_GENERATE_START_WRITE);
2075
2076 /* Process Unlocked */
2077 __HAL_UNLOCK(hi2c);
2078
2079 /* Note : The I2C interrupts must be enabled after unlocking current process
2080 to avoid the risk of I2C interrupt handle execution before current
2081 process unlock */
2082 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2083 /* possible to enable all of these */
2084 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2085 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2086 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2087 }
2088
2089 return HAL_OK;
2090 }
2091 else
2092 {
2093 return HAL_BUSY;
2094 }
2095 }
2096
2097 /**
2098 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2099 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2100 * the configuration information for the specified I2C.
2101 * @param DevAddress Target device address: The device 7 bits address value
2102 * in datasheet must be shifted to the left before calling the interface
2103 * @param pData Pointer to data buffer
2104 * @param Size Amount of data to be sent
2105 * @retval HAL status
2106 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2107 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2108 uint16_t Size)
2109 {
2110 uint32_t xfermode;
2111 HAL_StatusTypeDef dmaxferstatus;
2112
2113 if (hi2c->State == HAL_I2C_STATE_READY)
2114 {
2115 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2116 {
2117 return HAL_BUSY;
2118 }
2119
2120 /* Process Locked */
2121 __HAL_LOCK(hi2c);
2122
2123 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2124 hi2c->Mode = HAL_I2C_MODE_MASTER;
2125 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2126
2127 /* Prepare transfer parameters */
2128 hi2c->pBuffPtr = pData;
2129 hi2c->XferCount = Size;
2130 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2131 hi2c->XferISR = I2C_Master_ISR_DMA;
2132
2133 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2134 {
2135 hi2c->XferSize = MAX_NBYTE_SIZE;
2136 xfermode = I2C_RELOAD_MODE;
2137 }
2138 else
2139 {
2140 hi2c->XferSize = hi2c->XferCount;
2141 xfermode = I2C_AUTOEND_MODE;
2142 }
2143
2144 if (hi2c->XferSize > 0U)
2145 {
2146 if (hi2c->hdmarx != NULL)
2147 {
2148 /* Set the I2C DMA transfer complete callback */
2149 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2150
2151 /* Set the DMA error callback */
2152 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2153
2154 /* Set the unused DMA callbacks to NULL */
2155 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2156 hi2c->hdmarx->XferAbortCallback = NULL;
2157
2158 /* Enable the DMA channel */
2159 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2160 {
2161 if (hi2c->hdmarx->LinkedListQueue != NULL)
2162 {
2163 /* Set DMA data size */
2164 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2165
2166 /* Set DMA source address */
2167 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
2168 = (uint32_t)&hi2c->Instance->RXDR;
2169
2170 /* Set DMA destination address */
2171 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
2172
2173 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
2174 }
2175 else
2176 {
2177 /* Update I2C state */
2178 hi2c->State = HAL_I2C_STATE_READY;
2179 hi2c->Mode = HAL_I2C_MODE_NONE;
2180
2181 /* Update I2C error code */
2182 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2183
2184 /* Process Unlocked */
2185 __HAL_UNLOCK(hi2c);
2186
2187 return HAL_ERROR;
2188 }
2189 }
2190 else
2191 {
2192 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2193 hi2c->XferSize);
2194 }
2195 }
2196 else
2197 {
2198 /* Update I2C state */
2199 hi2c->State = HAL_I2C_STATE_READY;
2200 hi2c->Mode = HAL_I2C_MODE_NONE;
2201
2202 /* Update I2C error code */
2203 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2204
2205 /* Process Unlocked */
2206 __HAL_UNLOCK(hi2c);
2207
2208 return HAL_ERROR;
2209 }
2210
2211 if (dmaxferstatus == HAL_OK)
2212 {
2213 /* Send Slave Address */
2214 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2215 /* Check if the Autonomous mode is enabled */
2216 if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
2217 {
2218 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
2219 I2C_GENERATE_NO_START_READ);
2220 }
2221 else
2222 {
2223 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2224 }
2225
2226 /* Update XferCount value */
2227 hi2c->XferCount -= hi2c->XferSize;
2228
2229 /* Process Unlocked */
2230 __HAL_UNLOCK(hi2c);
2231
2232 /* Note : The I2C interrupts must be enabled after unlocking current process
2233 to avoid the risk of I2C interrupt handle execution before current
2234 process unlock */
2235 /* Enable ERR and NACK interrupts */
2236 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2237
2238 /* Enable DMA Request */
2239 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2240 }
2241 else
2242 {
2243 /* Update I2C state */
2244 hi2c->State = HAL_I2C_STATE_READY;
2245 hi2c->Mode = HAL_I2C_MODE_NONE;
2246
2247 /* Update I2C error code */
2248 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2249
2250 /* Process Unlocked */
2251 __HAL_UNLOCK(hi2c);
2252
2253 return HAL_ERROR;
2254 }
2255 }
2256 else
2257 {
2258 /* Update Transfer ISR function pointer */
2259 hi2c->XferISR = I2C_Master_ISR_IT;
2260
2261 /* Send Slave Address */
2262 /* Set NBYTES to read and generate START condition */
2263 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2264 I2C_GENERATE_START_READ);
2265
2266 /* Process Unlocked */
2267 __HAL_UNLOCK(hi2c);
2268
2269 /* Note : The I2C interrupts must be enabled after unlocking current process
2270 to avoid the risk of I2C interrupt handle execution before current
2271 process unlock */
2272 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2273 /* possible to enable all of these */
2274 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2275 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2276 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2277 }
2278
2279 return HAL_OK;
2280 }
2281 else
2282 {
2283 return HAL_BUSY;
2284 }
2285 }
2286
2287 /**
2288 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2289 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2290 * the configuration information for the specified I2C.
2291 * @param pData Pointer to data buffer
2292 * @param Size Amount of data to be sent
2293 * @retval HAL status
2294 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2295 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2296 {
2297 HAL_StatusTypeDef dmaxferstatus;
2298
2299 if (hi2c->State == HAL_I2C_STATE_READY)
2300 {
2301 if ((pData == NULL) || (Size == 0U))
2302 {
2303 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2304 return HAL_ERROR;
2305 }
2306 /* Process Locked */
2307 __HAL_LOCK(hi2c);
2308
2309 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2310 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2311 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2312
2313 /* Prepare transfer parameters */
2314 hi2c->pBuffPtr = pData;
2315 hi2c->XferCount = Size;
2316 hi2c->XferSize = hi2c->XferCount;
2317 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2318 hi2c->XferISR = I2C_Slave_ISR_DMA;
2319
2320 /* Preload TX data if no stretch enable */
2321 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
2322 {
2323 /* Preload TX register */
2324 /* Write data to TXDR */
2325 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2326
2327 /* Increment Buffer pointer */
2328 hi2c->pBuffPtr++;
2329
2330 hi2c->XferCount--;
2331 hi2c->XferSize--;
2332 }
2333
2334 if (hi2c->XferCount != 0U)
2335 {
2336 if (hi2c->hdmatx != NULL)
2337 {
2338 /* Set the I2C DMA transfer complete callback */
2339 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2340
2341 /* Set the DMA error callback */
2342 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2343
2344 /* Set the unused DMA callbacks to NULL */
2345 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2346 hi2c->hdmatx->XferAbortCallback = NULL;
2347
2348 /* Enable the DMA channel */
2349 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2350 {
2351 if (hi2c->hdmatx->LinkedListQueue != NULL)
2352 {
2353 /* Set DMA data size */
2354 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2355
2356 /* Set DMA source address */
2357 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
2358
2359 /* Set DMA destination address */
2360 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
2361 = (uint32_t)&hi2c->Instance->TXDR;
2362
2363 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
2364 }
2365 else
2366 {
2367 /* Update I2C state */
2368 hi2c->State = HAL_I2C_STATE_LISTEN;
2369 hi2c->Mode = HAL_I2C_MODE_NONE;
2370
2371 /* Update I2C error code */
2372 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2373
2374 /* Process Unlocked */
2375 __HAL_UNLOCK(hi2c);
2376
2377 return HAL_ERROR;
2378 }
2379 }
2380 else
2381 {
2382 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
2383 (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
2384 hi2c->XferSize);
2385 }
2386 }
2387 else
2388 {
2389 /* Update I2C state */
2390 hi2c->State = HAL_I2C_STATE_LISTEN;
2391 hi2c->Mode = HAL_I2C_MODE_NONE;
2392
2393 /* Update I2C error code */
2394 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2395
2396 /* Process Unlocked */
2397 __HAL_UNLOCK(hi2c);
2398
2399 return HAL_ERROR;
2400 }
2401
2402 if (dmaxferstatus == HAL_OK)
2403 {
2404 /* Enable Address Acknowledge */
2405 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2406
2407 /* Process Unlocked */
2408 __HAL_UNLOCK(hi2c);
2409
2410 /* Note : The I2C interrupts must be enabled after unlocking current process
2411 to avoid the risk of I2C interrupt handle execution before current
2412 process unlock */
2413 /* Enable ERR, STOP, NACK, ADDR interrupts */
2414 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2415
2416 /* Enable DMA Request */
2417 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2418 }
2419 else
2420 {
2421 /* Update I2C state */
2422 hi2c->State = HAL_I2C_STATE_LISTEN;
2423 hi2c->Mode = HAL_I2C_MODE_NONE;
2424
2425 /* Update I2C error code */
2426 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2427
2428 /* Process Unlocked */
2429 __HAL_UNLOCK(hi2c);
2430
2431 return HAL_ERROR;
2432 }
2433 }
2434 else
2435 {
2436 /* Enable Address Acknowledge */
2437 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2438
2439 /* Process Unlocked */
2440 __HAL_UNLOCK(hi2c);
2441
2442 /* Note : The I2C interrupts must be enabled after unlocking current process
2443 to avoid the risk of I2C interrupt handle execution before current
2444 process unlock */
2445 /* Enable ERR, STOP, NACK, ADDR interrupts */
2446 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2447 }
2448
2449 return HAL_OK;
2450 }
2451 else
2452 {
2453 return HAL_BUSY;
2454 }
2455 }
2456
2457 /**
2458 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2459 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2460 * the configuration information for the specified I2C.
2461 * @param pData Pointer to data buffer
2462 * @param Size Amount of data to be sent
2463 * @retval HAL status
2464 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2465 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2466 {
2467 HAL_StatusTypeDef dmaxferstatus;
2468
2469 if (hi2c->State == HAL_I2C_STATE_READY)
2470 {
2471 if ((pData == NULL) || (Size == 0U))
2472 {
2473 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2474 return HAL_ERROR;
2475 }
2476 /* Process Locked */
2477 __HAL_LOCK(hi2c);
2478
2479 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2480 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2481 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2482
2483 /* Prepare transfer parameters */
2484 hi2c->pBuffPtr = pData;
2485 hi2c->XferCount = Size;
2486 hi2c->XferSize = hi2c->XferCount;
2487 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2488 hi2c->XferISR = I2C_Slave_ISR_DMA;
2489
2490 if (hi2c->hdmarx != NULL)
2491 {
2492 /* Set the I2C DMA transfer complete callback */
2493 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2494
2495 /* Set the DMA error callback */
2496 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2497
2498 /* Set the unused DMA callbacks to NULL */
2499 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2500 hi2c->hdmarx->XferAbortCallback = NULL;
2501
2502 /* Enable the DMA channel */
2503 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2504 {
2505 if (hi2c->hdmarx->LinkedListQueue != NULL)
2506 {
2507 /* Set DMA data size */
2508 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2509
2510 /* Set DMA source address */
2511 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
2512 = (uint32_t)&hi2c->Instance->RXDR;
2513
2514 /* Set DMA destination address */
2515 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
2516
2517 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
2518 }
2519 else
2520 {
2521 /* Update I2C state */
2522 hi2c->State = HAL_I2C_STATE_LISTEN;
2523 hi2c->Mode = HAL_I2C_MODE_NONE;
2524
2525 /* Update I2C error code */
2526 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2527
2528 /* Process Unlocked */
2529 __HAL_UNLOCK(hi2c);
2530
2531 return HAL_ERROR;
2532 }
2533 }
2534 else
2535 {
2536 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2537 hi2c->XferSize);
2538 }
2539 }
2540 else
2541 {
2542 /* Update I2C state */
2543 hi2c->State = HAL_I2C_STATE_LISTEN;
2544 hi2c->Mode = HAL_I2C_MODE_NONE;
2545
2546 /* Update I2C error code */
2547 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2548
2549 /* Process Unlocked */
2550 __HAL_UNLOCK(hi2c);
2551
2552 return HAL_ERROR;
2553 }
2554
2555 if (dmaxferstatus == HAL_OK)
2556 {
2557 /* Enable Address Acknowledge */
2558 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2559
2560 /* Process Unlocked */
2561 __HAL_UNLOCK(hi2c);
2562
2563 /* Note : The I2C interrupts must be enabled after unlocking current process
2564 to avoid the risk of I2C interrupt handle execution before current
2565 process unlock */
2566 /* Enable ERR, STOP, NACK, ADDR interrupts */
2567 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2568
2569 /* Enable DMA Request */
2570 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2571 }
2572 else
2573 {
2574 /* Update I2C state */
2575 hi2c->State = HAL_I2C_STATE_LISTEN;
2576 hi2c->Mode = HAL_I2C_MODE_NONE;
2577
2578 /* Update I2C error code */
2579 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2580
2581 /* Process Unlocked */
2582 __HAL_UNLOCK(hi2c);
2583
2584 return HAL_ERROR;
2585 }
2586
2587 return HAL_OK;
2588 }
2589 else
2590 {
2591 return HAL_BUSY;
2592 }
2593 }
2594 #endif /* HAL_DMA_MODULE_ENABLED */
2595
2596 /**
2597 * @brief Write an amount of data in blocking mode to a specific memory address
2598 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2599 * the configuration information for the specified I2C.
2600 * @param DevAddress Target device address: The device 7 bits address value
2601 * in datasheet must be shifted to the left before calling the interface
2602 * @param MemAddress Internal memory address
2603 * @param MemAddSize Size of internal memory address
2604 * @param pData Pointer to data buffer
2605 * @param Size Amount of data to be sent
2606 * @param Timeout Timeout duration
2607 * @retval HAL status
2608 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2609 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2610 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2611 {
2612 uint32_t tickstart;
2613
2614 /* Check the parameters */
2615 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2616
2617 if (hi2c->State == HAL_I2C_STATE_READY)
2618 {
2619 if ((pData == NULL) || (Size == 0U))
2620 {
2621 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2622 return HAL_ERROR;
2623 }
2624
2625 /* Process Locked */
2626 __HAL_LOCK(hi2c);
2627
2628 /* Init tickstart for timeout management*/
2629 tickstart = HAL_GetTick();
2630
2631 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2632 {
2633 return HAL_ERROR;
2634 }
2635
2636 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2637 hi2c->Mode = HAL_I2C_MODE_MEM;
2638 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2639
2640 /* Prepare transfer parameters */
2641 hi2c->pBuffPtr = pData;
2642 hi2c->XferCount = Size;
2643 hi2c->XferISR = NULL;
2644
2645 /* Send Slave Address and Memory Address */
2646 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2647 {
2648 /* Process Unlocked */
2649 __HAL_UNLOCK(hi2c);
2650 return HAL_ERROR;
2651 }
2652
2653 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2654 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2655 {
2656 hi2c->XferSize = MAX_NBYTE_SIZE;
2657 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2658 }
2659 else
2660 {
2661 hi2c->XferSize = hi2c->XferCount;
2662 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2663 }
2664
2665 do
2666 {
2667 /* Wait until TXIS flag is set */
2668 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2669 {
2670 return HAL_ERROR;
2671 }
2672
2673 /* Write data to TXDR */
2674 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2675
2676 /* Increment Buffer pointer */
2677 hi2c->pBuffPtr++;
2678
2679 hi2c->XferCount--;
2680 hi2c->XferSize--;
2681
2682 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2683 {
2684 /* Wait until TCR flag is set */
2685 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2686 {
2687 return HAL_ERROR;
2688 }
2689
2690 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2691 {
2692 hi2c->XferSize = MAX_NBYTE_SIZE;
2693 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2694 I2C_NO_STARTSTOP);
2695 }
2696 else
2697 {
2698 hi2c->XferSize = hi2c->XferCount;
2699 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2700 I2C_NO_STARTSTOP);
2701 }
2702 }
2703
2704 } while (hi2c->XferCount > 0U);
2705
2706 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2707 /* Wait until STOPF flag is reset */
2708 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2709 {
2710 return HAL_ERROR;
2711 }
2712
2713 /* Clear STOP Flag */
2714 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2715
2716 /* Clear Configuration Register 2 */
2717 I2C_RESET_CR2(hi2c);
2718
2719 hi2c->State = HAL_I2C_STATE_READY;
2720 hi2c->Mode = HAL_I2C_MODE_NONE;
2721
2722 /* Process Unlocked */
2723 __HAL_UNLOCK(hi2c);
2724
2725 return HAL_OK;
2726 }
2727 else
2728 {
2729 return HAL_BUSY;
2730 }
2731 }
2732
2733 /**
2734 * @brief Read an amount of data in blocking mode from a specific memory address
2735 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2736 * the configuration information for the specified I2C.
2737 * @param DevAddress Target device address: The device 7 bits address value
2738 * in datasheet must be shifted to the left before calling the interface
2739 * @param MemAddress Internal memory address
2740 * @param MemAddSize Size of internal memory address
2741 * @param pData Pointer to data buffer
2742 * @param Size Amount of data to be sent
2743 * @param Timeout Timeout duration
2744 * @retval HAL status
2745 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2746 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2747 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2748 {
2749 uint32_t tickstart;
2750
2751 /* Check the parameters */
2752 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2753
2754 if (hi2c->State == HAL_I2C_STATE_READY)
2755 {
2756 if ((pData == NULL) || (Size == 0U))
2757 {
2758 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2759 return HAL_ERROR;
2760 }
2761
2762 /* Process Locked */
2763 __HAL_LOCK(hi2c);
2764
2765 /* Init tickstart for timeout management*/
2766 tickstart = HAL_GetTick();
2767
2768 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2769 {
2770 return HAL_ERROR;
2771 }
2772
2773 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2774 hi2c->Mode = HAL_I2C_MODE_MEM;
2775 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2776
2777 /* Prepare transfer parameters */
2778 hi2c->pBuffPtr = pData;
2779 hi2c->XferCount = Size;
2780 hi2c->XferISR = NULL;
2781
2782 /* Send Slave Address and Memory Address */
2783 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2784 {
2785 /* Process Unlocked */
2786 __HAL_UNLOCK(hi2c);
2787 return HAL_ERROR;
2788 }
2789
2790 /* Send Slave Address */
2791 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2792 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2793 {
2794 hi2c->XferSize = MAX_NBYTE_SIZE;
2795 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2796 I2C_GENERATE_START_READ);
2797 }
2798 else
2799 {
2800 hi2c->XferSize = hi2c->XferCount;
2801 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2802 I2C_GENERATE_START_READ);
2803 }
2804
2805 do
2806 {
2807 /* Wait until RXNE flag is set */
2808 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2809 {
2810 return HAL_ERROR;
2811 }
2812
2813 /* Read data from RXDR */
2814 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2815
2816 /* Increment Buffer pointer */
2817 hi2c->pBuffPtr++;
2818
2819 hi2c->XferSize--;
2820 hi2c->XferCount--;
2821
2822 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2823 {
2824 /* Wait until TCR flag is set */
2825 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2826 {
2827 return HAL_ERROR;
2828 }
2829
2830 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2831 {
2832 hi2c->XferSize = MAX_NBYTE_SIZE;
2833 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2834 I2C_NO_STARTSTOP);
2835 }
2836 else
2837 {
2838 hi2c->XferSize = hi2c->XferCount;
2839 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2840 I2C_NO_STARTSTOP);
2841 }
2842 }
2843 } while (hi2c->XferCount > 0U);
2844
2845 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2846 /* Wait until STOPF flag is reset */
2847 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2848 {
2849 return HAL_ERROR;
2850 }
2851
2852 /* Clear STOP Flag */
2853 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2854
2855 /* Clear Configuration Register 2 */
2856 I2C_RESET_CR2(hi2c);
2857
2858 hi2c->State = HAL_I2C_STATE_READY;
2859 hi2c->Mode = HAL_I2C_MODE_NONE;
2860
2861 /* Process Unlocked */
2862 __HAL_UNLOCK(hi2c);
2863
2864 return HAL_OK;
2865 }
2866 else
2867 {
2868 return HAL_BUSY;
2869 }
2870 }
2871 /**
2872 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2873 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2874 * the configuration information for the specified I2C.
2875 * @param DevAddress Target device address: The device 7 bits address value
2876 * in datasheet must be shifted to the left before calling the interface
2877 * @param MemAddress Internal memory address
2878 * @param MemAddSize Size of internal memory address
2879 * @param pData Pointer to data buffer
2880 * @param Size Amount of data to be sent
2881 * @retval HAL status
2882 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2883 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2884 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2885 {
2886 /* Check the parameters */
2887 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2888
2889 if (hi2c->State == HAL_I2C_STATE_READY)
2890 {
2891 if ((pData == NULL) || (Size == 0U))
2892 {
2893 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2894 return HAL_ERROR;
2895 }
2896
2897 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2898 {
2899 return HAL_BUSY;
2900 }
2901
2902 /* Process Locked */
2903 __HAL_LOCK(hi2c);
2904
2905 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2906 hi2c->Mode = HAL_I2C_MODE_MEM;
2907 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2908
2909 /* Prepare transfer parameters */
2910 hi2c->pBuffPtr = pData;
2911 hi2c->XferCount = Size;
2912 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2913 hi2c->XferISR = I2C_Mem_ISR_IT;
2914 hi2c->Devaddress = DevAddress;
2915
2916 /* If Memory address size is 8Bit */
2917 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2918 {
2919 /* Prefetch Memory Address */
2920 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2921
2922 /* Reset Memaddress content */
2923 hi2c->Memaddress = 0xFFFFFFFFU;
2924 }
2925 /* If Memory address size is 16Bit */
2926 else
2927 {
2928 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2929 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2930
2931 /* Prepare Memaddress buffer for LSB part */
2932 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2933 }
2934 /* Send Slave Address and Memory Address */
2935 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2936
2937 /* Process Unlocked */
2938 __HAL_UNLOCK(hi2c);
2939
2940 /* Note : The I2C interrupts must be enabled after unlocking current process
2941 to avoid the risk of I2C interrupt handle execution before current
2942 process unlock */
2943
2944 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2945 /* possible to enable all of these */
2946 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2947 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2948 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2949
2950 return HAL_OK;
2951 }
2952 else
2953 {
2954 return HAL_BUSY;
2955 }
2956 }
2957
2958 /**
2959 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2960 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2961 * the configuration information for the specified I2C.
2962 * @param DevAddress Target device address: The device 7 bits address value
2963 * in datasheet must be shifted to the left before calling the interface
2964 * @param MemAddress Internal memory address
2965 * @param MemAddSize Size of internal memory address
2966 * @param pData Pointer to data buffer
2967 * @param Size Amount of data to be sent
2968 * @retval HAL status
2969 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2970 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2971 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2972 {
2973 /* Check the parameters */
2974 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2975
2976 if (hi2c->State == HAL_I2C_STATE_READY)
2977 {
2978 if ((pData == NULL) || (Size == 0U))
2979 {
2980 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2981 return HAL_ERROR;
2982 }
2983
2984 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2985 {
2986 return HAL_BUSY;
2987 }
2988
2989 /* Process Locked */
2990 __HAL_LOCK(hi2c);
2991
2992 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2993 hi2c->Mode = HAL_I2C_MODE_MEM;
2994 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2995
2996 /* Prepare transfer parameters */
2997 hi2c->pBuffPtr = pData;
2998 hi2c->XferCount = Size;
2999 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3000 hi2c->XferISR = I2C_Mem_ISR_IT;
3001 hi2c->Devaddress = DevAddress;
3002
3003 /* If Memory address size is 8Bit */
3004 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3005 {
3006 /* Prefetch Memory Address */
3007 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3008
3009 /* Reset Memaddress content */
3010 hi2c->Memaddress = 0xFFFFFFFFU;
3011 }
3012 /* If Memory address size is 16Bit */
3013 else
3014 {
3015 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3016 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3017
3018 /* Prepare Memaddress buffer for LSB part */
3019 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3020 }
3021 /* Send Slave Address and Memory Address */
3022 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3023
3024 /* Process Unlocked */
3025 __HAL_UNLOCK(hi2c);
3026
3027 /* Note : The I2C interrupts must be enabled after unlocking current process
3028 to avoid the risk of I2C interrupt handle execution before current
3029 process unlock */
3030
3031 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
3032 /* possible to enable all of these */
3033 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3034 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3035 I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
3036
3037 return HAL_OK;
3038 }
3039 else
3040 {
3041 return HAL_BUSY;
3042 }
3043 }
3044
3045 #if defined(HAL_DMA_MODULE_ENABLED)
3046 /**
3047 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
3048 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3049 * the configuration information for the specified I2C.
3050 * @param DevAddress Target device address: The device 7 bits address value
3051 * in datasheet must be shifted to the left before calling the interface
3052 * @param MemAddress Internal memory address
3053 * @param MemAddSize Size of internal memory address
3054 * @param pData Pointer to data buffer
3055 * @param Size Amount of data to be sent
3056 * @retval HAL status
3057 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3058 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3059 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3060 {
3061 HAL_StatusTypeDef dmaxferstatus;
3062
3063 /* Check the parameters */
3064 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3065
3066 if (hi2c->State == HAL_I2C_STATE_READY)
3067 {
3068 if ((pData == NULL) || (Size == 0U))
3069 {
3070 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3071 return HAL_ERROR;
3072 }
3073
3074 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3075 {
3076 return HAL_BUSY;
3077 }
3078
3079 /* Process Locked */
3080 __HAL_LOCK(hi2c);
3081
3082 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3083 hi2c->Mode = HAL_I2C_MODE_MEM;
3084 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3085
3086 /* Prepare transfer parameters */
3087 hi2c->pBuffPtr = pData;
3088 hi2c->XferCount = Size;
3089 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3090 hi2c->XferISR = I2C_Mem_ISR_DMA;
3091 hi2c->Devaddress = DevAddress;
3092
3093 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3094 {
3095 hi2c->XferSize = MAX_NBYTE_SIZE;
3096 }
3097 else
3098 {
3099 hi2c->XferSize = hi2c->XferCount;
3100 }
3101
3102 /* If Memory address size is 8Bit */
3103 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3104 {
3105 /* Prefetch Memory Address */
3106 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3107
3108 /* Reset Memaddress content */
3109 hi2c->Memaddress = 0xFFFFFFFFU;
3110 }
3111 /* If Memory address size is 16Bit */
3112 else
3113 {
3114 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3115 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3116
3117 /* Prepare Memaddress buffer for LSB part */
3118 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3119 }
3120
3121 if (hi2c->hdmatx != NULL)
3122 {
3123 /* Set the I2C DMA transfer complete callback */
3124 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3125
3126 /* Set the DMA error callback */
3127 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3128
3129 /* Set the unused DMA callbacks to NULL */
3130 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3131 hi2c->hdmatx->XferAbortCallback = NULL;
3132
3133 /* Enable the DMA channel */
3134 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3135 {
3136 if (hi2c->hdmatx->LinkedListQueue != NULL)
3137 {
3138 /* Set DMA data size */
3139 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3140
3141 /* Set DMA source address */
3142 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
3143
3144 /* Set DMA destination address */
3145 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
3146 = (uint32_t)&hi2c->Instance->TXDR;
3147
3148 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
3149 }
3150 else
3151 {
3152 /* Update I2C state */
3153 hi2c->State = HAL_I2C_STATE_READY;
3154 hi2c->Mode = HAL_I2C_MODE_NONE;
3155
3156 /* Update I2C error code */
3157 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3158
3159 /* Process Unlocked */
3160 __HAL_UNLOCK(hi2c);
3161
3162 return HAL_ERROR;
3163 }
3164 }
3165 else
3166 {
3167 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3168 hi2c->XferSize);
3169 }
3170 }
3171 else
3172 {
3173 /* Update I2C state */
3174 hi2c->State = HAL_I2C_STATE_READY;
3175 hi2c->Mode = HAL_I2C_MODE_NONE;
3176
3177 /* Update I2C error code */
3178 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3179
3180 /* Process Unlocked */
3181 __HAL_UNLOCK(hi2c);
3182
3183 return HAL_ERROR;
3184 }
3185
3186 if (dmaxferstatus == HAL_OK)
3187 {
3188 /* Send Slave Address and Memory Address */
3189 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
3190
3191 /* Process Unlocked */
3192 __HAL_UNLOCK(hi2c);
3193
3194 /* Note : The I2C interrupts must be enabled after unlocking current process
3195 to avoid the risk of I2C interrupt handle execution before current
3196 process unlock */
3197 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3198 /* possible to enable all of these */
3199 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3200 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3201 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3202 }
3203 else
3204 {
3205 /* Update I2C state */
3206 hi2c->State = HAL_I2C_STATE_READY;
3207 hi2c->Mode = HAL_I2C_MODE_NONE;
3208
3209 /* Update I2C error code */
3210 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3211
3212 /* Process Unlocked */
3213 __HAL_UNLOCK(hi2c);
3214
3215 return HAL_ERROR;
3216 }
3217
3218 return HAL_OK;
3219 }
3220 else
3221 {
3222 return HAL_BUSY;
3223 }
3224 }
3225
3226 /**
3227 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3228 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3229 * the configuration information for the specified I2C.
3230 * @param DevAddress Target device address: The device 7 bits address value
3231 * in datasheet must be shifted to the left before calling the interface
3232 * @param MemAddress Internal memory address
3233 * @param MemAddSize Size of internal memory address
3234 * @param pData Pointer to data buffer
3235 * @param Size Amount of data to be read
3236 * @retval HAL status
3237 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3238 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3239 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3240 {
3241 HAL_StatusTypeDef dmaxferstatus;
3242
3243 /* Check the parameters */
3244 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3245
3246 if (hi2c->State == HAL_I2C_STATE_READY)
3247 {
3248 if ((pData == NULL) || (Size == 0U))
3249 {
3250 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3251 return HAL_ERROR;
3252 }
3253
3254 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3255 {
3256 return HAL_BUSY;
3257 }
3258
3259 /* Process Locked */
3260 __HAL_LOCK(hi2c);
3261
3262 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3263 hi2c->Mode = HAL_I2C_MODE_MEM;
3264 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3265
3266 /* Prepare transfer parameters */
3267 hi2c->pBuffPtr = pData;
3268 hi2c->XferCount = Size;
3269 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3270 hi2c->XferISR = I2C_Mem_ISR_DMA;
3271 hi2c->Devaddress = DevAddress;
3272
3273 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3274 {
3275 hi2c->XferSize = MAX_NBYTE_SIZE;
3276 }
3277 else
3278 {
3279 hi2c->XferSize = hi2c->XferCount;
3280 }
3281
3282 /* If Memory address size is 8Bit */
3283 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3284 {
3285 /* Prefetch Memory Address */
3286 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3287
3288 /* Reset Memaddress content */
3289 hi2c->Memaddress = 0xFFFFFFFFU;
3290 }
3291 /* If Memory address size is 16Bit */
3292 else
3293 {
3294 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3295 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3296
3297 /* Prepare Memaddress buffer for LSB part */
3298 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3299 }
3300
3301 if (hi2c->hdmarx != NULL)
3302 {
3303 /* Set the I2C DMA transfer complete callback */
3304 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3305
3306 /* Set the DMA error callback */
3307 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3308
3309 /* Set the unused DMA callbacks to NULL */
3310 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3311 hi2c->hdmarx->XferAbortCallback = NULL;
3312
3313 /* Enable the DMA channel */
3314 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3315 {
3316 if (hi2c->hdmarx->LinkedListQueue != NULL)
3317 {
3318 /* Set DMA data size */
3319 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3320
3321 /* Set DMA source address */
3322 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
3323 = (uint32_t)&hi2c->Instance->RXDR;
3324
3325 /* Set DMA destination address */
3326 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
3327
3328 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
3329 }
3330 else
3331 {
3332 /* Update I2C state */
3333 hi2c->State = HAL_I2C_STATE_READY;
3334 hi2c->Mode = HAL_I2C_MODE_NONE;
3335
3336 /* Update I2C error code */
3337 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3338
3339 /* Process Unlocked */
3340 __HAL_UNLOCK(hi2c);
3341
3342 return HAL_ERROR;
3343 }
3344 }
3345 else
3346 {
3347 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3348 hi2c->XferSize);
3349 }
3350 }
3351 else
3352 {
3353 /* Update I2C state */
3354 hi2c->State = HAL_I2C_STATE_READY;
3355 hi2c->Mode = HAL_I2C_MODE_NONE;
3356
3357 /* Update I2C error code */
3358 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3359
3360 /* Process Unlocked */
3361 __HAL_UNLOCK(hi2c);
3362
3363 return HAL_ERROR;
3364 }
3365
3366 if (dmaxferstatus == HAL_OK)
3367 {
3368 /* Send Slave Address and Memory Address */
3369 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3370
3371 /* Process Unlocked */
3372 __HAL_UNLOCK(hi2c);
3373
3374 /* Note : The I2C interrupts must be enabled after unlocking current process
3375 to avoid the risk of I2C interrupt handle execution before current
3376 process unlock */
3377 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3378 /* possible to enable all of these */
3379 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3380 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3381 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3382 }
3383 else
3384 {
3385 /* Update I2C state */
3386 hi2c->State = HAL_I2C_STATE_READY;
3387 hi2c->Mode = HAL_I2C_MODE_NONE;
3388
3389 /* Update I2C error code */
3390 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3391
3392 /* Process Unlocked */
3393 __HAL_UNLOCK(hi2c);
3394
3395 return HAL_ERROR;
3396 }
3397
3398 return HAL_OK;
3399 }
3400 else
3401 {
3402 return HAL_BUSY;
3403 }
3404 }
3405 #endif /* HAL_DMA_MODULE_ENABLED */
3406
3407 /**
3408 * @brief Checks if target device is ready for communication.
3409 * @note This function is used with Memory devices
3410 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3411 * the configuration information for the specified I2C.
3412 * @param DevAddress Target device address: The device 7 bits address value
3413 * in datasheet must be shifted to the left before calling the interface
3414 * @param Trials Number of trials
3415 * @param Timeout Timeout duration
3416 * @retval HAL status
3417 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3418 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3419 uint32_t Timeout)
3420 {
3421 uint32_t tickstart;
3422
3423 __IO uint32_t I2C_Trials = 0UL;
3424
3425 FlagStatus tmp1;
3426 FlagStatus tmp2;
3427
3428 if (hi2c->State == HAL_I2C_STATE_READY)
3429 {
3430 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3431 {
3432 return HAL_BUSY;
3433 }
3434
3435 /* Process Locked */
3436 __HAL_LOCK(hi2c);
3437
3438 hi2c->State = HAL_I2C_STATE_BUSY;
3439 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3440
3441 do
3442 {
3443 /* Generate Start */
3444 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3445
3446 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3447 /* Wait until STOPF flag is set or a NACK flag is set*/
3448 tickstart = HAL_GetTick();
3449
3450 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3451 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3452
3453 while ((tmp1 == RESET) && (tmp2 == RESET))
3454 {
3455 if (Timeout != HAL_MAX_DELAY)
3456 {
3457 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3458 {
3459 /* Update I2C state */
3460 hi2c->State = HAL_I2C_STATE_READY;
3461
3462 /* Update I2C error code */
3463 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3464
3465 /* Process Unlocked */
3466 __HAL_UNLOCK(hi2c);
3467
3468 return HAL_ERROR;
3469 }
3470 }
3471
3472 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3473 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3474 }
3475
3476 /* Check if the NACKF flag has not been set */
3477 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3478 {
3479 /* Wait until STOPF flag is reset */
3480 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3481 {
3482 return HAL_ERROR;
3483 }
3484
3485 /* Clear STOP Flag */
3486 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3487
3488 /* Device is ready */
3489 hi2c->State = HAL_I2C_STATE_READY;
3490
3491 /* Process Unlocked */
3492 __HAL_UNLOCK(hi2c);
3493
3494 return HAL_OK;
3495 }
3496 else
3497 {
3498 /* Wait until STOPF flag is reset */
3499 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3500 {
3501 return HAL_ERROR;
3502 }
3503
3504 /* Clear NACK Flag */
3505 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3506
3507 /* Clear STOP Flag, auto generated with autoend*/
3508 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3509 }
3510
3511 /* Check if the maximum allowed number of trials has been reached */
3512 if (I2C_Trials == Trials)
3513 {
3514 /* Generate Stop */
3515 hi2c->Instance->CR2 |= I2C_CR2_STOP;
3516
3517 /* Wait until STOPF flag is reset */
3518 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3519 {
3520 return HAL_ERROR;
3521 }
3522
3523 /* Clear STOP Flag */
3524 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3525 }
3526
3527 /* Increment Trials */
3528 I2C_Trials++;
3529 } while (I2C_Trials < Trials);
3530
3531 /* Update I2C state */
3532 hi2c->State = HAL_I2C_STATE_READY;
3533
3534 /* Update I2C error code */
3535 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3536
3537 /* Process Unlocked */
3538 __HAL_UNLOCK(hi2c);
3539
3540 return HAL_ERROR;
3541 }
3542 else
3543 {
3544 return HAL_BUSY;
3545 }
3546 }
3547
3548 /**
3549 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3550 * @note This interface allow to manage repeated start condition when a direction change during transfer
3551 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3552 * the configuration information for the specified I2C.
3553 * @param DevAddress Target device address: The device 7 bits address value
3554 * in datasheet must be shifted to the left before calling the interface
3555 * @param pData Pointer to data buffer
3556 * @param Size Amount of data to be sent
3557 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3558 * @retval HAL status
3559 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3560 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3561 uint16_t Size, uint32_t XferOptions)
3562 {
3563 uint32_t xfermode;
3564 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3565
3566 /* Check the parameters */
3567 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3568
3569 if (hi2c->State == HAL_I2C_STATE_READY)
3570 {
3571 /* Process Locked */
3572 __HAL_LOCK(hi2c);
3573
3574 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3575 hi2c->Mode = HAL_I2C_MODE_MASTER;
3576 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3577
3578 /* Prepare transfer parameters */
3579 hi2c->pBuffPtr = pData;
3580 hi2c->XferCount = Size;
3581 hi2c->XferOptions = XferOptions;
3582 hi2c->XferISR = I2C_Master_ISR_IT;
3583
3584 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3585 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3586 {
3587 hi2c->XferSize = MAX_NBYTE_SIZE;
3588 xfermode = I2C_RELOAD_MODE;
3589 }
3590 else
3591 {
3592 hi2c->XferSize = hi2c->XferCount;
3593 xfermode = hi2c->XferOptions;
3594 }
3595
3596 /* If transfer direction not change and there is no request to start another frame,
3597 do not generate Restart Condition */
3598 /* Mean Previous state is same as current state */
3599 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3600 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3601 {
3602 xferrequest = I2C_NO_STARTSTOP;
3603 }
3604 else
3605 {
3606 /* Convert OTHER_xxx XferOptions if any */
3607 I2C_ConvertOtherXferOptions(hi2c);
3608
3609 /* Update xfermode accordingly if no reload is necessary */
3610 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3611 {
3612 xfermode = hi2c->XferOptions;
3613 }
3614 }
3615
3616 /* Send Slave Address and set NBYTES to write */
3617 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3618
3619 /* Process Unlocked */
3620 __HAL_UNLOCK(hi2c);
3621
3622 /* Note : The I2C interrupts must be enabled after unlocking current process
3623 to avoid the risk of I2C interrupt handle execution before current
3624 process unlock */
3625 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3626 /* possible to enable all of these */
3627 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3628 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3629 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3630
3631 return HAL_OK;
3632 }
3633 else
3634 {
3635 return HAL_BUSY;
3636 }
3637 }
3638
3639 #if defined(HAL_DMA_MODULE_ENABLED)
3640 /**
3641 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3642 * @note This interface allow to manage repeated start condition when a direction change during transfer
3643 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3644 * the configuration information for the specified I2C.
3645 * @param DevAddress Target device address: The device 7 bits address value
3646 * in datasheet must be shifted to the left before calling the interface
3647 * @param pData Pointer to data buffer
3648 * @param Size Amount of data to be sent
3649 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3650 * @retval HAL status
3651 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3652 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3653 uint16_t Size, uint32_t XferOptions)
3654 {
3655 uint32_t xfermode;
3656 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3657 HAL_StatusTypeDef dmaxferstatus;
3658
3659 /* Check the parameters */
3660 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3661
3662 if (hi2c->State == HAL_I2C_STATE_READY)
3663 {
3664 /* Process Locked */
3665 __HAL_LOCK(hi2c);
3666
3667 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3668 hi2c->Mode = HAL_I2C_MODE_MASTER;
3669 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3670
3671 /* Prepare transfer parameters */
3672 hi2c->pBuffPtr = pData;
3673 hi2c->XferCount = Size;
3674 hi2c->XferOptions = XferOptions;
3675 hi2c->XferISR = I2C_Master_ISR_DMA;
3676
3677 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3678 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3679 {
3680 hi2c->XferSize = MAX_NBYTE_SIZE;
3681 xfermode = I2C_RELOAD_MODE;
3682 }
3683 else
3684 {
3685 hi2c->XferSize = hi2c->XferCount;
3686 xfermode = hi2c->XferOptions;
3687 }
3688
3689 /* If transfer direction not change and there is no request to start another frame,
3690 do not generate Restart Condition */
3691 /* Mean Previous state is same as current state */
3692 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3693 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3694 {
3695 xferrequest = I2C_NO_STARTSTOP;
3696 }
3697 else
3698 {
3699 /* Convert OTHER_xxx XferOptions if any */
3700 I2C_ConvertOtherXferOptions(hi2c);
3701
3702 /* Update xfermode accordingly if no reload is necessary */
3703 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3704 {
3705 xfermode = hi2c->XferOptions;
3706 }
3707 }
3708
3709 if (hi2c->XferSize > 0U)
3710 {
3711 if (hi2c->hdmatx != NULL)
3712 {
3713 /* Set the I2C DMA transfer complete callback */
3714 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3715
3716 /* Set the DMA error callback */
3717 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3718
3719 /* Set the unused DMA callbacks to NULL */
3720 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3721 hi2c->hdmatx->XferAbortCallback = NULL;
3722
3723 /* Enable the DMA channel */
3724 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3725 {
3726 if (hi2c->hdmatx->LinkedListQueue != NULL)
3727 {
3728 /* Set DMA data size */
3729 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3730
3731 /* Set DMA source address */
3732 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
3733
3734 /* Set DMA destination address */
3735 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
3736 = (uint32_t)&hi2c->Instance->TXDR;
3737
3738 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
3739 }
3740 else
3741 {
3742 /* Update I2C state */
3743 hi2c->State = HAL_I2C_STATE_READY;
3744 hi2c->Mode = HAL_I2C_MODE_NONE;
3745
3746 /* Update I2C error code */
3747 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3748
3749 /* Process Unlocked */
3750 __HAL_UNLOCK(hi2c);
3751
3752 return HAL_ERROR;
3753 }
3754 }
3755 else
3756 {
3757 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3758 hi2c->XferSize);
3759 }
3760 }
3761 else
3762 {
3763 /* Update I2C state */
3764 hi2c->State = HAL_I2C_STATE_READY;
3765 hi2c->Mode = HAL_I2C_MODE_NONE;
3766
3767 /* Update I2C error code */
3768 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3769
3770 /* Process Unlocked */
3771 __HAL_UNLOCK(hi2c);
3772
3773 return HAL_ERROR;
3774 }
3775
3776 if (dmaxferstatus == HAL_OK)
3777 {
3778 /* Send Slave Address and set NBYTES to write */
3779 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3780
3781 /* Update XferCount value */
3782 hi2c->XferCount -= hi2c->XferSize;
3783
3784 /* Process Unlocked */
3785 __HAL_UNLOCK(hi2c);
3786
3787 /* Note : The I2C interrupts must be enabled after unlocking current process
3788 to avoid the risk of I2C interrupt handle execution before current
3789 process unlock */
3790 /* Enable ERR and NACK interrupts */
3791 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3792
3793 /* Enable DMA Request */
3794 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3795 }
3796 else
3797 {
3798 /* Update I2C state */
3799 hi2c->State = HAL_I2C_STATE_READY;
3800 hi2c->Mode = HAL_I2C_MODE_NONE;
3801
3802 /* Update I2C error code */
3803 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3804
3805 /* Process Unlocked */
3806 __HAL_UNLOCK(hi2c);
3807
3808 return HAL_ERROR;
3809 }
3810 }
3811 else
3812 {
3813 /* Update Transfer ISR function pointer */
3814 hi2c->XferISR = I2C_Master_ISR_IT;
3815
3816 /* Send Slave Address */
3817 /* Set NBYTES to write and generate START condition */
3818 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3819 I2C_GENERATE_START_WRITE);
3820
3821 /* Process Unlocked */
3822 __HAL_UNLOCK(hi2c);
3823
3824 /* Note : The I2C interrupts must be enabled after unlocking current process
3825 to avoid the risk of I2C interrupt handle execution before current
3826 process unlock */
3827 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3828 /* possible to enable all of these */
3829 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3830 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3831 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3832 }
3833
3834 return HAL_OK;
3835 }
3836 else
3837 {
3838 return HAL_BUSY;
3839 }
3840 }
3841 #endif /* HAL_DMA_MODULE_ENABLED */
3842
3843 /**
3844 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3845 * @note This interface allow to manage repeated start condition when a direction change during transfer
3846 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3847 * the configuration information for the specified I2C.
3848 * @param DevAddress Target device address: The device 7 bits address value
3849 * in datasheet must be shifted to the left before calling the interface
3850 * @param pData Pointer to data buffer
3851 * @param Size Amount of data to be sent
3852 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3853 * @retval HAL status
3854 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3855 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3856 uint16_t Size, uint32_t XferOptions)
3857 {
3858 uint32_t xfermode;
3859 uint32_t xferrequest = I2C_GENERATE_START_READ;
3860
3861 /* Check the parameters */
3862 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3863
3864 if (hi2c->State == HAL_I2C_STATE_READY)
3865 {
3866 /* Process Locked */
3867 __HAL_LOCK(hi2c);
3868
3869 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3870 hi2c->Mode = HAL_I2C_MODE_MASTER;
3871 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3872
3873 /* Prepare transfer parameters */
3874 hi2c->pBuffPtr = pData;
3875 hi2c->XferCount = Size;
3876 hi2c->XferOptions = XferOptions;
3877 hi2c->XferISR = I2C_Master_ISR_IT;
3878
3879 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3880 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3881 {
3882 hi2c->XferSize = MAX_NBYTE_SIZE;
3883 xfermode = I2C_RELOAD_MODE;
3884 }
3885 else
3886 {
3887 hi2c->XferSize = hi2c->XferCount;
3888 xfermode = hi2c->XferOptions;
3889 }
3890
3891 /* If transfer direction not change and there is no request to start another frame,
3892 do not generate Restart Condition */
3893 /* Mean Previous state is same as current state */
3894 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3895 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3896 {
3897 xferrequest = I2C_NO_STARTSTOP;
3898 }
3899 else
3900 {
3901 /* Convert OTHER_xxx XferOptions if any */
3902 I2C_ConvertOtherXferOptions(hi2c);
3903
3904 /* Update xfermode accordingly if no reload is necessary */
3905 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3906 {
3907 xfermode = hi2c->XferOptions;
3908 }
3909 }
3910
3911 /* Send Slave Address and set NBYTES to read */
3912 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3913
3914 /* Process Unlocked */
3915 __HAL_UNLOCK(hi2c);
3916
3917 /* Note : The I2C interrupts must be enabled after unlocking current process
3918 to avoid the risk of I2C interrupt handle execution before current
3919 process unlock */
3920 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3921
3922 return HAL_OK;
3923 }
3924 else
3925 {
3926 return HAL_BUSY;
3927 }
3928 }
3929
3930 #if defined(HAL_DMA_MODULE_ENABLED)
3931 /**
3932 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3933 * @note This interface allow to manage repeated start condition when a direction change during transfer
3934 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3935 * the configuration information for the specified I2C.
3936 * @param DevAddress Target device address: The device 7 bits address value
3937 * in datasheet must be shifted to the left before calling the interface
3938 * @param pData Pointer to data buffer
3939 * @param Size Amount of data to be sent
3940 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3941 * @retval HAL status
3942 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3943 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3944 uint16_t Size, uint32_t XferOptions)
3945 {
3946 uint32_t xfermode;
3947 uint32_t xferrequest = I2C_GENERATE_START_READ;
3948 HAL_StatusTypeDef dmaxferstatus;
3949
3950 /* Check the parameters */
3951 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3952
3953 if (hi2c->State == HAL_I2C_STATE_READY)
3954 {
3955 /* Process Locked */
3956 __HAL_LOCK(hi2c);
3957
3958 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3959 hi2c->Mode = HAL_I2C_MODE_MASTER;
3960 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3961
3962 /* Prepare transfer parameters */
3963 hi2c->pBuffPtr = pData;
3964 hi2c->XferCount = Size;
3965 hi2c->XferOptions = XferOptions;
3966 hi2c->XferISR = I2C_Master_ISR_DMA;
3967
3968 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3969 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3970 {
3971 hi2c->XferSize = MAX_NBYTE_SIZE;
3972 xfermode = I2C_RELOAD_MODE;
3973 }
3974 else
3975 {
3976 hi2c->XferSize = hi2c->XferCount;
3977 xfermode = hi2c->XferOptions;
3978 }
3979
3980 /* If transfer direction not change and there is no request to start another frame,
3981 do not generate Restart Condition */
3982 /* Mean Previous state is same as current state */
3983 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3984 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3985 {
3986 xferrequest = I2C_NO_STARTSTOP;
3987 }
3988 else
3989 {
3990 /* Convert OTHER_xxx XferOptions if any */
3991 I2C_ConvertOtherXferOptions(hi2c);
3992
3993 /* Update xfermode accordingly if no reload is necessary */
3994 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3995 {
3996 xfermode = hi2c->XferOptions;
3997 }
3998 }
3999
4000 if (hi2c->XferSize > 0U)
4001 {
4002 if (hi2c->hdmarx != NULL)
4003 {
4004 /* Set the I2C DMA transfer complete callback */
4005 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
4006
4007 /* Set the DMA error callback */
4008 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4009
4010 /* Set the unused DMA callbacks to NULL */
4011 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4012 hi2c->hdmarx->XferAbortCallback = NULL;
4013
4014 /* Enable the DMA channel */
4015 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4016 {
4017 if (hi2c->hdmarx->LinkedListQueue != NULL)
4018 {
4019 /* Set DMA data size */
4020 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4021
4022 /* Set DMA source address */
4023 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
4024 = (uint32_t)&hi2c->Instance->RXDR;
4025
4026 /* Set DMA destination address */
4027 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
4028
4029 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
4030 }
4031 else
4032 {
4033 hi2c->State = HAL_I2C_STATE_READY;
4034 hi2c->Mode = HAL_I2C_MODE_NONE;
4035
4036 /* Update I2C error code */
4037 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4038
4039 /* Process Unlocked */
4040 __HAL_UNLOCK(hi2c);
4041
4042 return HAL_ERROR;
4043 }
4044 }
4045 else
4046 {
4047 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
4048 hi2c->XferSize);
4049 }
4050 }
4051 else
4052 {
4053 /* Update I2C state */
4054 hi2c->State = HAL_I2C_STATE_READY;
4055 hi2c->Mode = HAL_I2C_MODE_NONE;
4056
4057 /* Update I2C error code */
4058 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4059
4060 /* Process Unlocked */
4061 __HAL_UNLOCK(hi2c);
4062
4063 return HAL_ERROR;
4064 }
4065
4066 if (dmaxferstatus == HAL_OK)
4067 {
4068 /* Send Slave Address and set NBYTES to read */
4069 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
4070
4071 /* Update XferCount value */
4072 hi2c->XferCount -= hi2c->XferSize;
4073
4074 /* Process Unlocked */
4075 __HAL_UNLOCK(hi2c);
4076
4077 /* Note : The I2C interrupts must be enabled after unlocking current process
4078 to avoid the risk of I2C interrupt handle execution before current
4079 process unlock */
4080 /* Enable ERR and NACK interrupts */
4081 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
4082
4083 /* Enable DMA Request */
4084 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4085 }
4086 else
4087 {
4088 /* Update I2C state */
4089 hi2c->State = HAL_I2C_STATE_READY;
4090 hi2c->Mode = HAL_I2C_MODE_NONE;
4091
4092 /* Update I2C error code */
4093 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4094
4095 /* Process Unlocked */
4096 __HAL_UNLOCK(hi2c);
4097
4098 return HAL_ERROR;
4099 }
4100 }
4101 else
4102 {
4103 /* Update Transfer ISR function pointer */
4104 hi2c->XferISR = I2C_Master_ISR_IT;
4105
4106 /* Send Slave Address */
4107 /* Set NBYTES to read and generate START condition */
4108 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
4109 I2C_GENERATE_START_READ);
4110
4111 /* Process Unlocked */
4112 __HAL_UNLOCK(hi2c);
4113
4114 /* Note : The I2C interrupts must be enabled after unlocking current process
4115 to avoid the risk of I2C interrupt handle execution before current
4116 process unlock */
4117 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
4118 /* possible to enable all of these */
4119 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
4120 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
4121 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
4122 }
4123
4124 return HAL_OK;
4125 }
4126 else
4127 {
4128 return HAL_BUSY;
4129 }
4130 }
4131 #endif /* HAL_DMA_MODULE_ENABLED */
4132
4133 /**
4134 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4135 * @note This interface allow to manage repeated start condition when a direction change during transfer
4136 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4137 * the configuration information for the specified I2C.
4138 * @param pData Pointer to data buffer
4139 * @param Size Amount of data to be sent
4140 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4141 * @retval HAL status
4142 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4143 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4144 uint32_t XferOptions)
4145 {
4146 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4147 FlagStatus tmp;
4148
4149 /* Check the parameters */
4150 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4151
4152 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4153 {
4154 if ((pData == NULL) || (Size == 0U))
4155 {
4156 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4157 return HAL_ERROR;
4158 }
4159
4160 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4161 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4162
4163 /* Process Locked */
4164 __HAL_LOCK(hi2c);
4165
4166 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4167 /* and then toggle the HAL slave RX state to TX state */
4168 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4169 {
4170 /* Disable associated Interrupts */
4171 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4172
4173 #if defined(HAL_DMA_MODULE_ENABLED)
4174 /* Abort DMA Xfer if any */
4175 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4176 {
4177 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4178
4179 if (hi2c->hdmarx != NULL)
4180 {
4181 /* Set the I2C DMA Abort callback :
4182 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4183 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4184
4185 /* Abort DMA RX */
4186 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4187 {
4188 /* Call Directly XferAbortCallback function in case of error */
4189 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4190 }
4191 }
4192 }
4193 #endif /* HAL_DMA_MODULE_ENABLED */
4194 }
4195
4196 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4197 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4198 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4199
4200 /* Enable Address Acknowledge */
4201 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4202
4203 /* Prepare transfer parameters */
4204 hi2c->pBuffPtr = pData;
4205 hi2c->XferCount = Size;
4206 hi2c->XferSize = hi2c->XferCount;
4207 hi2c->XferOptions = XferOptions;
4208 hi2c->XferISR = I2C_Slave_ISR_IT;
4209
4210 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4211 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4212 {
4213 /* Clear ADDR flag after prepare the transfer parameters */
4214 /* This action will generate an acknowledge to the Master */
4215 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4216 }
4217
4218 /* Process Unlocked */
4219 __HAL_UNLOCK(hi2c);
4220
4221 /* Note : The I2C interrupts must be enabled after unlocking current process
4222 to avoid the risk of I2C interrupt handle execution before current
4223 process unlock */
4224 /* REnable ADDR interrupt */
4225 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
4226
4227 return HAL_OK;
4228 }
4229 else
4230 {
4231 return HAL_ERROR;
4232 }
4233 }
4234
4235 #if defined(HAL_DMA_MODULE_ENABLED)
4236 /**
4237 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
4238 * @note This interface allow to manage repeated start condition when a direction change during transfer
4239 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4240 * the configuration information for the specified I2C.
4241 * @param pData Pointer to data buffer
4242 * @param Size Amount of data to be sent
4243 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4244 * @retval HAL status
4245 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4246 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4247 uint32_t XferOptions)
4248 {
4249 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4250 FlagStatus tmp;
4251 HAL_StatusTypeDef dmaxferstatus;
4252
4253 /* Check the parameters */
4254 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4255
4256 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4257 {
4258 if ((pData == NULL) || (Size == 0U))
4259 {
4260 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4261 return HAL_ERROR;
4262 }
4263
4264 /* Process Locked */
4265 __HAL_LOCK(hi2c);
4266
4267 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4268 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4269
4270 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4271 /* and then toggle the HAL slave RX state to TX state */
4272 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4273 {
4274 /* Disable associated Interrupts */
4275 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4276
4277 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4278 {
4279 /* Abort DMA Xfer if any */
4280 if (hi2c->hdmarx != NULL)
4281 {
4282 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4283
4284 /* Set the I2C DMA Abort callback :
4285 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4286 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4287
4288 /* Abort DMA RX */
4289 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4290 {
4291 /* Call Directly XferAbortCallback function in case of error */
4292 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4293 }
4294 }
4295 }
4296 }
4297 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4298 {
4299 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4300 {
4301 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4302
4303 /* Abort DMA Xfer if any */
4304 if (hi2c->hdmatx != NULL)
4305 {
4306 /* Set the I2C DMA Abort callback :
4307 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4308 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4309
4310 /* Abort DMA TX */
4311 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4312 {
4313 /* Call Directly XferAbortCallback function in case of error */
4314 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4315 }
4316 }
4317 }
4318 }
4319 else
4320 {
4321 /* Nothing to do */
4322 }
4323
4324 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4325 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4326 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4327
4328 /* Enable Address Acknowledge */
4329 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4330
4331 /* Prepare transfer parameters */
4332 hi2c->pBuffPtr = pData;
4333 hi2c->XferCount = Size;
4334 hi2c->XferSize = hi2c->XferCount;
4335 hi2c->XferOptions = XferOptions;
4336 hi2c->XferISR = I2C_Slave_ISR_DMA;
4337
4338 if (hi2c->hdmatx != NULL)
4339 {
4340 /* Set the I2C DMA transfer complete callback */
4341 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
4342
4343 /* Set the DMA error callback */
4344 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4345
4346 /* Set the unused DMA callbacks to NULL */
4347 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4348 hi2c->hdmatx->XferAbortCallback = NULL;
4349
4350 /* Enable the DMA channel */
4351 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4352 {
4353 if (hi2c->hdmatx->LinkedListQueue != NULL)
4354 {
4355 /* Set DMA data size */
4356 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4357
4358 /* Set DMA source address */
4359 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
4360
4361 /* Set DMA destination address */
4362 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
4363 = (uint32_t)&hi2c->Instance->TXDR;
4364
4365 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
4366 }
4367 else
4368 {
4369 /* Update I2C state */
4370 hi2c->State = HAL_I2C_STATE_LISTEN;
4371 hi2c->Mode = HAL_I2C_MODE_NONE;
4372
4373 /* Update I2C error code */
4374 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4375
4376 /* Process Unlocked */
4377 __HAL_UNLOCK(hi2c);
4378
4379 return HAL_ERROR;
4380 }
4381 }
4382 else
4383 {
4384 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
4385 hi2c->XferSize);
4386 }
4387 }
4388 else
4389 {
4390 /* Update I2C state */
4391 hi2c->State = HAL_I2C_STATE_LISTEN;
4392 hi2c->Mode = HAL_I2C_MODE_NONE;
4393
4394 /* Update I2C error code */
4395 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4396
4397 /* Process Unlocked */
4398 __HAL_UNLOCK(hi2c);
4399
4400 return HAL_ERROR;
4401 }
4402
4403 if (dmaxferstatus == HAL_OK)
4404 {
4405 /* Update XferCount value */
4406 hi2c->XferCount -= hi2c->XferSize;
4407
4408 /* Reset XferSize */
4409 hi2c->XferSize = 0;
4410 }
4411 else
4412 {
4413 /* Update I2C state */
4414 hi2c->State = HAL_I2C_STATE_LISTEN;
4415 hi2c->Mode = HAL_I2C_MODE_NONE;
4416
4417 /* Update I2C error code */
4418 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4419
4420 /* Process Unlocked */
4421 __HAL_UNLOCK(hi2c);
4422
4423 return HAL_ERROR;
4424 }
4425
4426 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4427 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4428 {
4429 /* Clear ADDR flag after prepare the transfer parameters */
4430 /* This action will generate an acknowledge to the Master */
4431 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4432 }
4433
4434 /* Process Unlocked */
4435 __HAL_UNLOCK(hi2c);
4436
4437 /* Enable DMA Request */
4438 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4439
4440 /* Note : The I2C interrupts must be enabled after unlocking current process
4441 to avoid the risk of I2C interrupt handle execution before current
4442 process unlock */
4443 /* Enable ERR, STOP, NACK, ADDR interrupts */
4444 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4445
4446 return HAL_OK;
4447 }
4448 else
4449 {
4450 return HAL_ERROR;
4451 }
4452 }
4453 #endif /* HAL_DMA_MODULE_ENABLED */
4454
4455 /**
4456 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4457 * @note This interface allow to manage repeated start condition when a direction change during transfer
4458 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4459 * the configuration information for the specified I2C.
4460 * @param pData Pointer to data buffer
4461 * @param Size Amount of data to be sent
4462 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4463 * @retval HAL status
4464 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4465 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4466 uint32_t XferOptions)
4467 {
4468 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4469 FlagStatus tmp;
4470
4471 /* Check the parameters */
4472 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4473
4474 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4475 {
4476 if ((pData == NULL) || (Size == 0U))
4477 {
4478 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4479 return HAL_ERROR;
4480 }
4481
4482 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4483 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4484
4485 /* Process Locked */
4486 __HAL_LOCK(hi2c);
4487
4488 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4489 /* and then toggle the HAL slave TX state to RX state */
4490 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4491 {
4492 /* Disable associated Interrupts */
4493 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4494
4495 #if defined(HAL_DMA_MODULE_ENABLED)
4496 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4497 {
4498 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4499
4500 /* Abort DMA Xfer if any */
4501 if (hi2c->hdmatx != NULL)
4502 {
4503 /* Set the I2C DMA Abort callback :
4504 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4505 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4506
4507 /* Abort DMA TX */
4508 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4509 {
4510 /* Call Directly XferAbortCallback function in case of error */
4511 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4512 }
4513 }
4514 }
4515 #endif /* HAL_DMA_MODULE_ENABLED */
4516 }
4517
4518 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4519 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4520 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4521
4522 /* Enable Address Acknowledge */
4523 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4524
4525 /* Prepare transfer parameters */
4526 hi2c->pBuffPtr = pData;
4527 hi2c->XferCount = Size;
4528 hi2c->XferSize = hi2c->XferCount;
4529 hi2c->XferOptions = XferOptions;
4530 hi2c->XferISR = I2C_Slave_ISR_IT;
4531
4532 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4533 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4534 {
4535 /* Clear ADDR flag after prepare the transfer parameters */
4536 /* This action will generate an acknowledge to the Master */
4537 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4538 }
4539
4540 /* Process Unlocked */
4541 __HAL_UNLOCK(hi2c);
4542
4543 /* Note : The I2C interrupts must be enabled after unlocking current process
4544 to avoid the risk of I2C interrupt handle execution before current
4545 process unlock */
4546 /* REnable ADDR interrupt */
4547 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4548
4549 return HAL_OK;
4550 }
4551 else
4552 {
4553 return HAL_ERROR;
4554 }
4555 }
4556
4557 #if defined(HAL_DMA_MODULE_ENABLED)
4558 /**
4559 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4560 * @note This interface allow to manage repeated start condition when a direction change during transfer
4561 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4562 * the configuration information for the specified I2C.
4563 * @param pData Pointer to data buffer
4564 * @param Size Amount of data to be sent
4565 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4566 * @retval HAL status
4567 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4568 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4569 uint32_t XferOptions)
4570 {
4571 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4572 FlagStatus tmp;
4573 HAL_StatusTypeDef dmaxferstatus;
4574
4575 /* Check the parameters */
4576 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4577
4578 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4579 {
4580 if ((pData == NULL) || (Size == 0U))
4581 {
4582 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4583 return HAL_ERROR;
4584 }
4585
4586 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4587 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4588
4589 /* Process Locked */
4590 __HAL_LOCK(hi2c);
4591
4592 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4593 /* and then toggle the HAL slave TX state to RX state */
4594 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4595 {
4596 /* Disable associated Interrupts */
4597 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4598
4599 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4600 {
4601 /* Abort DMA Xfer if any */
4602 if (hi2c->hdmatx != NULL)
4603 {
4604 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4605
4606 /* Set the I2C DMA Abort callback :
4607 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4608 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4609
4610 /* Abort DMA TX */
4611 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4612 {
4613 /* Call Directly XferAbortCallback function in case of error */
4614 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4615 }
4616 }
4617 }
4618 }
4619 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4620 {
4621 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4622 {
4623 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4624
4625 /* Abort DMA Xfer if any */
4626 if (hi2c->hdmarx != NULL)
4627 {
4628 /* Set the I2C DMA Abort callback :
4629 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4630 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4631
4632 /* Abort DMA RX */
4633 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4634 {
4635 /* Call Directly XferAbortCallback function in case of error */
4636 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4637 }
4638 }
4639 }
4640 }
4641 else
4642 {
4643 /* Nothing to do */
4644 }
4645
4646 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4647 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4648 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4649
4650 /* Enable Address Acknowledge */
4651 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4652
4653 /* Prepare transfer parameters */
4654 hi2c->pBuffPtr = pData;
4655 hi2c->XferCount = Size;
4656 hi2c->XferSize = hi2c->XferCount;
4657 hi2c->XferOptions = XferOptions;
4658 hi2c->XferISR = I2C_Slave_ISR_DMA;
4659
4660 if (hi2c->hdmarx != NULL)
4661 {
4662 /* Set the I2C DMA transfer complete callback */
4663 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4664
4665 /* Set the DMA error callback */
4666 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4667
4668 /* Set the unused DMA callbacks to NULL */
4669 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4670 hi2c->hdmarx->XferAbortCallback = NULL;
4671
4672 /* Enable the DMA channel */
4673 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4674 {
4675 if (hi2c->hdmarx->LinkedListQueue != NULL)
4676 {
4677 /* Set DMA data size */
4678 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4679
4680 /* Set DMA source address */
4681 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
4682 = (uint32_t)&hi2c->Instance->RXDR;
4683
4684 /* Set DMA destination address */
4685 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
4686
4687 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
4688 }
4689 else
4690 {
4691 /* Update I2C state */
4692 hi2c->State = HAL_I2C_STATE_LISTEN;
4693 hi2c->Mode = HAL_I2C_MODE_NONE;
4694
4695 /* Update I2C error code */
4696 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4697
4698 /* Process Unlocked */
4699 __HAL_UNLOCK(hi2c);
4700
4701 return HAL_ERROR;
4702 }
4703 }
4704 else
4705 {
4706 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
4707 hi2c->XferSize);
4708 }
4709 }
4710 else
4711 {
4712 /* Update I2C state */
4713 hi2c->State = HAL_I2C_STATE_LISTEN;
4714 hi2c->Mode = HAL_I2C_MODE_NONE;
4715
4716 /* Update I2C error code */
4717 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4718
4719 /* Process Unlocked */
4720 __HAL_UNLOCK(hi2c);
4721
4722 return HAL_ERROR;
4723 }
4724
4725 if (dmaxferstatus == HAL_OK)
4726 {
4727 /* Update XferCount value */
4728 hi2c->XferCount -= hi2c->XferSize;
4729
4730 /* Reset XferSize */
4731 hi2c->XferSize = 0;
4732 }
4733 else
4734 {
4735 /* Update I2C state */
4736 hi2c->State = HAL_I2C_STATE_LISTEN;
4737 hi2c->Mode = HAL_I2C_MODE_NONE;
4738
4739 /* Update I2C error code */
4740 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4741
4742 /* Process Unlocked */
4743 __HAL_UNLOCK(hi2c);
4744
4745 return HAL_ERROR;
4746 }
4747
4748 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4749 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4750 {
4751 /* Clear ADDR flag after prepare the transfer parameters */
4752 /* This action will generate an acknowledge to the Master */
4753 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4754 }
4755
4756 /* Process Unlocked */
4757 __HAL_UNLOCK(hi2c);
4758
4759 /* Enable DMA Request */
4760 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4761
4762 /* Note : The I2C interrupts must be enabled after unlocking current process
4763 to avoid the risk of I2C interrupt handle execution before current
4764 process unlock */
4765 /* REnable ADDR interrupt */
4766 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4767
4768 return HAL_OK;
4769 }
4770 else
4771 {
4772 return HAL_ERROR;
4773 }
4774 }
4775 #endif /* HAL_DMA_MODULE_ENABLED */
4776
4777 /**
4778 * @brief Enable the Address listen mode with Interrupt.
4779 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4780 * the configuration information for the specified I2C.
4781 * @retval HAL status
4782 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4783 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4784 {
4785 if (hi2c->State == HAL_I2C_STATE_READY)
4786 {
4787 hi2c->State = HAL_I2C_STATE_LISTEN;
4788 hi2c->XferISR = I2C_Slave_ISR_IT;
4789
4790 /* Enable the Address Match interrupt */
4791 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4792
4793 return HAL_OK;
4794 }
4795 else
4796 {
4797 return HAL_BUSY;
4798 }
4799 }
4800
4801 /**
4802 * @brief Disable the Address listen mode with Interrupt.
4803 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4804 * the configuration information for the specified I2C
4805 * @retval HAL status
4806 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4807 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4808 {
4809 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4810 uint32_t tmp;
4811
4812 /* Disable Address listen mode only if a transfer is not ongoing */
4813 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4814 {
4815 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4816 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4817 hi2c->State = HAL_I2C_STATE_READY;
4818 hi2c->Mode = HAL_I2C_MODE_NONE;
4819 hi2c->XferISR = NULL;
4820
4821 /* Disable the Address Match interrupt */
4822 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4823
4824 return HAL_OK;
4825 }
4826 else
4827 {
4828 return HAL_BUSY;
4829 }
4830 }
4831
4832 /**
4833 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4834 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4835 * the configuration information for the specified I2C.
4836 * @param DevAddress Target device address: The device 7 bits address value
4837 * in datasheet must be shifted to the left before calling the interface
4838 * @retval HAL status
4839 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4840 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4841 {
4842 if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4843 {
4844 /* Process Locked */
4845 __HAL_LOCK(hi2c);
4846
4847 /* Disable Interrupts and Store Previous state */
4848 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4849 {
4850 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4851 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4852 }
4853 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4854 {
4855 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4856 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4857 }
4858 else
4859 {
4860 /* Do nothing */
4861 }
4862
4863 /* Set State at HAL_I2C_STATE_ABORT */
4864 hi2c->State = HAL_I2C_STATE_ABORT;
4865
4866 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4867 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4868 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4869
4870 /* Process Unlocked */
4871 __HAL_UNLOCK(hi2c);
4872
4873 /* Note : The I2C interrupts must be enabled after unlocking current process
4874 to avoid the risk of I2C interrupt handle execution before current
4875 process unlock */
4876 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4877
4878 return HAL_OK;
4879 }
4880 else
4881 {
4882 /* Wrong usage of abort function */
4883 /* This function should be used only in case of abort monitored by master device */
4884 return HAL_ERROR;
4885 }
4886 }
4887
4888 /**
4889 * @}
4890 */
4891
4892 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4893 * @{
4894 */
4895
4896 /**
4897 * @brief This function handles I2C event interrupt request.
4898 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4899 * the configuration information for the specified I2C.
4900 * @retval None
4901 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4902 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4903 {
4904 /* Get current IT Flags and IT sources value */
4905 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4906 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4907
4908 /* I2C events treatment -------------------------------------*/
4909 if (hi2c->XferISR != NULL)
4910 {
4911 hi2c->XferISR(hi2c, itflags, itsources);
4912 }
4913 }
4914
4915 /**
4916 * @brief This function handles I2C error interrupt request.
4917 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4918 * the configuration information for the specified I2C.
4919 * @retval None
4920 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4921 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4922 {
4923 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4924 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4925 uint32_t tmperror;
4926
4927 /* I2C Bus error interrupt occurred ------------------------------------*/
4928 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4929 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4930 {
4931 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4932
4933 /* Clear BERR flag */
4934 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4935 }
4936
4937 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4938 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4939 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4940 {
4941 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4942
4943 /* Clear OVR flag */
4944 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4945 }
4946
4947 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4948 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4949 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4950 {
4951 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4952
4953 /* Clear ARLO flag */
4954 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4955 }
4956
4957 /* Store current volatile hi2c->ErrorCode, misra rule */
4958 tmperror = hi2c->ErrorCode;
4959
4960 /* Call the Error Callback in case of Error detected */
4961 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4962 {
4963 I2C_ITError(hi2c, tmperror);
4964 }
4965 }
4966
4967 /**
4968 * @brief Master Tx Transfer completed callback.
4969 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4970 * the configuration information for the specified I2C.
4971 * @retval None
4972 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4973 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4974 {
4975 /* Prevent unused argument(s) compilation warning */
4976 UNUSED(hi2c);
4977
4978 /* NOTE : This function should not be modified, when the callback is needed,
4979 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4980 */
4981 }
4982
4983 /**
4984 * @brief Master Rx Transfer completed callback.
4985 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4986 * the configuration information for the specified I2C.
4987 * @retval None
4988 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4989 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4990 {
4991 /* Prevent unused argument(s) compilation warning */
4992 UNUSED(hi2c);
4993
4994 /* NOTE : This function should not be modified, when the callback is needed,
4995 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4996 */
4997 }
4998
4999 /** @brief Slave Tx Transfer completed callback.
5000 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5001 * the configuration information for the specified I2C.
5002 * @retval None
5003 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)5004 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
5005 {
5006 /* Prevent unused argument(s) compilation warning */
5007 UNUSED(hi2c);
5008
5009 /* NOTE : This function should not be modified, when the callback is needed,
5010 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
5011 */
5012 }
5013
5014 /**
5015 * @brief Slave Rx Transfer completed callback.
5016 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5017 * the configuration information for the specified I2C.
5018 * @retval None
5019 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)5020 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
5021 {
5022 /* Prevent unused argument(s) compilation warning */
5023 UNUSED(hi2c);
5024
5025 /* NOTE : This function should not be modified, when the callback is needed,
5026 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
5027 */
5028 }
5029
5030 /**
5031 * @brief Slave Address Match callback.
5032 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5033 * the configuration information for the specified I2C.
5034 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
5035 * @param AddrMatchCode Address Match Code
5036 * @retval None
5037 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)5038 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
5039 {
5040 /* Prevent unused argument(s) compilation warning */
5041 UNUSED(hi2c);
5042 UNUSED(TransferDirection);
5043 UNUSED(AddrMatchCode);
5044
5045 /* NOTE : This function should not be modified, when the callback is needed,
5046 the HAL_I2C_AddrCallback() could be implemented in the user file
5047 */
5048 }
5049
5050 /**
5051 * @brief Listen Complete callback.
5052 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5053 * the configuration information for the specified I2C.
5054 * @retval None
5055 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)5056 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
5057 {
5058 /* Prevent unused argument(s) compilation warning */
5059 UNUSED(hi2c);
5060
5061 /* NOTE : This function should not be modified, when the callback is needed,
5062 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
5063 */
5064 }
5065
5066 /**
5067 * @brief Memory Tx Transfer completed callback.
5068 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5069 * the configuration information for the specified I2C.
5070 * @retval None
5071 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)5072 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
5073 {
5074 /* Prevent unused argument(s) compilation warning */
5075 UNUSED(hi2c);
5076
5077 /* NOTE : This function should not be modified, when the callback is needed,
5078 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
5079 */
5080 }
5081
5082 /**
5083 * @brief Memory Rx Transfer completed callback.
5084 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5085 * the configuration information for the specified I2C.
5086 * @retval None
5087 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)5088 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
5089 {
5090 /* Prevent unused argument(s) compilation warning */
5091 UNUSED(hi2c);
5092
5093 /* NOTE : This function should not be modified, when the callback is needed,
5094 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
5095 */
5096 }
5097
5098 /**
5099 * @brief I2C error callback.
5100 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5101 * the configuration information for the specified I2C.
5102 * @retval None
5103 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)5104 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
5105 {
5106 /* Prevent unused argument(s) compilation warning */
5107 UNUSED(hi2c);
5108
5109 /* NOTE : This function should not be modified, when the callback is needed,
5110 the HAL_I2C_ErrorCallback could be implemented in the user file
5111 */
5112 }
5113
5114 /**
5115 * @brief I2C abort callback.
5116 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5117 * the configuration information for the specified I2C.
5118 * @retval None
5119 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)5120 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
5121 {
5122 /* Prevent unused argument(s) compilation warning */
5123 UNUSED(hi2c);
5124
5125 /* NOTE : This function should not be modified, when the callback is needed,
5126 the HAL_I2C_AbortCpltCallback could be implemented in the user file
5127 */
5128 }
5129
5130 /**
5131 * @}
5132 */
5133
5134 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
5135 * @brief Peripheral State, Mode and Error functions
5136 *
5137 @verbatim
5138 ===============================================================================
5139 ##### Peripheral State, Mode and Error functions #####
5140 ===============================================================================
5141 [..]
5142 This subsection permit to get in run-time the status of the peripheral
5143 and the data flow.
5144
5145 @endverbatim
5146 * @{
5147 */
5148
5149 /**
5150 * @brief Return the I2C handle state.
5151 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5152 * the configuration information for the specified I2C.
5153 * @retval HAL state
5154 */
HAL_I2C_GetState(const I2C_HandleTypeDef * hi2c)5155 HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
5156 {
5157 /* Return I2C handle state */
5158 return hi2c->State;
5159 }
5160
5161 /**
5162 * @brief Returns the I2C Master, Slave, Memory or no mode.
5163 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5164 * the configuration information for I2C module
5165 * @retval HAL mode
5166 */
HAL_I2C_GetMode(const I2C_HandleTypeDef * hi2c)5167 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
5168 {
5169 return hi2c->Mode;
5170 }
5171
5172 /**
5173 * @brief Return the I2C error code.
5174 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5175 * the configuration information for the specified I2C.
5176 * @retval I2C Error Code
5177 */
HAL_I2C_GetError(const I2C_HandleTypeDef * hi2c)5178 uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
5179 {
5180 return hi2c->ErrorCode;
5181 }
5182
5183 /**
5184 * @}
5185 */
5186
5187 /**
5188 * @}
5189 */
5190
5191 /** @addtogroup I2C_Private_Functions
5192 * @{
5193 */
5194
5195 /**
5196 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
5197 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5198 * the configuration information for the specified I2C.
5199 * @param ITFlags Interrupt flags to handle.
5200 * @param ITSources Interrupt sources enabled.
5201 * @retval HAL status
5202 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5203 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5204 uint32_t ITSources)
5205 {
5206 uint16_t devaddress;
5207 uint32_t tmpITFlags = ITFlags;
5208
5209 /* Process Locked */
5210 __HAL_LOCK(hi2c);
5211
5212 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5213 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5214 {
5215 /* Clear NACK Flag */
5216 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5217
5218 /* Set corresponding Error Code */
5219 /* No need to generate STOP, it is automatically done */
5220 /* Error callback will be send during stop flag treatment */
5221 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5222
5223 /* Flush TX register */
5224 I2C_Flush_TXDR(hi2c);
5225 }
5226 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5227 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5228 {
5229 /* Remove RXNE flag on temporary variable as read done */
5230 tmpITFlags &= ~I2C_FLAG_RXNE;
5231
5232 /* Read data from RXDR */
5233 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5234
5235 /* Increment Buffer pointer */
5236 hi2c->pBuffPtr++;
5237
5238 hi2c->XferSize--;
5239 hi2c->XferCount--;
5240 }
5241 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5242 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5243 {
5244 /* Write data to TXDR */
5245 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5246
5247 /* Increment Buffer pointer */
5248 hi2c->pBuffPtr++;
5249
5250 hi2c->XferSize--;
5251 hi2c->XferCount--;
5252 }
5253 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5254 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5255 {
5256 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5257 {
5258 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5259
5260 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5261 {
5262 hi2c->XferSize = MAX_NBYTE_SIZE;
5263 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5264 }
5265 else
5266 {
5267 hi2c->XferSize = hi2c->XferCount;
5268 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5269 {
5270 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5271 hi2c->XferOptions, I2C_NO_STARTSTOP);
5272 }
5273 else
5274 {
5275 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5276 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5277 }
5278 }
5279 }
5280 else
5281 {
5282 /* Call TxCpltCallback() if no stop mode is set */
5283 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5284 {
5285 /* Call I2C Master Sequential complete process */
5286 I2C_ITMasterSeqCplt(hi2c);
5287 }
5288 else
5289 {
5290 /* Wrong size Status regarding TCR flag event */
5291 /* Call the corresponding callback to inform upper layer of End of Transfer */
5292 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5293 }
5294 }
5295 }
5296 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5297 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5298 {
5299 if (hi2c->XferCount == 0U)
5300 {
5301 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5302 {
5303 /* Generate a stop condition in case of no transfer option */
5304 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5305 {
5306 /* Generate Stop */
5307 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5308 }
5309 else
5310 {
5311 /* Call I2C Master Sequential complete process */
5312 I2C_ITMasterSeqCplt(hi2c);
5313 }
5314 }
5315 }
5316 else
5317 {
5318 /* Wrong size Status regarding TC flag event */
5319 /* Call the corresponding callback to inform upper layer of End of Transfer */
5320 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5321 }
5322 }
5323 else
5324 {
5325 /* Nothing to do */
5326 }
5327
5328 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5329 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5330 {
5331 /* Call I2C Master complete process */
5332 I2C_ITMasterCplt(hi2c, tmpITFlags);
5333 }
5334
5335 /* Process Unlocked */
5336 __HAL_UNLOCK(hi2c);
5337
5338 return HAL_OK;
5339 }
5340
5341 /**
5342 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
5343 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5344 * the configuration information for the specified I2C.
5345 * @param ITFlags Interrupt flags to handle.
5346 * @param ITSources Interrupt sources enabled.
5347 * @retval HAL status
5348 */
I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5349 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5350 uint32_t ITSources)
5351 {
5352 uint32_t direction = I2C_GENERATE_START_WRITE;
5353 uint32_t tmpITFlags = ITFlags;
5354
5355 /* Process Locked */
5356 __HAL_LOCK(hi2c);
5357
5358 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5359 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5360 {
5361 /* Clear NACK Flag */
5362 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5363
5364 /* Set corresponding Error Code */
5365 /* No need to generate STOP, it is automatically done */
5366 /* Error callback will be send during stop flag treatment */
5367 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5368
5369 /* Flush TX register */
5370 I2C_Flush_TXDR(hi2c);
5371 }
5372 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5373 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5374 {
5375 /* Remove RXNE flag on temporary variable as read done */
5376 tmpITFlags &= ~I2C_FLAG_RXNE;
5377
5378 /* Read data from RXDR */
5379 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5380
5381 /* Increment Buffer pointer */
5382 hi2c->pBuffPtr++;
5383
5384 hi2c->XferSize--;
5385 hi2c->XferCount--;
5386 }
5387 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5388 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5389 {
5390 if (hi2c->Memaddress == 0xFFFFFFFFU)
5391 {
5392 /* Write data to TXDR */
5393 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5394
5395 /* Increment Buffer pointer */
5396 hi2c->pBuffPtr++;
5397
5398 hi2c->XferSize--;
5399 hi2c->XferCount--;
5400 }
5401 else
5402 {
5403 /* Write LSB part of Memory Address */
5404 hi2c->Instance->TXDR = hi2c->Memaddress;
5405
5406 /* Reset Memaddress content */
5407 hi2c->Memaddress = 0xFFFFFFFFU;
5408 }
5409 }
5410 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5411 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5412 {
5413 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5414 {
5415 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5416 {
5417 hi2c->XferSize = MAX_NBYTE_SIZE;
5418 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5419 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5420 }
5421 else
5422 {
5423 hi2c->XferSize = hi2c->XferCount;
5424 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5425 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5426 }
5427 }
5428 else
5429 {
5430 /* Wrong size Status regarding TCR flag event */
5431 /* Call the corresponding callback to inform upper layer of End of Transfer */
5432 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5433 }
5434 }
5435 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5436 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5437 {
5438 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5439 {
5440 direction = I2C_GENERATE_START_READ;
5441 }
5442
5443 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5444 {
5445 hi2c->XferSize = MAX_NBYTE_SIZE;
5446
5447 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5448 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5449 I2C_RELOAD_MODE, direction);
5450 }
5451 else
5452 {
5453 hi2c->XferSize = hi2c->XferCount;
5454
5455 /* Set NBYTES to write and generate RESTART */
5456 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5457 I2C_AUTOEND_MODE, direction);
5458 }
5459 }
5460 else
5461 {
5462 /* Nothing to do */
5463 }
5464
5465 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5466 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5467 {
5468 /* Call I2C Master complete process */
5469 I2C_ITMasterCplt(hi2c, tmpITFlags);
5470 }
5471
5472 /* Process Unlocked */
5473 __HAL_UNLOCK(hi2c);
5474
5475 return HAL_OK;
5476 }
5477
5478 /**
5479 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5480 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5481 * the configuration information for the specified I2C.
5482 * @param ITFlags Interrupt flags to handle.
5483 * @param ITSources Interrupt sources enabled.
5484 * @retval HAL status
5485 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5486 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5487 uint32_t ITSources)
5488 {
5489 uint32_t tmpoptions = hi2c->XferOptions;
5490 uint32_t tmpITFlags = ITFlags;
5491
5492 /* Process locked */
5493 __HAL_LOCK(hi2c);
5494
5495 /* Check if STOPF is set */
5496 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5497 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5498 {
5499 /* Call I2C Slave complete process */
5500 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5501 }
5502
5503 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5504 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5505 {
5506 /* Check that I2C transfer finished */
5507 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5508 /* Mean XferCount == 0*/
5509 /* So clear Flag NACKF only */
5510 if (hi2c->XferCount == 0U)
5511 {
5512 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5513 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5514 Warning[Pa134]: left and right operands are identical */
5515 {
5516 /* Call I2C Listen complete process */
5517 I2C_ITListenCplt(hi2c, tmpITFlags);
5518 }
5519 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5520 {
5521 /* Clear NACK Flag */
5522 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5523
5524 /* Flush TX register */
5525 I2C_Flush_TXDR(hi2c);
5526
5527 /* Last Byte is Transmitted */
5528 /* Call I2C Slave Sequential complete process */
5529 I2C_ITSlaveSeqCplt(hi2c);
5530 }
5531 else
5532 {
5533 /* Clear NACK Flag */
5534 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5535 }
5536 }
5537 else
5538 {
5539 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5540 /* Clear NACK Flag */
5541 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5542
5543 /* Set ErrorCode corresponding to a Non-Acknowledge */
5544 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5545
5546 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5547 {
5548 /* Call the corresponding callback to inform upper layer of End of Transfer */
5549 I2C_ITError(hi2c, hi2c->ErrorCode);
5550 }
5551 }
5552 }
5553 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5554 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5555 {
5556 if (hi2c->XferCount > 0U)
5557 {
5558 /* Read data from RXDR */
5559 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5560
5561 /* Increment Buffer pointer */
5562 hi2c->pBuffPtr++;
5563
5564 hi2c->XferSize--;
5565 hi2c->XferCount--;
5566 }
5567
5568 if ((hi2c->XferCount == 0U) && \
5569 (tmpoptions != I2C_NO_OPTION_FRAME))
5570 {
5571 /* Call I2C Slave Sequential complete process */
5572 I2C_ITSlaveSeqCplt(hi2c);
5573 }
5574 }
5575 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5576 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5577 {
5578 I2C_ITAddrCplt(hi2c, tmpITFlags);
5579 }
5580 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5581 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5582 {
5583 /* Write data to TXDR only if XferCount not reach "0" */
5584 /* A TXIS flag can be set, during STOP treatment */
5585 /* Check if all Data have already been sent */
5586 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5587 if (hi2c->XferCount > 0U)
5588 {
5589 /* Write data to TXDR */
5590 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5591
5592 /* Increment Buffer pointer */
5593 hi2c->pBuffPtr++;
5594
5595 hi2c->XferCount--;
5596 hi2c->XferSize--;
5597 }
5598 else
5599 {
5600 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5601 {
5602 /* Last Byte is Transmitted */
5603 /* Call I2C Slave Sequential complete process */
5604 I2C_ITSlaveSeqCplt(hi2c);
5605 }
5606 }
5607 }
5608 else
5609 {
5610 /* Nothing to do */
5611 }
5612
5613 /* Process Unlocked */
5614 __HAL_UNLOCK(hi2c);
5615
5616 return HAL_OK;
5617 }
5618
5619 #if defined(HAL_DMA_MODULE_ENABLED)
5620 /**
5621 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5622 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5623 * the configuration information for the specified I2C.
5624 * @param ITFlags Interrupt flags to handle.
5625 * @param ITSources Interrupt sources enabled.
5626 * @retval HAL status
5627 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5628 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5629 uint32_t ITSources)
5630 {
5631 uint16_t devaddress;
5632 uint32_t xfermode;
5633
5634 /* Process Locked */
5635 __HAL_LOCK(hi2c);
5636
5637 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5638 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5639 {
5640 /* Clear NACK Flag */
5641 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5642
5643 /* Set corresponding Error Code */
5644 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5645
5646 /* No need to generate STOP, it is automatically done */
5647 /* But enable STOP interrupt, to treat it */
5648 /* Error callback will be send during stop flag treatment */
5649 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5650
5651 /* Flush TX register */
5652 I2C_Flush_TXDR(hi2c);
5653 }
5654 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5655 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5656 {
5657 /* Disable TC interrupt */
5658 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5659
5660 if (hi2c->XferCount != 0U)
5661 {
5662 /* Recover Slave address */
5663 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5664
5665 /* Prepare the new XferSize to transfer */
5666 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5667 {
5668 hi2c->XferSize = MAX_NBYTE_SIZE;
5669 xfermode = I2C_RELOAD_MODE;
5670 }
5671 else
5672 {
5673 hi2c->XferSize = hi2c->XferCount;
5674 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5675 {
5676 xfermode = hi2c->XferOptions;
5677 }
5678 else
5679 {
5680 xfermode = I2C_AUTOEND_MODE;
5681 }
5682 }
5683
5684 /* Set the new XferSize in Nbytes register */
5685 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5686
5687 /* Update XferCount value */
5688 hi2c->XferCount -= hi2c->XferSize;
5689
5690 /* Enable DMA Request */
5691 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5692 {
5693 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5694 }
5695 else
5696 {
5697 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5698 }
5699 }
5700 else
5701 {
5702 /* Call TxCpltCallback() if no stop mode is set */
5703 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5704 {
5705 /* Call I2C Master Sequential complete process */
5706 I2C_ITMasterSeqCplt(hi2c);
5707 }
5708 else
5709 {
5710 /* Wrong size Status regarding TCR flag event */
5711 /* Call the corresponding callback to inform upper layer of End of Transfer */
5712 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5713 }
5714 }
5715 }
5716 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5717 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5718 {
5719 if (hi2c->XferCount == 0U)
5720 {
5721 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5722 {
5723 /* Generate a stop condition in case of no transfer option */
5724 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5725 {
5726 /* Generate Stop */
5727 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5728 }
5729 else
5730 {
5731 /* Call I2C Master Sequential complete process */
5732 I2C_ITMasterSeqCplt(hi2c);
5733 }
5734 }
5735 }
5736 else
5737 {
5738 /* Wrong size Status regarding TC flag event */
5739 /* Call the corresponding callback to inform upper layer of End of Transfer */
5740 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5741 }
5742 }
5743 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5744 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5745 {
5746 /* Call I2C Master complete process */
5747 I2C_ITMasterCplt(hi2c, ITFlags);
5748 }
5749 else
5750 {
5751 /* Nothing to do */
5752 }
5753
5754 /* Process Unlocked */
5755 __HAL_UNLOCK(hi2c);
5756
5757 return HAL_OK;
5758 }
5759
5760 /**
5761 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
5762 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5763 * the configuration information for the specified I2C.
5764 * @param ITFlags Interrupt flags to handle.
5765 * @param ITSources Interrupt sources enabled.
5766 * @retval HAL status
5767 */
I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5768 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5769 uint32_t ITSources)
5770 {
5771 uint32_t direction = I2C_GENERATE_START_WRITE;
5772
5773 /* Process Locked */
5774 __HAL_LOCK(hi2c);
5775
5776 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5777 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5778 {
5779 /* Clear NACK Flag */
5780 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5781
5782 /* Set corresponding Error Code */
5783 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5784
5785 /* No need to generate STOP, it is automatically done */
5786 /* But enable STOP interrupt, to treat it */
5787 /* Error callback will be send during stop flag treatment */
5788 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5789
5790 /* Flush TX register */
5791 I2C_Flush_TXDR(hi2c);
5792 }
5793 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
5794 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5795 {
5796 /* Write LSB part of Memory Address */
5797 hi2c->Instance->TXDR = hi2c->Memaddress;
5798
5799 /* Reset Memaddress content */
5800 hi2c->Memaddress = 0xFFFFFFFFU;
5801 }
5802 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5803 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5804 {
5805 /* Enable only Error interrupt */
5806 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5807
5808 if (hi2c->XferCount != 0U)
5809 {
5810 /* Prepare the new XferSize to transfer */
5811 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5812 {
5813 hi2c->XferSize = MAX_NBYTE_SIZE;
5814 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5815 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5816 }
5817 else
5818 {
5819 hi2c->XferSize = hi2c->XferCount;
5820 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5821 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5822 }
5823
5824 /* Update XferCount value */
5825 hi2c->XferCount -= hi2c->XferSize;
5826
5827 /* Enable DMA Request */
5828 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5829 {
5830 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5831 }
5832 else
5833 {
5834 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5835 }
5836 }
5837 else
5838 {
5839 /* Wrong size Status regarding TCR flag event */
5840 /* Call the corresponding callback to inform upper layer of End of Transfer */
5841 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5842 }
5843 }
5844 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5845 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5846 {
5847 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5848 {
5849 direction = I2C_GENERATE_START_READ;
5850 }
5851
5852 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5853 {
5854 hi2c->XferSize = MAX_NBYTE_SIZE;
5855
5856 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5857 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5858 I2C_RELOAD_MODE, direction);
5859 }
5860 else
5861 {
5862 hi2c->XferSize = hi2c->XferCount;
5863
5864 /* Set NBYTES to write and generate RESTART */
5865 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5866 I2C_AUTOEND_MODE, direction);
5867 }
5868
5869 /* Update XferCount value */
5870 hi2c->XferCount -= hi2c->XferSize;
5871
5872 /* Enable DMA Request */
5873 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5874 {
5875 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5876 }
5877 else
5878 {
5879 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5880 }
5881 }
5882 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5883 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5884 {
5885 /* Call I2C Master complete process */
5886 I2C_ITMasterCplt(hi2c, ITFlags);
5887 }
5888 else
5889 {
5890 /* Nothing to do */
5891 }
5892
5893 /* Process Unlocked */
5894 __HAL_UNLOCK(hi2c);
5895
5896 return HAL_OK;
5897 }
5898
5899 /**
5900 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5901 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5902 * the configuration information for the specified I2C.
5903 * @param ITFlags Interrupt flags to handle.
5904 * @param ITSources Interrupt sources enabled.
5905 * @retval HAL status
5906 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5907 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5908 uint32_t ITSources)
5909 {
5910 uint32_t tmpoptions = hi2c->XferOptions;
5911 uint32_t treatdmanack = 0U;
5912 HAL_I2C_StateTypeDef tmpstate;
5913
5914 /* Process locked */
5915 __HAL_LOCK(hi2c);
5916
5917 /* Check if STOPF is set */
5918 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5919 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5920 {
5921 /* Call I2C Slave complete process */
5922 I2C_ITSlaveCplt(hi2c, ITFlags);
5923 }
5924
5925 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5926 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5927 {
5928 /* Check that I2C transfer finished */
5929 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5930 /* Mean XferCount == 0 */
5931 /* So clear Flag NACKF only */
5932 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5933 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5934 {
5935 /* Split check of hdmarx, for MISRA compliance */
5936 if (hi2c->hdmarx != NULL)
5937 {
5938 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5939 {
5940 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5941 {
5942 treatdmanack = 1U;
5943 }
5944 }
5945 }
5946
5947 /* Split check of hdmatx, for MISRA compliance */
5948 if (hi2c->hdmatx != NULL)
5949 {
5950 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5951 {
5952 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5953 {
5954 treatdmanack = 1U;
5955 }
5956 }
5957 }
5958
5959 if (treatdmanack == 1U)
5960 {
5961 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5962 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5963 Warning[Pa134]: left and right operands are identical */
5964 {
5965 /* Call I2C Listen complete process */
5966 I2C_ITListenCplt(hi2c, ITFlags);
5967 }
5968 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5969 {
5970 /* Clear NACK Flag */
5971 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5972
5973 /* Flush TX register */
5974 I2C_Flush_TXDR(hi2c);
5975
5976 /* Last Byte is Transmitted */
5977 /* Call I2C Slave Sequential complete process */
5978 I2C_ITSlaveSeqCplt(hi2c);
5979 }
5980 else
5981 {
5982 /* Clear NACK Flag */
5983 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5984 }
5985 }
5986 else
5987 {
5988 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5989 /* Clear NACK Flag */
5990 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5991
5992 /* Set ErrorCode corresponding to a Non-Acknowledge */
5993 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5994
5995 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
5996 tmpstate = hi2c->State;
5997
5998 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5999 {
6000 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6001 {
6002 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6003 }
6004 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6005 {
6006 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6007 }
6008 else
6009 {
6010 /* Do nothing */
6011 }
6012
6013 /* Call the corresponding callback to inform upper layer of End of Transfer */
6014 I2C_ITError(hi2c, hi2c->ErrorCode);
6015 }
6016 }
6017 }
6018 else
6019 {
6020 /* Only Clear NACK Flag, no DMA treatment is pending */
6021 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6022 }
6023 }
6024 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
6025 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
6026 {
6027 I2C_ITAddrCplt(hi2c, ITFlags);
6028 }
6029 else
6030 {
6031 /* Nothing to do */
6032 }
6033
6034 /* Process Unlocked */
6035 __HAL_UNLOCK(hi2c);
6036
6037 return HAL_OK;
6038 }
6039 #endif /* HAL_DMA_MODULE_ENABLED */
6040
6041 /**
6042 * @brief Master sends target device address followed by internal memory address for write request.
6043 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6044 * the configuration information for the specified I2C.
6045 * @param DevAddress Target device address: The device 7 bits address value
6046 * in datasheet must be shifted to the left before calling the interface
6047 * @param MemAddress Internal memory address
6048 * @param MemAddSize Size of internal memory address
6049 * @param Timeout Timeout duration
6050 * @param Tickstart Tick start value
6051 * @retval HAL status
6052 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6053 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
6054 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
6055 uint32_t Tickstart)
6056 {
6057 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
6058
6059 /* Wait until TXIS flag is set */
6060 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6061 {
6062 return HAL_ERROR;
6063 }
6064
6065 /* If Memory address size is 8Bit */
6066 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6067 {
6068 /* Send Memory Address */
6069 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6070 }
6071 /* If Memory address size is 16Bit */
6072 else
6073 {
6074 /* Send MSB of Memory Address */
6075 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
6076
6077 /* Wait until TXIS flag is set */
6078 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6079 {
6080 return HAL_ERROR;
6081 }
6082
6083 /* Send LSB of Memory Address */
6084 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6085 }
6086
6087 /* Wait until TCR flag is set */
6088 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
6089 {
6090 return HAL_ERROR;
6091 }
6092
6093 return HAL_OK;
6094 }
6095
6096 /**
6097 * @brief Master sends target device address followed by internal memory address for read request.
6098 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6099 * the configuration information for the specified I2C.
6100 * @param DevAddress Target device address: The device 7 bits address value
6101 * in datasheet must be shifted to the left before calling the interface
6102 * @param MemAddress Internal memory address
6103 * @param MemAddSize Size of internal memory address
6104 * @param Timeout Timeout duration
6105 * @param Tickstart Tick start value
6106 * @retval HAL status
6107 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6108 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
6109 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
6110 uint32_t Tickstart)
6111 {
6112 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
6113
6114 /* Wait until TXIS flag is set */
6115 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6116 {
6117 return HAL_ERROR;
6118 }
6119
6120 /* If Memory address size is 8Bit */
6121 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6122 {
6123 /* Send Memory Address */
6124 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6125 }
6126 /* If Memory address size is 16Bit */
6127 else
6128 {
6129 /* Send MSB of Memory Address */
6130 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
6131
6132 /* Wait until TXIS flag is set */
6133 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6134 {
6135 return HAL_ERROR;
6136 }
6137
6138 /* Send LSB of Memory Address */
6139 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6140 }
6141
6142 /* Wait until TC flag is set */
6143 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
6144 {
6145 return HAL_ERROR;
6146 }
6147
6148 return HAL_OK;
6149 }
6150
6151 /**
6152 * @brief I2C Address complete process callback.
6153 * @param hi2c I2C handle.
6154 * @param ITFlags Interrupt flags to handle.
6155 * @retval None
6156 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6157 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6158 {
6159 uint8_t transferdirection;
6160 uint16_t slaveaddrcode;
6161 uint16_t ownadd1code;
6162 uint16_t ownadd2code;
6163
6164 /* Prevent unused argument(s) compilation warning */
6165 UNUSED(ITFlags);
6166
6167 /* In case of Listen state, need to inform upper layer of address match code event */
6168 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6169 {
6170 transferdirection = I2C_GET_DIR(hi2c);
6171 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
6172 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
6173 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
6174
6175 /* If 10bits addressing mode is selected */
6176 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
6177 {
6178 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
6179 {
6180 slaveaddrcode = ownadd1code;
6181 hi2c->AddrEventCount++;
6182 if (hi2c->AddrEventCount == 2U)
6183 {
6184 /* Reset Address Event counter */
6185 hi2c->AddrEventCount = 0U;
6186
6187 /* Clear ADDR flag */
6188 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
6189
6190 /* Process Unlocked */
6191 __HAL_UNLOCK(hi2c);
6192
6193 /* Call Slave Addr callback */
6194 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6195 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6196 #else
6197 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6198 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6199 }
6200 }
6201 else
6202 {
6203 slaveaddrcode = ownadd2code;
6204
6205 /* Disable ADDR Interrupts */
6206 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
6207
6208 /* Process Unlocked */
6209 __HAL_UNLOCK(hi2c);
6210
6211 /* Call Slave Addr callback */
6212 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6213 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6214 #else
6215 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6216 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6217 }
6218 }
6219 /* else 7 bits addressing mode is selected */
6220 else
6221 {
6222 /* Disable ADDR Interrupts */
6223 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
6224
6225 /* Process Unlocked */
6226 __HAL_UNLOCK(hi2c);
6227
6228 /* Call Slave Addr callback */
6229 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6230 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6231 #else
6232 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6233 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6234 }
6235 }
6236 /* Else clear address flag only */
6237 else
6238 {
6239 /* Clear ADDR flag */
6240 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
6241
6242 /* Process Unlocked */
6243 __HAL_UNLOCK(hi2c);
6244 }
6245 }
6246
6247 /**
6248 * @brief I2C Master sequential complete process.
6249 * @param hi2c I2C handle.
6250 * @retval None
6251 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)6252 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
6253 {
6254 /* Reset I2C handle mode */
6255 hi2c->Mode = HAL_I2C_MODE_NONE;
6256
6257 /* No Generate Stop, to permit restart mode */
6258 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
6259 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6260 {
6261 hi2c->State = HAL_I2C_STATE_READY;
6262 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6263 hi2c->XferISR = NULL;
6264
6265 /* Disable Interrupts */
6266 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6267
6268 /* Process Unlocked */
6269 __HAL_UNLOCK(hi2c);
6270
6271 /* Call the corresponding callback to inform upper layer of End of Transfer */
6272 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6273 hi2c->MasterTxCpltCallback(hi2c);
6274 #else
6275 HAL_I2C_MasterTxCpltCallback(hi2c);
6276 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6277 }
6278 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6279 else
6280 {
6281 hi2c->State = HAL_I2C_STATE_READY;
6282 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6283 hi2c->XferISR = NULL;
6284
6285 /* Disable Interrupts */
6286 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6287
6288 /* Process Unlocked */
6289 __HAL_UNLOCK(hi2c);
6290
6291 /* Call the corresponding callback to inform upper layer of End of Transfer */
6292 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6293 hi2c->MasterRxCpltCallback(hi2c);
6294 #else
6295 HAL_I2C_MasterRxCpltCallback(hi2c);
6296 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6297 }
6298 }
6299
6300 /**
6301 * @brief I2C Slave sequential complete process.
6302 * @param hi2c I2C handle.
6303 * @retval None
6304 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)6305 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
6306 {
6307 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6308
6309 /* Reset I2C handle mode */
6310 hi2c->Mode = HAL_I2C_MODE_NONE;
6311
6312 #if defined(HAL_DMA_MODULE_ENABLED)
6313 /* If a DMA is ongoing, Update handle size context */
6314 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6315 {
6316 /* Disable DMA Request */
6317 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6318 }
6319 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6320 {
6321 /* Disable DMA Request */
6322 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6323 }
6324 else
6325 {
6326 /* Do nothing */
6327 }
6328 #endif /* HAL_DMA_MODULE_ENABLED */
6329
6330 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
6331 {
6332 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
6333 hi2c->State = HAL_I2C_STATE_LISTEN;
6334 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6335
6336 /* Disable Interrupts */
6337 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6338
6339 /* Process Unlocked */
6340 __HAL_UNLOCK(hi2c);
6341
6342 /* Call the corresponding callback to inform upper layer of End of Transfer */
6343 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6344 hi2c->SlaveTxCpltCallback(hi2c);
6345 #else
6346 HAL_I2C_SlaveTxCpltCallback(hi2c);
6347 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6348 }
6349
6350 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
6351 {
6352 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
6353 hi2c->State = HAL_I2C_STATE_LISTEN;
6354 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6355
6356 /* Disable Interrupts */
6357 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6358
6359 /* Process Unlocked */
6360 __HAL_UNLOCK(hi2c);
6361
6362 /* Call the corresponding callback to inform upper layer of End of Transfer */
6363 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6364 hi2c->SlaveRxCpltCallback(hi2c);
6365 #else
6366 HAL_I2C_SlaveRxCpltCallback(hi2c);
6367 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6368 }
6369 else
6370 {
6371 /* Nothing to do */
6372 }
6373 }
6374
6375 /**
6376 * @brief I2C Master complete process.
6377 * @param hi2c I2C handle.
6378 * @param ITFlags Interrupt flags to handle.
6379 * @retval None
6380 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6381 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6382 {
6383 uint32_t tmperror;
6384 uint32_t tmpITFlags = ITFlags;
6385 __IO uint32_t tmpreg;
6386
6387 /* Clear STOP Flag */
6388 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6389
6390 /* Disable Interrupts and Store Previous state */
6391 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6392 {
6393 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6394 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6395 }
6396 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6397 {
6398 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6399 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6400 }
6401 else
6402 {
6403 /* Do nothing */
6404 }
6405
6406 /* Clear Configuration Register 2 */
6407 I2C_RESET_CR2(hi2c);
6408
6409 /* Reset handle parameters */
6410 hi2c->XferISR = NULL;
6411 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6412
6413 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
6414 {
6415 /* Clear NACK Flag */
6416 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6417
6418 /* Set acknowledge error code */
6419 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6420 }
6421
6422 /* Fetch Last receive data if any */
6423 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
6424 {
6425 /* Read data from RXDR */
6426 tmpreg = (uint8_t)hi2c->Instance->RXDR;
6427 UNUSED(tmpreg);
6428 }
6429
6430 /* Flush TX register */
6431 I2C_Flush_TXDR(hi2c);
6432
6433 /* Store current volatile hi2c->ErrorCode, misra rule */
6434 tmperror = hi2c->ErrorCode;
6435
6436 /* Call the corresponding callback to inform upper layer of End of Transfer */
6437 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
6438 {
6439 /* Call the corresponding callback to inform upper layer of End of Transfer */
6440 I2C_ITError(hi2c, hi2c->ErrorCode);
6441 }
6442 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
6443 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6444 {
6445 hi2c->State = HAL_I2C_STATE_READY;
6446 hi2c->PreviousState = I2C_STATE_NONE;
6447
6448 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6449 {
6450 hi2c->Mode = HAL_I2C_MODE_NONE;
6451
6452 /* Process Unlocked */
6453 __HAL_UNLOCK(hi2c);
6454
6455 /* Call the corresponding callback to inform upper layer of End of Transfer */
6456 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6457 hi2c->MemTxCpltCallback(hi2c);
6458 #else
6459 HAL_I2C_MemTxCpltCallback(hi2c);
6460 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6461 }
6462 else
6463 {
6464 hi2c->Mode = HAL_I2C_MODE_NONE;
6465
6466 /* Process Unlocked */
6467 __HAL_UNLOCK(hi2c);
6468
6469 /* Call the corresponding callback to inform upper layer of End of Transfer */
6470 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6471 hi2c->MasterTxCpltCallback(hi2c);
6472 #else
6473 HAL_I2C_MasterTxCpltCallback(hi2c);
6474 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6475 }
6476 }
6477 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6478 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6479 {
6480 hi2c->State = HAL_I2C_STATE_READY;
6481 hi2c->PreviousState = I2C_STATE_NONE;
6482
6483 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6484 {
6485 hi2c->Mode = HAL_I2C_MODE_NONE;
6486
6487 /* Process Unlocked */
6488 __HAL_UNLOCK(hi2c);
6489
6490 /* Call the corresponding callback to inform upper layer of End of Transfer */
6491 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6492 hi2c->MemRxCpltCallback(hi2c);
6493 #else
6494 HAL_I2C_MemRxCpltCallback(hi2c);
6495 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6496 }
6497 else
6498 {
6499 hi2c->Mode = HAL_I2C_MODE_NONE;
6500
6501 /* Process Unlocked */
6502 __HAL_UNLOCK(hi2c);
6503
6504 /* Call the corresponding callback to inform upper layer of End of Transfer */
6505 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6506 hi2c->MasterRxCpltCallback(hi2c);
6507 #else
6508 HAL_I2C_MasterRxCpltCallback(hi2c);
6509 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6510 }
6511 }
6512 else
6513 {
6514 /* Nothing to do */
6515 }
6516 }
6517
6518 /**
6519 * @brief I2C Slave complete process.
6520 * @param hi2c I2C handle.
6521 * @param ITFlags Interrupt flags to handle.
6522 * @retval None
6523 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6524 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6525 {
6526 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6527 uint32_t tmpITFlags = ITFlags;
6528 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6529
6530 /* Clear STOP Flag */
6531 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6532
6533 /* Disable Interrupts and Store Previous state */
6534 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6535 {
6536 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6537 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6538 }
6539 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6540 {
6541 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6542 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6543 }
6544 else
6545 {
6546 /* Do nothing */
6547 }
6548
6549 /* Disable Address Acknowledge */
6550 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6551
6552 /* Clear Configuration Register 2 */
6553 I2C_RESET_CR2(hi2c);
6554
6555 /* Flush TX register */
6556 I2C_Flush_TXDR(hi2c);
6557
6558 #if defined(HAL_DMA_MODULE_ENABLED)
6559 /* If a DMA is ongoing, Update handle size context */
6560 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6561 {
6562 /* Disable DMA Request */
6563 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6564
6565 if (hi2c->hdmatx != NULL)
6566 {
6567 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6568 }
6569 }
6570 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6571 {
6572 /* Disable DMA Request */
6573 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6574
6575 if (hi2c->hdmarx != NULL)
6576 {
6577 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6578 }
6579 }
6580 else
6581 {
6582 /* Do nothing */
6583 }
6584 #endif /* HAL_DMA_MODULE_ENABLED */
6585
6586 /* Store Last receive data if any */
6587 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6588 {
6589 /* Remove RXNE flag on temporary variable as read done */
6590 tmpITFlags &= ~I2C_FLAG_RXNE;
6591
6592 /* Read data from RXDR */
6593 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6594
6595 /* Increment Buffer pointer */
6596 hi2c->pBuffPtr++;
6597
6598 if ((hi2c->XferSize > 0U))
6599 {
6600 hi2c->XferSize--;
6601 hi2c->XferCount--;
6602 }
6603 }
6604
6605 /* All data are not transferred, so set error code accordingly */
6606 if (hi2c->XferCount != 0U)
6607 {
6608 /* Set ErrorCode corresponding to a Non-Acknowledge */
6609 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6610 }
6611
6612 hi2c->Mode = HAL_I2C_MODE_NONE;
6613 hi2c->XferISR = NULL;
6614
6615 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6616 {
6617 /* Call the corresponding callback to inform upper layer of End of Transfer */
6618 I2C_ITError(hi2c, hi2c->ErrorCode);
6619
6620 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6621 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6622 {
6623 /* Call I2C Listen complete process */
6624 I2C_ITListenCplt(hi2c, tmpITFlags);
6625 }
6626 }
6627 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6628 {
6629 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6630 I2C_ITSlaveSeqCplt(hi2c);
6631
6632 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6633 hi2c->State = HAL_I2C_STATE_READY;
6634 hi2c->PreviousState = I2C_STATE_NONE;
6635
6636 /* Process Unlocked */
6637 __HAL_UNLOCK(hi2c);
6638
6639 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6640 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6641 hi2c->ListenCpltCallback(hi2c);
6642 #else
6643 HAL_I2C_ListenCpltCallback(hi2c);
6644 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6645 }
6646 /* Call the corresponding callback to inform upper layer of End of Transfer */
6647 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6648 {
6649 hi2c->State = HAL_I2C_STATE_READY;
6650 hi2c->PreviousState = I2C_STATE_NONE;
6651
6652 /* Process Unlocked */
6653 __HAL_UNLOCK(hi2c);
6654
6655 /* Call the corresponding callback to inform upper layer of End of Transfer */
6656 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6657 hi2c->SlaveRxCpltCallback(hi2c);
6658 #else
6659 HAL_I2C_SlaveRxCpltCallback(hi2c);
6660 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6661 }
6662 else
6663 {
6664 hi2c->State = HAL_I2C_STATE_READY;
6665 hi2c->PreviousState = I2C_STATE_NONE;
6666
6667 /* Process Unlocked */
6668 __HAL_UNLOCK(hi2c);
6669
6670 /* Call the corresponding callback to inform upper layer of End of Transfer */
6671 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6672 hi2c->SlaveTxCpltCallback(hi2c);
6673 #else
6674 HAL_I2C_SlaveTxCpltCallback(hi2c);
6675 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6676 }
6677 }
6678
6679 /**
6680 * @brief I2C Listen complete process.
6681 * @param hi2c I2C handle.
6682 * @param ITFlags Interrupt flags to handle.
6683 * @retval None
6684 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6685 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6686 {
6687 /* Reset handle parameters */
6688 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6689 hi2c->PreviousState = I2C_STATE_NONE;
6690 hi2c->State = HAL_I2C_STATE_READY;
6691 hi2c->Mode = HAL_I2C_MODE_NONE;
6692 hi2c->XferISR = NULL;
6693
6694 /* Store Last receive data if any */
6695 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6696 {
6697 /* Read data from RXDR */
6698 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6699
6700 /* Increment Buffer pointer */
6701 hi2c->pBuffPtr++;
6702
6703 if ((hi2c->XferSize > 0U))
6704 {
6705 hi2c->XferSize--;
6706 hi2c->XferCount--;
6707
6708 /* Set ErrorCode corresponding to a Non-Acknowledge */
6709 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6710 }
6711 }
6712
6713 /* Disable all Interrupts*/
6714 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6715
6716 /* Clear NACK Flag */
6717 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6718
6719 /* Process Unlocked */
6720 __HAL_UNLOCK(hi2c);
6721
6722 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6723 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6724 hi2c->ListenCpltCallback(hi2c);
6725 #else
6726 HAL_I2C_ListenCpltCallback(hi2c);
6727 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6728 }
6729
6730 /**
6731 * @brief I2C interrupts error process.
6732 * @param hi2c I2C handle.
6733 * @param ErrorCode Error code to handle.
6734 * @retval None
6735 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6736 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6737 {
6738 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6739
6740 #if defined(HAL_DMA_MODULE_ENABLED)
6741 uint32_t tmppreviousstate;
6742 #endif /* HAL_DMA_MODULE_ENABLED */
6743
6744 /* Reset handle parameters */
6745 hi2c->Mode = HAL_I2C_MODE_NONE;
6746 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6747 hi2c->XferCount = 0U;
6748
6749 /* Set new error code */
6750 hi2c->ErrorCode |= ErrorCode;
6751
6752 /* Disable Interrupts */
6753 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6754 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6755 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6756 {
6757 /* Disable all interrupts, except interrupts related to LISTEN state */
6758 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6759
6760 /* keep HAL_I2C_STATE_LISTEN if set */
6761 hi2c->State = HAL_I2C_STATE_LISTEN;
6762 hi2c->XferISR = I2C_Slave_ISR_IT;
6763 }
6764 else
6765 {
6766 /* Disable all interrupts */
6767 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6768
6769 /* Flush TX register */
6770 I2C_Flush_TXDR(hi2c);
6771
6772 /* If state is an abort treatment on going, don't change state */
6773 /* This change will be do later */
6774 if (hi2c->State != HAL_I2C_STATE_ABORT)
6775 {
6776 /* Set HAL_I2C_STATE_READY */
6777 hi2c->State = HAL_I2C_STATE_READY;
6778
6779 /* Check if a STOPF is detected */
6780 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6781 {
6782 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6783 {
6784 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6785 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6786 }
6787
6788 /* Clear STOP Flag */
6789 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6790 }
6791
6792 }
6793 hi2c->XferISR = NULL;
6794 }
6795
6796 #if defined(HAL_DMA_MODULE_ENABLED)
6797 /* Abort DMA TX transfer if any */
6798 tmppreviousstate = hi2c->PreviousState;
6799
6800 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6801 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6802 {
6803 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6804 {
6805 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6806 }
6807
6808 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6809 {
6810 /* Set the I2C DMA Abort callback :
6811 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6812 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6813
6814 /* Process Unlocked */
6815 __HAL_UNLOCK(hi2c);
6816
6817 /* Abort DMA TX */
6818 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6819 {
6820 /* Call Directly XferAbortCallback function in case of error */
6821 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6822 }
6823 }
6824 else
6825 {
6826 I2C_TreatErrorCallback(hi2c);
6827 }
6828 }
6829 /* Abort DMA RX transfer if any */
6830 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6831 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6832 {
6833 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6834 {
6835 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6836 }
6837
6838 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6839 {
6840 /* Set the I2C DMA Abort callback :
6841 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6842 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6843
6844 /* Process Unlocked */
6845 __HAL_UNLOCK(hi2c);
6846
6847 /* Abort DMA RX */
6848 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6849 {
6850 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6851 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6852 }
6853 }
6854 else
6855 {
6856 I2C_TreatErrorCallback(hi2c);
6857 }
6858 }
6859 else
6860 #endif /* HAL_DMA_MODULE_ENABLED */
6861 {
6862 I2C_TreatErrorCallback(hi2c);
6863 }
6864 }
6865
6866 /**
6867 * @brief I2C Error callback treatment.
6868 * @param hi2c I2C handle.
6869 * @retval None
6870 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6871 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6872 {
6873 if (hi2c->State == HAL_I2C_STATE_ABORT)
6874 {
6875 hi2c->State = HAL_I2C_STATE_READY;
6876 hi2c->PreviousState = I2C_STATE_NONE;
6877
6878 /* Process Unlocked */
6879 __HAL_UNLOCK(hi2c);
6880
6881 /* Call the corresponding callback to inform upper layer of End of Transfer */
6882 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6883 hi2c->AbortCpltCallback(hi2c);
6884 #else
6885 HAL_I2C_AbortCpltCallback(hi2c);
6886 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6887 }
6888 else
6889 {
6890 hi2c->PreviousState = I2C_STATE_NONE;
6891
6892 /* Process Unlocked */
6893 __HAL_UNLOCK(hi2c);
6894
6895 /* Call the corresponding callback to inform upper layer of End of Transfer */
6896 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6897 hi2c->ErrorCallback(hi2c);
6898 #else
6899 HAL_I2C_ErrorCallback(hi2c);
6900 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6901 }
6902 }
6903
6904 /**
6905 * @brief I2C Tx data register flush process.
6906 * @param hi2c I2C handle.
6907 * @retval None
6908 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6909 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6910 {
6911 /* If a pending TXIS flag is set */
6912 /* Write a dummy data in TXDR to clear it */
6913 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
6914 {
6915 hi2c->Instance->TXDR = 0x00U;
6916 }
6917
6918 /* Flush TX register if not empty */
6919 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6920 {
6921 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
6922 }
6923 }
6924
6925 #if defined(HAL_DMA_MODULE_ENABLED)
6926 /**
6927 * @brief DMA I2C master transmit process complete callback.
6928 * @param hdma DMA handle
6929 * @retval None
6930 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)6931 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
6932 {
6933 HAL_StatusTypeDef dmaxferstatus = HAL_OK;
6934 /* Derogation MISRAC2012-Rule-11.5 */
6935 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6936
6937 /* Disable DMA Request */
6938 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6939
6940 /* If last transfer, enable STOP interrupt */
6941 if (hi2c->XferCount == 0U)
6942 {
6943 /* Enable STOP interrupt */
6944 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6945 }
6946 /* else prepare a new DMA transfer and enable TCReload interrupt */
6947 else
6948 {
6949 /* Update Buffer pointer */
6950 hi2c->pBuffPtr += hi2c->XferSize;
6951
6952 /* Set the XferSize to transfer */
6953 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6954 {
6955 hi2c->XferSize = MAX_NBYTE_SIZE;
6956 }
6957 else
6958 {
6959 hi2c->XferSize = hi2c->XferCount;
6960 }
6961
6962 /* Enable the DMA channel */
6963 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
6964 {
6965 if (hi2c->hdmatx->LinkedListQueue != NULL)
6966 {
6967 /* Set DMA data size */
6968 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
6969
6970 /* Set DMA source address */
6971 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
6972
6973 /* Set DMA destination address */
6974 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR;
6975
6976 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
6977 }
6978 else
6979 {
6980 /* Call the corresponding callback to inform upper layer of End of Transfer */
6981 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6982 }
6983 }
6984 else
6985 {
6986 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
6987 hi2c->XferSize);
6988 }
6989
6990 if (dmaxferstatus != HAL_OK)
6991 {
6992 /* Call the corresponding callback to inform upper layer of End of Transfer */
6993 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6994 }
6995 else
6996 {
6997 /* Enable TC interrupts */
6998 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6999 }
7000 }
7001 }
7002
7003
7004 /**
7005 * @brief DMA I2C slave transmit process complete callback.
7006 * @param hdma DMA handle
7007 * @retval None
7008 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)7009 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
7010 {
7011 /* Derogation MISRAC2012-Rule-11.5 */
7012 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7013 uint32_t tmpoptions = hi2c->XferOptions;
7014
7015 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
7016 {
7017 /* Disable DMA Request */
7018 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
7019
7020 /* Last Byte is Transmitted */
7021 /* Call I2C Slave Sequential complete process */
7022 I2C_ITSlaveSeqCplt(hi2c);
7023 }
7024 else
7025 {
7026 /* No specific action, Master fully manage the generation of STOP condition */
7027 /* Mean that this generation can arrive at any time, at the end or during DMA process */
7028 /* So STOP condition should be manage through Interrupt treatment */
7029 }
7030 }
7031
7032
7033 /**
7034 * @brief DMA I2C master receive process complete callback.
7035 * @param hdma DMA handle
7036 * @retval None
7037 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)7038 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
7039 {
7040 HAL_StatusTypeDef dmaxferstatus = HAL_OK;
7041 /* Derogation MISRAC2012-Rule-11.5 */
7042 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7043
7044 /* Disable DMA Request */
7045 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
7046
7047 /* If last transfer, enable STOP interrupt */
7048 if (hi2c->XferCount == 0U)
7049 {
7050 /* Enable STOP interrupt */
7051 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
7052 }
7053 /* else prepare a new DMA transfer and enable TCReload interrupt */
7054 else
7055 {
7056 /* Update Buffer pointer */
7057 hi2c->pBuffPtr += hi2c->XferSize;
7058
7059 /* Set the XferSize to transfer */
7060 if (hi2c->XferCount > MAX_NBYTE_SIZE)
7061 {
7062 hi2c->XferSize = MAX_NBYTE_SIZE;
7063 }
7064 else
7065 {
7066 hi2c->XferSize = hi2c->XferCount;
7067 }
7068
7069 /* Enable the DMA channel */
7070 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
7071 {
7072 if (hi2c->hdmarx->LinkedListQueue != NULL)
7073 {
7074 /* Set DMA data size */
7075 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
7076
7077 /* Set DMA source address */
7078 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR;
7079
7080 /* Set DMA destination address */
7081 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
7082
7083 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
7084 }
7085 else
7086 {
7087 /* Call the corresponding callback to inform upper layer of End of Transfer */
7088 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7089 }
7090 }
7091 else
7092 {
7093 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
7094 hi2c->XferSize);
7095 }
7096
7097 if (dmaxferstatus != HAL_OK)
7098 {
7099 /* Call the corresponding callback to inform upper layer of End of Transfer */
7100 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7101 }
7102 else
7103 {
7104 /* Enable TC interrupts */
7105 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
7106 }
7107 }
7108 }
7109
7110
7111 /**
7112 * @brief DMA I2C slave receive process complete callback.
7113 * @param hdma DMA handle
7114 * @retval None
7115 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)7116 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
7117 {
7118 /* Derogation MISRAC2012-Rule-11.5 */
7119 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7120 uint32_t tmpoptions = hi2c->XferOptions;
7121
7122 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
7123 (tmpoptions != I2C_NO_OPTION_FRAME))
7124 {
7125 /* Disable DMA Request */
7126 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
7127
7128 /* Call I2C Slave Sequential complete process */
7129 I2C_ITSlaveSeqCplt(hi2c);
7130 }
7131 else
7132 {
7133 /* No specific action, Master fully manage the generation of STOP condition */
7134 /* Mean that this generation can arrive at any time, at the end or during DMA process */
7135 /* So STOP condition should be manage through Interrupt treatment */
7136 }
7137 }
7138
7139
7140 /**
7141 * @brief DMA I2C communication error callback.
7142 * @param hdma DMA handle
7143 * @retval None
7144 */
I2C_DMAError(DMA_HandleTypeDef * hdma)7145 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
7146 {
7147 /* Derogation MISRAC2012-Rule-11.5 */
7148 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7149
7150 /* Disable Acknowledge */
7151 hi2c->Instance->CR2 |= I2C_CR2_NACK;
7152
7153 /* Call the corresponding callback to inform upper layer of End of Transfer */
7154 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7155 }
7156
7157
7158 /**
7159 * @brief DMA I2C communication abort callback
7160 * (To be called at end of DMA Abort procedure).
7161 * @param hdma DMA handle.
7162 * @retval None
7163 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)7164 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
7165 {
7166 /* Derogation MISRAC2012-Rule-11.5 */
7167 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7168
7169 /* Reset AbortCpltCallback */
7170 if (hi2c->hdmatx != NULL)
7171 {
7172 hi2c->hdmatx->XferAbortCallback = NULL;
7173 }
7174 if (hi2c->hdmarx != NULL)
7175 {
7176 hi2c->hdmarx->XferAbortCallback = NULL;
7177 }
7178
7179 I2C_TreatErrorCallback(hi2c);
7180 }
7181
7182 #endif /* HAL_DMA_MODULE_ENABLED */
7183
7184 /**
7185 * @brief This function handles I2C Communication Timeout. It waits
7186 * until a flag is no longer in the specified status.
7187 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7188 * the configuration information for the specified I2C.
7189 * @param Flag Specifies the I2C flag to check.
7190 * @param Status The actual Flag status (SET or RESET).
7191 * @param Timeout Timeout duration
7192 * @param Tickstart Tick start value
7193 * @retval HAL status
7194 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)7195 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
7196 uint32_t Timeout, uint32_t Tickstart)
7197 {
7198 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
7199 {
7200 /* Check for the Timeout */
7201 if (Timeout != HAL_MAX_DELAY)
7202 {
7203 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7204 {
7205 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
7206 {
7207 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7208 hi2c->State = HAL_I2C_STATE_READY;
7209 hi2c->Mode = HAL_I2C_MODE_NONE;
7210
7211 /* Process Unlocked */
7212 __HAL_UNLOCK(hi2c);
7213 return HAL_ERROR;
7214 }
7215 }
7216 }
7217 }
7218 return HAL_OK;
7219 }
7220
7221 /**
7222 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
7223 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7224 * the configuration information for the specified I2C.
7225 * @param Timeout Timeout duration
7226 * @param Tickstart Tick start value
7227 * @retval HAL status
7228 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7229 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7230 uint32_t Tickstart)
7231 {
7232 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
7233 {
7234 /* Check if an error is detected */
7235 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7236 {
7237 return HAL_ERROR;
7238 }
7239
7240 /* Check for the Timeout */
7241 if (Timeout != HAL_MAX_DELAY)
7242 {
7243 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7244 {
7245 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
7246 {
7247 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7248 hi2c->State = HAL_I2C_STATE_READY;
7249 hi2c->Mode = HAL_I2C_MODE_NONE;
7250
7251 /* Process Unlocked */
7252 __HAL_UNLOCK(hi2c);
7253
7254 return HAL_ERROR;
7255 }
7256 }
7257 }
7258 }
7259 return HAL_OK;
7260 }
7261
7262 /**
7263 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7264 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7265 * the configuration information for the specified I2C.
7266 * @param Timeout Timeout duration
7267 * @param Tickstart Tick start value
7268 * @retval HAL status
7269 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7270 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7271 uint32_t Tickstart)
7272 {
7273 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7274 {
7275 /* Check if an error is detected */
7276 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7277 {
7278 return HAL_ERROR;
7279 }
7280
7281 /* Check for the Timeout */
7282 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7283 {
7284 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
7285 {
7286 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7287 hi2c->State = HAL_I2C_STATE_READY;
7288 hi2c->Mode = HAL_I2C_MODE_NONE;
7289
7290 /* Process Unlocked */
7291 __HAL_UNLOCK(hi2c);
7292
7293 return HAL_ERROR;
7294 }
7295 }
7296 }
7297 return HAL_OK;
7298 }
7299
7300 /**
7301 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7302 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7303 * the configuration information for the specified I2C.
7304 * @param Timeout Timeout duration
7305 * @param Tickstart Tick start value
7306 * @retval HAL status
7307 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7308 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7309 uint32_t Tickstart)
7310 {
7311 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
7312 {
7313 /* Check if an error is detected */
7314 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7315 {
7316 return HAL_ERROR;
7317 }
7318
7319 /* Check if a STOPF is detected */
7320 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
7321 {
7322 /* Check if an RXNE is pending */
7323 /* Store Last receive data if any */
7324 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
7325 {
7326 /* Return HAL_OK */
7327 /* The Reading of data from RXDR will be done in caller function */
7328 return HAL_OK;
7329 }
7330 else
7331 {
7332 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7333 {
7334 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7335 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
7336 }
7337 else
7338 {
7339 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7340 }
7341
7342 /* Clear STOP Flag */
7343 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7344
7345 /* Clear Configuration Register 2 */
7346 I2C_RESET_CR2(hi2c);
7347
7348 hi2c->State = HAL_I2C_STATE_READY;
7349 hi2c->Mode = HAL_I2C_MODE_NONE;
7350
7351 /* Process Unlocked */
7352 __HAL_UNLOCK(hi2c);
7353
7354 return HAL_ERROR;
7355 }
7356 }
7357
7358 /* Check for the Timeout */
7359 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7360 {
7361 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
7362 {
7363 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7364 hi2c->State = HAL_I2C_STATE_READY;
7365
7366 /* Process Unlocked */
7367 __HAL_UNLOCK(hi2c);
7368
7369 return HAL_ERROR;
7370 }
7371 }
7372 }
7373 return HAL_OK;
7374 }
7375
7376 /**
7377 * @brief This function handles errors detection during an I2C Communication.
7378 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7379 * the configuration information for the specified I2C.
7380 * @param Timeout Timeout duration
7381 * @param Tickstart Tick start value
7382 * @retval HAL status
7383 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7384 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7385 {
7386 HAL_StatusTypeDef status = HAL_OK;
7387 uint32_t itflag = hi2c->Instance->ISR;
7388 uint32_t error_code = 0;
7389 uint32_t tickstart = Tickstart;
7390 uint32_t tmp1;
7391 HAL_I2C_ModeTypeDef tmp2;
7392
7393 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
7394 {
7395 /* Clear NACKF Flag */
7396 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7397
7398 /* Wait until STOP Flag is set or timeout occurred */
7399 /* AutoEnd should be initiate after AF */
7400 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
7401 {
7402 /* Check for the Timeout */
7403 if (Timeout != HAL_MAX_DELAY)
7404 {
7405 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7406 {
7407 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
7408 tmp2 = hi2c->Mode;
7409
7410 /* In case of I2C still busy, try to regenerate a STOP manually */
7411 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
7412 (tmp1 != I2C_CR2_STOP) && \
7413 (tmp2 != HAL_I2C_MODE_SLAVE))
7414 {
7415 /* Generate Stop */
7416 hi2c->Instance->CR2 |= I2C_CR2_STOP;
7417
7418 /* Update Tick with new reference */
7419 tickstart = HAL_GetTick();
7420 }
7421
7422 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7423 {
7424 /* Check for the Timeout */
7425 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
7426 {
7427 error_code |= HAL_I2C_ERROR_TIMEOUT;
7428
7429 status = HAL_ERROR;
7430
7431 break;
7432 }
7433 }
7434 }
7435 }
7436 }
7437
7438 /* In case STOP Flag is detected, clear it */
7439 if (status == HAL_OK)
7440 {
7441 /* Clear STOP Flag */
7442 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7443 }
7444
7445 error_code |= HAL_I2C_ERROR_AF;
7446
7447 status = HAL_ERROR;
7448 }
7449
7450 /* Refresh Content of Status register */
7451 itflag = hi2c->Instance->ISR;
7452
7453 /* Then verify if an additional errors occurs */
7454 /* Check if a Bus error occurred */
7455 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
7456 {
7457 error_code |= HAL_I2C_ERROR_BERR;
7458
7459 /* Clear BERR flag */
7460 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
7461
7462 status = HAL_ERROR;
7463 }
7464
7465 /* Check if an Over-Run/Under-Run error occurred */
7466 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
7467 {
7468 error_code |= HAL_I2C_ERROR_OVR;
7469
7470 /* Clear OVR flag */
7471 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
7472
7473 status = HAL_ERROR;
7474 }
7475
7476 /* Check if an Arbitration Loss error occurred */
7477 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
7478 {
7479 error_code |= HAL_I2C_ERROR_ARLO;
7480
7481 /* Clear ARLO flag */
7482 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
7483
7484 status = HAL_ERROR;
7485 }
7486
7487 if (status != HAL_OK)
7488 {
7489 /* Flush TX register */
7490 I2C_Flush_TXDR(hi2c);
7491
7492 /* Clear Configuration Register 2 */
7493 I2C_RESET_CR2(hi2c);
7494
7495 hi2c->ErrorCode |= error_code;
7496 hi2c->State = HAL_I2C_STATE_READY;
7497 hi2c->Mode = HAL_I2C_MODE_NONE;
7498
7499 /* Process Unlocked */
7500 __HAL_UNLOCK(hi2c);
7501 }
7502
7503 return status;
7504 }
7505
7506 /**
7507 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
7508 * @param hi2c I2C handle.
7509 * @param DevAddress Specifies the slave address to be programmed.
7510 * @param Size Specifies the number of bytes to be programmed.
7511 * This parameter must be a value between 0 and 255.
7512 * @param Mode New state of the I2C START condition generation.
7513 * This parameter can be one of the following values:
7514 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
7515 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
7516 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
7517 * @param Request New state of the I2C START condition generation.
7518 * This parameter can be one of the following values:
7519 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
7520 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
7521 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
7522 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
7523 * @retval None
7524 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)7525 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
7526 uint32_t Request)
7527 {
7528 /* Check the parameters */
7529 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
7530 assert_param(IS_TRANSFER_MODE(Mode));
7531 assert_param(IS_TRANSFER_REQUEST(Request));
7532
7533 /* Declaration of tmp to prevent undefined behavior of volatile usage */
7534 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
7535 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
7536 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
7537
7538 /* update CR2 register */
7539 MODIFY_REG(hi2c->Instance->CR2, \
7540 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
7541 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
7542 I2C_CR2_START | I2C_CR2_STOP)), tmp);
7543 }
7544
7545 /**
7546 * @brief Manage the enabling of Interrupts.
7547 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7548 * the configuration information for the specified I2C.
7549 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7550 * @retval None
7551 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7552 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7553 {
7554 uint32_t tmpisr = 0U;
7555
7556 #if defined(HAL_DMA_MODULE_ENABLED)
7557 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
7558 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
7559 (hi2c->XferISR != I2C_Mem_ISR_DMA))
7560 #endif /* HAL_DMA_MODULE_ENABLED */
7561 {
7562 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7563 {
7564 /* Enable ERR, STOP, NACK, and ADDR interrupts */
7565 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7566 }
7567
7568 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7569 {
7570 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7571 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7572 }
7573
7574 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7575 {
7576 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7577 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7578 }
7579
7580 if (InterruptRequest == I2C_XFER_ERROR_IT)
7581 {
7582 /* Enable ERR and NACK interrupts */
7583 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7584 }
7585
7586 if (InterruptRequest == I2C_XFER_CPLT_IT)
7587 {
7588 /* Enable STOP interrupts */
7589 tmpisr |= I2C_IT_STOPI;
7590 }
7591 }
7592
7593 #if defined(HAL_DMA_MODULE_ENABLED)
7594 else
7595 {
7596 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7597 {
7598 /* Enable ERR, STOP, NACK and ADDR interrupts */
7599 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7600 }
7601
7602 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7603 {
7604 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7605 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7606 }
7607
7608 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7609 {
7610 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7611 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7612 }
7613
7614 if (InterruptRequest == I2C_XFER_ERROR_IT)
7615 {
7616 /* Enable ERR and NACK interrupts */
7617 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7618 }
7619
7620 if (InterruptRequest == I2C_XFER_CPLT_IT)
7621 {
7622 /* Enable STOP interrupts */
7623 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7624 }
7625
7626 if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT))
7627 {
7628 /* Enable TC interrupts */
7629 tmpisr |= I2C_IT_TCI;
7630 }
7631 }
7632 #endif /* HAL_DMA_MODULE_ENABLED */
7633
7634 /* Enable interrupts only at the end */
7635 /* to avoid the risk of I2C interrupt handle execution before */
7636 /* all interrupts requested done */
7637 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7638 }
7639
7640
7641 /**
7642 * @brief Manage the disabling of Interrupts.
7643 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7644 * the configuration information for the specified I2C.
7645 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7646 * @retval None
7647 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7648 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7649 {
7650 uint32_t tmpisr = 0U;
7651
7652 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7653 {
7654 /* Disable TC and TXI interrupts */
7655 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7656
7657 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7658 {
7659 /* Disable NACK and STOP interrupts */
7660 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7661 }
7662 }
7663
7664 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7665 {
7666 /* Disable TC and RXI interrupts */
7667 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7668
7669 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7670 {
7671 /* Disable NACK and STOP interrupts */
7672 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7673 }
7674 }
7675
7676 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7677 {
7678 /* Disable ADDR, NACK and STOP interrupts */
7679 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7680 }
7681
7682 if (InterruptRequest == I2C_XFER_ERROR_IT)
7683 {
7684 /* Enable ERR and NACK interrupts */
7685 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7686 }
7687
7688 if (InterruptRequest == I2C_XFER_CPLT_IT)
7689 {
7690 /* Enable STOP interrupts */
7691 tmpisr |= I2C_IT_STOPI;
7692 }
7693
7694 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7695 {
7696 /* Enable TC interrupts */
7697 tmpisr |= I2C_IT_TCI;
7698 }
7699
7700 /* Disable interrupts only at the end */
7701 /* to avoid a breaking situation like at "t" time */
7702 /* all disable interrupts request are not done */
7703 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7704 }
7705
7706 /**
7707 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7708 * @param hi2c I2C handle.
7709 * @retval None
7710 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7711 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7712 {
7713 /* if user set XferOptions to I2C_OTHER_FRAME */
7714 /* it request implicitly to generate a restart condition */
7715 /* set XferOptions to I2C_FIRST_FRAME */
7716 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7717 {
7718 hi2c->XferOptions = I2C_FIRST_FRAME;
7719 }
7720 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7721 /* it request implicitly to generate a restart condition */
7722 /* then generate a stop condition at the end of transfer */
7723 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7724 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7725 {
7726 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7727 }
7728 else
7729 {
7730 /* Nothing to do */
7731 }
7732 }
7733
7734 /**
7735 * @}
7736 */
7737
7738 #endif /* HAL_I2C_MODULE_ENABLED */
7739 /**
7740 * @}
7741 */
7742
7743 /**
7744 * @}
7745 */
7746
