1 /* SPDX-License-Identifier: Apache-2.0 */ 2 /* 3 * Copyright © 2023 Calian Ltd. All rights reserved. 4 * 5 * Driver for the Xilinx AXI IIC Bus Interface. 6 * This is an FPGA logic core as described by Xilinx document PG090. 7 */ 8 9 #ifndef ZEPHYR_DRIVERS_I2C_I2C_XILINX_AXI_H_ 10 #define ZEPHYR_DRIVERS_I2C_I2C_XILINX_AXI_H_ 11 12 #include <zephyr/sys/util_macro.h> 13 14 /* Register offsets */ 15 enum xilinx_axi_i2c_register { 16 REG_GIE = 0x01C, /* Global Interrupt Enable */ 17 REG_ISR = 0x020, /* Interrupt Status */ 18 REG_IER = 0x028, /* Interrupt Enable */ 19 REG_SOFTR = 0x040, /* Soft Reset */ 20 REG_CR = 0x100, /* Control */ 21 REG_SR = 0x104, /* Status */ 22 REG_TX_FIFO = 0x108, /* Transmit FIFO */ 23 REG_RX_FIFO = 0x10C, /* Receive FIFO */ 24 REG_ADR = 0x110, /* Target Address */ 25 REG_TX_FIFO_OCY = 0x114, /* Transmit FIFO Occupancy */ 26 REG_RX_FIFO_OCY = 0x118, /* Receive FIFO Occupancy */ 27 REG_TEN_ADR = 0x11C, /* Target Ten Bit Address */ 28 REG_RX_FIFO_PIRQ = 0x120, /* Receive FIFO Programmable Depth Interrupt */ 29 REG_GPO = 0x124, /* General Purpose Output */ 30 REG_TSUSTA = 0x128, /* Timing Parameter */ 31 REG_TSUSTO = 0x12C, /* Timing Parameter */ 32 REG_THDSTA = 0x130, /* Timing Parameter */ 33 REG_TSUDAT = 0x134, /* Timing Parameter */ 34 REG_TBUF = 0x138, /* Timing Parameter */ 35 REG_THIGH = 0x13C, /* Timing Parameter */ 36 REG_TLOW = 0x140, /* Timing Parameter */ 37 REG_THDDAT = 0x144, /* Timing Parameter */ 38 }; 39 40 /* Register bits */ 41 /* Global Interrupt Enable */ 42 enum xilinx_axi_i2c_gie_bits { 43 GIE_ENABLE = BIT(31), 44 }; 45 46 /* Interrupt Status/Interrupt Enable */ 47 enum xilinx_axi_i2c_isr_bits { 48 ISR_TX_HALF_EMPTY = BIT(7), /* Transmit FIFO Half Empty */ 49 ISR_NOT_ADDR_TARGET = BIT(6), /* Not Addressed As Target */ 50 ISR_ADDR_TARGET = BIT(5), /* Addressed As Target */ 51 ISR_BUS_NOT_BUSY = BIT(4), /* IIC Bus is Not Busy */ 52 ISR_RX_FIFO_FULL = BIT(3), /* Receive FIFO Full */ 53 ISR_TX_FIFO_EMPTY = BIT(2), /* Transmit FIFO Empty */ 54 ISR_TX_ERR_TARGET_COMP = BIT(1), /* Transmit Error/Target Transmit Complete */ 55 ISR_ARB_LOST = BIT(0), /* Arbitration Lost */ 56 }; 57 58 /* Soft Reset */ 59 enum xilinx_axi_i2c_softr_vals { 60 SOFTR_KEY = 0xA, 61 }; 62 63 /* Control */ 64 enum xilinx_axi_i2c_cr_bits { 65 CR_GC_EN = BIT(6), /* General Call Enable */ 66 CR_RSTA = BIT(5), /* Repeated Start */ 67 CR_TXAK = BIT(4), /* Transmit Acknowledge Enable */ 68 CR_TX = BIT(3), /* Transmit/Receive Mode Select */ 69 CR_MSMS = BIT(2), /* Controller/Target Mode Select */ 70 CR_TX_FIFO_RST = BIT(1), /* Transmit FIFO Reset */ 71 CR_EN = BIT(0), /* AXI IIC Enable */ 72 }; 73 74 /* Status */ 75 enum xilinx_axi_i2c_sr_bits { 76 SR_TX_FIFO_EMPTY = BIT(7), /* Transmit FIFO empty */ 77 SR_RX_FIFO_EMPTY = BIT(6), /* Receive FIFO empty */ 78 SR_RX_FIFO_FULL = BIT(5), /* Receive FIFO full */ 79 SR_TX_FIFO_FULL = BIT(4), /* Transmit FIFO full */ 80 SR_SRW = BIT(3), /* Target Read/Write */ 81 SR_BB = BIT(2), /* Bus Busy */ 82 SR_AAS = BIT(1), /* Addressed As Target */ 83 SR_ABGC = BIT(0), /* Addressed By a General Call */ 84 }; 85 86 /* TX FIFO */ 87 enum xilinx_axi_i2c_tx_fifo_bits { 88 TX_FIFO_STOP = BIT(9), 89 TX_FIFO_START = BIT(8), 90 }; 91 92 /* RX FIFO */ 93 enum xilinx_axi_i2c_rx_fifo_bits { 94 RX_FIFO_DATA_MASK = 0xFF, 95 }; 96 97 /* TX_FIFO_OCY */ 98 enum xilinx_axi_i2c_tx_fifo_ocy_bits { 99 TX_FIFO_OCY_MASK = 0x0F, 100 }; 101 102 /* RX_FIFO_OCY */ 103 enum xilinx_axi_i2c_rx_fifo_ocy_bits { 104 RX_FIFO_OCY_MASK = 0x0F, 105 }; 106 107 /* other constants */ 108 enum { 109 /* Size of RX/TX FIFO */ 110 FIFO_SIZE = 16, 111 112 /* Maximum number of bytes that can be read in dynamic mode */ 113 MAX_DYNAMIC_READ_LEN = 255, 114 }; 115 116 #endif 117
