1 /* 2 * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_H 8 #define ARCH_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(24) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_VAR_MASK U(0xf) 20 #define MIDR_REV_SHIFT U(0) 21 #define MIDR_REV_BITS U(4) 22 #define MIDR_REV_MASK U(0xf) 23 #define MIDR_PN_MASK U(0xfff) 24 #define MIDR_PN_SHIFT U(4) 25 26 /******************************************************************************* 27 * MPIDR macros 28 ******************************************************************************/ 29 #define MPIDR_MT_MASK (U(1) << 24) 30 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 31 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 32 #define MPIDR_AFFINITY_BITS U(8) 33 #define MPIDR_AFFLVL_MASK U(0xff) 34 #define MPIDR_AFFLVL_SHIFT U(3) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 39 #define MPIDR_AFFINITY_MASK U(0x00ffffff) 40 #define MPIDR_AFFLVL0 U(0) 41 #define MPIDR_AFFLVL1 U(1) 42 #define MPIDR_AFFLVL2 U(2) 43 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 44 45 #define MPIDR_AFFLVL0_VAL(mpidr) \ 46 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 47 #define MPIDR_AFFLVL1_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL2_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL3_VAL(mpidr) U(0) 52 53 #define MPIDR_AFF_ID(mpid, n) \ 54 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 55 56 #define MPID_MASK (MPIDR_MT_MASK |\ 57 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\ 58 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\ 59 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 60 61 /* 62 * An invalid MPID. This value can be used by functions that return an MPID to 63 * indicate an error. 64 */ 65 #define INVALID_MPID U(0xFFFFFFFF) 66 67 /* 68 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 69 * add one while using this macro to define array sizes. 70 */ 71 #define MPIDR_MAX_AFFLVL U(2) 72 73 /* Data Cache set/way op type defines */ 74 #define DC_OP_ISW U(0x0) 75 #define DC_OP_CISW U(0x1) 76 #if ERRATA_A53_827319 77 #define DC_OP_CSW DC_OP_CISW 78 #else 79 #define DC_OP_CSW U(0x2) 80 #endif 81 82 /******************************************************************************* 83 * Generic timer memory mapped registers & offsets 84 ******************************************************************************/ 85 #define CNTCR_OFF U(0x000) 86 /* Counter Count Value Lower register */ 87 #define CNTCVL_OFF U(0x008) 88 /* Counter Count Value Upper register */ 89 #define CNTCVU_OFF U(0x00C) 90 #define CNTFID_OFF U(0x020) 91 92 #define CNTCR_EN (U(1) << 0) 93 #define CNTCR_HDBG (U(1) << 1) 94 #define CNTCR_FCREQ(x) ((x) << 8) 95 96 /******************************************************************************* 97 * System register bit definitions 98 ******************************************************************************/ 99 /* CLIDR definitions */ 100 #define LOUIS_SHIFT U(21) 101 #define LOC_SHIFT U(24) 102 #define CLIDR_FIELD_WIDTH U(3) 103 104 /* CSSELR definitions */ 105 #define LEVEL_SHIFT U(1) 106 107 /* ID_DFR0_EL1 definitions */ 108 #define ID_DFR0_COPTRC_SHIFT U(12) 109 #define ID_DFR0_COPTRC_MASK U(0xf) 110 #define ID_DFR0_COPTRC_SUPPORTED U(1) 111 #define ID_DFR0_COPTRC_LENGTH U(4) 112 #define ID_DFR0_TRACEFILT_SHIFT U(28) 113 #define ID_DFR0_TRACEFILT_MASK U(0xf) 114 #define ID_DFR0_TRACEFILT_SUPPORTED U(1) 115 #define ID_DFR0_TRACEFILT_LENGTH U(4) 116 117 /* ID_DFR1_EL1 definitions */ 118 #define ID_DFR1_MTPMU_SHIFT U(0) 119 #define ID_DFR1_MTPMU_MASK U(0xf) 120 #define ID_DFR1_MTPMU_SUPPORTED U(1) 121 122 /* ID_MMFR4 definitions */ 123 #define ID_MMFR4_CNP_SHIFT U(12) 124 #define ID_MMFR4_CNP_LENGTH U(4) 125 #define ID_MMFR4_CNP_MASK U(0xf) 126 127 #define ID_MMFR4_CCIDX_SHIFT U(24) 128 #define ID_MMFR4_CCIDX_LENGTH U(4) 129 #define ID_MMFR4_CCIDX_MASK U(0xf) 130 131 /* ID_PFR0 definitions */ 132 #define ID_PFR0_AMU_SHIFT U(20) 133 #define ID_PFR0_AMU_LENGTH U(4) 134 #define ID_PFR0_AMU_MASK U(0xf) 135 #define ID_PFR0_AMU_NOT_SUPPORTED U(0x0) 136 #define ID_PFR0_AMU_V1 U(0x1) 137 #define ID_PFR0_AMU_V1P1 U(0x2) 138 139 #define ID_PFR0_DIT_SHIFT U(24) 140 #define ID_PFR0_DIT_LENGTH U(4) 141 #define ID_PFR0_DIT_MASK U(0xf) 142 #define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT) 143 144 /* ID_PFR1 definitions */ 145 #define ID_PFR1_VIRTEXT_SHIFT U(12) 146 #define ID_PFR1_VIRTEXT_MASK U(0xf) 147 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 148 & ID_PFR1_VIRTEXT_MASK) 149 #define ID_PFR1_GENTIMER_SHIFT U(16) 150 #define ID_PFR1_GENTIMER_MASK U(0xf) 151 #define ID_PFR1_GIC_SHIFT U(28) 152 #define ID_PFR1_GIC_MASK U(0xf) 153 #define ID_PFR1_SEC_SHIFT U(4) 154 #define ID_PFR1_SEC_MASK U(0xf) 155 #define ID_PFR1_ELx_ENABLED U(1) 156 157 /* SCTLR definitions */ 158 #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \ 159 (U(1) << 3)) 160 #if ARM_ARCH_MAJOR == 7 161 #define SCTLR_RES1 SCTLR_RES1_DEF 162 #else 163 #define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11)) 164 #endif 165 #define SCTLR_M_BIT (U(1) << 0) 166 #define SCTLR_A_BIT (U(1) << 1) 167 #define SCTLR_C_BIT (U(1) << 2) 168 #define SCTLR_CP15BEN_BIT (U(1) << 5) 169 #define SCTLR_ITD_BIT (U(1) << 7) 170 #define SCTLR_Z_BIT (U(1) << 11) 171 #define SCTLR_I_BIT (U(1) << 12) 172 #define SCTLR_V_BIT (U(1) << 13) 173 #define SCTLR_RR_BIT (U(1) << 14) 174 #define SCTLR_NTWI_BIT (U(1) << 16) 175 #define SCTLR_NTWE_BIT (U(1) << 18) 176 #define SCTLR_WXN_BIT (U(1) << 19) 177 #define SCTLR_UWXN_BIT (U(1) << 20) 178 #define SCTLR_EE_BIT (U(1) << 25) 179 #define SCTLR_TRE_BIT (U(1) << 28) 180 #define SCTLR_AFE_BIT (U(1) << 29) 181 #define SCTLR_TE_BIT (U(1) << 30) 182 #define SCTLR_DSSBS_BIT (U(1) << 31) 183 #define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ 184 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT) 185 186 /* SDCR definitions */ 187 #define SDCR_SPD(x) ((x) << 14) 188 #define SDCR_SPD_LEGACY U(0x0) 189 #define SDCR_SPD_DISABLE U(0x2) 190 #define SDCR_SPD_ENABLE U(0x3) 191 #define SDCR_SCCD_BIT (U(1) << 23) 192 #define SDCR_TTRF_BIT (U(1) << 19) 193 #define SDCR_SPME_BIT (U(1) << 17) 194 #define SDCR_RESET_VAL U(0x0) 195 #define SDCR_MTPME_BIT (U(1) << 28) 196 197 /* HSCTLR definitions */ 198 #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 199 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 200 (U(1) << 11) | (U(1) << 4) | (U(1) << 3)) 201 202 #define HSCTLR_M_BIT (U(1) << 0) 203 #define HSCTLR_A_BIT (U(1) << 1) 204 #define HSCTLR_C_BIT (U(1) << 2) 205 #define HSCTLR_CP15BEN_BIT (U(1) << 5) 206 #define HSCTLR_ITD_BIT (U(1) << 7) 207 #define HSCTLR_SED_BIT (U(1) << 8) 208 #define HSCTLR_I_BIT (U(1) << 12) 209 #define HSCTLR_WXN_BIT (U(1) << 19) 210 #define HSCTLR_EE_BIT (U(1) << 25) 211 #define HSCTLR_TE_BIT (U(1) << 30) 212 213 /* CPACR definitions */ 214 #define CPACR_FPEN(x) ((x) << 20) 215 #define CPACR_FP_TRAP_PL0 UL(0x1) 216 #define CPACR_FP_TRAP_ALL UL(0x2) 217 #define CPACR_FP_TRAP_NONE UL(0x3) 218 219 /* SCR definitions */ 220 #define SCR_TWE_BIT (UL(1) << 13) 221 #define SCR_TWI_BIT (UL(1) << 12) 222 #define SCR_SIF_BIT (UL(1) << 9) 223 #define SCR_HCE_BIT (UL(1) << 8) 224 #define SCR_SCD_BIT (UL(1) << 7) 225 #define SCR_NET_BIT (UL(1) << 6) 226 #define SCR_AW_BIT (UL(1) << 5) 227 #define SCR_FW_BIT (UL(1) << 4) 228 #define SCR_EA_BIT (UL(1) << 3) 229 #define SCR_FIQ_BIT (UL(1) << 2) 230 #define SCR_IRQ_BIT (UL(1) << 1) 231 #define SCR_NS_BIT (UL(1) << 0) 232 #define SCR_VALID_BIT_MASK U(0x33ff) 233 #define SCR_RESET_VAL U(0x0) 234 235 #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) 236 237 /* HCR definitions */ 238 #define HCR_TGE_BIT (U(1) << 27) 239 #define HCR_AMO_BIT (U(1) << 5) 240 #define HCR_IMO_BIT (U(1) << 4) 241 #define HCR_FMO_BIT (U(1) << 3) 242 #define HCR_RESET_VAL U(0x0) 243 244 /* CNTHCTL definitions */ 245 #define CNTHCTL_RESET_VAL U(0x0) 246 #define PL1PCEN_BIT (U(1) << 1) 247 #define PL1PCTEN_BIT (U(1) << 0) 248 249 /* CNTKCTL definitions */ 250 #define PL0PTEN_BIT (U(1) << 9) 251 #define PL0VTEN_BIT (U(1) << 8) 252 #define PL0PCTEN_BIT (U(1) << 0) 253 #define PL0VCTEN_BIT (U(1) << 1) 254 #define EVNTEN_BIT (U(1) << 2) 255 #define EVNTDIR_BIT (U(1) << 3) 256 #define EVNTI_SHIFT U(4) 257 #define EVNTI_MASK U(0xf) 258 259 /* HCPTR definitions */ 260 #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff)) 261 #define TCPAC_BIT (U(1) << 31) 262 #define TAM_SHIFT U(30) 263 #define TAM_BIT (U(1) << TAM_SHIFT) 264 #define TTA_BIT (U(1) << 20) 265 #define TCP11_BIT (U(1) << 11) 266 #define TCP10_BIT (U(1) << 10) 267 #define HCPTR_RESET_VAL HCPTR_RES1 268 269 /* VTTBR definitions */ 270 #define VTTBR_RESET_VAL ULL(0x0) 271 #define VTTBR_VMID_MASK ULL(0xff) 272 #define VTTBR_VMID_SHIFT U(48) 273 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 274 #define VTTBR_BADDR_SHIFT U(0) 275 276 /* HDCR definitions */ 277 #define HDCR_MTPME_BIT (U(1) << 28) 278 #define HDCR_HLP_BIT (U(1) << 26) 279 #define HDCR_HPME_BIT (U(1) << 7) 280 #define HDCR_RESET_VAL U(0x0) 281 282 /* HSTR definitions */ 283 #define HSTR_RESET_VAL U(0x0) 284 285 /* CNTHP_CTL definitions */ 286 #define CNTHP_CTL_RESET_VAL U(0x0) 287 288 /* NSACR definitions */ 289 #define NSASEDIS_BIT (U(1) << 15) 290 #define NSTRCDIS_BIT (U(1) << 20) 291 #define NSACR_CP11_BIT (U(1) << 11) 292 #define NSACR_CP10_BIT (U(1) << 10) 293 #define NSACR_IMP_DEF_MASK (U(0x7) << 16) 294 #define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT) 295 #define NSACR_RESET_VAL U(0x0) 296 297 /* CPACR definitions */ 298 #define ASEDIS_BIT (U(1) << 31) 299 #define TRCDIS_BIT (U(1) << 28) 300 #define CPACR_CP11_SHIFT U(22) 301 #define CPACR_CP10_SHIFT U(20) 302 #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\ 303 (U(0x3) << CPACR_CP10_SHIFT)) 304 #define CPACR_RESET_VAL U(0x0) 305 306 /* FPEXC definitions */ 307 #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8)) 308 #define FPEXC_EN_BIT (U(1) << 30) 309 #define FPEXC_RESET_VAL FPEXC_RES1 310 311 /* SPSR/CPSR definitions */ 312 #define SPSR_FIQ_BIT (U(1) << 0) 313 #define SPSR_IRQ_BIT (U(1) << 1) 314 #define SPSR_ABT_BIT (U(1) << 2) 315 #define SPSR_AIF_SHIFT U(6) 316 #define SPSR_AIF_MASK U(0x7) 317 318 #define SPSR_E_SHIFT U(9) 319 #define SPSR_E_MASK U(0x1) 320 #define SPSR_E_LITTLE U(0) 321 #define SPSR_E_BIG U(1) 322 323 #define SPSR_T_SHIFT U(5) 324 #define SPSR_T_MASK U(0x1) 325 #define SPSR_T_ARM U(0) 326 #define SPSR_T_THUMB U(1) 327 328 #define SPSR_MODE_SHIFT U(0) 329 #define SPSR_MODE_MASK U(0x7) 330 331 #define SPSR_SSBS_BIT BIT_32(23) 332 333 #define DISABLE_ALL_EXCEPTIONS \ 334 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) 335 336 #define CPSR_DIT_BIT (U(1) << 21) 337 /* 338 * TTBCR definitions 339 */ 340 #define TTBCR_EAE_BIT (U(1) << 31) 341 342 #define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28) 343 #define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28) 344 #define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28) 345 346 #define TTBCR_RGN1_OUTER_NC (U(0x0) << 26) 347 #define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26) 348 #define TTBCR_RGN1_OUTER_WT (U(0x2) << 26) 349 #define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26) 350 351 #define TTBCR_RGN1_INNER_NC (U(0x0) << 24) 352 #define TTBCR_RGN1_INNER_WBA (U(0x1) << 24) 353 #define TTBCR_RGN1_INNER_WT (U(0x2) << 24) 354 #define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24) 355 356 #define TTBCR_EPD1_BIT (U(1) << 23) 357 #define TTBCR_A1_BIT (U(1) << 22) 358 359 #define TTBCR_T1SZ_SHIFT U(16) 360 #define TTBCR_T1SZ_MASK U(0x7) 361 #define TTBCR_TxSZ_MIN U(0) 362 #define TTBCR_TxSZ_MAX U(7) 363 364 #define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12) 365 #define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 366 #define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 367 368 #define TTBCR_RGN0_OUTER_NC (U(0x0) << 10) 369 #define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10) 370 #define TTBCR_RGN0_OUTER_WT (U(0x2) << 10) 371 #define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10) 372 373 #define TTBCR_RGN0_INNER_NC (U(0x0) << 8) 374 #define TTBCR_RGN0_INNER_WBA (U(0x1) << 8) 375 #define TTBCR_RGN0_INNER_WT (U(0x2) << 8) 376 #define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8) 377 378 #define TTBCR_EPD0_BIT (U(1) << 7) 379 #define TTBCR_T0SZ_SHIFT U(0) 380 #define TTBCR_T0SZ_MASK U(0x7) 381 382 /* 383 * HTCR definitions 384 */ 385 #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23)) 386 387 #define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12) 388 #define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 389 #define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 390 391 #define HTCR_RGN0_OUTER_NC (U(0x0) << 10) 392 #define HTCR_RGN0_OUTER_WBA (U(0x1) << 10) 393 #define HTCR_RGN0_OUTER_WT (U(0x2) << 10) 394 #define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10) 395 396 #define HTCR_RGN0_INNER_NC (U(0x0) << 8) 397 #define HTCR_RGN0_INNER_WBA (U(0x1) << 8) 398 #define HTCR_RGN0_INNER_WT (U(0x2) << 8) 399 #define HTCR_RGN0_INNER_WBNA (U(0x3) << 8) 400 401 #define HTCR_T0SZ_SHIFT U(0) 402 #define HTCR_T0SZ_MASK U(0x7) 403 404 #define MODE_RW_SHIFT U(0x4) 405 #define MODE_RW_MASK U(0x1) 406 #define MODE_RW_32 U(0x1) 407 408 #define MODE32_SHIFT U(0) 409 #define MODE32_MASK U(0x1f) 410 #define MODE32_usr U(0x10) 411 #define MODE32_fiq U(0x11) 412 #define MODE32_irq U(0x12) 413 #define MODE32_svc U(0x13) 414 #define MODE32_mon U(0x16) 415 #define MODE32_abt U(0x17) 416 #define MODE32_hyp U(0x1a) 417 #define MODE32_und U(0x1b) 418 #define MODE32_sys U(0x1f) 419 420 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 421 422 #define SPSR_MODE32(mode, isa, endian, aif) \ 423 ( \ 424 ( \ 425 (MODE_RW_32 << MODE_RW_SHIFT) | \ 426 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 427 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 428 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 429 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \ 430 ) & \ 431 (~(SPSR_SSBS_BIT)) \ 432 ) 433 434 /* 435 * TTBR definitions 436 */ 437 #define TTBR_CNP_BIT ULL(0x1) 438 439 /* 440 * CTR definitions 441 */ 442 #define CTR_CWG_SHIFT U(24) 443 #define CTR_CWG_MASK U(0xf) 444 #define CTR_ERG_SHIFT U(20) 445 #define CTR_ERG_MASK U(0xf) 446 #define CTR_DMINLINE_SHIFT U(16) 447 #define CTR_DMINLINE_WIDTH U(4) 448 #define CTR_DMINLINE_MASK ((U(1) << 4) - U(1)) 449 #define CTR_L1IP_SHIFT U(14) 450 #define CTR_L1IP_MASK U(0x3) 451 #define CTR_IMINLINE_SHIFT U(0) 452 #define CTR_IMINLINE_MASK U(0xf) 453 454 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 455 456 /* PMCR definitions */ 457 #define PMCR_N_SHIFT U(11) 458 #define PMCR_N_MASK U(0x1f) 459 #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) 460 #define PMCR_LP_BIT (U(1) << 7) 461 #define PMCR_LC_BIT (U(1) << 6) 462 #define PMCR_DP_BIT (U(1) << 5) 463 #define PMCR_RESET_VAL U(0x0) 464 465 /******************************************************************************* 466 * Definitions of register offsets, fields and macros for CPU system 467 * instructions. 468 ******************************************************************************/ 469 470 #define TLBI_ADDR_SHIFT U(0) 471 #define TLBI_ADDR_MASK U(0xFFFFF000) 472 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 473 474 /******************************************************************************* 475 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 476 * system level implementation of the Generic Timer. 477 ******************************************************************************/ 478 #define CNTCTLBASE_CNTFRQ U(0x0) 479 #define CNTNSAR U(0x4) 480 #define CNTNSAR_NS_SHIFT(x) (x) 481 482 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 483 #define CNTACR_RPCT_SHIFT U(0x0) 484 #define CNTACR_RVCT_SHIFT U(0x1) 485 #define CNTACR_RFRQ_SHIFT U(0x2) 486 #define CNTACR_RVOFF_SHIFT U(0x3) 487 #define CNTACR_RWVT_SHIFT U(0x4) 488 #define CNTACR_RWPT_SHIFT U(0x5) 489 490 /******************************************************************************* 491 * Definitions of register offsets and fields in the CNTBaseN Frame of the 492 * system level implementation of the Generic Timer. 493 ******************************************************************************/ 494 /* Physical Count register. */ 495 #define CNTPCT_LO U(0x0) 496 /* Counter Frequency register. */ 497 #define CNTBASEN_CNTFRQ U(0x10) 498 /* Physical Timer CompareValue register. */ 499 #define CNTP_CVAL_LO U(0x20) 500 /* Physical Timer Control register. */ 501 #define CNTP_CTL U(0x2c) 502 503 /* Physical timer control register bit fields shifts and masks */ 504 #define CNTP_CTL_ENABLE_SHIFT 0 505 #define CNTP_CTL_IMASK_SHIFT 1 506 #define CNTP_CTL_ISTATUS_SHIFT 2 507 508 #define CNTP_CTL_ENABLE_MASK U(1) 509 #define CNTP_CTL_IMASK_MASK U(1) 510 #define CNTP_CTL_ISTATUS_MASK U(1) 511 512 /* MAIR macros */ 513 #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3))) 514 #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3))) 515 516 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ 517 #define SCR p15, 0, c1, c1, 0 518 #define SCTLR p15, 0, c1, c0, 0 519 #define ACTLR p15, 0, c1, c0, 1 520 #define SDCR p15, 0, c1, c3, 1 521 #define MPIDR p15, 0, c0, c0, 5 522 #define MIDR p15, 0, c0, c0, 0 523 #define HVBAR p15, 4, c12, c0, 0 524 #define VBAR p15, 0, c12, c0, 0 525 #define MVBAR p15, 0, c12, c0, 1 526 #define NSACR p15, 0, c1, c1, 2 527 #define CPACR p15, 0, c1, c0, 2 528 #define DCCIMVAC p15, 0, c7, c14, 1 529 #define DCCMVAC p15, 0, c7, c10, 1 530 #define DCIMVAC p15, 0, c7, c6, 1 531 #define DCCISW p15, 0, c7, c14, 2 532 #define DCCSW p15, 0, c7, c10, 2 533 #define DCISW p15, 0, c7, c6, 2 534 #define CTR p15, 0, c0, c0, 1 535 #define CNTFRQ p15, 0, c14, c0, 0 536 #define ID_MMFR4 p15, 0, c0, c2, 6 537 #define ID_DFR0 p15, 0, c0, c1, 2 538 #define ID_DFR1 p15, 0, c0, c3, 5 539 #define ID_PFR0 p15, 0, c0, c1, 0 540 #define ID_PFR1 p15, 0, c0, c1, 1 541 #define MAIR0 p15, 0, c10, c2, 0 542 #define MAIR1 p15, 0, c10, c2, 1 543 #define TTBCR p15, 0, c2, c0, 2 544 #define TTBR0 p15, 0, c2, c0, 0 545 #define TTBR1 p15, 0, c2, c0, 1 546 #define TLBIALL p15, 0, c8, c7, 0 547 #define TLBIALLH p15, 4, c8, c7, 0 548 #define TLBIALLIS p15, 0, c8, c3, 0 549 #define TLBIMVA p15, 0, c8, c7, 1 550 #define TLBIMVAA p15, 0, c8, c7, 3 551 #define TLBIMVAAIS p15, 0, c8, c3, 3 552 #define TLBIMVAHIS p15, 4, c8, c3, 1 553 #define BPIALLIS p15, 0, c7, c1, 6 554 #define BPIALL p15, 0, c7, c5, 6 555 #define ICIALLU p15, 0, c7, c5, 0 556 #define HSCTLR p15, 4, c1, c0, 0 557 #define HCR p15, 4, c1, c1, 0 558 #define HCPTR p15, 4, c1, c1, 2 559 #define HSTR p15, 4, c1, c1, 3 560 #define CNTHCTL p15, 4, c14, c1, 0 561 #define CNTKCTL p15, 0, c14, c1, 0 562 #define VPIDR p15, 4, c0, c0, 0 563 #define VMPIDR p15, 4, c0, c0, 5 564 #define ISR p15, 0, c12, c1, 0 565 #define CLIDR p15, 1, c0, c0, 1 566 #define CSSELR p15, 2, c0, c0, 0 567 #define CCSIDR p15, 1, c0, c0, 0 568 #define CCSIDR2 p15, 1, c0, c0, 2 569 #define HTCR p15, 4, c2, c0, 2 570 #define HMAIR0 p15, 4, c10, c2, 0 571 #define ATS1CPR p15, 0, c7, c8, 0 572 #define ATS1HR p15, 4, c7, c8, 0 573 #define DBGOSDLR p14, 0, c1, c3, 4 574 575 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 576 #define HDCR p15, 4, c1, c1, 1 577 #define PMCR p15, 0, c9, c12, 0 578 #define CNTHP_TVAL p15, 4, c14, c2, 0 579 #define CNTHP_CTL p15, 4, c14, c2, 1 580 581 /* AArch32 coproc registers for 32bit MMU descriptor support */ 582 #define PRRR p15, 0, c10, c2, 0 583 #define NMRR p15, 0, c10, c2, 1 584 #define DACR p15, 0, c3, c0, 0 585 586 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 587 #define ICC_IAR1 p15, 0, c12, c12, 0 588 #define ICC_IAR0 p15, 0, c12, c8, 0 589 #define ICC_EOIR1 p15, 0, c12, c12, 1 590 #define ICC_EOIR0 p15, 0, c12, c8, 1 591 #define ICC_HPPIR1 p15, 0, c12, c12, 2 592 #define ICC_HPPIR0 p15, 0, c12, c8, 2 593 #define ICC_BPR1 p15, 0, c12, c12, 3 594 #define ICC_BPR0 p15, 0, c12, c8, 3 595 #define ICC_DIR p15, 0, c12, c11, 1 596 #define ICC_PMR p15, 0, c4, c6, 0 597 #define ICC_RPR p15, 0, c12, c11, 3 598 #define ICC_CTLR p15, 0, c12, c12, 4 599 #define ICC_MCTLR p15, 6, c12, c12, 4 600 #define ICC_SRE p15, 0, c12, c12, 5 601 #define ICC_HSRE p15, 4, c12, c9, 5 602 #define ICC_MSRE p15, 6, c12, c12, 5 603 #define ICC_IGRPEN0 p15, 0, c12, c12, 6 604 #define ICC_IGRPEN1 p15, 0, c12, c12, 7 605 #define ICC_MGRPEN1 p15, 6, c12, c12, 7 606 607 /* 64 bit system register defines The format is: coproc, opt1, CRm */ 608 #define TTBR0_64 p15, 0, c2 609 #define TTBR1_64 p15, 1, c2 610 #define CNTVOFF_64 p15, 4, c14 611 #define VTTBR_64 p15, 6, c2 612 #define CNTPCT_64 p15, 0, c14 613 #define HTTBR_64 p15, 4, c2 614 #define CNTHP_CVAL_64 p15, 6, c14 615 #define PAR_64 p15, 0, c7 616 617 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */ 618 #define ICC_SGI1R_EL1_64 p15, 0, c12 619 #define ICC_ASGI1R_EL1_64 p15, 1, c12 620 #define ICC_SGI0R_EL1_64 p15, 2, c12 621 622 /* Fault registers. The format is: coproc, opt1, CRn, CRm, opt2 */ 623 #define DFSR p15, 0, c5, c0, 0 624 #define IFSR p15, 0, c5, c0, 1 625 #define DFAR p15, 0, c6, c0, 0 626 #define IFAR p15, 0, c6, c0, 2 627 628 /******************************************************************************* 629 * Definitions of MAIR encodings for device and normal memory 630 ******************************************************************************/ 631 /* 632 * MAIR encodings for device memory attributes. 633 */ 634 #define MAIR_DEV_nGnRnE U(0x0) 635 #define MAIR_DEV_nGnRE U(0x4) 636 #define MAIR_DEV_nGRE U(0x8) 637 #define MAIR_DEV_GRE U(0xc) 638 639 /* 640 * MAIR encodings for normal memory attributes. 641 * 642 * Cache Policy 643 * WT: Write Through 644 * WB: Write Back 645 * NC: Non-Cacheable 646 * 647 * Transient Hint 648 * NTR: Non-Transient 649 * TR: Transient 650 * 651 * Allocation Policy 652 * RA: Read Allocate 653 * WA: Write Allocate 654 * RWA: Read and Write Allocate 655 * NA: No Allocation 656 */ 657 #define MAIR_NORM_WT_TR_WA U(0x1) 658 #define MAIR_NORM_WT_TR_RA U(0x2) 659 #define MAIR_NORM_WT_TR_RWA U(0x3) 660 #define MAIR_NORM_NC U(0x4) 661 #define MAIR_NORM_WB_TR_WA U(0x5) 662 #define MAIR_NORM_WB_TR_RA U(0x6) 663 #define MAIR_NORM_WB_TR_RWA U(0x7) 664 #define MAIR_NORM_WT_NTR_NA U(0x8) 665 #define MAIR_NORM_WT_NTR_WA U(0x9) 666 #define MAIR_NORM_WT_NTR_RA U(0xa) 667 #define MAIR_NORM_WT_NTR_RWA U(0xb) 668 #define MAIR_NORM_WB_NTR_NA U(0xc) 669 #define MAIR_NORM_WB_NTR_WA U(0xd) 670 #define MAIR_NORM_WB_NTR_RA U(0xe) 671 #define MAIR_NORM_WB_NTR_RWA U(0xf) 672 673 #define MAIR_NORM_OUTER_SHIFT U(4) 674 675 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 676 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 677 678 /* PAR fields */ 679 #define PAR_F_SHIFT U(0) 680 #define PAR_F_MASK ULL(0x1) 681 #define PAR_ADDR_SHIFT U(12) 682 #define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */ 683 684 /******************************************************************************* 685 * Definitions for system register interface to AMU for FEAT_AMUv1 686 ******************************************************************************/ 687 #define AMCR p15, 0, c13, c2, 0 688 #define AMCFGR p15, 0, c13, c2, 1 689 #define AMCGCR p15, 0, c13, c2, 2 690 #define AMUSERENR p15, 0, c13, c2, 3 691 #define AMCNTENCLR0 p15, 0, c13, c2, 4 692 #define AMCNTENSET0 p15, 0, c13, c2, 5 693 #define AMCNTENCLR1 p15, 0, c13, c3, 0 694 #define AMCNTENSET1 p15, 0, c13, c3, 1 695 696 /* Activity Monitor Group 0 Event Counter Registers */ 697 #define AMEVCNTR00 p15, 0, c0 698 #define AMEVCNTR01 p15, 1, c0 699 #define AMEVCNTR02 p15, 2, c0 700 #define AMEVCNTR03 p15, 3, c0 701 702 /* Activity Monitor Group 0 Event Type Registers */ 703 #define AMEVTYPER00 p15, 0, c13, c6, 0 704 #define AMEVTYPER01 p15, 0, c13, c6, 1 705 #define AMEVTYPER02 p15, 0, c13, c6, 2 706 #define AMEVTYPER03 p15, 0, c13, c6, 3 707 708 /* Activity Monitor Group 1 Event Counter Registers */ 709 #define AMEVCNTR10 p15, 0, c4 710 #define AMEVCNTR11 p15, 1, c4 711 #define AMEVCNTR12 p15, 2, c4 712 #define AMEVCNTR13 p15, 3, c4 713 #define AMEVCNTR14 p15, 4, c4 714 #define AMEVCNTR15 p15, 5, c4 715 #define AMEVCNTR16 p15, 6, c4 716 #define AMEVCNTR17 p15, 7, c4 717 #define AMEVCNTR18 p15, 0, c5 718 #define AMEVCNTR19 p15, 1, c5 719 #define AMEVCNTR1A p15, 2, c5 720 #define AMEVCNTR1B p15, 3, c5 721 #define AMEVCNTR1C p15, 4, c5 722 #define AMEVCNTR1D p15, 5, c5 723 #define AMEVCNTR1E p15, 6, c5 724 #define AMEVCNTR1F p15, 7, c5 725 726 /* Activity Monitor Group 1 Event Type Registers */ 727 #define AMEVTYPER10 p15, 0, c13, c14, 0 728 #define AMEVTYPER11 p15, 0, c13, c14, 1 729 #define AMEVTYPER12 p15, 0, c13, c14, 2 730 #define AMEVTYPER13 p15, 0, c13, c14, 3 731 #define AMEVTYPER14 p15, 0, c13, c14, 4 732 #define AMEVTYPER15 p15, 0, c13, c14, 5 733 #define AMEVTYPER16 p15, 0, c13, c14, 6 734 #define AMEVTYPER17 p15, 0, c13, c14, 7 735 #define AMEVTYPER18 p15, 0, c13, c15, 0 736 #define AMEVTYPER19 p15, 0, c13, c15, 1 737 #define AMEVTYPER1A p15, 0, c13, c15, 2 738 #define AMEVTYPER1B p15, 0, c13, c15, 3 739 #define AMEVTYPER1C p15, 0, c13, c15, 4 740 #define AMEVTYPER1D p15, 0, c13, c15, 5 741 #define AMEVTYPER1E p15, 0, c13, c15, 6 742 #define AMEVTYPER1F p15, 0, c13, c15, 7 743 744 /* AMCNTENSET0 definitions */ 745 #define AMCNTENSET0_Pn_SHIFT U(0) 746 #define AMCNTENSET0_Pn_MASK U(0xffff) 747 748 /* AMCNTENSET1 definitions */ 749 #define AMCNTENSET1_Pn_SHIFT U(0) 750 #define AMCNTENSET1_Pn_MASK U(0xffff) 751 752 /* AMCNTENCLR0 definitions */ 753 #define AMCNTENCLR0_Pn_SHIFT U(0) 754 #define AMCNTENCLR0_Pn_MASK U(0xffff) 755 756 /* AMCNTENCLR1 definitions */ 757 #define AMCNTENCLR1_Pn_SHIFT U(0) 758 #define AMCNTENCLR1_Pn_MASK U(0xffff) 759 760 /* AMCR definitions */ 761 #define AMCR_CG1RZ_SHIFT U(17) 762 #define AMCR_CG1RZ_BIT (ULL(1) << AMCR_CG1RZ_SHIFT) 763 764 /* AMCFGR definitions */ 765 #define AMCFGR_NCG_SHIFT U(28) 766 #define AMCFGR_NCG_MASK U(0xf) 767 #define AMCFGR_N_SHIFT U(0) 768 #define AMCFGR_N_MASK U(0xff) 769 770 /* AMCGCR definitions */ 771 #define AMCGCR_CG0NC_SHIFT U(0) 772 #define AMCGCR_CG0NC_MASK U(0xff) 773 #define AMCGCR_CG1NC_SHIFT U(8) 774 #define AMCGCR_CG1NC_MASK U(0xff) 775 776 /******************************************************************************* 777 * Definitions for DynamicIQ Shared Unit registers 778 ******************************************************************************/ 779 #define CLUSTERPWRDN p15, 0, c15, c3, 6 780 781 /* CLUSTERPWRDN register definitions */ 782 #define DSU_CLUSTER_PWR_OFF 0 783 #define DSU_CLUSTER_PWR_ON 1 784 #define DSU_CLUSTER_PWR_MASK U(1) 785 786 #endif /* ARCH_H */ 787
