1 /*! 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * 5 * \file tsm_timing_ble.h 6 * Header file for the BLE TSM timing definitions. 7 * 8 * Redistribution and use in source and binary forms, with or without modification, 9 * are permitted provided that the following conditions are met: 10 * 11 * o Redistributions of source code must retain the above copyright notice, this list 12 * of conditions and the following disclaimer. 13 * 14 * o Redistributions in binary form must reproduce the above copyright notice, this 15 * list of conditions and the following disclaimer in the documentation and/or 16 * other materials provided with the distribution. 17 * 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 19 * contributors may be used to endorse or promote products derived from this 20 * software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef TSM_TIMING_BLE_H 35 #define TSM_TIMING_BLE_H 36 37 /*! ********************************************************************************* 38 ************************************************************************************* 39 * Include 40 ************************************************************************************* 41 ********************************************************************************** */ 42 #include "BLEDefaults.h" 43 44 /*! ********************************************************************************* 45 ************************************************************************************* 46 * Macros 47 ************************************************************************************* 48 ********************************************************************************** */ 49 50 /* *** Common TSM defines *** */ 51 #define TSM_SIG_DIS (0xFF) /* Setting start and end time to 0xFF disables a signal */ 52 /*Assertion time setting for signal or group TX sequence.*/ 53 #define TSM_TX_HI_MASK 0xFF 54 #define TSM_TX_HI_SHIFT 0 55 /*Deassertion time setting for signal or group TX sequence.*/ 56 #define TSM_TX_LO_MASK 0xFF00 57 #define TSM_TX_LO_SHIFT 8 58 /*Assertion time setting for signal or group RX sequence.*/ 59 #define TSM_RX_HI_MASK 0xFF0000 60 #define TSM_RX_HI_SHIFT 16 61 /*Deassertion time setting for signal or group TX sequence.*/ 62 #define TSM_RX_LO_MASK 0xFF000000 63 #define TSM_RX_LO_SHIFT 24 64 /* Make a register write value */ 65 #define TSM_REG_VALUE(rx_wd,rx_wu,tx_wd,tx_wu) ((((unsigned int)rx_wd<<TSM_RX_LO_SHIFT)&TSM_RX_LO_MASK) | \ 66 (((unsigned int)rx_wu<<TSM_RX_HI_SHIFT)&TSM_RX_HI_MASK) | \ 67 (((unsigned int)tx_wd<<TSM_TX_LO_SHIFT)&TSM_TX_LO_MASK) | \ 68 (((unsigned int)tx_wu<<TSM_TX_HI_SHIFT)&TSM_TX_HI_MASK)) 69 70 /* Shortcuts for TSM disabled signals */ 71 #define TSM_SIGNAL_TX_RX_DIS (0xFFFFFFFF) /* Entire signal is disabled */ 72 #define TSM_SIGNAL_RX_DIS (0xFFFF0000) /* RX portion of signal is disabled */ 73 #define TSM_SIGNAL_TX_DIS (0x0000FFFF) /* TX portion of signal is disabled */ 74 75 /* Define some delays that apply to entire TX or RX WU/WD sequences */ 76 #define TX_WU_START_DELAY (0) /* Delay for the whole startup sequence */ 77 #define TX_WD_START_DELAY (0) /* Delay for the whole shutdown sequence */ 78 #define RX_WU_START_DELAY (0) /* Delay for the whole startup sequence */ 79 #define RX_WD_START_DELAY (0) /* Delay for the whole shutdown sequence */ 80 #define RX_WD_COMMON_DELAY (3) /* Delay for the end of the whole shutdown sequence */ 81 82 /* Define TX PA Ramp UP/DOWN time */ 83 #define PA_RAMP_2US (2+1) /* 2 microseconds ramp plus 1 for settling */ 84 85 /* Define PA_BIAS_TBL entries */ 86 #define PA_BIAS_ENTRIES_2US {1,2,4,6,8,10,13,15} 87 88 #define PA_RAMP_TIME (PA_RAMP_2US) /* Ramp up/down time in microseconds */ 89 #define TXDIG_RAMP_DOWN_TIME (PA_RAMP_2US) /* Ramp up/down time in microseconds */ 90 #define PA_BIAS_ENTRIES PA_BIAS_ENTRIES_2US 91 92 /* Data padding time constant */ 93 #define DATA_PADDING_TIME (8) /* Data padding is always ON */ 94 95 /* Define some specifics about regulators,PLL, ADC, how long to settle and whether to sequence startup */ 96 #define REG_WU_TIME (10) /* Regulators are completely up at this point */ 97 #define REG_WU_SKEW (0) /* Each reg starts up SKEW microsec later than the last */ 98 #define PLL_CTUNE_TIME (15) /* CTUNE algorithm time */ 99 #define PLL_HPMCAL1_TIME (25) /* HPMCAL1 algorithm time */ 100 #define PLL_HPMCAL2_TIME (25) /* HPMCAL2 algorithm time */ 101 #define PLL_SEQ_SETTLE (1) /* Settling time between PLL sequence changes. */ 102 #define TX_PLL_LOCK_TIME (16) /* Time from completion of CTUNE/HPMCAL process */ 103 #define RX_PLL_LOCK_TIME (25) /* Time from completion of CTUNE/HPMCAL process */ 104 #define ADC_PRECHARGE_TIME (6) /* Time for ADC precharge enable to be held high */ 105 #define ADC_RST_TIME (1) /* Time for ADC reset enable to be held high */ 106 #define AGC_SEQ_SETTLE (8) /* Settling time between AGC sequence changes. */ 107 #define AGC_ADAPT_TIME (10) /* Time for AGC to adapt in adaptation mode */ 108 #define DCOC_INIT_TIME (1) /* Length of DCOC init pulse */ 109 #define DCOC_TIME (70) /* Time for DCOC to complete, compare to PLL Lock for RX */ 110 #define RX_INIT_TIME (1) /* Length of RX init pulse */ 111 #define RX_INIT_SETTLE_TIME (1) /* Setting time after RX init pulse deasserts */ 112 113 #define DCOC_ADJUST_WORKAROUND (0) /* DEPRECATED - SHOULD ALWAYS BE ZERO! */ 114 #define PDET_RESET_WORKAROUND (0) /* DEPRECATED - SHOULD ALWAYS BE ZERO! */ 115 116 /* Define overlaps between different startup groups where some startup can be done 117 * in parallel. Overlap between later REG startup and initial PLL startup 118 */ 119 #define REG_PLL_WU_OVERLAP (5) /* Start PLL WU this long before regs startup completes. */ 120 121 /* Prep time for PLL lock start, how much earlier sigma-delta, PHDET, & PLL filter can start */ 122 #define PLL_LOCK_PREP_TIME (10) /* Start a set of signals this amount before PLL_LOCK_START_TIME */ 123 124 /* TX warmup sequence timings */ 125 #define PLL_REG_EN_TX_WU (TX_WU_START_DELAY) /* This is the first signal in the sequences */ 126 #define PLL_VCO_REG_EN_TX_WU (PLL_REG_EN_TX_WU+REG_WU_SKEW) /* Same as PLL_REG_EN_TX_WU or +SKEW */ 127 #define PLL_QGEN_REG_EN_TX_WU (PLL_VCO_REG_EN_TX_WU+REG_WU_SKEW) /* Same as PLL_VCO_REG_EN_TX_WU or +SKEW */ 128 #define PLL_TCA_TX_REG_EN_TX_WU (PLL_QGEN_REG_EN_TX_WU+REG_WU_SKEW) /* Same as PLL_QGEN_REG_EN_TX_WU or +SKEW */ 129 130 #define PLL_VCO_AUTOTUNE_TX_WU (TX_WU_START_DELAY) /* Enable AUTOTUNE at the start of the WU sequence */ 131 132 #define PLL_VCO_EN_TX_WU (TX_WU_START_DELAY+REG_WU_TIME+(4*REG_WU_SKEW)- 7 /*REG_PLL_WU_OVERLAP*/) /* Account for overlap in REG & PLL startups */ 133 #define PLL_DIG_EN_TX_WU (PLL_VCO_EN_TX_WU+16) /* This is the start of PLL calibration sequence */ 134 #define PLL_VCO_BUF_TX_EN_TX_WU (PLL_VCO_EN_TX_WU+2) /* Turn on buffer 2us after vco_en */ 135 #define PLL_TX_LDV_RIPPLE_MUX_EN_TX_WU (PLL_VCO_BUF_TX_EN_TX_WU) /* Ripple counter on */ 136 137 #define PLL_LOCK_START_TIME_TX (PLL_DIG_EN_TX_WU+PLL_CTUNE_TIME+PLL_HPMCAL1_TIME+PLL_HPMCAL2_TIME+(4*PLL_SEQ_SETTLE)) 138 #define PLL_REF_CLK_EN_TX_WU (PLL_LOCK_START_TIME_TX-PLL_LOCK_PREP_TIME-5) /* Relative to start of PLL lock */ 139 #define PLL_FILTER_CHARGE_EN_TX_WU (PLL_LOCK_START_TIME_TX-PLL_LOCK_PREP_TIME) /* Relative to start of PLL lock */ 140 #define PLL_PHDET_EN_TX_WU (PLL_LOCK_START_TIME_TX-PLL_LOCK_PREP_TIME) /* Relative to start of PLL lock */ 141 #define SIGMA_DELTA_EN_TX_WU (PLL_LOCK_START_TIME_TX-PLL_LOCK_PREP_TIME) /* Relative to start of PLL lock */ 142 #define PLL_LDV_EN_TX_WU (PLL_LOCK_START_TIME_TX) /* Can start LDV enable right at lock start */ 143 #define PLL_LOCKED_TIME_TX (PLL_LOCK_START_TIME_TX+TX_PLL_LOCK_TIME) 144 #define TX_EN_TX_WU (PLL_LOCKED_TIME_TX) 145 #define PLL_PA_BUF_EN_TX_WU (TX_EN_TX_WU) /* 1 usec before TX_EN */ 146 #define PLL_CYCLE_SLIP_LD_EN_TX_WU (PLL_LOCKED_TIME_TX+3) 147 #define TX_DIG_EN_TX_WU (PLL_CYCLE_SLIP_LD_EN_TX_WU-DATA_PADDING_TIME) /* Affected by padding (must start earlier for padding) */ 148 #define FREQ_TARG_LD_EN_TX_WU (PLL_CYCLE_SLIP_LD_EN_TX_WU+2) /* Asserted concurrent with end of warmup */ 149 #define END_OF_TX_WARMUP (PLL_CYCLE_SLIP_LD_EN_TX_WU+6) /* End of warmup is driven by 6us delay from end of ramp to allow for settling */ 150 151 /* Unused signals */ 152 #define ADC_REG_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 153 #define ADC_CLK_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 154 #define PLL_VCO_BUF_RX_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 155 #define PLL_RX_LDV_RIPPLE_MUX_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 156 #define QGEN25_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 157 #define ADC_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 158 #define ADC_I_Q_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 159 #define ADC_DAC_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 160 #define ADC_RST_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 161 #define BBF_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 162 #define TCA_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 163 #define RX_DIG_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 164 #define RX_INIT_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 165 #define ZBDEM_RX_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 166 #define DCOC_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 167 #define DCOC_INIT_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 168 #define SAR_ADC_TRIG_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 169 #define TSM_SPARE0_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 170 #define TSM_SPARE1_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 171 #define TSM_SPARE2_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 172 #define TSM_SPARE03_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 173 #define GPIO0_TRIG_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 174 #define GPIO1_TRIG_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 175 #define GPIO2_TRIG_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 176 #define GPIO3_TRIG_EN_TX_WU (TSM_SIG_DIS) /* Not used in TX scenarios */ 177 178 #define END_OF_TX_WU_BLE (END_OF_TX_WARMUP) /* This is the last signal */ 179 180 /* TX warmdown sequence timings */ 181 #define PLL_REG_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 182 #define PLL_VCO_REG_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 183 #define PLL_QGEN_REG_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 184 #define PLL_TCA_TX_REG_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 185 186 #define PLL_VCO_AUTOTUNE_TX_WD (PLL_LOCK_START_TIME_TX) /* End of PLL Lock sequence */ 187 #define PLL_VCO_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 188 #define PLL_DIG_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 189 #define PLL_VCO_BUF_TX_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 190 #define PLL_TX_LDV_RIPPLE_MUX_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 191 #define PLL_REF_CLK_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 192 #define PLL_FILTER_CHARGE_EN_TX_WD (PLL_LOCK_START_TIME_TX) /* End of PLL cal. sequence */ 193 #define PLL_PHDET_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 194 #define SIGMA_DELTA_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 195 #define PLL_LDV_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 196 #define PLL_CYCLE_SLIP_LD_EN_TX_WD (END_OF_TX_WU_BLE+1) /* End of warmdown, before PA ramps down */ 197 #define FREQ_TARG_LD_EN_TX_WD (END_OF_TX_WU_BLE+1) /* End of warmdown, before PA ramps down */ 198 #define TX_EN_TX_WD (END_OF_TX_WU_BLE+TXDIG_RAMP_DOWN_TIME) /* TX_DIG_EN has a special case for noramp warmdown! */ 199 #define PLL_PA_BUF_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 200 #define TX_DIG_EN_TX_WD (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* End of warmdown */ 201 202 /* Unused signals */ 203 #define ADC_REG_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 204 #define ADC_CLK_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 205 #define PLL_VCO_BUF_RX_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 206 #define PLL_RX_LDV_RIPPLE_MUX_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 207 #define QGEN25_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 208 #define ADC_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 209 #define ADC_I_Q_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 210 #define ADC_DAC_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 211 #define ADC_RST_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 212 #define BBF_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 213 #define TCA_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 214 #define RX_DIG_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 215 #define RX_INIT_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 216 #define ZBDEM_RX_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 217 #define DCOC_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 218 #define DCOC_INIT_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 219 #define SAR_ADC_TRIG_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 220 #define TSM_SPARE0_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 221 #define TSM_SPARE1_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 222 #define TSM_SPARE2_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 223 #define TSM_SPARE03_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 224 #define GPIO0_TRIG_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 225 #define GPIO1_TRIG_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 226 #define GPIO2_TRIG_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 227 #define GPIO3_TRIG_EN_TX_WD (TSM_SIG_DIS) /* Not used in TX scenarios */ 228 229 #define END_OF_TX_WD_BLE (END_OF_TX_WU_BLE+PA_RAMP_TIME) /* TX warmdown lasts only as long a PA rampdown */ 230 231 /* RX warmup sequence timings */ 232 #define PLL_REG_EN_RX_WU (RX_WU_START_DELAY) /* This is the first signal in the sequences */ 233 #define PLL_VCO_REG_EN_RX_WU (PLL_REG_EN_RX_WU+REG_WU_SKEW) /* Same as PLL_REG_EN_RX_WU or +SKEW */ 234 #define PLL_QGEN_REG_EN_RX_WU (PLL_VCO_REG_EN_RX_WU+REG_WU_SKEW) /* Same as PLL_VCO_REG_EN_RX_WU or +SKEW */ 235 #define PLL_TCA_TX_REG_EN_RX_WU (PLL_QGEN_REG_EN_RX_WU+REG_WU_SKEW) /* Same as PLL_QGEN_REG_EN_RX_WU or +SKEW */ 236 #define ADC_REG_EN_RX_WU (PLL_TCA_TX_REG_EN_RX_WU+REG_WU_SKEW) /* Same as PLL_TCA_TX_REG_EN_RX_WU or +SKEW */ 237 238 /* PLL startup */ 239 #define PLL_VCO_AUTOTUNE_RX_WU (RX_WU_START_DELAY) /* Enable AUTOTUNE at the start of the WU sequence */ 240 #define PLL_VCO_EN_RX_WU (RX_WU_START_DELAY+REG_WU_TIME+(5*REG_WU_SKEW)-REG_PLL_WU_OVERLAP-2) 241 #define QGEN25_EN_RX_WU (PLL_VCO_EN_RX_WU) /* Same as PLL_VCO_EN_RX_WU */ 242 #define PLL_VCO_BUF_RX_EN_RX_WU (RX_WU_START_DELAY+REG_WU_TIME+(5*REG_WU_SKEW)-REG_PLL_WU_OVERLAP) 243 #define PLL_RX_LDV_RIPPLE_MUX_EN_RX_WU (RX_WU_START_DELAY+REG_WU_TIME+(5*REG_WU_SKEW)-REG_PLL_WU_OVERLAP) 244 #define PLL_DIG_EN_RX_WU (PLL_RX_LDV_RIPPLE_MUX_EN_RX_WU+14) 245 246 /* RX PLL locking definitions */ 247 #define PLL_LOCK_START_TIME_RX (PLL_DIG_EN_RX_WU+PLL_CTUNE_TIME+(2*PLL_SEQ_SETTLE)) /* When locking starts */ 248 #define PLL_LOCKED_TIME_RX (PLL_LOCK_START_TIME_RX+RX_PLL_LOCK_TIME) /* When locking is complete */ 249 #define PLL_FILTER_CHARGE_EN_RX_WU (PLL_LOCK_START_TIME_RX-10) /* Starts 10us before locking starts */ 250 #define PLL_PHDET_EN_RX_WU (PLL_FILTER_CHARGE_EN_RX_WU) /* Same as PLL_FILTER_CHARGE_EN_RX_WU */ 251 #define PLL_LDV_EN_RX_WU (PLL_LOCK_START_TIME_RX) /* Not used in RX scenarios */ 252 #define SIGMA_DELTA_EN_RX_WU (PLL_FILTER_CHARGE_EN_RX_WU) /* Same as PLL_FILTER_CHARGE_EN_RX_WU */ 253 #define PLL_REF_CLK_EN_RX_WU (PLL_FILTER_CHARGE_EN_RX_WU-5) /* Starts 5us before PLL_FILTER_CHARGE_EN_RX_WU */ 254 #define FREQ_TARG_LD_EN_RX_WU (PLL_LOCKED_TIME_RX) /* Starts when PLL locking is complete */ 255 #define PLL_CYCLE_SLIP_LD_EN_RX_WU (PLL_LOCKED_TIME_RX) /* Starts when PLL locking is complete */ 256 #define ADC_EN_RX_WU (PLL_LOCK_START_TIME_RX-1) /* 1us before start of PLL locking */ 257 #define ADC_DAC_EN_RX_WU (ADC_EN_RX_WU) /* 1us before start of PLL locking */ 258 #define ADC_CLK_EN_RX_WU (ADC_EN_RX_WU) /* 1us before start of PLL locking */ 259 #define ADC_I_Q_EN_RX_WU (ADC_EN_RX_WU) /* 1us before start of PLL locking */ 260 #define ADC_RST_EN_RX_WU (ADC_EN_RX_WU+1) /* 1us after ADC enabled */ 261 #define BBF_EN_RX_WU (PLL_LOCK_START_TIME_RX-2) /* 2us before start of PLL locking */ 262 #define TCA_EN_RX_WU (BBF_EN_RX_WU) /* Same as BBF_EN_RX_WU */ 263 264 /* DCOC startup */ 265 #define DCOC_EN_RX_WU (ADC_RST_EN_RX_WU+ADC_RST_TIME+AGC_SEQ_SETTLE) /* Start DCOC after ADC reset */ 266 #define DCOC_INIT_EN_RX_WU (DCOC_EN_RX_WU) /* Same as DCOC_EN_RX_WU */ 267 268 /* Don't enable RX dig until both DCOC completes and PLL lock time is complete */ 269 #define DCOC_COMPLETED_TIME_RX (DCOC_EN_RX_WU+DCOC_TIME) 270 #define RX_DIG_EN_RX_WU ((DCOC_COMPLETED_TIME_RX>PLL_LOCKED_TIME_RX) ? DCOC_COMPLETED_TIME_RX : PLL_LOCKED_TIME_RX) 271 #define RX_INIT_RX_WU (RX_DIG_EN_RX_WU) 272 #define END_OF_RX_WU_BLE (RX_DIG_EN_RX_WU+RX_INIT_TIME+RX_INIT_SETTLE_TIME) /* End of RX WU */ 273 274 /* Unused signals */ 275 #define PLL_VCO_BUF_TX_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 276 #define PLL_PA_BUF_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 277 #define PLL_TX_LDV_RIPPLE_MUX_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 278 #define TX_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 279 #define TX_DIG_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 280 #define ZBDEM_RX_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 281 #define SAR_ADC_TRIG_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 282 #define TSM_SPARE0_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 283 #define TSM_SPARE1_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 284 #define TSM_SPARE2_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 285 #define TSM_SPARE03_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 286 #define GPIO0_TRIG_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 287 #define GPIO1_TRIG_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 288 #define GPIO2_TRIG_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 289 #define GPIO3_TRIG_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ 290 291 /* RX warmdown sequence timings */ 292 #define PLL_REG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 293 #define PLL_VCO_REG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 294 #define PLL_QGEN_REG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 295 #define PLL_TCA_TX_REG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 296 #define ADC_REG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 297 #define PLL_VCO_AUTOTUNE_RX_WD (PLL_LOCK_START_TIME_RX) /* Turn off AUTOTUNE at the start of the PLL locking sequence */ 298 #define PLL_VCO_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 299 #define QGEN25_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 300 #define PLL_VCO_BUF_RX_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 301 #define PLL_DIG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 302 #define PLL_RX_LDV_RIPPLE_MUX_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 303 #define PLL_FILTER_CHARGE_EN_RX_WD (PLL_FILTER_CHARGE_EN_RX_WU+10) /* 10us pulse */ 304 #define PLL_PHDET_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 305 #define PLL_LDV_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 306 #define SIGMA_DELTA_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 307 #define PLL_REF_CLK_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 308 #define FREQ_TARG_LD_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 309 #define PLL_CYCLE_SLIP_LD_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 310 #define ADC_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 311 #define ADC_DAC_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 312 #define ADC_CLK_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 313 #define ADC_I_Q_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 314 #define ADC_RST_EN_RX_WD (ADC_RST_EN_RX_WU+ADC_RST_TIME) /* Pulse length = ADC_RST_TIME */ 315 #define BBF_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 316 #define TCA_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 317 #define DCOC_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 318 #define DCOC_INIT_EN_RX_WD (DCOC_INIT_EN_RX_WU+DCOC_INIT_TIME) /* Pulse length = DCOC_INIT_TIME */ 319 #define RX_DIG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ 320 #define RX_INIT_RX_WD (RX_INIT_RX_WU+RX_INIT_TIME) /* Pulse length = RX_INIT_TIME */ 321 322 #if (DCOC_ADJUST_WORKAROUND) 323 #define GPIO0_TRIG_EN_RX_WD (DCOC_COMPLETED_TIME_RX) /* Release this signal at end of allocated time */ 324 #else 325 #define GPIO0_TRIG_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 326 #endif 327 328 /* Unused signals */ 329 #define PLL_VCO_BUF_TX_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 330 #define PLL_PA_BUF_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 331 #define PLL_TX_LDV_RIPPLE_MUX_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 332 #define TX_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 333 #define TX_DIG_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 334 #define ZBDEM_RX_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 335 #define SAR_ADC_TRIG_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 336 #define TSM_SPARE0_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 337 #define TSM_SPARE1_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 338 #define TSM_SPARE2_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 339 #define TSM_SPARE03_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 340 #define GPIO1_TRIG_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 341 #define GPIO2_TRIG_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 342 #define GPIO3_TRIG_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ 343 344 #define END_OF_RX_WD_BLE (END_OF_RX_WU_BLE+1) /* RX warmdown has no delay */ 345 346 #define END_OF_SEQ_VALUE ( (END_OF_RX_WD_BLE<<END_OF_SEQ_END_OF_RX_WD_SHIFT) | \ 347 (END_OF_RX_WU_BLE<<END_OF_SEQ_END_OF_RX_WU_SHIFT) | \ 348 (END_OF_TX_WD_BLE<<END_OF_SEQ_END_OF_TX_WD_SHIFT) | \ 349 (END_OF_TX_WU_BLE<<END_OF_SEQ_END_OF_TX_WU_SHIFT)) 350 351 /*! ********************************************************************************* 352 ************************************************************************************* 353 * Public prototypes 354 ************************************************************************************* 355 ********************************************************************************** */ 356 #ifdef __cplusplus 357 extern "C" 358 { 359 #endif 360 361 /* No functions defined, only timing data */ 362 363 #ifdef __cplusplus 364 } 365 #endif 366 367 368 #endif /* TSM_TIMING_BLE_H */ 369
