1 /*! 2 \file gd32f3x0_tsi.h 3 \brief definitions for the TSI 4 5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0 6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0 7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F3X0_TSI_H 38 #define GD32F3X0_TSI_H 39 40 #include "gd32f3x0.h" 41 42 /* TSI definitions */ 43 #define TSI TSI_BASE /*!< TSI base address */ 44 45 /* registers definitions */ 46 #define TSI_CTL0 REG32(TSI + 0x00000000U)/*!< TSI control register0 */ 47 #define TSI_INTEN REG32(TSI + 0x00000004U)/*!< TSI interrupt enable register */ 48 #define TSI_INTC REG32(TSI + 0x00000008U)/*!< TSI interrupt flag clear register */ 49 #define TSI_INTF REG32(TSI + 0x0000000CU)/*!< TSI interrupt flag register */ 50 #define TSI_PHM REG32(TSI + 0x00000010U)/*!< TSI pin hysteresis mode register */ 51 #define TSI_ASW REG32(TSI + 0x00000018U)/*!< TSI analog switch register */ 52 #define TSI_SAMPCFG REG32(TSI + 0x00000020U)/*!< TSI sample configuration register */ 53 #define TSI_CHCFG REG32(TSI + 0x00000028U)/*!< TSI channel configuration register */ 54 #define TSI_GCTL REG32(TSI + 0x00000030U)/*!< TSI group control register */ 55 #define TSI_G0CYCN REG32(TSI + 0x00000034U)/*!< TSI group 0 cycle number register */ 56 #define TSI_G1CYCN REG32(TSI + 0x00000038U)/*!< TSI group 1 cycle number register */ 57 #define TSI_G2CYCN REG32(TSI + 0x0000003CU)/*!< TSI group 2 cycle number register */ 58 #define TSI_G3CYCN REG32(TSI + 0x00000040U)/*!< TSI group 3 cycle number register */ 59 #define TSI_G4CYCN REG32(TSI + 0x00000044U)/*!< TSI group 4 cycle number register */ 60 #define TSI_G5CYCN REG32(TSI + 0x00000048U)/*!< TSI group 5 cycle number register */ 61 #define TSI_CTL1 REG32(TSI + 0x00000300U)/*!< TSI control registers1 */ 62 63 /* bits definitions */ 64 /* TSI_CTL0 */ 65 #define TSI_CTL0_TSIEN BIT(0) /*!< TSI enable */ 66 #define TSI_CTL0_TSIS BIT(1) /*!< TSI start */ 67 #define TSI_CTL0_TRGMOD BIT(2) /*!< trigger mode selection */ 68 #define TSI_CTL0_EGSEL BIT(3) /*!< edge selection */ 69 #define TSI_CTL0_PINMOD BIT(4) /*!< pin mode */ 70 #define TSI_CTL0_MCN BITS(5,7) /*!< max cycle number of a sequence */ 71 #define TSI_CTL0_CTCDIV BITS(12,14) /*!< CTCLK clock division factor */ 72 #define TSI_CTL0_ECDIV BIT(15) /*!< ECCLK clock division factor */ 73 #define TSI_CTL0_ECEN BIT(16) /*!< extend charge state enable */ 74 #define TSI_CTL0_ECDT BITS(17,23) /*!< extend charge State maximum duration time */ 75 #define TSI_CTL0_CTDT BITS(24,27) /*!< charge transfer state duration time */ 76 #define TSI_CTL0_CDT BITS(28,31) /*!< charge state duration time */ 77 78 /* TSI_INTEN */ 79 #define TSI_INTEN_CTCFIE BIT(0) /*!< charge transfer complete flag interrupt enable */ 80 #define TSI_INTEN_MNERRIE BIT(1) /*!< max cycle number error interrupt enable */ 81 82 /* TSI_INTC */ 83 #define TSI_INTC_CCTCF BIT(0) /*!< clear charge transfer complete flag */ 84 #define TSI_INTC_CMNERR BIT(1) /*!< clear max cycle number error */ 85 86 /* TSI_INTF */ 87 #define TSI_INTF_CTCF BIT(0) /*!< charge transfer complete flag */ 88 #define TSI_INTF_MNERR BIT(1) /*!< max cycle number error */ 89 90 /* TSI_PHM */ 91 #define TSI_PHM_G0P0 BIT(0) /*!< pin G0P0 Schmitt trigger hysteresis state */ 92 #define TSI_PHM_G0P1 BIT(1) /*!< pin G0P1 Schmitt trigger hysteresis state */ 93 #define TSI_PHM_G0P2 BIT(2) /*!< pin G0P2 Schmitt trigger hysteresis state */ 94 #define TSI_PHM_G0P3 BIT(3) /*!< pin G0P3 Schmitt trigger hysteresis state */ 95 #define TSI_PHM_G1P0 BIT(4) /*!< pin G1P0 Schmitt trigger hysteresis state */ 96 #define TSI_PHM_G1P1 BIT(5) /*!< pin G1P1 Schmitt trigger hysteresis state */ 97 #define TSI_PHM_G1P2 BIT(6) /*!< pin G1P2 Schmitt trigger hysteresis state */ 98 #define TSI_PHM_G1P3 BIT(7) /*!< pin G1P3 Schmitt trigger hysteresis state */ 99 #define TSI_PHM_G2P0 BIT(8) /*!< pin G2P0 Schmitt trigger hysteresis state */ 100 #define TSI_PHM_G2P1 BIT(9) /*!< pin G2P1 Schmitt trigger hysteresis state */ 101 #define TSI_PHM_G2P2 BIT(10) /*!< pin G2P2 Schmitt trigger hysteresis state */ 102 #define TSI_PHM_G2P3 BIT(11) /*!< pin G2P3 Schmitt trigger hysteresis state */ 103 #define TSI_PHM_G3P0 BIT(12) /*!< pin G3P0 Schmitt trigger hysteresis state */ 104 #define TSI_PHM_G3P1 BIT(13) /*!< pin G3P1 Schmitt trigger hysteresis state */ 105 #define TSI_PHM_G3P2 BIT(14) /*!< pin G3P2 Schmitt trigger hysteresis state */ 106 #define TSI_PHM_G3P3 BIT(15) /*!< pin G3P3 Schmitt trigger hysteresis state */ 107 #define TSI_PHM_G4P0 BIT(16) /*!< pin G4P0 Schmitt trigger hysteresis state */ 108 #define TSI_PHM_G4P1 BIT(17) /*!< pin G4P1 Schmitt trigger hysteresis state */ 109 #define TSI_PHM_G4P2 BIT(18) /*!< pin G4P2 Schmitt trigger hysteresis state */ 110 #define TSI_PHM_G4P3 BIT(19) /*!< pin G4P3 Schmitt trigger hysteresis state */ 111 #define TSI_PHM_G5P0 BIT(20) /*!< pin G5P0 Schmitt trigger hysteresis state */ 112 #define TSI_PHM_G5P1 BIT(21) /*!< pin G5P1 Schmitt trigger hysteresis state */ 113 #define TSI_PHM_G5P2 BIT(22) /*!< pin G5P2 Schmitt trigger hysteresis state */ 114 #define TSI_PHM_G5P3 BIT(23) /*!< pin G5P3 Schmitt trigger hysteresis state */ 115 116 /* TSI_ASW */ 117 #define TSI_ASW_G0P0 BIT(0) /*!< pin G0P0 analog switch state */ 118 #define TSI_ASW_G0P1 BIT(1) /*!< pin G0P1 analog switch state */ 119 #define TSI_ASW_G0P2 BIT(2) /*!< pin G0P2 analog switch state */ 120 #define TSI_ASW_G0P3 BIT(3) /*!< pin G0P3 analog switch state */ 121 #define TSI_ASW_G1P0 BIT(4) /*!< pin G1P0 analog switch state */ 122 #define TSI_ASW_G1P1 BIT(5) /*!< pin G1P1 analog switch state */ 123 #define TSI_ASW_G1P2 BIT(6) /*!< pin G1P2 analog switch state */ 124 #define TSI_ASW_G1P3 BIT(7) /*!< pin G1P3 analog switch state */ 125 #define TSI_ASW_G2P0 BIT(8) /*!< pin G2P0 analog switch state */ 126 #define TSI_ASW_G2P1 BIT(9) /*!< pin G2P1 analog switch state */ 127 #define TSI_ASW_G2P2 BIT(10) /*!< pin G2P2 analog switch state */ 128 #define TSI_ASW_G2P3 BIT(11) /*!< pin G2P3 analog switch state */ 129 #define TSI_ASW_G3P0 BIT(12) /*!< pin G3P0 analog switch state */ 130 #define TSI_ASW_G3P1 BIT(13) /*!< pin G3P1 analog switch state */ 131 #define TSI_ASW_G3P2 BIT(14) /*!< pin G3P2 analog switch state */ 132 #define TSI_ASW_G3P3 BIT(15) /*!< pin G3P3 analog switch state */ 133 #define TSI_ASW_G4P0 BIT(16) /*!< pin G4P0 analog switch state */ 134 #define TSI_ASW_G4P1 BIT(17) /*!< pin G4P1 analog switch state */ 135 #define TSI_ASW_G4P2 BIT(18) /*!< pin G4P2 analog switch state */ 136 #define TSI_ASW_G4P3 BIT(19) /*!< pin G4P3 analog switch state */ 137 #define TSI_ASW_G5P0 BIT(20) /*!< pin G5P0 analog switch state */ 138 #define TSI_ASW_G5P1 BIT(21) /*!< pin G5P1 analog switch state */ 139 #define TSI_ASW_G5P2 BIT(22) /*!< pin G5P2 analog switch state */ 140 #define TSI_ASW_G5P3 BIT(23) /*!< pin G5P3 analog switch state */ 141 142 /* TSI_SAMPCFG */ 143 #define TSI_SAMPCFG_G0P0 BIT(0) /*!< pin G0P0 sample pin mode */ 144 #define TSI_SAMPCFG_G0P1 BIT(1) /*!< pin G0P1 sample pin mode */ 145 #define TSI_SAMPCFG_G0P2 BIT(2) /*!< pin G0P2 sample pin mode */ 146 #define TSI_SAMPCFG_G0P3 BIT(3) /*!< pin G0P3 sample pin mode */ 147 #define TSI_SAMPCFG_G1P0 BIT(4) /*!< pin G1P0 sample pin mode */ 148 #define TSI_SAMPCFG_G1P1 BIT(5) /*!< pin G1P1 sample pin mode */ 149 #define TSI_SAMPCFG_G1P2 BIT(6) /*!< pin G1P2 sample pin mode */ 150 #define TSI_SAMPCFG_G1P3 BIT(7) /*!< pin G1P3 sample pin mode */ 151 #define TSI_SAMPCFG_G2P0 BIT(8) /*!< pin G2P0 sample pin mode */ 152 #define TSI_SAMPCFG_G2P1 BIT(9) /*!< pin G2P1 sample pin mode */ 153 #define TSI_SAMPCFG_G2P2 BIT(10) /*!< pin G2P2 sample pin mode */ 154 #define TSI_SAMPCFG_G2P3 BIT(11) /*!< pin G2P3 sample pin mode */ 155 #define TSI_SAMPCFG_G3P0 BIT(12) /*!< pin G3P0 sample pin mode */ 156 #define TSI_SAMPCFG_G3P1 BIT(13) /*!< pin G3P1 sample pin mode */ 157 #define TSI_SAMPCFG_G3P2 BIT(14) /*!< pin G3P2 sample pin mode */ 158 #define TSI_SAMPCFG_G3P3 BIT(15) /*!< pin G3P3 sample pin mode */ 159 #define TSI_SAMPCFG_G4P0 BIT(16) /*!< pin G4P0 sample pin mode */ 160 #define TSI_SAMPCFG_G4P1 BIT(17) /*!< pin G4P1 sample pin mode */ 161 #define TSI_SAMPCFG_G4P2 BIT(18) /*!< pin G4P2 sample pin mode */ 162 #define TSI_SAMPCFG_G4P3 BIT(19) /*!< pin G4P3 sample pin mode */ 163 #define TSI_SAMPCFG_G5P0 BIT(20) /*!< pin G5P0 sample pin mode */ 164 #define TSI_SAMPCFG_G5P1 BIT(21) /*!< pin G5P1 sample pin mode */ 165 #define TSI_SAMPCFG_G5P2 BIT(22) /*!< pin G5P2 sample pin mode */ 166 #define TSI_SAMPCFG_G5P3 BIT(23) /*!< pin G5P3 sample pin mode */ 167 168 /* TSI_CHCFG */ 169 #define TSI_CHCFG_G0P0 BIT(0) /*!< pin G0P0 channel pin mode */ 170 #define TSI_CHCFG_G0P1 BIT(1) /*!< pin G0P1 channel pin mode */ 171 #define TSI_CHCFG_G0P2 BIT(2) /*!< pin G0P2 channel pin mode */ 172 #define TSI_CHCFG_G0P3 BIT(3) /*!< pin G0P3 channel pin mode */ 173 #define TSI_CHCFG_G1P0 BIT(4) /*!< pin G1P0 channel pin mode */ 174 #define TSI_CHCFG_G1P1 BIT(5) /*!< pin G1P1 channel pin mode */ 175 #define TSI_CHCFG_G1P2 BIT(6) /*!< pin G1P2 channel pin mode */ 176 #define TSI_CHCFG_G1P3 BIT(7) /*!< pin G1P3 channel pin mode */ 177 #define TSI_CHCFG_G2P0 BIT(8) /*!< pin G2P0 channel pin mode */ 178 #define TSI_CHCFG_G2P1 BIT(9) /*!< pin G2P1 channel pin mode */ 179 #define TSI_CHCFG_G2P2 BIT(10) /*!< pin G2P2 channel pin mode */ 180 #define TSI_CHCFG_G2P3 BIT(11) /*!< pin G2P3 channel pin mode */ 181 #define TSI_CHCFG_G3P0 BIT(12) /*!< pin G3P0 channel pin mode */ 182 #define TSI_CHCFG_G3P1 BIT(13) /*!< pin G3P1 channel pin mode */ 183 #define TSI_CHCFG_G3P2 BIT(14) /*!< pin G3P2 channel pin mode */ 184 #define TSI_CHCFG_G3P3 BIT(15) /*!< pin G3P3 channel pin mode */ 185 #define TSI_CHCFG_G4P0 BIT(16) /*!< pin G4P0 channel pin mode */ 186 #define TSI_CHCFG_G4P1 BIT(17) /*!< pin G4P1 channel pin mode */ 187 #define TSI_CHCFG_G4P2 BIT(18) /*!< pin G4P2 channel pin mode */ 188 #define TSI_CHCFG_G4P3 BIT(19) /*!< pin G4P3 channel pin mode */ 189 #define TSI_CHCFG_G5P0 BIT(20) /*!< pin G5P0 channel pin mode */ 190 #define TSI_CHCFG_G5P1 BIT(21) /*!< pin G5P1 channel pin mode */ 191 #define TSI_CHCFG_G5P2 BIT(22) /*!< pin G5P2 channel pin mode */ 192 #define TSI_CHCFG_G5P3 BIT(23) /*!< pin G5P3 channel pin mode */ 193 194 /* TSI_GCTL */ 195 #define TSI_GCTL_GE0 BIT(0) /*!< group0 enable */ 196 #define TSI_GCTL_GE1 BIT(1) /*!< group1 enable */ 197 #define TSI_GCTL_GE2 BIT(2) /*!< group2 enable */ 198 #define TSI_GCTL_GE3 BIT(3) /*!< group3 enable */ 199 #define TSI_GCTL_GE4 BIT(4) /*!< group4 enable */ 200 #define TSI_GCTL_GE5 BIT(5) /*!< group5 enable */ 201 #define TSI_GCTL_GC0 BIT(16) /*!< group0 complete */ 202 #define TSI_GCTL_GC1 BIT(17) /*!< group1 complete */ 203 #define TSI_GCTL_GC2 BIT(18) /*!< group2 complete */ 204 #define TSI_GCTL_GC3 BIT(19) /*!< group3 complete */ 205 #define TSI_GCTL_GC4 BIT(20) /*!< group4 complete */ 206 #define TSI_GCTL_GC5 BIT(21) /*!< group5 complete */ 207 208 /* TSI_CTL1 */ 209 #define TSI_CTL1_CTCDIV BIT(24) /*!< CTCLK clock division factor */ 210 #define TSI_CTL1_ECDIV BITS(28,29) /*!< ECCLK clock division factor */ 211 212 /* constants definitions */ 213 /* TSI interrupt enable bit */ 214 #define TSI_INT_CCTCF TSI_INTEN_CTCFIE /*!< charge transfer complete flag interrupt enable */ 215 #define TSI_INT_MNERR TSI_INTEN_MNERRIE /*!< max cycle number error interrupt enable */ 216 217 /* TSI interrupt flags */ 218 #define TSI_INT_FLAG_CTCF TSI_INTF_CTCF /*!< charge transfer complete flag */ 219 #define TSI_INT_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */ 220 221 /* TSI flags */ 222 #define TSI_FLAG_CTCF TSI_INTF_CTCF /*!< charge transfer complete flag */ 223 #define TSI_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */ 224 225 /* CTCLK clock division factor */ 226 #define TSI_CTCDIV_DIV1 ((uint32_t)0x00000000U) /*!< fCTCLK = fHCLK */ 227 #define TSI_CTCDIV_DIV2 ((uint32_t)0x00000001U) /*!< fCTCLK = fHCLK/2 */ 228 #define TSI_CTCDIV_DIV4 ((uint32_t)0x00000002U) /*!< fCTCLK = fHCLK/4 */ 229 #define TSI_CTCDIV_DIV8 ((uint32_t)0x00000003U) /*!< fCTCLK = fHCLK/8 */ 230 #define TSI_CTCDIV_DIV16 ((uint32_t)0x00000004U) /*!< fCTCLK = fHCLK/16 */ 231 #define TSI_CTCDIV_DIV32 ((uint32_t)0x00000005U) /*!< fCTCLK = fHCLK/32 */ 232 #define TSI_CTCDIV_DIV64 ((uint32_t)0x00000006U) /*!< fCTCLK = fHCLK/64 */ 233 #define TSI_CTCDIV_DIV128 ((uint32_t)0x00000007U) /*!< fCTCLK = fHCLK/128 */ 234 #define TSI_CTCDIV_DIV256 ((uint32_t)0x00000008U) /*!< fCTCLK = fHCLK/256 */ 235 #define TSI_CTCDIV_DIV512 ((uint32_t)0x00000009U) /*!< fCTCLK = fHCLK/512 */ 236 #define TSI_CTCDIV_DIV1024 ((uint32_t)0x0000000AU) /*!< fCTCLK = fHCLK/1024 */ 237 #define TSI_CTCDIV_DIV2048 ((uint32_t)0x0000000BU) /*!< fCTCLK = fHCLK/2048 */ 238 #define TSI_CTCDIV_DIV4096 ((uint32_t)0x0000000CU) /*!< fCTCLK = fHCLK/4096 */ 239 #define TSI_CTCDIV_DIV8192 ((uint32_t)0x0000000DU) /*!< fCTCLK = fHCLK/8192 */ 240 #define TSI_CTCDIV_DIV16384 ((uint32_t)0x0000000EU) /*!< fCTCLK = fHCLK/16384 */ 241 #define TSI_CTCDIV_DIV32768 ((uint32_t)0x0000000FU) /*!< fCTCLK = fHCLK/32768 */ 242 243 /* charge transfer state duration Time */ 244 #define CTL_CTDT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) 245 #define TSI_TRANSFER_1CTCLK CTL_CTDT(0) /*!< the duration time of transfer state is 1 CTCLK */ 246 #define TSI_TRANSFER_2CTCLK CTL_CTDT(1) /*!< the duration time of transfer state is 2 CTCLK */ 247 #define TSI_TRANSFER_3CTCLK CTL_CTDT(2) /*!< the duration time of transfer state is 3 CTCLK */ 248 #define TSI_TRANSFER_4CTCLK CTL_CTDT(3) /*!< the duration time of transfer state is 4 CTCLK */ 249 #define TSI_TRANSFER_5CTCLK CTL_CTDT(4) /*!< the duration time of transfer state is 5 CTCLK */ 250 #define TSI_TRANSFER_6CTCLK CTL_CTDT(5) /*!< the duration time of transfer state is 6 CTCLK */ 251 #define TSI_TRANSFER_7CTCLK CTL_CTDT(6) /*!< the duration time of transfer state is 7 CTCLK */ 252 #define TSI_TRANSFER_8CTCLK CTL_CTDT(7) /*!< the duration time of transfer state is 8 CTCLK */ 253 #define TSI_TRANSFER_9CTCLK CTL_CTDT(8) /*!< the duration time of transfer state is 9 CTCLK */ 254 #define TSI_TRANSFER_10CTCLK CTL_CTDT(9) /*!< the duration time of transfer state is 10 CTCLK */ 255 #define TSI_TRANSFER_11CTCLK CTL_CTDT(10) /*!< the duration time of transfer state is 11 CTCLK */ 256 #define TSI_TRANSFER_12CTCLK CTL_CTDT(11) /*!< the duration time of transfer state is 12 CTCLK */ 257 #define TSI_TRANSFER_13CTCLK CTL_CTDT(12) /*!< the duration time of transfer state is 13 CTCLK */ 258 #define TSI_TRANSFER_14CTCLK CTL_CTDT(13) /*!< the duration time of transfer state is 14 CTCLK */ 259 #define TSI_TRANSFER_15CTCLK CTL_CTDT(14) /*!< the duration time of transfer state is 15 CTCLK */ 260 #define TSI_TRANSFER_16CTCLK CTL_CTDT(15) /*!< the duration time of transfer state is 16 CTCLK */ 261 262 /* charge state duration time */ 263 #define CTL_CDT(regval) (BITS(28,31) & ((uint32_t)(regval) << 28U)) 264 #define TSI_CHARGE_1CTCLK CTL_CDT(0) /*!< the duration time of charge state is 1 CTCLK */ 265 #define TSI_CHARGE_2CTCLK CTL_CDT(1) /*!< the duration time of charge state is 2 CTCLK */ 266 #define TSI_CHARGE_3CTCLK CTL_CDT(2) /*!< the duration time of charge state is 3 CTCLK */ 267 #define TSI_CHARGE_4CTCLK CTL_CDT(3) /*!< the duration time of charge state is 4 CTCLK */ 268 #define TSI_CHARGE_5CTCLK CTL_CDT(4) /*!< the duration time of charge state is 5 CTCLK */ 269 #define TSI_CHARGE_6CTCLK CTL_CDT(5) /*!< the duration time of charge state is 6 CTCLK */ 270 #define TSI_CHARGE_7CTCLK CTL_CDT(6) /*!< the duration time of charge state is 7 CTCLK */ 271 #define TSI_CHARGE_8CTCLK CTL_CDT(7) /*!< the duration time of charge state is 8 CTCLK */ 272 #define TSI_CHARGE_9CTCLK CTL_CDT(8) /*!< the duration time of charge state is 9 CTCLK */ 273 #define TSI_CHARGE_10CTCLK CTL_CDT(9) /*!< the duration time of charge state is 10 CTCLK */ 274 #define TSI_CHARGE_11CTCLK CTL_CDT(10) /*!< the duration time of charge state is 11 CTCLK */ 275 #define TSI_CHARGE_12CTCLK CTL_CDT(11) /*!< the duration time of charge state is 12 CTCLK */ 276 #define TSI_CHARGE_13CTCLK CTL_CDT(12) /*!< the duration time of charge state is 13 CTCLK */ 277 #define TSI_CHARGE_14CTCLK CTL_CDT(13) /*!< the duration time of charge state is 14 CTCLK */ 278 #define TSI_CHARGE_15CTCLK CTL_CDT(14) /*!< the duration time of charge state is 15 CTCLK */ 279 #define TSI_CHARGE_16CTCLK CTL_CDT(15) /*!< the duration time of charge state is 16 CTCLK */ 280 281 /* max cycle number of a sequence */ 282 #define CTL_MCN(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U)) 283 #define TSI_MAXNUM255 CTL_MCN(0) /*!< the max cycle number of a sequence is 255 */ 284 #define TSI_MAXNUM511 CTL_MCN(1) /*!< the max cycle number of a sequence is 511 */ 285 #define TSI_MAXNUM1023 CTL_MCN(2) /*!< the max cycle number of a sequence is 1023 */ 286 #define TSI_MAXNUM2047 CTL_MCN(3) /*!< the max cycle number of a sequence is 2047 */ 287 #define TSI_MAXNUM4095 CTL_MCN(4) /*!< the max cycle number of a sequence is 4095 */ 288 #define TSI_MAXNUM8191 CTL_MCN(5) /*!< the max cycle number of a sequence is 8191 */ 289 #define TSI_MAXNUM16383 CTL_MCN(6) /*!< the max cycle number of a sequence is 16383 */ 290 291 /* ECCLK clock division factor */ 292 #define TSI_EXTEND_DIV1 ((uint32_t)0x00000000U) /*!< fECCLK = fHCLK */ 293 #define TSI_EXTEND_DIV2 ((uint32_t)0x00000001U) /*!< fECCLK = fHCLK/2 */ 294 #define TSI_EXTEND_DIV3 ((uint32_t)0x00000002U) /*!< fECCLK = fHCLK/3 */ 295 #define TSI_EXTEND_DIV4 ((uint32_t)0x00000003U) /*!< fECCLK = fHCLK/4 */ 296 #define TSI_EXTEND_DIV5 ((uint32_t)0x00000004U) /*!< fECCLK = fHCLK/5 */ 297 #define TSI_EXTEND_DIV6 ((uint32_t)0x00000005U) /*!< fECCLK = fHCLK/6 */ 298 #define TSI_EXTEND_DIV7 ((uint32_t)0x00000006U) /*!< fECCLK = fHCLK/7 */ 299 #define TSI_EXTEND_DIV8 ((uint32_t)0x00000007U) /*!< fECCLK = fHCLK/8 */ 300 301 /* extend charge state maximum duration time */ 302 #define TSI_EXTENDMAX(regval) (BITS(17,23) & ((uint32_t)(regval) << 17U)) /* value range 1..128,extend charge state maximum duration time */ 303 304 /* hardware trigger mode */ 305 #define TSI_FALLING_TRIGGER 0x00U /*!< falling edge trigger TSI charge transfer sequence */ 306 #define TSI_RISING_TRIGGER 0x01U /*!< rising edge trigger TSI charge transfer sequence */ 307 308 /* pin mode */ 309 #define TSI_OUTPUT_LOW 0x00U /*!< TSI pin will output low when IDLE */ 310 #define TSI_INPUT_FLOATING 0x01U /*!< TSI pin will keep input_floating when IDLE */ 311 312 /* function declarations */ 313 /* reset TSI peripheral */ 314 void tsi_deinit(void); 315 /* initialize TSI plus prescaler,charge plus,transfer plus,max cycle number */ 316 void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number); 317 /* enable TSI module */ 318 void tsi_enable(void); 319 /* disable TSI module */ 320 void tsi_disable(void); 321 /* enable sample pin */ 322 void tsi_sample_pin_enable(uint32_t sample); 323 /* disable sample pin */ 324 void tsi_sample_pin_disable(uint32_t sample); 325 /* enable channel pin */ 326 void tsi_channel_pin_enable(uint32_t channel); 327 /* disable channel pin */ 328 void tsi_channel_pin_disable(uint32_t channel); 329 330 /* configure TSI triggering by software */ 331 void tsi_sofeware_mode_config(void); 332 /* start a charge-transfer sequence when TSI is in software trigger mode */ 333 void tsi_software_start(void); 334 /* stop a charge-transfer sequence when TSI is in software trigger mode */ 335 void tsi_software_stop(void); 336 /* configure TSI triggering by hardware */ 337 void tsi_hardware_mode_config(uint8_t trigger_edge); 338 /* configure TSI pin mode when charge-transfer sequence is IDLE */ 339 void tsi_pin_mode_config(uint8_t pin_mode); 340 /* configure extend charge state */ 341 void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration); 342 343 /* configure charge plus and transfer plus */ 344 void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration); 345 /* configure the max cycle number of a charge-transfer sequence */ 346 void tsi_max_number_config(uint32_t max_number); 347 /* switch on hysteresis pin */ 348 void tsi_hysteresis_on(uint32_t group_pin); 349 /* switch off hysteresis pin */ 350 void tsi_hysteresis_off(uint32_t group_pin); 351 /* switch on analog pin */ 352 void tsi_analog_on(uint32_t group_pin); 353 /* switch off analog pin */ 354 void tsi_analog_off(uint32_t group_pin); 355 356 /* enable TSI interrupt */ 357 void tsi_interrupt_enable(uint32_t source); 358 /* disable TSI interrupt */ 359 void tsi_interrupt_disable(uint32_t source); 360 /* clear interrupt flag */ 361 void tsi_interrupt_flag_clear(uint32_t flag); 362 /* get TSI interrupt flag */ 363 FlagStatus tsi_interrupt_flag_get(uint32_t flag); 364 365 /* clear flag */ 366 void tsi_flag_clear(uint32_t flag); 367 /* get flag */ 368 FlagStatus tsi_flag_get(uint32_t flag); 369 370 /* enbale group */ 371 void tsi_group_enable(uint32_t group); 372 /* disbale group */ 373 void tsi_group_disable(uint32_t group); 374 /* get group complete status */ 375 FlagStatus tsi_group_status_get(uint32_t group); 376 /* get the cycle number for group0 as soon as a charge-transfer sequence completes */ 377 uint16_t tsi_group0_cycle_get(void); 378 /* get the cycle number for group1 as soon as a charge-transfer sequence completes */ 379 uint16_t tsi_group1_cycle_get(void); 380 /* get the cycle number for group2 as soon as a charge-transfer sequence completes */ 381 uint16_t tsi_group2_cycle_get(void); 382 /* get the cycle number for group3 as soon as a charge-transfer sequence completes */ 383 uint16_t tsi_group3_cycle_get(void); 384 /* get the cycle number for group4 as soon as a charge-transfer sequence completes */ 385 uint16_t tsi_group4_cycle_get(void); 386 /* get the cycle number for group5 as soon as a charge-transfer sequence completes */ 387 uint16_t tsi_group5_cycle_get(void); 388 389 #endif /* GD32F3X0_TSI_H */ 390
