1 /***************************************************************************//** 2 * \file cyip_tcpwm.h 3 * 4 * \brief 5 * TCPWM IP definitions 6 * 7 * \note 8 * Generator version: 1.6.0.409 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _CYIP_TCPWM_H_ 29 #define _CYIP_TCPWM_H_ 30 31 #include "cyip_headers.h" 32 33 /******************************************************************************* 34 * TCPWM 35 *******************************************************************************/ 36 37 #define TCPWM_CNT_SECTION_SIZE 0x00000040UL 38 #define TCPWM_SECTION_SIZE 0x00010000UL 39 40 /** 41 * \brief Timer/Counter/PWM Counter Module (TCPWM_CNT) 42 */ 43 typedef struct { 44 __IOM uint32_t CTRL; /*!< 0x00000000 Counter control register */ 45 __IM uint32_t STATUS; /*!< 0x00000004 Counter status register */ 46 __IOM uint32_t COUNTER; /*!< 0x00000008 Counter count register */ 47 __IOM uint32_t CC; /*!< 0x0000000C Counter compare/capture register */ 48 __IOM uint32_t CC_BUFF; /*!< 0x00000010 Counter buffered compare/capture register */ 49 __IOM uint32_t PERIOD; /*!< 0x00000014 Counter period register */ 50 __IOM uint32_t PERIOD_BUFF; /*!< 0x00000018 Counter buffered period register */ 51 __IM uint32_t RESERVED; 52 __IOM uint32_t TR_CTRL0; /*!< 0x00000020 Counter trigger control register 0 */ 53 __IOM uint32_t TR_CTRL1; /*!< 0x00000024 Counter trigger control register 1 */ 54 __IOM uint32_t TR_CTRL2; /*!< 0x00000028 Counter trigger control register 2 */ 55 __IM uint32_t RESERVED1; 56 __IOM uint32_t INTR; /*!< 0x00000030 Interrupt request register */ 57 __IOM uint32_t INTR_SET; /*!< 0x00000034 Interrupt set request register */ 58 __IOM uint32_t INTR_MASK; /*!< 0x00000038 Interrupt mask register */ 59 __IM uint32_t INTR_MASKED; /*!< 0x0000003C Interrupt masked request register */ 60 } TCPWM_CNT_V1_Type; /*!< Size = 64 (0x40) */ 61 62 /** 63 * \brief Timer/Counter/PWM (TCPWM) 64 */ 65 typedef struct { 66 __IOM uint32_t CTRL; /*!< 0x00000000 TCPWM control register */ 67 __IOM uint32_t CTRL_CLR; /*!< 0x00000004 TCPWM control clear register */ 68 __IOM uint32_t CTRL_SET; /*!< 0x00000008 TCPWM control set register */ 69 __IOM uint32_t CMD_CAPTURE; /*!< 0x0000000C TCPWM capture command register */ 70 __IOM uint32_t CMD_RELOAD; /*!< 0x00000010 TCPWM reload command register */ 71 __IOM uint32_t CMD_STOP; /*!< 0x00000014 TCPWM stop command register */ 72 __IOM uint32_t CMD_START; /*!< 0x00000018 TCPWM start command register */ 73 __IM uint32_t INTR_CAUSE; /*!< 0x0000001C TCPWM Counter interrupt cause register */ 74 __IM uint32_t RESERVED[56]; 75 TCPWM_CNT_V1_Type CNT[32]; /*!< 0x00000100 Timer/Counter/PWM Counter Module */ 76 } TCPWM_V1_Type; /*!< Size = 2304 (0x900) */ 77 78 79 /* TCPWM_CNT.CTRL */ 80 #define TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Pos 0UL 81 #define TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk 0x1UL 82 #define TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos 1UL 83 #define TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk 0x2UL 84 #define TCPWM_CNT_CTRL_PWM_SYNC_KILL_Pos 2UL 85 #define TCPWM_CNT_CTRL_PWM_SYNC_KILL_Msk 0x4UL 86 #define TCPWM_CNT_CTRL_PWM_STOP_ON_KILL_Pos 3UL 87 #define TCPWM_CNT_CTRL_PWM_STOP_ON_KILL_Msk 0x8UL 88 #define TCPWM_CNT_CTRL_GENERIC_Pos 8UL 89 #define TCPWM_CNT_CTRL_GENERIC_Msk 0xFF00UL 90 #define TCPWM_CNT_CTRL_UP_DOWN_MODE_Pos 16UL 91 #define TCPWM_CNT_CTRL_UP_DOWN_MODE_Msk 0x30000UL 92 #define TCPWM_CNT_CTRL_ONE_SHOT_Pos 18UL 93 #define TCPWM_CNT_CTRL_ONE_SHOT_Msk 0x40000UL 94 #define TCPWM_CNT_CTRL_QUADRATURE_MODE_Pos 20UL 95 #define TCPWM_CNT_CTRL_QUADRATURE_MODE_Msk 0x300000UL 96 #define TCPWM_CNT_CTRL_MODE_Pos 24UL 97 #define TCPWM_CNT_CTRL_MODE_Msk 0x7000000UL 98 /* TCPWM_CNT.STATUS */ 99 #define TCPWM_CNT_STATUS_DOWN_Pos 0UL 100 #define TCPWM_CNT_STATUS_DOWN_Msk 0x1UL 101 #define TCPWM_CNT_STATUS_GENERIC_Pos 8UL 102 #define TCPWM_CNT_STATUS_GENERIC_Msk 0xFF00UL 103 #define TCPWM_CNT_STATUS_RUNNING_Pos 31UL 104 #define TCPWM_CNT_STATUS_RUNNING_Msk 0x80000000UL 105 /* TCPWM_CNT.COUNTER */ 106 #define TCPWM_CNT_COUNTER_COUNTER_Pos 0UL 107 #define TCPWM_CNT_COUNTER_COUNTER_Msk 0xFFFFFFFFUL 108 /* TCPWM_CNT.CC */ 109 #define TCPWM_CNT_CC_CC_Pos 0UL 110 #define TCPWM_CNT_CC_CC_Msk 0xFFFFFFFFUL 111 /* TCPWM_CNT.CC_BUFF */ 112 #define TCPWM_CNT_CC_BUFF_CC_Pos 0UL 113 #define TCPWM_CNT_CC_BUFF_CC_Msk 0xFFFFFFFFUL 114 /* TCPWM_CNT.PERIOD */ 115 #define TCPWM_CNT_PERIOD_PERIOD_Pos 0UL 116 #define TCPWM_CNT_PERIOD_PERIOD_Msk 0xFFFFFFFFUL 117 /* TCPWM_CNT.PERIOD_BUFF */ 118 #define TCPWM_CNT_PERIOD_BUFF_PERIOD_Pos 0UL 119 #define TCPWM_CNT_PERIOD_BUFF_PERIOD_Msk 0xFFFFFFFFUL 120 /* TCPWM_CNT.TR_CTRL0 */ 121 #define TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Pos 0UL 122 #define TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Msk 0xFUL 123 #define TCPWM_CNT_TR_CTRL0_COUNT_SEL_Pos 4UL 124 #define TCPWM_CNT_TR_CTRL0_COUNT_SEL_Msk 0xF0UL 125 #define TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Pos 8UL 126 #define TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Msk 0xF00UL 127 #define TCPWM_CNT_TR_CTRL0_STOP_SEL_Pos 12UL 128 #define TCPWM_CNT_TR_CTRL0_STOP_SEL_Msk 0xF000UL 129 #define TCPWM_CNT_TR_CTRL0_START_SEL_Pos 16UL 130 #define TCPWM_CNT_TR_CTRL0_START_SEL_Msk 0xF0000UL 131 /* TCPWM_CNT.TR_CTRL1 */ 132 #define TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE_Pos 0UL 133 #define TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE_Msk 0x3UL 134 #define TCPWM_CNT_TR_CTRL1_COUNT_EDGE_Pos 2UL 135 #define TCPWM_CNT_TR_CTRL1_COUNT_EDGE_Msk 0xCUL 136 #define TCPWM_CNT_TR_CTRL1_RELOAD_EDGE_Pos 4UL 137 #define TCPWM_CNT_TR_CTRL1_RELOAD_EDGE_Msk 0x30UL 138 #define TCPWM_CNT_TR_CTRL1_STOP_EDGE_Pos 6UL 139 #define TCPWM_CNT_TR_CTRL1_STOP_EDGE_Msk 0xC0UL 140 #define TCPWM_CNT_TR_CTRL1_START_EDGE_Pos 8UL 141 #define TCPWM_CNT_TR_CTRL1_START_EDGE_Msk 0x300UL 142 /* TCPWM_CNT.TR_CTRL2 */ 143 #define TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE_Pos 0UL 144 #define TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE_Msk 0x3UL 145 #define TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE_Pos 2UL 146 #define TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE_Msk 0xCUL 147 #define TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE_Pos 4UL 148 #define TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE_Msk 0x30UL 149 /* TCPWM_CNT.INTR */ 150 #define TCPWM_CNT_INTR_TC_Pos 0UL 151 #define TCPWM_CNT_INTR_TC_Msk 0x1UL 152 #define TCPWM_CNT_INTR_CC_MATCH_Pos 1UL 153 #define TCPWM_CNT_INTR_CC_MATCH_Msk 0x2UL 154 /* TCPWM_CNT.INTR_SET */ 155 #define TCPWM_CNT_INTR_SET_TC_Pos 0UL 156 #define TCPWM_CNT_INTR_SET_TC_Msk 0x1UL 157 #define TCPWM_CNT_INTR_SET_CC_MATCH_Pos 1UL 158 #define TCPWM_CNT_INTR_SET_CC_MATCH_Msk 0x2UL 159 /* TCPWM_CNT.INTR_MASK */ 160 #define TCPWM_CNT_INTR_MASK_TC_Pos 0UL 161 #define TCPWM_CNT_INTR_MASK_TC_Msk 0x1UL 162 #define TCPWM_CNT_INTR_MASK_CC_MATCH_Pos 1UL 163 #define TCPWM_CNT_INTR_MASK_CC_MATCH_Msk 0x2UL 164 /* TCPWM_CNT.INTR_MASKED */ 165 #define TCPWM_CNT_INTR_MASKED_TC_Pos 0UL 166 #define TCPWM_CNT_INTR_MASKED_TC_Msk 0x1UL 167 #define TCPWM_CNT_INTR_MASKED_CC_MATCH_Pos 1UL 168 #define TCPWM_CNT_INTR_MASKED_CC_MATCH_Msk 0x2UL 169 170 171 /* TCPWM.CTRL */ 172 #define TCPWM_CTRL_COUNTER_ENABLED_Pos 0UL 173 #define TCPWM_CTRL_COUNTER_ENABLED_Msk 0xFFFFFFFFUL 174 /* TCPWM.CTRL_CLR */ 175 #define TCPWM_CTRL_CLR_COUNTER_ENABLED_Pos 0UL 176 #define TCPWM_CTRL_CLR_COUNTER_ENABLED_Msk 0xFFFFFFFFUL 177 /* TCPWM.CTRL_SET */ 178 #define TCPWM_CTRL_SET_COUNTER_ENABLED_Pos 0UL 179 #define TCPWM_CTRL_SET_COUNTER_ENABLED_Msk 0xFFFFFFFFUL 180 /* TCPWM.CMD_CAPTURE */ 181 #define TCPWM_CMD_CAPTURE_COUNTER_CAPTURE_Pos 0UL 182 #define TCPWM_CMD_CAPTURE_COUNTER_CAPTURE_Msk 0xFFFFFFFFUL 183 /* TCPWM.CMD_RELOAD */ 184 #define TCPWM_CMD_RELOAD_COUNTER_RELOAD_Pos 0UL 185 #define TCPWM_CMD_RELOAD_COUNTER_RELOAD_Msk 0xFFFFFFFFUL 186 /* TCPWM.CMD_STOP */ 187 #define TCPWM_CMD_STOP_COUNTER_STOP_Pos 0UL 188 #define TCPWM_CMD_STOP_COUNTER_STOP_Msk 0xFFFFFFFFUL 189 /* TCPWM.CMD_START */ 190 #define TCPWM_CMD_START_COUNTER_START_Pos 0UL 191 #define TCPWM_CMD_START_COUNTER_START_Msk 0xFFFFFFFFUL 192 /* TCPWM.INTR_CAUSE */ 193 #define TCPWM_INTR_CAUSE_COUNTER_INT_Pos 0UL 194 #define TCPWM_INTR_CAUSE_COUNTER_INT_Msk 0xFFFFFFFFUL 195 196 197 #endif /* _CYIP_TCPWM_H_ */ 198 199 200 /* [] END OF FILE */ 201
