1 /***************************************************************************//** 2 * \file cyip_main_reg.h 3 * 4 * \brief 5 * MAIN_REG IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_MAIN_REG_H_ 28 #define _CYIP_MAIN_REG_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * MAIN_REG 34 *******************************************************************************/ 35 36 #define MAIN_REG_TR_GR_SECTION_SIZE 0x00000400UL 37 #define MAIN_REG_TR_ASSIST_GR_SECTION_SIZE 0x00000400UL 38 #define MAIN_REG_SECTION_SIZE 0x00001000UL 39 40 /** 41 * \brief Trigger group (MAIN_REG_TR_GR) 42 */ 43 typedef struct { 44 __IM uint32_t RESERVED[32]; 45 __IOM uint32_t TR_CTL[64]; /*!< 0x00000080 Trigger control register */ 46 __IOM uint32_t TR_CDMA_CTL[16]; /*!< 0x00000180 Central DMA Trigger control register */ 47 __IM uint32_t RESERVED1[144]; 48 } MAIN_REG_TR_GR_V1_Type; /*!< Size = 1024 (0x400) */ 49 50 /** 51 * \brief Trigger Assist - for CDMA triggers (MAIN_REG_TR_ASSIST_GR) 52 */ 53 typedef struct { 54 __IOM uint32_t TRA_CTRL[16]; /*!< 0x00000000 Trigger Assist Control Registers */ 55 __IM uint32_t RESERVED[48]; 56 __IOM uint32_t TRA_SLP_CTRL[16]; /*!< 0x00000100 Trigger Assist Short Length Packet / Zero Length Packet Control */ 57 __IM uint32_t RESERVED1[48]; 58 __IM uint32_t TRA_STAT[16]; /*!< 0x00000200 Trigger Assist Status Registers */ 59 __IM uint32_t RESERVED2[112]; 60 } MAIN_REG_TR_ASSIST_GR_V1_Type; /*!< Size = 1024 (0x400) */ 61 62 /** 63 * \brief HBWSS Main Registers (MAIN_REG) 64 */ 65 typedef struct { 66 __IOM uint32_t CTRL; /*!< 0x00000000 Main Control Register */ 67 __IOM uint32_t HBWSS_SPARE; /*!< 0x00000004 SPARE Config/Status */ 68 __IOM uint32_t SPCTRL; /*!< 0x00000008 SRAM Power Control Register */ 69 __IM uint32_t RESERVED[5]; 70 __IOM uint32_t TR_CMD; /*!< 0x00000020 Trigger command */ 71 __IM uint32_t RESERVED1[7]; 72 __IOM uint32_t TRA_CO_INTR; /*!< 0x00000040 CDMA output tr_assist Interrupt Status */ 73 __IOM uint32_t TRA_CO_INTR_SET; /*!< 0x00000044 CDMA output tr_assist Interrupt Set */ 74 __IOM uint32_t TRA_CO_INTR_MASK; /*!< 0x00000048 CDMA output tr_assist Interrupt Mask */ 75 __IM uint32_t TRA_CO_INTR_MASKED; /*!< 0x0000004C CDMA output tr_assist Interrupt Masked */ 76 __IOM uint32_t DDFT_MUX; /*!< 0x00000050 DDFT0/1 mux selection Register */ 77 __IM uint32_t RESERVED2[235]; 78 MAIN_REG_TR_GR_V1_Type TR_GR[1]; /*!< 0x00000400 Trigger group */ 79 MAIN_REG_TR_ASSIST_GR_V1_Type TR_ASSIST_GR[1]; /*!< 0x00000800 Trigger Assist - for CDMA triggers */ 80 } MAIN_REG_V1_Type; /*!< Size = 3072 (0xC00) */ 81 82 83 /* MAIN_REG_TR_GR.TR_CTL */ 84 #define MAIN_REG_TR_GR_TR_CTL_TR_SEL0_Pos 0UL 85 #define MAIN_REG_TR_GR_TR_CTL_TR_SEL0_Msk 0x7FUL 86 #define MAIN_REG_TR_GR_TR_CTL_TR_SEL1_Pos 7UL 87 #define MAIN_REG_TR_GR_TR_CTL_TR_SEL1_Msk 0x3F80UL 88 #define MAIN_REG_TR_GR_TR_CTL_TR_SEL2_Pos 14UL 89 #define MAIN_REG_TR_GR_TR_CTL_TR_SEL2_Msk 0x1FC000UL 90 #define MAIN_REG_TR_GR_TR_CTL_TR_SEL3_Pos 21UL 91 #define MAIN_REG_TR_GR_TR_CTL_TR_SEL3_Msk 0xFE00000UL 92 #define MAIN_REG_TR_GR_TR_CTL_DBG_FREEZE_EN_Pos 31UL 93 #define MAIN_REG_TR_GR_TR_CTL_DBG_FREEZE_EN_Msk 0x80000000UL 94 /* MAIN_REG_TR_GR.TR_CDMA_CTL */ 95 #define MAIN_REG_TR_GR_TR_CDMA_CTL_TR_SEL0_Pos 0UL 96 #define MAIN_REG_TR_GR_TR_CDMA_CTL_TR_SEL0_Msk 0x7FUL 97 #define MAIN_REG_TR_GR_TR_CDMA_CTL_TR_SEL1_Pos 7UL 98 #define MAIN_REG_TR_GR_TR_CDMA_CTL_TR_SEL1_Msk 0x3F80UL 99 #define MAIN_REG_TR_GR_TR_CDMA_CTL_TR_INV_Pos 17UL 100 #define MAIN_REG_TR_GR_TR_CDMA_CTL_TR_INV_Msk 0x20000UL 101 #define MAIN_REG_TR_GR_TR_CDMA_CTL_TR_EDGE_Pos 18UL 102 #define MAIN_REG_TR_GR_TR_CDMA_CTL_TR_EDGE_Msk 0x40000UL 103 #define MAIN_REG_TR_GR_TR_CDMA_CTL_DBG_FREEZE_EN_Pos 31UL 104 #define MAIN_REG_TR_GR_TR_CDMA_CTL_DBG_FREEZE_EN_Msk 0x80000000UL 105 106 107 /* MAIN_REG_TR_ASSIST_GR.TRA_CTRL */ 108 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_DSCR_NUM_Pos 0UL 109 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_DSCR_NUM_Msk 0xFFFFUL 110 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_STREAM_EN_Pos 16UL 111 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_STREAM_EN_Msk 0x10000UL 112 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_HBWSS_IS_CONS_Pos 20UL 113 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_HBWSS_IS_CONS_Msk 0x100000UL 114 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_PKT_MODE_Pos 21UL 115 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_PKT_MODE_Msk 0x200000UL 116 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_WRAP_UP_SKT_Pos 24UL 117 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_WRAP_UP_SKT_Msk 0x1000000UL 118 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_SUPPR_1ST_TR_Pos 28UL 119 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_SUPPR_1ST_TR_Msk 0x10000000UL 120 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_SUPPR_1ST_INT_Pos 29UL 121 #define MAIN_REG_TR_ASSIST_GR_TRA_CTRL_TRA_SUPPR_1ST_INT_Msk 0x20000000UL 122 /* MAIN_REG_TR_ASSIST_GR.TRA_SLP_CTRL */ 123 #define MAIN_REG_TR_ASSIST_GR_TRA_SLP_CTRL_TRA_SHORT_CONFIG_Pos 0UL 124 #define MAIN_REG_TR_ASSIST_GR_TRA_SLP_CTRL_TRA_SHORT_CONFIG_Msk 0x1UL 125 #define MAIN_REG_TR_ASSIST_GR_TRA_SLP_CTRL_TRA_BYTE_COUNT_Pos 16UL 126 #define MAIN_REG_TR_ASSIST_GR_TRA_SLP_CTRL_TRA_BYTE_COUNT_Msk 0xFFFF0000UL 127 /* MAIN_REG_TR_ASSIST_GR.TRA_STAT */ 128 #define MAIN_REG_TR_ASSIST_GR_TRA_STAT_TRA_STATE_Pos 0UL 129 #define MAIN_REG_TR_ASSIST_GR_TRA_STAT_TRA_STATE_Msk 0xFUL 130 131 132 /* MAIN_REG.CTRL */ 133 #define MAIN_REG_CTRL_DMA_SRC_SEL_Pos 0UL 134 #define MAIN_REG_CTRL_DMA_SRC_SEL_Msk 0x3UL 135 #define MAIN_REG_CTRL_DMA_DIV_SEL_Pos 4UL 136 #define MAIN_REG_CTRL_DMA_DIV_SEL_Msk 0x30UL 137 #define MAIN_REG_CTRL_BUFFSIZE_64KB_EN_Pos 8UL 138 #define MAIN_REG_CTRL_BUFFSIZE_64KB_EN_Msk 0x100UL 139 #define MAIN_REG_CTRL_EVICT_SLOW_AHB_RD_CACHE_Pos 16UL 140 #define MAIN_REG_CTRL_EVICT_SLOW_AHB_RD_CACHE_Msk 0x10000UL 141 #define MAIN_REG_CTRL_EVICT_FAST_AHB_RD_CACHE_Pos 17UL 142 #define MAIN_REG_CTRL_EVICT_FAST_AHB_RD_CACHE_Msk 0x20000UL 143 #define MAIN_REG_CTRL_NUM_SLOW_AHB_STALL_CYCLES_Pos 20UL 144 #define MAIN_REG_CTRL_NUM_SLOW_AHB_STALL_CYCLES_Msk 0x700000UL 145 #define MAIN_REG_CTRL_STALL_SLOW_AHB_WRITE_Pos 23UL 146 #define MAIN_REG_CTRL_STALL_SLOW_AHB_WRITE_Msk 0x800000UL 147 #define MAIN_REG_CTRL_NUM_FAST_AHB_STALL_CYCLES_Pos 24UL 148 #define MAIN_REG_CTRL_NUM_FAST_AHB_STALL_CYCLES_Msk 0x7000000UL 149 #define MAIN_REG_CTRL_STALL_FAST_AHB_WRITE_Pos 27UL 150 #define MAIN_REG_CTRL_STALL_FAST_AHB_WRITE_Msk 0x8000000UL 151 #define MAIN_REG_CTRL_IP_ENABLED_Pos 31UL 152 #define MAIN_REG_CTRL_IP_ENABLED_Msk 0x80000000UL 153 /* MAIN_REG.HBWSS_SPARE */ 154 #define MAIN_REG_HBWSS_SPARE_SPARE_CFG_Pos 0UL 155 #define MAIN_REG_HBWSS_SPARE_SPARE_CFG_Msk 0xFFFFUL 156 /* MAIN_REG.SPCTRL */ 157 #define MAIN_REG_SPCTRL_PWR_MODE_MACRO_0_Pos 0UL 158 #define MAIN_REG_SPCTRL_PWR_MODE_MACRO_0_Msk 0x3UL 159 #define MAIN_REG_SPCTRL_PWR_MODE_MACRO_1_Pos 2UL 160 #define MAIN_REG_SPCTRL_PWR_MODE_MACRO_1_Msk 0xCUL 161 #define MAIN_REG_SPCTRL_PWRUP_DELAY_Pos 8UL 162 #define MAIN_REG_SPCTRL_PWRUP_DELAY_Msk 0x3FF00UL 163 /* MAIN_REG.TR_CMD */ 164 #define MAIN_REG_TR_CMD_TR_SEL_Pos 0UL 165 #define MAIN_REG_TR_CMD_TR_SEL_Msk 0xFFUL 166 #define MAIN_REG_TR_CMD_TRA_MINTENAB_Pos 28UL 167 #define MAIN_REG_TR_CMD_TRA_MINTENAB_Msk 0x10000000UL 168 #define MAIN_REG_TR_CMD_TR_EDGE_Pos 29UL 169 #define MAIN_REG_TR_CMD_TR_EDGE_Msk 0x20000000UL 170 #define MAIN_REG_TR_CMD_OUT_SEL_Pos 30UL 171 #define MAIN_REG_TR_CMD_OUT_SEL_Msk 0x40000000UL 172 #define MAIN_REG_TR_CMD_ACTIVATE_Pos 31UL 173 #define MAIN_REG_TR_CMD_ACTIVATE_Msk 0x80000000UL 174 /* MAIN_REG.TRA_CO_INTR */ 175 #define MAIN_REG_TRA_CO_INTR_OINTR_BITS_Pos 0UL 176 #define MAIN_REG_TRA_CO_INTR_OINTR_BITS_Msk 0xFFFFUL 177 /* MAIN_REG.TRA_CO_INTR_SET */ 178 #define MAIN_REG_TRA_CO_INTR_SET_OINTRS_BITS_Pos 0UL 179 #define MAIN_REG_TRA_CO_INTR_SET_OINTRS_BITS_Msk 0xFFFFUL 180 /* MAIN_REG.TRA_CO_INTR_MASK */ 181 #define MAIN_REG_TRA_CO_INTR_MASK_OINTRM_BITS_Pos 0UL 182 #define MAIN_REG_TRA_CO_INTR_MASK_OINTRM_BITS_Msk 0xFFFFUL 183 /* MAIN_REG.TRA_CO_INTR_MASKED */ 184 #define MAIN_REG_TRA_CO_INTR_MASKED_OINTRMD_BITS_Pos 0UL 185 #define MAIN_REG_TRA_CO_INTR_MASKED_OINTRMD_BITS_Msk 0xFFFFUL 186 /* MAIN_REG.DDFT_MUX */ 187 #define MAIN_REG_DDFT_MUX_TOP_DDFT0_SEL_Pos 0UL 188 #define MAIN_REG_DDFT_MUX_TOP_DDFT0_SEL_Msk 0xFFUL 189 #define MAIN_REG_DDFT_MUX_TOP_DDFT1_SEL_Pos 8UL 190 #define MAIN_REG_DDFT_MUX_TOP_DDFT1_SEL_Msk 0xFF00UL 191 #define MAIN_REG_DDFT_MUX_HS_DDFT0_SEL_Pos 16UL 192 #define MAIN_REG_DDFT_MUX_HS_DDFT0_SEL_Msk 0xFF0000UL 193 #define MAIN_REG_DDFT_MUX_HS_DDFT1_SEL_Pos 24UL 194 #define MAIN_REG_DDFT_MUX_HS_DDFT1_SEL_Msk 0xFF000000UL 195 196 197 #endif /* _CYIP_MAIN_REG_H_ */ 198 199 200 /* [] END OF FILE */ 201
