1 /**************************************************************************//** 2 * @file trng_reg.h 3 * @version V1.00 4 * @brief TRNG register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __TRNG_REG_H__ 10 #define __TRNG_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- True Random Number Generator -------------------------*/ 19 /** 20 @addtogroup TRNG True Random Number Generator(TRNG) 21 Memory Mapped Structure for TRNG Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var TRNG_T::CTL 31 * Offset: 0x00 TRNG Control Register and Status 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[0] |TRNGEN |Random Number Generator Enable Bit 36 * | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became to 1. 37 * | | |0 = TRNG Disabled. 38 * | | |1 = TRNG Enabled. 39 * | | |Note: TRNGEN is an enable bit of digital part 40 * | | |When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption. 41 * |[1] |DVIF |Data Valid (Read Only) 42 * | | |0 = Data is not valid. Reading from RNGD returns 0x00000000. 43 * | | |1 = Data is valid. A valid random number can be read form RNGD. 44 * | | |This bit is cleared to u20180u2019 by read TRNG_DATA. 45 * |[5:2] |CLKPSC |Clock Prescaler 46 * | | |The CLKP is the peripheral clock frequency range for the selected value , the CLKP must higher than or equal to the actual peripheral clock frequency (for correct random bit generation) 47 * | | |To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP; finally, set TRNGEN bit to 1 to re-enable the TRNG module. 48 * | | |0000 = 80 ~ 100 MHz. 49 * | | |0001 = 60 ~ 80 MHz. 50 * | | |0010 = 50 ~60 MHz. 51 * | | |0011 = 40 ~50 MHz. 52 * | | |0100 = 30 ~40 MHz. 53 * | | |0101 = 25 ~30 MHz. 54 * | | |0110 = 20 ~25 MHz. 55 * | | |0111 = 15 ~20 MHz. 56 * | | |1000 = 12 ~15 MHz. 57 * | | |1001 = 9 ~12 MHz. 58 * | | |1010 = 7 ~9 MHz. 59 * | | |1011 = 6 ~7 MHz. 60 * | | |1100 = 5 ~6 MHz. 61 * | | |1101 = 4 ~5 MHz. 62 * | | |1111 = Reserved. 63 * |[6] |DVIEN |Data Valid Interrupt Enable Bit 64 * | | |0 = Interrupt Disabled. 65 * | | |1 = Interrupt Enabled. 66 * |[7] |READY |Random Number Generator Ready (Read Only) 67 * | | |After ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us. 68 * | | |0 = RNG is not ready or was not activated. 69 * | | |1 = RNG is ready to be enabled.. 70 * |[8] |SEEDGEN |Random Number Seed Generator Enable Bit [for TRNG+PRNG] 71 * | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became to 1. 72 * | | |0 = Seed generator disabled. 73 * | | |1 = Seed generator enabled. 74 * | | |Note: If users want to execute TRNG+PRNG mode, they should set SEEDGEN to 1 75 * | | |When SEEDGEN was set to 1, users canu2019t read the data from TRNG Data Register. 76 * |[9] |SEEDRDY |Random Number Seed Ready (Read Only) [for TRNG+PRNG] 77 * | | |0 = Seed is not ready or was not activated. 78 * | | |1 = Seed is ready for PRNG. 79 * | | |Note 1:This bit is cleared to u20180u2019 when SEEDGEN is 1. 80 * | | |Note 2: If SEEDRDY become to 1, then SEEDGEN will be cleared to 0. 81 * |[31:10] |Reversed |Reversed 82 * @var TRNG_T::DATA 83 * Offset: 0x04 TRNG Data Register 84 * --------------------------------------------------------------------------------------------------- 85 * |Bits |Field |Descriptions 86 * | :----: | :----: | :---- | 87 * |[7:0] |DATA |Random Number Generator Data (Read Only) 88 * | | |The DATA store the random number generated by TRNG and can be read only once. 89 * @var TRNG_T::ACT 90 * Offset: 0x0C TRNG Activation Register 91 * --------------------------------------------------------------------------------------------------- 92 * |Bits |Field |Descriptions 93 * | :----: | :----: | :---- | 94 * |[6:0] |VER |TRNG Version 95 * | | |TRNG version number is dependent on TRNG module. 96 * | | |0x02:(Current Version Number) 97 * |[7] |ACT |Random Number Generator Activation 98 * | | |After enabling the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1. 99 * | | |0 = TRNG inactive. 100 * | | |1 = TRNG active. 101 * | | |Note: ACT is an enable bit of analog part 102 * | | |When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption. 103 */ 104 __IO uint32_t CTL; /*!< [0x0000] TRNG Control Register and Status */ 105 __I uint32_t DATA; /*!< [0x0004] TRNG Data Register */ 106 __I uint32_t RESERVE0[1]; 107 __IO uint32_t ACT; /*!< [0x000c] TRNG Activation Register */ 108 109 } TRNG_T; 110 111 /** 112 @addtogroup TRNG_CONST TRNG Bit Field Definition 113 Constant Definitions for TRNG Controller 114 @{ 115 */ 116 117 #define TRNG_CTL_TRNGEN_Pos (0) /*!< TRNG_T::CTL: TRNGEN Position */ 118 #define TRNG_CTL_TRNGEN_Msk (0x1ul << TRNG_CTL_TRNGEN_Pos) /*!< TRNG_T::CTL: TRNGEN Mask */ 119 120 #define TRNG_CTL_DVIF_Pos (1) /*!< TRNG_T::CTL: DVIF Position */ 121 #define TRNG_CTL_DVIF_Msk (0x1ul << TRNG_CTL_DVIF_Pos) /*!< TRNG_T::CTL: DVIF Mask */ 122 123 #define TRNG_CTL_CLKPSC_Pos (2) /*!< TRNG_T::CTL: CLKPSC Position */ 124 #define TRNG_CTL_CLKPSC_Msk (0xful << TRNG_CTL_CLKPSC_Pos) /*!< TRNG_T::CTL: CLKPSC Mask */ 125 126 #define TRNG_CTL_DVIEN_Pos (6) /*!< TRNG_T::CTL: DVIEN Position */ 127 #define TRNG_CTL_DVIEN_Msk (0x1ul << TRNG_CTL_DVIEN_Pos) /*!< TRNG_T::CTL: DVIEN Mask */ 128 129 #define TRNG_CTL_READY_Pos (7) /*!< TRNG_T::CTL: READY Position */ 130 #define TRNG_CTL_READY_Msk (0x1ul << TRNG_CTL_READY_Pos) /*!< TRNG_T::CTL: READY Mask */ 131 132 #define TRNG_CTL_SEEDGEN_Pos (8) /*!< TRNG_T::CTL: SEEDGEN Position */ 133 #define TRNG_CTL_SEEDGEN_Msk (0x1ul << TRNG_CTL_SEEDGEN_Pos) /*!< TRNG_T::CTL: SEEDGEN Mask */ 134 135 #define TRNG_CTL_SEEDRDY_Pos (9) /*!< TRNG_T::CTL: SEEDRDY Position */ 136 #define TRNG_CTL_SEEDRDY_Msk (0x1ul << TRNG_CTL_SEEDRDY_Pos) /*!< TRNG_T::CTL: SEEDRDY Mask */ 137 138 #define TRNG_CTL_Reversed_Pos (10) /*!< TRNG_T::CTL: Reversed Position */ 139 #define TRNG_CTL_Reversed_Msk (0x3ffffful << TRNG_CTL_Reversed_Pos) /*!< TRNG_T::CTL: Reversed Mask */ 140 141 #define TRNG_DATA_DATA_Pos (0) /*!< TRNG_T::DATA: DATA Position */ 142 #define TRNG_DATA_DATA_Msk (0xfful << TRNG_DATA_DATA_Pos) /*!< TRNG_T::DATA: DATA Mask */ 143 144 #define TRNG_ACT_VER_Pos (0) /*!< TRNG_T::ACT: VER Position */ 145 #define TRNG_ACT_VER_Msk (0x7ful << TRNG_ACT_VER_Pos) /*!< TRNG_T::ACT: VER Mask */ 146 147 #define TRNG_ACT_ACT_Pos (7) /*!< TRNG_T::ACT: ACT Position */ 148 #define TRNG_ACT_ACT_Msk (0x1ul << TRNG_ACT_ACT_Pos) /*!< TRNG_T::ACT: ACT Mask */ 149 150 /**@}*/ /* TRNG_CONST */ 151 /**@}*/ /* end of TRNG register group */ 152 153 /**@}*/ /* end of REGISTER group */ 154 155 156 #endif /* __TRNG_REG_H__ */ 157
