1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017, 2020-2023 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #include "fsl_trng.h"
9
10 #if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT
11
12 /*******************************************************************************
13 * Definitions
14 *******************************************************************************/
15
16 /* Component ID definition, used by tools. */
17 #ifndef FSL_COMPONENT_ID
18 #define FSL_COMPONENT_ID "platform.drivers.trng"
19 #endif
20
21 /* Default values for user configuration structure.*/
22 #if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES) || \
23 defined(MCIMX7U5_M4_SERIES) || defined(KW36Z4_SERIES) || defined(KW37A4_SERIES) || defined(KW37Z4_SERIES) || \
24 defined(KW38A4_SERIES) || defined(KW38Z4_SERIES) || defined(KW39A4_SERIES) || defined(KW35Z4_SERIES) || \
25 defined(KW36A4_SERIES) || defined(KW35A4_SERIES) || defined(KW34A4_SERIES))
26 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8
27 #elif (defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \
28 defined(KL82Z7_SERIES) || defined(K32L2A41A_SERIES))
29 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4
30 #elif ( \
31 defined(K81F25615_SERIES) || defined(K32L3A60_cm4_SERIES) || defined(K32L3A60_cm0plus_SERIES) || \
32 defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \
33 defined(MCXN547_cm33_core1_SERIES) || defined(MCXN945_cm33_core0_SERIES) || defined(MCXN945_cm33_core1_SERIES) || \
34 defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || defined(MCXN947_cm33_core0_SERIES) || \
35 defined(MCXN947_cm33_core1_SERIES) || defined(MCXN948_cm33_core0_SERIES) || defined(MCXN948_cm33_core1_SERIES))
36 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2
37 #else
38 /* Default value for the TRNG user configuration structure can be optionally
39 defined by device specific preprocessor macros. */
40 #if defined(FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_OSC_DIV) && \
41 (FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_OSC_DIV > 0)
42 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV (FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_OSC_DIV_VALUE)
43 #else
44 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv0
45 #endif
46 #endif
47
48 #if (defined(RW610_SERIES) || defined(RW612_SERIES))
49
50 /* RW610 specific settings for the TRNG */
51 #define TRNG_USER_CONFIG_DEFAULT_LOCK 0
52 #define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 20000
53 #define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 1024
54 #define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 0 // unused!
55 #define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1
56 #define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 32
57
58 #define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 596
59 #define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 169)
60 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 187
61 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 112)
62 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 105
63 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 77)
64 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 97
65 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 64)
66 // The following ones are unused, RW61x RNG does not support those.
67 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 0
68 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM 0
69 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 0
70 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM 0
71 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 0
72 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM 0
73 #define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 0
74 #define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM 0
75
76 #define TRNG_USER_CONFIG_DEFAULT_OSCILLATOR_MODE kTRNG_DualOscillatorMode
77 #define TRNG_USER_CONFIG_DEFAULT_OSC2_DIV kTRNG_RingOscDiv0
78
79 #define FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1
80 #define FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM_VALUE 20008
81 #define FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 1
82 #define FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM_VALUE 31952
83
84 #else
85
86 #ifndef TRNG_ENT_COUNT
87 #define TRNG_ENT_COUNT TRNG_ENTA_ENT_COUNT
88 #endif
89
90 #define TRNG_USER_CONFIG_DEFAULT_LOCK 0
91 #define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200
92 #define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 512
93 #define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63
94 #define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1
95 #define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 32
96
97 #define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 317
98 #define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 122)
99 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 107
100 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 80)
101 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 62
102 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 55)
103 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 39
104 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 39)
105 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 26
106 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 26)
107 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 18
108 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 18)
109 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 17
110 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 17)
111 #define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 1600
112 #define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 570)
113
114 // Only applicable for TRNG implementations that have two oscillators.
115 #if defined(FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS) && (FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS > 0)
116 #define TRNG_USER_CONFIG_DEFAULT_OSCILLATOR_MODE kTRNG_SingleOscillatorModeOsc1
117 #define TRNG_USER_CONFIG_DEFAULT_OSC2_DIV kTRNG_RingOscDiv4
118 #endif
119
120 #endif
121
122 #if defined(FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM) && \
123 (FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM > 0)
124 #define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM (FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM_VALUE)
125 #else
126 #define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 30000
127 #endif
128
129 #if defined(FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM) && \
130 (FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM > 0)
131 #define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM (FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM_VALUE)
132 #else
133 #define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1600
134 #endif
135
136 /*! @brief TRNG work mode */
137 typedef enum _trng_work_mode
138 {
139 kTRNG_WorkModeRun = 0U, /*!< Run Mode. */
140 kTRNG_WorkModeProgram = 1U /*!< Program Mode. */
141 } trng_work_mode_t;
142
143 /*! @brief TRNG statistical check type*/
144 typedef enum _trng_statistical_check
145 {
146 kTRNG_StatisticalCheckMonobit =
147 1U, /*!< Statistical check of number of ones/zero detected during entropy generation. */
148 kTRNG_StatisticalCheckRunBit1, /*!< Statistical check of number of runs of length 1 detected during entropy
149 generation. */
150 kTRNG_StatisticalCheckRunBit2, /*!< Statistical check of number of runs of length 2 detected during entropy
151 generation. */
152 kTRNG_StatisticalCheckRunBit3, /*!< Statistical check of number of runs of length 3 detected during entropy
153 generation. */
154 kTRNG_StatisticalCheckRunBit4, /*!< Statistical check of number of runs of length 4 detected during entropy
155 generation. */
156 kTRNG_StatisticalCheckRunBit5, /*!< Statistical check of number of runs of length 5 detected during entropy
157 generation. */
158 kTRNG_StatisticalCheckRunBit6Plus, /*!< Statistical check of number of runs of length 6 or more detected during
159 entropy generation. */
160 kTRNG_StatisticalCheckPoker, /*!< Statistical check of "Poker Test". */
161 kTRNG_StatisticalCheckFrequencyCount /*!< Statistical check of entropy sample frequency count. */
162 } trng_statistical_check_t;
163
164 /*******************************************************************************
165 * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register
166 ******************************************************************************/
167 /*!
168 * @name Register TRNG_SCMISC, field RTY_CT[19:16] (RW)
169 *
170 * RETRY COUNT. If a statistical check fails during the TRNG Entropy Generation,
171 * the RTY_CT value indicates the number of times a retry should occur before
172 * generating an error. This field is writable only if MCTL[PRGM] bit is 1. This
173 * field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 1h by writing
174 * the MCTL[RST_DEF] bit to 1.
175 */
176 /*@{*/
177 /*! @brief Read current value of the TRNG_SCMISC_RTY_CT field. */
178 #define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMISC_RTY_CT_SHIFT)
179
180 /*! @brief Set the RTY_CT field to a new value. */
181 #define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCMISC_RTY_CT(value)))
182 /*@}*/
183
184 /*******************************************************************************
185 * TRNG_SCML - RNG Statistical Check Monobit Limit Register
186 ******************************************************************************/
187 /*!
188 * @brief TRNG_SCML - RNG Statistical Check Monobit Limit Register (RW)
189 *
190 * Reset value: 0x010C0568U
191 *
192 * The RNG Statistical Check Monobit Limit Register defines the allowable
193 * maximum and minimum number of ones/zero detected during entropy generation. To pass
194 * the test, the number of ones/zeroes generated must be less than the programmed
195 * maximum value, and the number of ones/zeroes generated must be greater than
196 * (maximum - range). If this test fails, the Retry Counter in SCMISC will be
197 * decremented, and a retry will occur if the Retry Count has not reached zero. If
198 * the Retry Count has reached zero, an error will be generated. Note that this
199 * offset (0xBASE_0620) is used as SCML only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0,
200 * this offset is used as SCMC readback register.
201 */
202 /*!
203 * @name Constants and macros for entire TRNG_SCML register
204 */
205 /*@{*/
206 #define TRNG_SCML_REG(base) ((base)->SCML)
207 #define TRNG_RD_SCML(base) (TRNG_SCML_REG(base))
208 #define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value))
209 #define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (value)))
210 /*@}*/
211 /*!
212 * @name Register TRNG_SCML, field MONO_MAX[15:0] (RW)
213 *
214 * Monobit Maximum Limit. Defines the maximum allowable count taken during
215 * entropy generation. The number of ones/zeroes detected during entropy generation
216 * must be less than MONO_MAX, else a retry or error will occur. This register is
217 * cleared to 00056Bh (decimal 1387) by writing the MCTL[RST_DEF] bit to 1.
218 */
219 /*@{*/
220 /*! @brief Read current value of the TRNG_SCML_MONO_MAX field. */
221 #define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_MONO_MAX_SHIFT)
222
223 /*! @brief Set the MONO_MAX field to a new value. */
224 #define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_MONO_MAX(value)))
225 /*@}*/
226 /*!
227 * @name Register TRNG_SCML, field MONO_RNG[31:16] (RW)
228 *
229 * Monobit Range. The number of ones/zeroes detected during entropy generation
230 * must be greater than MONO_MAX - MONO_RNG, else a retry or error will occur.
231 * This register is cleared to 000112h (decimal 274) by writing the MCTL[RST_DEF]
232 * bit to 1.
233 */
234 /*@{*/
235 /*! @brief Read current value of the TRNG_SCML_MONO_RNG field. */
236 #define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_MONO_RNG_SHIFT)
237
238 /*! @brief Set the MONO_RNG field to a new value. */
239 #define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_MONO_RNG(value)))
240 /*@}*/
241
242 /*******************************************************************************
243 * TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register
244 ******************************************************************************/
245
246 /*!
247 * @brief TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register (RW)
248 *
249 * Reset value: 0x00B20195U
250 *
251 * The RNG Statistical Check Run Length 1 Limit Register defines the allowable
252 * maximum and minimum number of runs of length 1 detected during entropy
253 * generation. To pass the test, the number of runs of length 1 (for samples of both 0
254 * and 1) must be less than the programmed maximum value, and the number of runs of
255 * length 1 must be greater than (maximum - range). If this test fails, the
256 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
257 * Count has not reached zero. If the Retry Count has reached zero, an error will
258 * be generated. Note that this address (0xBASE_0624) is used as SCR1L only if
259 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR1C readback
260 * register.
261 */
262 /*!
263 * @name Constants and macros for entire TRNG_SCR1L register
264 */
265 /*@{*/
266 #define TRNG_SCR1L_REG(base) ((base)->SCR1L)
267 #define TRNG_RD_SCR1L(base) (TRNG_SCR1L_REG(base))
268 #define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value))
269 #define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (value)))
270 /*@}*/
271
272 /*!
273 * @name Register TRNG_SCR1L, field RUN1_MAX[14:0] (RW)
274 *
275 * Run Length 1 Maximum Limit. Defines the maximum allowable runs of length 1
276 * (for both 0 and 1) detected during entropy generation. The number of runs of
277 * length 1 detected during entropy generation must be less than RUN1_MAX, else a
278 * retry or error will occur. This register is cleared to 01E5h (decimal 485) by
279 * writing the MCTL[RST_DEF] bit to 1.
280 */
281 /*@{*/
282 /*! @brief Read current value of the TRNG_SCR1L_RUN1_MAX field. */
283 #define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR1L_RUN1_MAX_SHIFT)
284
285 /*! @brief Set the RUN1_MAX field to a new value. */
286 #define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SCR1L_RUN1_MAX(value)))
287 /*@}*/
288
289 /*!
290 * @name Register TRNG_SCR1L, field RUN1_RNG[30:16] (RW)
291 *
292 * Run Length 1 Range. The number of runs of length 1 (for both 0 and 1)
293 * detected during entropy generation must be greater than RUN1_MAX - RUN1_RNG, else a
294 * retry or error will occur. This register is cleared to 0102h (decimal 258) by
295 * writing the MCTL[RST_DEF] bit to 1.
296 */
297 /*@{*/
298 /*! @brief Read current value of the TRNG_SCR1L_RUN1_RNG field. */
299 #define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR1L_RUN1_RNG_SHIFT)
300
301 /*! @brief Set the RUN1_RNG field to a new value. */
302 #define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SCR1L_RUN1_RNG(value)))
303 /*@}*/
304
305 /*******************************************************************************
306 * TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register
307 ******************************************************************************/
308
309 /*!
310 * @brief TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register (RW)
311 *
312 * Reset value: 0x007A00DCU
313 *
314 * The RNG Statistical Check Run Length 2 Limit Register defines the allowable
315 * maximum and minimum number of runs of length 2 detected during entropy
316 * generation. To pass the test, the number of runs of length 2 (for samples of both 0
317 * and 1) must be less than the programmed maximum value, and the number of runs of
318 * length 2 must be greater than (maximum - range). If this test fails, the
319 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
320 * Count has not reached zero. If the Retry Count has reached zero, an error will
321 * be generated. Note that this address (0xBASE_0628) is used as SCR2L only if
322 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR2C readback
323 * register.
324 */
325 /*!
326 * @name Constants and macros for entire TRNG_SCR2L register
327 */
328 /*@{*/
329 #define TRNG_SCR2L_REG(base) ((base)->SCR2L)
330 #define TRNG_RD_SCR2L(base) (TRNG_SCR2L_REG(base))
331 #define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value))
332 #define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (value)))
333 /*@}*/
334
335 /*
336 * Constants & macros for individual TRNG_SCR2L bitfields
337 */
338
339 /*!
340 * @name Register TRNG_SCR2L, field RUN2_MAX[13:0] (RW)
341 *
342 * Run Length 2 Maximum Limit. Defines the maximum allowable runs of length 2
343 * (for both 0 and 1) detected during entropy generation. The number of runs of
344 * length 2 detected during entropy generation must be less than RUN2_MAX, else a
345 * retry or error will occur. This register is cleared to 00DCh (decimal 220) by
346 * writing the MCTL[RST_DEF] bit to 1.
347 */
348 /*@{*/
349 /*! @brief Read current value of the TRNG_SCR2L_RUN2_MAX field. */
350 #define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR2L_RUN2_MAX_SHIFT)
351
352 /*! @brief Set the RUN2_MAX field to a new value. */
353 #define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SCR2L_RUN2_MAX(value)))
354 /*@}*/
355
356 /*!
357 * @name Register TRNG_SCR2L, field RUN2_RNG[29:16] (RW)
358 *
359 * Run Length 2 Range. The number of runs of length 2 (for both 0 and 1)
360 * detected during entropy generation must be greater than RUN2_MAX - RUN2_RNG, else a
361 * retry or error will occur. This register is cleared to 007Ah (decimal 122) by
362 * writing the MCTL[RST_DEF] bit to 1.
363 */
364 /*@{*/
365 /*! @brief Read current value of the TRNG_SCR2L_RUN2_RNG field. */
366 #define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR2L_RUN2_RNG_SHIFT)
367
368 /*! @brief Set the RUN2_RNG field to a new value. */
369 #define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SCR2L_RUN2_RNG(value)))
370 /*@}*/
371
372 /*******************************************************************************
373 * TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register
374 ******************************************************************************/
375
376 /*!
377 * @brief TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register (RW)
378 *
379 * Reset value: 0x0058007DU
380 *
381 * The RNG Statistical Check Run Length 3 Limit Register defines the allowable
382 * maximum and minimum number of runs of length 3 detected during entropy
383 * generation. To pass the test, the number of runs of length 3 (for samples of both 0
384 * and 1) must be less than the programmed maximum value, and the number of runs of
385 * length 3 must be greater than (maximum - range). If this test fails, the
386 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
387 * Count has not reached zero. If the Retry Count has reached zero, an error will
388 * be generated. Note that this address (0xBASE_062C) is used as SCR3L only if
389 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR3C readback
390 * register.
391 */
392 /*!
393 * @name Constants and macros for entire TRNG_SCR3L register
394 */
395 /*@{*/
396 #define TRNG_SCR3L_REG(base) ((base)->SCR3L)
397 #define TRNG_RD_SCR3L(base) (TRNG_SCR3L_REG(base))
398 #define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value))
399 #define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (value)))
400 /*@}*/
401
402 /*
403 * Constants & macros for individual TRNG_SCR3L bitfields
404 */
405
406 /*!
407 * @name Register TRNG_SCR3L, field RUN3_MAX[12:0] (RW)
408 *
409 * Run Length 3 Maximum Limit. Defines the maximum allowable runs of length 3
410 * (for both 0 and 1) detected during entropy generation. The number of runs of
411 * length 3 detected during entropy generation must be less than RUN3_MAX, else a
412 * retry or error will occur. This register is cleared to 007Dh (decimal 125) by
413 * writing the MCTL[RST_DEF] bit to 1.
414 */
415 /*@{*/
416 /*! @brief Read current value of the TRNG_SCR3L_RUN3_MAX field. */
417 #define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR3L_RUN3_MAX_SHIFT)
418
419 /*! @brief Set the RUN3_MAX field to a new value. */
420 #define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SCR3L_RUN3_MAX(value)))
421 /*@}*/
422
423 /*!
424 * @name Register TRNG_SCR3L, field RUN3_RNG[28:16] (RW)
425 *
426 * Run Length 3 Range. The number of runs of length 3 (for both 0 and 1)
427 * detected during entropy generation must be greater than RUN3_MAX - RUN3_RNG, else a
428 * retry or error will occur. This register is cleared to 0058h (decimal 88) by
429 * writing the MCTL[RST_DEF] bit to 1.
430 */
431 /*@{*/
432 /*! @brief Read current value of the TRNG_SCR3L_RUN3_RNG field. */
433 #define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR3L_RUN3_RNG_SHIFT)
434
435 /*! @brief Set the RUN3_RNG field to a new value. */
436 #define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SCR3L_RUN3_RNG(value)))
437 /*@}*/
438
439 /*******************************************************************************
440 * TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register
441 ******************************************************************************/
442
443 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L)
444 /*!
445 * @brief TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register (RW)
446 *
447 * Reset value: 0x0040004BU
448 *
449 * The RNG Statistical Check Run Length 4 Limit Register defines the allowable
450 * maximum and minimum number of runs of length 4 detected during entropy
451 * generation. To pass the test, the number of runs of length 4 (for samples of both 0
452 * and 1) must be less than the programmed maximum value, and the number of runs of
453 * length 4 must be greater than (maximum - range). If this test fails, the
454 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
455 * Count has not reached zero. If the Retry Count has reached zero, an error will
456 * be generated. Note that this address (0xBASE_0630) is used as SCR4L only if
457 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR4C readback
458 * register.
459 */
460 /*!
461 * @name Constants and macros for entire TRNG_SCR4L register
462 */
463 /*@{*/
464 #define TRNG_SCR4L_REG(base) ((base)->SCR4L)
465 #define TRNG_RD_SCR4L(base) (TRNG_SCR4L_REG(base))
466 #define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value))
467 #define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (value)))
468 /*@}*/
469
470 /*
471 * Constants & macros for individual TRNG_SCR4L bitfields
472 */
473
474 /*!
475 * @name Register TRNG_SCR4L, field RUN4_MAX[11:0] (RW)
476 *
477 * Run Length 4 Maximum Limit. Defines the maximum allowable runs of length 4
478 * (for both 0 and 1) detected during entropy generation. The number of runs of
479 * length 4 detected during entropy generation must be less than RUN4_MAX, else a
480 * retry or error will occur. This register is cleared to 004Bh (decimal 75) by
481 * writing the MCTL[RST_DEF] bit to 1.
482 */
483 /*@{*/
484 /*! @brief Read current value of the TRNG_SCR4L_RUN4_MAX field. */
485 #define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR4L_RUN4_MAX_SHIFT)
486
487 /*! @brief Set the RUN4_MAX field to a new value. */
488 #define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SCR4L_RUN4_MAX(value)))
489 /*@}*/
490
491 /*!
492 * @name Register TRNG_SCR4L, field RUN4_RNG[27:16] (RW)
493 *
494 * Run Length 4 Range. The number of runs of length 4 (for both 0 and 1)
495 * detected during entropy generation must be greater than RUN4_MAX - RUN4_RNG, else a
496 * retry or error will occur. This register is cleared to 0040h (decimal 64) by
497 * writing the MCTL[RST_DEF] bit to 1.
498 */
499 /*@{*/
500 /*! @brief Read current value of the TRNG_SCR4L_RUN4_RNG field. */
501 #define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR4L_RUN4_RNG_SHIFT)
502
503 /*! @brief Set the RUN4_RNG field to a new value. */
504 #define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SCR4L_RUN4_RNG(value)))
505 /*@}*/
506 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L */
507
508 /*******************************************************************************
509 * TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register
510 ******************************************************************************/
511
512 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L)
513 /*!
514 * @brief TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register (RW)
515 *
516 * Reset value: 0x002E002FU
517 *
518 * The RNG Statistical Check Run Length 5 Limit Register defines the allowable
519 * maximum and minimum number of runs of length 5 detected during entropy
520 * generation. To pass the test, the number of runs of length 5 (for samples of both 0
521 * and 1) must be less than the programmed maximum value, and the number of runs of
522 * length 5 must be greater than (maximum - range). If this test fails, the
523 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
524 * Count has not reached zero. If the Retry Count has reached zero, an error will
525 * be generated. Note that this address (0xBASE_0634) is used as SCR5L only if
526 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR5C readback
527 * register.
528 */
529 /*!
530 * @name Constants and macros for entire TRNG_SCR5L register
531 */
532 /*@{*/
533 #define TRNG_SCR5L_REG(base) ((base)->SCR5L)
534 #define TRNG_RD_SCR5L(base) (TRNG_SCR5L_REG(base))
535 #define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value))
536 #define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (value)))
537 /*@}*/
538
539 /*
540 * Constants & macros for individual TRNG_SCR5L bitfields
541 */
542
543 /*!
544 * @name Register TRNG_SCR5L, field RUN5_MAX[10:0] (RW)
545 *
546 * Run Length 5 Maximum Limit. Defines the maximum allowable runs of length 5
547 * (for both 0 and 1) detected during entropy generation. The number of runs of
548 * length 5 detected during entropy generation must be less than RUN5_MAX, else a
549 * retry or error will occur. This register is cleared to 002Fh (decimal 47) by
550 * writing the MCTL[RST_DEF] bit to 1.
551 */
552 /*@{*/
553 /*! @brief Read current value of the TRNG_SCR5L_RUN5_MAX field. */
554 #define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR5L_RUN5_MAX_SHIFT)
555
556 /*! @brief Set the RUN5_MAX field to a new value. */
557 #define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SCR5L_RUN5_MAX(value)))
558 /*@}*/
559
560 /*!
561 * @name Register TRNG_SCR5L, field RUN5_RNG[26:16] (RW)
562 *
563 * Run Length 5 Range. The number of runs of length 5 (for both 0 and 1)
564 * detected during entropy generation must be greater than RUN5_MAX - RUN5_RNG, else a
565 * retry or error will occur. This register is cleared to 002Eh (decimal 46) by
566 * writing the MCTL[RST_DEF] bit to 1.
567 */
568 /*@{*/
569 /*! @brief Read current value of the TRNG_SCR5L_RUN5_RNG field. */
570 #define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR5L_RUN5_RNG_SHIFT)
571
572 /*! @brief Set the RUN5_RNG field to a new value. */
573 #define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SCR5L_RUN5_RNG(value)))
574 /*@}*/
575 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L */
576
577 /*******************************************************************************
578 * TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register
579 ******************************************************************************/
580
581 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L)
582 /*!
583 * @brief TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register (RW)
584 *
585 * Reset value: 0x002E002FU
586 *
587 * The RNG Statistical Check Run Length 6+ Limit Register defines the allowable
588 * maximum and minimum number of runs of length 6 or more detected during entropy
589 * generation. To pass the test, the number of runs of length 6 or more (for
590 * samples of both 0 and 1) must be less than the programmed maximum value, and the
591 * number of runs of length 6 or more must be greater than (maximum - range). If
592 * this test fails, the Retry Counter in SCMISC will be decremented, and a retry
593 * will occur if the Retry Count has not reached zero. If the Retry Count has
594 * reached zero, an error will be generated. Note that this offset (0xBASE_0638) is
595 * used as SCR6PL only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is
596 * used as SCR6PC readback register.
597 */
598 /*!
599 * @name Constants and macros for entire TRNG_SCR6PL register
600 */
601 /*@{*/
602 #define TRNG_SCR6PL_REG(base) ((base)->SCR6PL)
603 #define TRNG_RD_SCR6PL(base) (TRNG_SCR6PL_REG(base))
604 #define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value))
605 #define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) | (value)))
606 /*@}*/
607
608 /*
609 * Constants & macros for individual TRNG_SCR6PL bitfields
610 */
611
612 /*!
613 * @name Register TRNG_SCR6PL, field RUN6P_MAX[10:0] (RW)
614 *
615 * Run Length 6+ Maximum Limit. Defines the maximum allowable runs of length 6
616 * or more (for both 0 and 1) detected during entropy generation. The number of
617 * runs of length 6 or more detected during entropy generation must be less than
618 * RUN6P_MAX, else a retry or error will occur. This register is cleared to 002Fh
619 * (decimal 47) by writing the MCTL[RST_DEF] bit to 1.
620 */
621 /*@{*/
622 /*! @brief Read current value of the TRNG_SCR6PL_RUN6P_MAX field. */
623 #define TRNG_RD_SCR6PL_RUN6P_MAX(base) \
624 ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRNG_SCR6PL_RUN6P_MAX_SHIFT)
625
626 /*! @brief Set the RUN6P_MAX field to a new value. */
627 #define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) \
628 (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TRNG_SCR6PL_RUN6P_MAX(value)))
629 /*@}*/
630
631 /*!
632 * @name Register TRNG_SCR6PL, field RUN6P_RNG[26:16] (RW)
633 *
634 * Run Length 6+ Range. The number of runs of length 6 or more (for both 0 and
635 * 1) detected during entropy generation must be greater than RUN6P_MAX -
636 * RUN6P_RNG, else a retry or error will occur. This register is cleared to 002Eh
637 * (decimal 46) by writing the MCTL[RST_DEF] bit to 1.
638 */
639 /*@{*/
640 /*! @brief Read current value of the TRNG_SCR6PL_RUN6P_RNG field. */
641 #define TRNG_RD_SCR6PL_RUN6P_RNG(base) \
642 ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRNG_SCR6PL_RUN6P_RNG_SHIFT)
643
644 /*! @brief Set the RUN6P_RNG field to a new value. */
645 #define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) \
646 (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TRNG_SCR6PL_RUN6P_RNG(value)))
647 /*@}*/
648 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L */
649
650 /*******************************************************************************
651 * TRNG_PKRMAX - RNG Poker Maximum Limit Register
652 ******************************************************************************/
653
654 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX) && FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX)
655 /*!
656 * @brief TRNG_PKRMAX - RNG Poker Maximum Limit Register (RW)
657 *
658 * Reset value: 0x00006920U
659 *
660 * The RNG Poker Maximum Limit Register defines Maximum Limit allowable during
661 * the TRNG Statistical Check Poker Test. Note that this offset (0xBASE_060C) is
662 * used as PKRMAX only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used
663 * as the PKRSQ readback register.
664 */
665 /*!
666 * @name Constants and macros for entire TRNG_PKRMAX register
667 */
668 /*@{*/
669 #define TRNG_PKRMAX_REG(base) ((base)->PKRMAX)
670 #define TRNG_RD_PKRMAX(base) (TRNG_PKRMAX_REG(base))
671 #define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value))
672 #define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) | (value)))
673 /*@}*/
674
675 /*
676 * Constants & macros for individual TRNG_PKRMAX bitfields
677 */
678
679 /*!
680 * @name Register TRNG_PKRMAX, field PKR_MAX[23:0] (RW)
681 *
682 * Poker Maximum Limit. During the TRNG Statistical Checks, a "Poker Test" is
683 * run which requires a maximum and minimum limit. The maximum allowable result is
684 * programmed in the PKRMAX[PKR_MAX] register. This field is writable only if
685 * MCTL[PRGM] bit is 1. This register is cleared to 006920h (decimal 26912) by
686 * writing the MCTL[RST_DEF] bit to 1. Note that the PKRMAX and PKRRNG registers
687 * combined are used to define the minimum allowable Poker result, which is PKR_MAX -
688 * PKR_RNG + 1. Note that if MCTL[PRGM] bit is 0, this register address is used
689 * to read the Poker Test Square Calculation result in register PKRSQ, as defined
690 * in the following section.
691 */
692 /*@{*/
693 /*! @brief Read current value of the TRNG_PKRMAX_PKR_MAX field. */
694 #define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PKRMAX_PKR_MAX_SHIFT)
695
696 /*! @brief Set the PKR_MAX field to a new value. */
697 #define TRNG_WR_PKRMAX_PKR_MAX(base, value) \
698 (TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_PKRMAX_PKR_MAX(value)))
699 /*@}*/
700 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX */
701
702 /*******************************************************************************
703 * TRNG_PKRRNG - RNG Poker Range Register
704 ******************************************************************************/
705
706 /*!
707 * @brief TRNG_PKRRNG - RNG Poker Range Register (RW)
708 *
709 * Reset value: 0x000009A3U
710 *
711 * The RNG Poker Range Register defines the difference between the TRNG Poker
712 * Maximum Limit and the minimum limit. These limits are used during the TRNG
713 * Statistical Check Poker Test.
714 */
715 /*!
716 * @name Constants and macros for entire TRNG_PKRRNG register
717 */
718 /*@{*/
719 #define TRNG_PKRRNG_REG(base) ((base)->PKRRNG)
720 #define TRNG_RD_PKRRNG(base) (TRNG_PKRRNG_REG(base))
721 #define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value))
722 #define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) | (value)))
723 /*@}*/
724
725 /*
726 * Constants & macros for individual TRNG_PKRRNG bitfields
727 */
728
729 /*!
730 * @name Register TRNG_PKRRNG, field PKR_RNG[15:0] (RW)
731 *
732 * Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which
733 * requires a maximum and minimum limit. The maximum is programmed in the
734 * RTPKRMAX[PKR_MAX] register, and the minimum is derived by subtracting the PKR_RNG
735 * value from the programmed maximum value. This field is writable only if
736 * MCTL[PRGM] bit is 1. This field will read zeroes if MCTL[PRGM] = 0. This field is
737 * cleared to 09A3h (decimal 2467) by writing the MCTL[RST_DEF] bit to 1. Note that
738 * the minimum allowable Poker result is PKR_MAX - PKR_RNG + 1.
739 */
740 /*@{*/
741 /*! @brief Read current value of the TRNG_PKRRNG_PKR_RNG field. */
742 #define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PKRRNG_PKR_RNG_SHIFT)
743
744 /*! @brief Set the PKR_RNG field to a new value. */
745 #define TRNG_WR_PKRRNG_PKR_RNG(base, value) \
746 (TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_PKRRNG_PKR_RNG(value)))
747 /*@}*/
748
749 /*******************************************************************************
750 * TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register
751 ******************************************************************************/
752
753 /*!
754 * @brief TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register (RW)
755 *
756 * Reset value: 0x00006400U
757 *
758 * The RNG Frequency Count Maximum Limit Register defines the maximum allowable
759 * count taken by the Entropy sample counter during each Entropy sample. During
760 * any sample period, if the count is greater than this programmed maximum, a
761 * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. Note
762 * that this address (061C) is used as FRQMAX only if MCTL[PRGM] is 1. If
763 * MCTL[PRGM] is 0, this address is used as FRQCNT readback register.
764 */
765 /*!
766 * @name Constants and macros for entire TRNG_FRQMAX register
767 */
768 /*@{*/
769 #define TRNG_FRQMAX_REG(base) ((base)->FRQMAX)
770 #define TRNG_RD_FRQMAX(base) (TRNG_FRQMAX_REG(base))
771 #define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value))
772 #define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) | (value)))
773 /*@}*/
774
775 /*
776 * Constants & macros for individual TRNG_FRQMAX bitfields
777 */
778
779 /*!
780 * @name Register TRNG_FRQMAX, field FRQ_MAX[21:0] (RW)
781 *
782 * Frequency Counter Maximum Limit. Defines the maximum allowable count taken
783 * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1.
784 * This register is cleared to 000640h by writing the MCTL[RST_DEF] bit to 1.
785 * Note that if MCTL[PRGM] bit is 0, this register address is used to read the
786 * Frequency Count result in register FRQCNT, as defined in the following section.
787 */
788 /*@{*/
789 /*! @brief Read current value of the TRNG_FRQMAX_FRQ_MAX field. */
790 #define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FRQMAX_FRQ_MAX_SHIFT)
791
792 /*! @brief Set the FRQ_MAX field to a new value. */
793 #define TRNG_WR_FRQMAX_FRQ_MAX(base, value) \
794 (TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_FRQMAX_FRQ_MAX(value)))
795 /*@}*/
796
797 /*******************************************************************************
798 * TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register
799 ******************************************************************************/
800
801 /*!
802 * @brief TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register (RW)
803 *
804 * Reset value: 0x00000640U
805 *
806 * The RNG Frequency Count Minimum Limit Register defines the minimum allowable
807 * count taken by the Entropy sample counter during each Entropy sample. During
808 * any sample period, if the count is less than this programmed minimum, a
809 * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated.
810 */
811 /*!
812 * @name Constants and macros for entire TRNG_FRQMIN register
813 */
814 /*@{*/
815 #define TRNG_FRQMIN_REG(base) ((base)->FRQMIN)
816 #define TRNG_RD_FRQMIN(base) (TRNG_FRQMIN_REG(base))
817 #define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value))
818 #define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) | (value)))
819 /*@}*/
820
821 /*
822 * Constants & macros for individual TRNG_FRQMIN bitfields
823 */
824
825 /*!
826 * @name Register TRNG_FRQMIN, field FRQ_MIN[21:0] (RW)
827 *
828 * Frequency Count Minimum Limit. Defines the minimum allowable count taken
829 * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1.
830 * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 0000h64
831 * by writing the MCTL[RST_DEF] bit to 1.
832 */
833 /*@{*/
834 /*! @brief Read current value of the TRNG_FRQMIN_FRQ_MIN field. */
835 #define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FRQMIN_FRQ_MIN_SHIFT)
836
837 /*! @brief Set the FRQ_MIN field to a new value. */
838 #define TRNG_WR_FRQMIN_FRQ_MIN(base, value) \
839 (TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_FRQMIN_FRQ_MIN(value)))
840 /*@}*/
841
842 /*******************************************************************************
843 * TRNG_MCTL - RNG Miscellaneous Control Register
844 ******************************************************************************/
845
846 /*!
847 * @brief TRNG_MCTL - RNG Miscellaneous Control Register (RW)
848 *
849 * Reset value: 0x00012001U
850 *
851 * This register is intended to be used for programming, configuring and testing
852 * the RNG. It is the main register to read/write, in order to enable Entropy
853 * generation, to stop entropy generation and to block access to entropy registers.
854 * This is done via the special TRNG_ACC and PRGM bits below. The RNG
855 * Miscellaneous Control Register is a read/write register used to control the RNG's True
856 * Random Number Generator (TRNG) access, operation and test. Note that in many
857 * cases two RNG registers share the same address, and a particular register at the
858 * shared address is selected based upon the value in the PRGM field of the MCTL
859 * register.
860 */
861 /*!
862 * @name Constants and macros for entire TRNG_MCTL register
863 */
864 /*@{*/
865 #define TRNG_MCTL_REG(base) ((base)->MCTL)
866 #define TRNG_RD_MCTL(base) (TRNG_MCTL_REG(base))
867 #define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value))
868 #define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (value)))
869 /*@}*/
870
871 /*!
872 * @name Register TRNG_MCTL, field FOR_SCLK[7] (RW)
873 *
874 * Force System Clock. If set, the system clock is used to operate the TRNG,
875 * instead of the ring oscillator. This is for test use only, and indeterminate
876 * results may occur. This bit is writable only if PRGM bit is 1, or PRGM bit is
877 * being written to 1 simultaneously to writing this bit. This bit is cleared by
878 * writing the RST_DEF bit to 1.
879 */
880 /*@{*/
881 /*! @brief Read current value of the TRNG_MCTL_FOR_SCLK field. */
882 #define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_FOR_SCLK_SHIFT)
883
884 /*! @brief Set the FOR_SCLK field to a new value. */
885 #define TRNG_WR_MCTL_FOR_SCLK(base, value) \
886 (TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_FOR_SCLK(value)))
887 /*@}*/
888
889 /*!
890 * @name Register TRNG_MCTL, field OSC_DIV[3:2] (RW)
891 *
892 * Oscillator Divide. Determines the amount of dividing done to the ring
893 * oscillator before it is used by the TRNG.This field is writable only if PRGM bit is
894 * 1, or PRGM bit is being written to 1 simultaneously to writing this field. This
895 * field is cleared to 00 by writing the RST_DEF bit to 1.
896 *
897 * Values:
898 * - 0b00 - use ring oscillator with no divide
899 * - 0b01 - use ring oscillator divided-by-2
900 * - 0b10 - use ring oscillator divided-by-4
901 * - 0b11 - use ring oscillator divided-by-8
902 */
903 /*@{*/
904 /*! @brief Read current value of the TRNG_MCTL_OSC_DIV field. */
905 #define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC_DIV_SHIFT)
906
907 /*! @brief Set the OSC_DIV field to a new value. */
908 #define TRNG_WR_MCTL_OSC_DIV(base, value) \
909 (TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_OSC_DIV(value)))
910 /*@}*/
911
912 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE) && FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE)
913 /*!
914 * @name Register TRNG_MCTL, field SAMP_MODE[1:0] (RW)
915 *
916 * Sample Mode. Determines the method of sampling the ring oscillator while
917 * generating the Entropy value:This field is writable only if PRGM bit is 1, or PRGM
918 * bit is being written to 1 simultaneously with writing this field. This field
919 * is cleared to 01 by writing the RST_DEF bit to 1.
920 *
921 * Values:
922 * - 0b00 - use Von Neumann data into both Entropy shifter and Statistical
923 * Checker
924 * - 0b01 - use raw data into both Entropy shifter and Statistical Checker
925 * - 0b10 - use Von Neumann data into Entropy shifter. Use raw data into
926 * Statistical Checker
927 * - 0b11 - reserved.
928 */
929 /*@{*/
930 /*! @brief Read current value of the TRNG_MCTL_SAMP_MODE field. */
931 #define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL_SAMP_MODE_SHIFT)
932
933 /*! @brief Set the SAMP_MODE field to a new value. */
934 #define TRNG_WR_MCTL_SAMP_MODE(base, value) \
935 (TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_SAMP_MODE(value)))
936 /*@}*/
937 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE */
938
939 /*!
940 * @name Register TRNG_MCTL, field PRGM[16] (RW)
941 *
942 * Programming Mode Select. When this bit is 1, the TRNG is in Program Mode,
943 * otherwise it is in Run Mode. No Entropy value will be generated while the TRNG is
944 * in Program Mode. Note that different RNG registers are accessible at the same
945 * address depending on whether PRGM is set to 1 or 0. This is noted in the RNG
946 * register descriptions.
947 */
948 /*@{*/
949 /*! @brief Read current value of the TRNG_MCTL_PRGM field. */
950 #define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIFT)
951
952 /*! @brief Set the PRGM field to a new value. */
953 #define TRNG_WR_MCTL_PRGM(base, value) \
954 (TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_PRGM(value)))
955 /*@}*/
956
957 /*!
958 * @name Register TRNG_MCTL, field RST_DEF[6] (WO)
959 *
960 * Reset Defaults. Writing a 1 to this bit clears various TRNG registers, and
961 * bits within registers, to their default state. This bit is writable only if PRGM
962 * bit is 1, or PRGM bit is being written to 1 simultaneously to writing this
963 * bit. Reading this bit always produces a 0.
964 */
965 /*@{*/
966 /*! @brief Set the RST_DEF field to a new value. */
967 #define TRNG_WR_MCTL_RST_DEF(base, value) \
968 (TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_RST_DEF(value)))
969 /*@}*/
970
971 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0))
972 /*!
973 * @name Register TRNG_MCTL, field TRNG_ACC[5] (RW)
974 *
975 * TRNG Access Mode. If this bit is set to 1, the TRNG will generate an Entropy
976 * value that can be read via the ENT0-ENT15 registers. The Entropy value may be
977 * read once the ENT VAL bit is asserted. Also see ENTa register descriptions
978 * (For a = 0 to 15).
979 */
980 /*@{*/
981 /*! @brief Read current value of the TRNG_MCTL_TRNG_ACC field. */
982 #define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_TRNG_ACC_SHIFT)
983
984 /*! @brief Set the TRNG_ACC field to a new value. */
985 #define TRNG_WR_MCTL_TRNG_ACC(base, value) \
986 (TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_TRNG_ACC(value)))
987 /*@}*/
988 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC */
989
990 /*!
991 * @name Register TRNG_MCTL, field TSTOP_OK[13] (RO)
992 *
993 * TRNG_OK_TO_STOP. Software should check that this bit is a 1 before
994 * transitioning RNG to low power mode (RNG clock stopped). RNG turns on the TRNG
995 * free-running ring oscillator whenever new entropy is being generated and turns off the
996 * ring oscillator when entropy generation is complete. If the RNG clock is
997 * stopped while the TRNG ring oscillator is running, the oscillator will continue
998 * running even though the RNG clock is stopped. TSTOP_OK is asserted when the TRNG
999 * ring oscillator is not running. and therefore it is ok to stop the RNG clock.
1000 */
1001 /*@{*/
1002 /*! @brief Read current value of the TRNG_MCTL_TSTOP_OK field. */
1003 #define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_TSTOP_OK_SHIFT)
1004 /*@}*/
1005
1006 /*!
1007 * @name Register TRNG_MCTL, field ENT_VAL[10] (RO)
1008 *
1009 * Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then
1010 * after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0
1011 * through ENT14 should be read before reading ENT15).
1012 */
1013 /*@{*/
1014 /*! @brief Read current value of the TRNG_MCTL_ENT_VAL field. */
1015 #define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT_VAL_SHIFT)
1016 /*@}*/
1017
1018 /*!
1019 * @name Register TRNG_MCTL, field ERR[12] (W1C)
1020 *
1021 * Read: Error status. 1 = error detected. 0 = no error.Write: Write 1 to clear
1022 * errors. Writing 0 has no effect.
1023 */
1024 /*@{*/
1025 /*! @brief Read current value of the TRNG_MCTL_ERR field. */
1026 #define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT)
1027
1028 /*! @brief Set the ERR field to a new value. */
1029 #define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value)))
1030 /*@}*/
1031
1032 /*******************************************************************************
1033 * TRNG_SDCTL - RNG Seed Control Register
1034 ******************************************************************************/
1035
1036 /*!
1037 * @brief TRNG_SDCTL - RNG Seed Control Register (RW)
1038 *
1039 * Reset value: 0x0C8009C4U
1040 *
1041 * The RNG Seed Control Register contains two fields. One field defines the
1042 * length (in system clocks) of each Entropy sample (ENT_DLY), and the other field
1043 * indicates the number of samples that will taken during each TRNG Entropy
1044 * generation (SAMP_SIZE).
1045 */
1046 /*!
1047 * @name Constants and macros for entire TRNG_SDCTL register
1048 */
1049 /*@{*/
1050 #define TRNG_SDCTL_REG(base) ((base)->SDCTL)
1051 #define TRNG_RD_SDCTL(base) (TRNG_SDCTL_REG(base))
1052 #define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value))
1053 #define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (value)))
1054 /*@}*/
1055
1056 /*
1057 * Constants & macros for individual TRNG_SDCTL bitfields
1058 */
1059
1060 /*!
1061 * @name Register TRNG_SDCTL, field SAMP_SIZE[15:0] (RW)
1062 *
1063 * Sample Size. Defines the total number of Entropy samples that will be taken
1064 * during Entropy generation. This field is writable only if MCTL[PRGM] bit is 1.
1065 * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 09C4h
1066 * (decimal 2500) by writing the MCTL[RST_DEF] bit to 1.
1067 */
1068 /*@{*/
1069 /*! @brief Read current value of the TRNG_SDCTL_SAMP_SIZE field. */
1070 #define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_SDCTL_SAMP_SIZE_SHIFT)
1071
1072 /*! @brief Set the SAMP_SIZE field to a new value. */
1073 #define TRNG_WR_SDCTL_SAMP_SIZE(base, value) \
1074 (TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_SDCTL_SAMP_SIZE(value)))
1075 /*@}*/
1076
1077 /*!
1078 * @name Register TRNG_SDCTL, field ENT_DLY[31:16] (RW)
1079 *
1080 * Entropy Delay. Defines the length (in system clocks) of each Entropy sample
1081 * taken. This field is writable only if MCTL[PRGM] bit is 1. This field will read
1082 * zeroes if MCTL[PRGM] = 0. This field is cleared to 0C80h (decimal 3200) by
1083 * writing the MCTL[RST_DEF] bit to 1.
1084 */
1085 /*@{*/
1086 /*! @brief Read current value of the TRNG_SDCTL_ENT_DLY field. */
1087 #define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL_ENT_DLY_SHIFT)
1088
1089 /*! @brief Set the ENT_DLY field to a new value. */
1090 #define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCTL_ENT_DLY(value)))
1091 /*@}*/
1092
1093 /*******************************************************************************
1094 * TRNG_SBLIM - RNG Sparse Bit Limit Register
1095 ******************************************************************************/
1096
1097 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM > 0))
1098 /*!
1099 * @brief TRNG_SBLIM - RNG Sparse Bit Limit Register (RW)
1100 *
1101 * Reset value: 0x0000003FU
1102 *
1103 * The RNG Sparse Bit Limit Register is used when Von Neumann sampling is
1104 * selected during Entropy Generation. It defines the maximum number of consecutive Von
1105 * Neumann samples which may be discarded before an error is generated. Note
1106 * that this address (0xBASE_0614) is used as SBLIM only if MCTL[PRGM] is 1. If
1107 * MCTL[PRGM] is 0, this address is used as TOTSAM readback register.
1108 */
1109 /*!
1110 * @name Constants and macros for entire TRNG_SBLIM register
1111 */
1112 /*@{*/
1113 #define TRNG_SBLIM_REG(base) ((base)->SBLIM)
1114 #define TRNG_RD_SBLIM(base) (TRNG_SBLIM_REG(base))
1115 #define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value))
1116 #define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (value)))
1117 /*@}*/
1118
1119 /*
1120 * Constants & macros for individual TRNG_SBLIM bitfields
1121 */
1122
1123 /*!
1124 * @name Register TRNG_SBLIM, field SB_LIM[9:0] (RW)
1125 *
1126 * Sparse Bit Limit. During Von Neumann sampling (if enabled by MCTL[SAMP_MODE],
1127 * samples are discarded if two consecutive raw samples are both 0 or both 1. If
1128 * this discarding occurs for a long period of time, it indicates that there is
1129 * insufficient Entropy. The Sparse Bit Limit defines the maximum number of
1130 * consecutive samples that may be discarded before an error is generated. This field
1131 * is writable only if MCTL[PRGM] bit is 1. This register is cleared to 03hF by
1132 * writing the MCTL[RST_DEF] bit to 1. Note that if MCTL[PRGM] bit is 0, this
1133 * register address is used to read the Total Samples count in register TOTSAM, as
1134 * defined in the following section.
1135 */
1136 /*@{*/
1137 /*! @brief Read current value of the TRNG_SBLIM_SB_LIM field. */
1138 #define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_SB_LIM_SHIFT)
1139
1140 /*! @brief Set the SB_LIM field to a new value. */
1141 #define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_SB_LIM(value)))
1142 /*@}*/
1143 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM */
1144
1145 /*******************************************************************************
1146 * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register
1147 ******************************************************************************/
1148
1149 /*!
1150 * @brief TRNG_SCMISC - RNG Statistical Check Miscellaneous Register (RW)
1151 *
1152 * Reset value: 0x0001001FU
1153 *
1154 * The RNG Statistical Check Miscellaneous Register contains the Long Run
1155 * Maximum Limit value and the Retry Count value. This register is accessible only when
1156 * the MCTL[PRGM] bit is 1, otherwise this register will read zeroes, and cannot
1157 * be written.
1158 */
1159 /*!
1160 * @name Constants and macros for entire TRNG_SCMISC register
1161 */
1162 /*@{*/
1163 #define TRNG_SCMISC_REG(base) ((base)->SCMISC)
1164 #define TRNG_RD_SCMISC(base) (TRNG_SCMISC_REG(base))
1165 #define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value))
1166 #define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) | (value)))
1167 /*@}*/
1168
1169 /*
1170 * Constants & macros for individual TRNG_SCMISC bitfields
1171 */
1172
1173 /*!
1174 * @name Register TRNG_SCMISC, field LRUN_MAX[7:0] (RW)
1175 *
1176 * LONG RUN MAX LIMIT. This value is the largest allowable number of consecutive
1177 * samples of all 1, or all 0, that is allowed during the Entropy generation.
1178 * This field is writable only if MCTL[PRGM] bit is 1. This field will read zeroes
1179 * if MCTL[PRGM] = 0. This field is cleared to 22h by writing the MCTL[RST_DEF]
1180 * bit to 1.
1181 */
1182 /*@{*/
1183 /*! @brief Read current value of the TRNG_SCMISC_LRUN_MAX field. */
1184 #define TRNG_RD_SCMISC_LRUN_MAX(base) \
1185 ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_SCMISC_LRUN_MAX_SHIFT)
1186
1187 /*! @brief Set the LRUN_MAX field to a new value. */
1188 #define TRNG_WR_SCMISC_LRUN_MAX(base, value) \
1189 (TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG_SCMISC_LRUN_MAX(value)))
1190 /*@}*/
1191
1192 /*******************************************************************************
1193 * TRNG_ENT - RNG TRNG Entropy Read Register
1194 ******************************************************************************/
1195
1196 /*!
1197 * @brief TRNG_ENT - RNG TRNG Entropy Read Register (RO)
1198 *
1199 * Reset value: 0x00000000U
1200 *
1201 * The RNG TRNG can be programmed to generate an entropy value that is readable
1202 * via the SkyBlue bus. To do this, set the MCTL[TRNG_ACC] bit to 1. Once the
1203 * entropy value has been generated, the MCTL[ENT_VAL] bit will be set to 1. At this
1204 * point, ENT0 through ENT15 may be read to retrieve the 512-bit entropy value.
1205 * Note that once ENT15 is read, the entropy value will be cleared and a new
1206 * value will begin generation, so it is important that ENT15 be read last. These
1207 * registers are readable only when MCTL[PRGM] = 0 (Run Mode), MCTL[TRNG_ACC] = 1
1208 * (TRNG access mode) and MCTL[ENT_VAL] = 1, otherwise zeroes will be read.
1209 */
1210 /*!
1211 * @name Constants and macros for entire TRNG_ENT register
1212 */
1213 /*@{*/
1214 #define TRNG_ENT_REG(base, index) ((base)->ENT[index])
1215 #define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index))
1216 /*@}*/
1217
1218 /*******************************************************************************
1219 * TRNG_SEC_CFG - RNG Security Configuration Register
1220 ******************************************************************************/
1221
1222 /*!
1223 * @brief TRNG_SEC_CFG - RNG Security Configuration Register (RW)
1224 *
1225 * Reset value: 0x00000000U
1226 *
1227 * The RNG Security Configuration Register is a read/write register used to
1228 * control the test mode, programmability and state modes of the RNG. Many bits are
1229 * place holders for this version. More configurability will be added here. Clears
1230 * on asynchronous reset. For SA-TRNG releases before 2014/July/01, offsets 0xA0
1231 * to 0xAC used to be 0xB0 to 0xBC respectively. So, update newer tests that use
1232 * these registers, if hard coded.
1233 */
1234 /*!
1235 * @name Constants and macros for entire TRNG_SEC_CFG register
1236 */
1237 /*@{*/
1238 #define TRNG_SEC_CFG_REG(base) ((base)->SEC_CFG)
1239 #define TRNG_RD_SEC_CFG(base) (TRNG_SEC_CFG_REG(base))
1240 #define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value))
1241 #define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)) | (value)))
1242 /*@}*/
1243
1244 /*!
1245 * @name Register TRNG_SEC_CFG, field NO_PRGM[1] (RW)
1246 *
1247 * If set the TRNG registers cannot be programmed. That is, regardless of the
1248 * TRNG access mode in the SA-TRNG Miscellaneous Control Register.
1249 *
1250 * Values:
1251 * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous
1252 * Control Register's access mode bit.
1253 * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents
1254 * TRNG register programming.
1255 */
1256 /*@{*/
1257 /*! @brief Read current value of the TRNG_SEC_CFG_NO_PRGM field. */
1258 #define TRNG_RD_SEC_CFG_NO_PRGM(base) \
1259 ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG_SEC_CFG_NO_PRGM_SHIFT)
1260
1261 /*! @brief Set the NO_PRGM field to a new value. */
1262 #define TRNG_WR_SEC_CFG_NO_PRGM(base, value) \
1263 (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRNG_SEC_CFG_NO_PRGM(value)))
1264 /*@}*/
1265
1266 /*! @brief Array to map TRNG instance number to base pointer. */
1267 static TRNG_Type *const s_trngBases[] = TRNG_BASE_PTRS;
1268
1269 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1270 /*! @brief Clock array name */
1271 static const clock_ip_name_t s_trngClock[] = TRNG_CLOCKS;
1272 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1273
1274 #if defined(FSL_FEATURE_TRNG_HAS_RSTCTL) && (FSL_FEATURE_TRNG_HAS_RSTCTL > 0)
1275 static const reset_ip_name_t trng_reset = TRNG_RSTS;
1276 #endif /* FSL_FEATURE_TRNG_HAS_RSTCTL */
1277
1278 /*******************************************************************************
1279 * Prototypes
1280 *******************************************************************************/
1281 static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig);
1282 static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count);
1283 static status_t trng_SetMonobitLimit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1284 static status_t trng_SetRunBit1Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1285 static status_t trng_SetRunBit2Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1286 static status_t trng_SetRunBit3Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1287 static status_t trng_SetRunBit4Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1288 static status_t trng_SetRunBit5Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1289 static status_t trng_SetRunBit6Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1290 static status_t trng_SetPokerMaxLimit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1291 static status_t trng_SetFrequencyCountMaxLimit(TRNG_Type *base, uint32_t limit_minimum, uint32_t limit_maximum);
1292 static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base,
1293 trng_statistical_check_t statistical_check,
1294 const trng_statistical_check_limit_t *limit);
1295 static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index);
1296 static uint32_t trng_GetInstance(TRNG_Type *base);
1297
1298 /*******************************************************************************
1299 * Code
1300 ******************************************************************************/
1301
trng_GetInstance(TRNG_Type * base)1302 static uint32_t trng_GetInstance(TRNG_Type *base)
1303 {
1304 uint32_t instance;
1305
1306 /* Find the instance index from base address mappings. */
1307 for (instance = 0; instance < ARRAY_SIZE(s_trngBases); instance++)
1308 {
1309 if (s_trngBases[instance] == base)
1310 {
1311 break;
1312 }
1313 }
1314
1315 assert(instance < ARRAY_SIZE(s_trngBases));
1316
1317 return instance;
1318 }
1319
1320 /*FUNCTION*********************************************************************
1321 *
1322 * Function Name : TRNG_InitUserConfigDefault
1323 * Description : Initializes user configuration structure to default settings.
1324 *
1325 *END*************************************************************************/
1326 /*!
1327 * brief Initializes the user configuration structure to default values.
1328 *
1329 * This function initializes the configuration structure to default values. The default
1330 * values are platform dependent.
1331 *
1332 * param userConfig User configuration structure.
1333 * return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error.
1334 */
TRNG_GetDefaultConfig(trng_config_t * userConfig)1335 status_t TRNG_GetDefaultConfig(trng_config_t *userConfig)
1336 {
1337 status_t result;
1338
1339 if (userConfig != NULL)
1340 {
1341 /* Initializes the configuration structure to default values. */
1342
1343 /* Lock programmability of TRNG registers. */
1344 userConfig->lock = (bool)TRNG_USER_CONFIG_DEFAULT_LOCK;
1345 /* Clock settings */
1346 userConfig->clockMode = kTRNG_ClockModeRingOscillator;
1347 userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV;
1348 userConfig->sampleMode = kTRNG_SampleModeRaw;
1349 #if defined(FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS) && (FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS > 0)
1350 userConfig->oscillatorMode = TRNG_USER_CONFIG_DEFAULT_OSCILLATOR_MODE;
1351 userConfig->ringOsc2Div = TRNG_USER_CONFIG_DEFAULT_OSC2_DIV;
1352 #endif /* FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS */
1353 /* Seed control*/
1354 userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY;
1355 userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE;
1356 userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT;
1357
1358 /* Statistical Check Parameters.*/
1359 userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT;
1360 userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT;
1361
1362 userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM;
1363 userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM;
1364 userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM;
1365 userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM;
1366 userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM;
1367 userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM;
1368 userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM;
1369 userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM;
1370 userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM;
1371 userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM;
1372 userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM;
1373 userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM;
1374 userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM;
1375 userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM;
1376 /* Limits for statistical check of "Poker Test". */
1377 userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM;
1378 userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM;
1379 /* Limits for statistical check of entropy sample frequency count. */
1380 userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM;
1381 userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM;
1382
1383 result = kStatus_Success;
1384 }
1385 else
1386 {
1387 result = kStatus_InvalidArgument;
1388 }
1389
1390 return result;
1391 }
1392
1393 /*!
1394 * @brief Sets the TRNG retry count.
1395 *
1396 * This function sets the retry counter which defines the number of times a
1397 * statistical check may fails during the TRNG Entropy Generation before
1398 * generating an error.
1399 */
trng_SetRetryCount(TRNG_Type * base,uint8_t retry_count)1400 static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count)
1401 {
1402 status_t status;
1403
1404 if ((retry_count >= 1u) && (retry_count <= 15u))
1405 {
1406 /* Set retry count.*/
1407 TRNG_WR_SCMISC_RTY_CT(base, retry_count);
1408 status = kStatus_Success;
1409 }
1410 else
1411 {
1412 status = kStatus_InvalidArgument;
1413 }
1414 return status;
1415 }
1416
1417 /*!
1418 * @brief Sets statistical Check Monobit Limit Register .
1419 *
1420 * This function set register TRNG_SCML - Statistical Check Monobit Limit Register
1421 */
trng_SetMonobitLimit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1422 static status_t trng_SetMonobitLimit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1423 {
1424 status_t status;
1425
1426 /* Check input parameters*/
1427 if ((range <= 0xffffu) && (limit_maximum <= 0xffffu))
1428
1429 {
1430 /* Set TRNG_SCML register */
1431 TRNG_WR_SCML_MONO_MAX(base, limit_maximum);
1432 TRNG_WR_SCML_MONO_RNG(base, range);
1433 status = kStatus_Success;
1434 }
1435 else
1436 {
1437 status = kStatus_InvalidArgument;
1438 }
1439 return status;
1440 }
1441
1442 /*!
1443 * @brief Sets statistical Statistical Check Run Length 1 Limit Register .
1444 *
1445 * This function set register TRNG_SCR1L - Statistical Check Run Length 1 Limit Register
1446 */
trng_SetRunBit1Limit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1447 static status_t trng_SetRunBit1Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1448 {
1449 status_t status;
1450
1451 /* Check input parameters*/
1452 if ((range <= 0x7fffu) && (limit_maximum <= 0x7fffu))
1453 {
1454 /* Set TRNG_SCR1L register */
1455 TRNG_WR_SCR1L_RUN1_MAX(base, limit_maximum);
1456 TRNG_WR_SCR1L_RUN1_RNG(base, range);
1457 status = kStatus_Success;
1458 }
1459 else
1460 {
1461 status = kStatus_InvalidArgument;
1462 }
1463 return status;
1464 }
1465
1466 /*!
1467 * @brief Sets statistical Statistical Check Run Length 2 Limit Register .
1468 *
1469 * This function set register TRNG_SCR2L - Statistical Check Run Length 2 Limit Register
1470 */
trng_SetRunBit2Limit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1471 static status_t trng_SetRunBit2Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1472 {
1473 status_t status;
1474
1475 /* Check input parameters*/
1476 if ((range <= 0x3fffu) && (limit_maximum <= 0x3fffu))
1477 {
1478 /* Set TRNG_SCR2L register */
1479 TRNG_WR_SCR2L_RUN2_MAX(base, limit_maximum);
1480 TRNG_WR_SCR2L_RUN2_RNG(base, range);
1481 status = kStatus_Success;
1482 }
1483 else
1484 {
1485 status = kStatus_InvalidArgument;
1486 }
1487 return status;
1488 }
1489
1490 /*!
1491 * @brief Sets statistical Statistical Check Run Length 3 Limit Register .
1492 *
1493 * This function set register TRNG_SCR3L - Statistical Check Run Length 3 Limit Register
1494 */
trng_SetRunBit3Limit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1495 static status_t trng_SetRunBit3Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1496 {
1497 status_t status;
1498
1499 /* Check input parameters*/
1500 if ((range <= 0x1fffu) && (limit_maximum <= 0x1fffu))
1501 {
1502 /* Set TRNG_SCR3L register */
1503 TRNG_WR_SCR3L_RUN3_MAX(base, limit_maximum);
1504 TRNG_WR_SCR3L_RUN3_RNG(base, range);
1505 status = kStatus_Success;
1506 }
1507 else
1508 {
1509 status = kStatus_InvalidArgument;
1510 }
1511 return status;
1512 }
1513
1514 /*!
1515 * @brief Sets statistical Statistical Check Run Length 4 Limit Register .
1516 * This function set register TRNG_SCR4L - Statistical Check Run Length 4 Limit Register
1517 */
trng_SetRunBit4Limit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1518 static status_t trng_SetRunBit4Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1519 {
1520 status_t status;
1521
1522 /* Check input parameters*/
1523 if ((range <= 0xfffu) && (limit_maximum <= 0xfffu))
1524 {
1525 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L)
1526 /* Set TRNG_SCR4L register */
1527 TRNG_WR_SCR4L_RUN4_MAX(base, limit_maximum);
1528 TRNG_WR_SCR4L_RUN4_RNG(base, range);
1529 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L */
1530 status = kStatus_Success;
1531 }
1532 else
1533 {
1534 status = kStatus_InvalidArgument;
1535 }
1536 return status;
1537 }
1538
1539 /*!
1540 * @brief Sets statistical Statistical Check Run Length 5 Limit Register .
1541 * This function set register TRNG_SCR5L - Statistical Check Run Length 5 Limit Register
1542 */
trng_SetRunBit5Limit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1543 static status_t trng_SetRunBit5Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1544 {
1545 status_t status;
1546
1547 /* Check input parameters*/
1548 if ((range <= 0x7ffu) && (limit_maximum <= 0x7ffu))
1549 {
1550 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L)
1551 /* Set TRNG_SCR5L register */
1552 TRNG_WR_SCR5L_RUN5_MAX(base, limit_maximum);
1553 TRNG_WR_SCR5L_RUN5_RNG(base, range);
1554 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L */
1555 status = kStatus_Success;
1556 }
1557 else
1558 {
1559 status = kStatus_InvalidArgument;
1560 }
1561 return status;
1562 }
1563
1564 /*!
1565 * @brief Sets statistical Statistical Check Run Length 6 Limit Register .
1566 * This function set register TRNG_SCR6L - Statistical Check Run Length 6 Limit Register
1567 */
trng_SetRunBit6Limit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1568 static status_t trng_SetRunBit6Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1569 {
1570 status_t status;
1571
1572 /* Check input parameters*/
1573 if ((range <= 0x7ffu) && (limit_maximum <= 0x7ffu))
1574 {
1575 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L)
1576 /* Set TRNG_SCR6L register */
1577 TRNG_WR_SCR6PL_RUN6P_MAX(base, limit_maximum);
1578 TRNG_WR_SCR6PL_RUN6P_RNG(base, range);
1579 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L */
1580 status = kStatus_Success;
1581 }
1582 else
1583 {
1584 status = kStatus_InvalidArgument;
1585 }
1586 return status;
1587 }
1588
1589 /*!
1590 * @brief Sets statistical Poker Maximum Limit Register.
1591 * This function set register TRNG_PKRMAX - Poker Maximum Limit Register
1592 */
trng_SetPokerMaxLimit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1593 static status_t trng_SetPokerMaxLimit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1594 {
1595 status_t status;
1596
1597 /* Check input parameters*/
1598 if ((range <= 0xffffu) && (limit_maximum <= 0xffffffu))
1599 {
1600 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX) && FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX)
1601 /* Set TRNG_PKRMAX register */
1602 TRNG_WR_PKRMAX_PKR_MAX(base, limit_maximum);
1603 TRNG_WR_PKRRNG_PKR_RNG(base, range);
1604 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX */
1605 status = kStatus_Success;
1606 }
1607 else
1608 {
1609 status = kStatus_InvalidArgument;
1610 }
1611 return status;
1612 }
1613
1614 /*!
1615 * @brief Sets statistical Frequency Count Maximum Limit Register.
1616 * This function set register TRNG_FRQMAX - Frequency Count Maximum Limit Register
1617 */
trng_SetFrequencyCountMaxLimit(TRNG_Type * base,uint32_t limit_minimum,uint32_t limit_maximum)1618 static status_t trng_SetFrequencyCountMaxLimit(TRNG_Type *base, uint32_t limit_minimum, uint32_t limit_maximum)
1619 {
1620 status_t status;
1621
1622 /* Check input parameters*/
1623 if ((limit_minimum <= 0x3fffffu) && (limit_maximum <= 0x3fffffu))
1624 {
1625 /* Set FRQMAX register */
1626 TRNG_WR_FRQMAX_FRQ_MAX(base, limit_maximum);
1627 TRNG_WR_FRQMIN_FRQ_MIN(base, limit_minimum);
1628 status = kStatus_Success;
1629 }
1630 else
1631 {
1632 status = kStatus_InvalidArgument;
1633 }
1634 return status;
1635 }
1636
1637 /*!
1638 * @brief Sets statistical check limits.
1639 *
1640 * This function is used to set minimum and maximum limits of statistical checks.
1641 *
1642 */
trng_SetStatisticalCheckLimit(TRNG_Type * base,trng_statistical_check_t statistical_check,const trng_statistical_check_limit_t * limit)1643 static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base,
1644 trng_statistical_check_t statistical_check,
1645 const trng_statistical_check_limit_t *limit)
1646 {
1647 uint32_t range;
1648 status_t status = kStatus_Success;
1649
1650 if ((NULL != limit) && (limit->maximum > limit->minimum))
1651 {
1652 range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/
1653
1654 if (statistical_check == kTRNG_StatisticalCheckMonobit) /* Allowable maximum and minimum number of ones/zero
1655 detected during entropy generation. */
1656 {
1657 status = trng_SetMonobitLimit(base, range, limit->maximum);
1658 }
1659 else if (statistical_check == kTRNG_StatisticalCheckRunBit1) /* Allowable maximum and minimum number of runs of
1660 length 1 detected during entropy generation. */
1661 {
1662 status = trng_SetRunBit1Limit(base, range, limit->maximum);
1663 }
1664 else if (statistical_check == kTRNG_StatisticalCheckRunBit2) /* Allowable maximum and minimum number of runs of
1665 length 2 detected during entropy generation. */
1666 {
1667 status = trng_SetRunBit2Limit(base, range, limit->maximum);
1668 }
1669 else if (statistical_check == kTRNG_StatisticalCheckRunBit3) /* Allowable maximum and minimum number of runs of
1670 length 3 detected during entropy generation. */
1671 {
1672 status = trng_SetRunBit3Limit(base, range, limit->maximum);
1673 }
1674 else if (statistical_check == kTRNG_StatisticalCheckRunBit4) /* Allowable maximum and minimum number of runs of
1675 length 4 detected during entropy generation. */
1676 {
1677 status = trng_SetRunBit4Limit(base, range, limit->maximum);
1678 }
1679 else if (statistical_check == kTRNG_StatisticalCheckRunBit5) /* Allowable maximum and minimum number of runs of
1680 length 5 detected during entropy generation. */
1681 {
1682 status = trng_SetRunBit5Limit(base, range, limit->maximum);
1683 }
1684 else if (statistical_check == kTRNG_StatisticalCheckRunBit6Plus) /* Allowable maximum and minimum number of
1685 length 6 or more detected during entropy
1686 generation */
1687 {
1688 status = trng_SetRunBit6Limit(base, range, limit->maximum);
1689 }
1690 else if (statistical_check == kTRNG_StatisticalCheckPoker) /* Allowable maximum and minimum limit of "Poker
1691 Test" detected during entropy generation . */
1692 {
1693 status = trng_SetPokerMaxLimit(base, range, limit->maximum);
1694 }
1695 else if (statistical_check == kTRNG_StatisticalCheckFrequencyCount) /* Allowable maximum and minimum limit of
1696 entropy sample frquency count during
1697 entropy generation . */
1698 {
1699 status = trng_SetFrequencyCountMaxLimit(base, limit->minimum, limit->maximum);
1700 }
1701 else
1702 {
1703 status = kStatus_InvalidArgument;
1704 }
1705 }
1706
1707 return status;
1708 }
1709
1710 /*FUNCTION*********************************************************************
1711 *
1712 * Function Name : trng_ApplyUserConfig
1713 * Description : Apply user configuration settings to TRNG module.
1714 *
1715 *END*************************************************************************/
trng_ApplyUserConfig(TRNG_Type * base,const trng_config_t * userConfig)1716 static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig)
1717 {
1718 status_t status;
1719
1720 /* Set retry count */
1721 status = trng_SetRetryCount(base, userConfig->retryCount);
1722
1723 /* Set statistical check limit */
1724 if (kStatus_Success == status)
1725 {
1726 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit);
1727 }
1728
1729 if (kStatus_Success == status)
1730 {
1731 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit);
1732 }
1733
1734 if (kStatus_Success == status)
1735 {
1736 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit);
1737 }
1738
1739 if (kStatus_Success == status)
1740 {
1741 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit);
1742 }
1743
1744 if (kStatus_Success == status)
1745 {
1746 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit);
1747 }
1748
1749 if (kStatus_Success == status)
1750 {
1751 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit);
1752 }
1753
1754 if (kStatus_Success == status)
1755 {
1756 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus, &userConfig->runBit6PlusLimit);
1757 }
1758
1759 if (kStatus_Success == status)
1760 {
1761 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit);
1762 }
1763
1764 if (kStatus_Success == status)
1765 {
1766 status =
1767 trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount, &userConfig->frequencyCountLimit);
1768 }
1769
1770 if (kStatus_Success == status)
1771 {
1772 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE) && FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE)
1773 /* Set clock mode used to operate TRNG */
1774 TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode);
1775 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE */
1776 /* Set ring oscillator divider used by TRNG */
1777 TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv);
1778 #if defined(FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS) && (FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS > 0)
1779 base->OSC2_CTL |= TRNG_OSC2_CTL_TRNG_ENT_CTL(userConfig->oscillatorMode);
1780 base->OSC2_CTL |= TRNG_OSC2_CTL_OSC2_DIV(userConfig->ringOsc2Div);
1781 #endif /* FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS */
1782 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE) && FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE)
1783 /* Set sample mode of the TRNG ring oscillator. */
1784 TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode);
1785 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE */
1786 /* Set length of each Entropy sample taken */
1787 TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay);
1788 /* Set number of entropy samples that will be taken during Entropy generation */
1789 TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize);
1790 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM > 0))
1791 /* Set Sparse Bit Limit */
1792 TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit);
1793 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM */
1794 TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit);
1795 }
1796
1797 return status;
1798 }
1799
1800 /*!
1801 * @brief Gets a entry data from the TRNG.
1802 *
1803 * This function gets an entropy data from TRNG.
1804 * Entropy data is spread over TRNG_ENT_COUNT registers.
1805 * Read register number is defined by index parameter.
1806 */
trng_ReadEntropy(TRNG_Type * base,uint32_t index)1807 static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index)
1808 {
1809 uint32_t data;
1810
1811 index = index % TRNG_ENT_COUNT; /* This way we can use incremental index without limit control from application.*/
1812
1813 data = TRNG_RD_ENT(base, index);
1814
1815 if (index == (TRNG_ENT_COUNT - 1u))
1816 {
1817 /* Dummy read. Defect workaround.
1818 * TRNG could not clear ENT_VAL flag automatically, application
1819 * had to do a dummy reading operation for anyone TRNG register
1820 * to clear it firstly, then to read the RTENT0 to RTENT15 again */
1821 index = TRNG_RD_ENT(base, 0);
1822 }
1823
1824 return data;
1825 }
1826
1827 /*!
1828 * brief Initializes the TRNG.
1829 *
1830 * This function initializes the TRNG.
1831 * When called, the TRNG entropy generation starts immediately.
1832 *
1833 * param base TRNG base address
1834 * param userConfig Pointer to the initialization configuration structure.
1835 * return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error.
1836 */
TRNG_Init(TRNG_Type * base,const trng_config_t * userConfig)1837 status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig)
1838 {
1839 status_t result;
1840
1841 /* Check input parameters.*/
1842 if ((base != NULL) && (userConfig != NULL))
1843 {
1844 #if defined(FSL_FEATURE_TRNG_HAS_RSTCTL) && (FSL_FEATURE_TRNG_HAS_RSTCTL > 0)
1845 /* Reset TRNG peripheral */
1846 #if defined(FSL_FEATURE_TRNG_HAS_CTRL_PIN) && (FSL_FEATURE_TRNG_HAS_CTRL_PIN > 0)
1847 SYSCTL2->TRNG_PIN_CTRL |= SYSCTL2_TRNG_PIN_CTRL_ENABLE_MASK;
1848 #endif /* FSL_FEATURE_TRNG_HAS_CTRL_PIN */
1849 RESET_PeripheralReset(trng_reset);
1850 #endif /* FSL_FEATURE_TRNG_HAS_RSTCTL */
1851 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1852 /* Enable the clock gate. */
1853 CLOCK_EnableClock(s_trngClock[trng_GetInstance(base)]);
1854 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1855
1856 /* Clear pending errors, set program mode and reset the registers to default values.*/
1857 /* MCTL[PRGM] = 1 (kTRNG_WorkModeProgram); MCTL[ERR] = 1; MCTL[RST_DEF] = 1 */
1858 TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK | TRNG_MCTL_RST_DEF_MASK),
1859 TRNG_MCTL_PRGM(kTRNG_WorkModeProgram) | TRNG_MCTL_ERR(1) | TRNG_MCTL_RST_DEF(1));
1860
1861 /* Set configuration.*/
1862 if ((result = trng_ApplyUserConfig(base, userConfig)) == kStatus_Success)
1863 {
1864 /* Start entropy generation.*/
1865 /* Set to Run mode.*/
1866 TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun);
1867 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0))
1868 /* Enable TRNG Access Mode. To generate an Entropy
1869 * value that can be read via the true0-true15 registers.*/
1870 TRNG_WR_MCTL_TRNG_ACC(base, 1);
1871 #endif /* !FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC */
1872
1873 (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u));
1874
1875 if (true == userConfig->lock) /* Disable programmability of TRNG registers. */
1876 {
1877 TRNG_WR_SEC_CFG_NO_PRGM(base, 1);
1878 }
1879
1880 result = kStatus_Success;
1881 }
1882 }
1883 else
1884 {
1885 result = kStatus_InvalidArgument;
1886 }
1887
1888 return result;
1889 }
1890
1891 /*!
1892 * brief Shuts down the TRNG.
1893 *
1894 * This function shuts down the TRNG.
1895 *
1896 * param base TRNG base address.
1897 */
TRNG_Deinit(TRNG_Type * base)1898 void TRNG_Deinit(TRNG_Type *base)
1899 {
1900 /* Check input parameters.*/
1901 if (NULL != base)
1902 {
1903 /* Move to program mode. Stop entropy generation.*/
1904 TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram);
1905
1906 /* Check before clock stop.
1907 TRNG turns on the TRNG free-running ring oscillator whenever new entropy
1908 is being generated and turns off the ring oscillator when entropy generation
1909 is complete. If the TRNG clock is stopped while the TRNG ring oscillator
1910 is running, the oscillator continues running though the RNG clock.
1911 is stopped. */
1912 while (TRNG_RD_MCTL_TSTOP_OK(base) == 0u)
1913 {
1914 }
1915
1916 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1917 /* Disable Clock*/
1918 CLOCK_DisableClock(s_trngClock[trng_GetInstance(base)]);
1919 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1920 }
1921 }
1922
1923 /*!
1924 * brief Gets random data.
1925 *
1926 * This function gets random data from the TRNG.
1927 *
1928 * param base TRNG base address.
1929 * param data Pointer address used to store random data.
1930 * param dataSize Size of the buffer pointed by the data parameter.
1931 * return random data
1932 */
TRNG_GetRandomData(TRNG_Type * base,void * data,size_t dataSize)1933 status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize)
1934 {
1935 status_t result = kStatus_Success;
1936 uint32_t random_32;
1937 uint8_t *random_p;
1938 uint32_t random_size;
1939 uint8_t *data_p = (uint8_t *)data;
1940 uint32_t i;
1941 uint32_t tmpValidFlag;
1942 uint32_t tmpErrorFlag;
1943
1944 int index = 0;
1945
1946 /* Check input parameters.*/
1947 if ((NULL != base) && (NULL != data) && (0U != dataSize))
1948 {
1949 /* After a deepsleep exit some errors bits are set in MCTL and must be cleared before processing further.
1950 Also, trigger new 512 bits entropy generation to be sure we will have fresh bits.*/
1951 if (0U != TRNG_RD_MCTL_ERR(base))
1952 {
1953 /* clear errors bits */
1954 TRNG_WR_MCTL_ERR(base, 1);
1955 /* restart new entropy generation */
1956 (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u));
1957 }
1958
1959 do
1960 {
1961 /* Wait for Valid or Error flag*/
1962 tmpValidFlag = TRNG_RD_MCTL_ENT_VAL(base);
1963 tmpErrorFlag = TRNG_RD_MCTL_ERR(base);
1964 while ((tmpValidFlag == 0u) && (tmpErrorFlag == 0u))
1965 {
1966 tmpValidFlag = TRNG_RD_MCTL_ENT_VAL(base);
1967 tmpErrorFlag = TRNG_RD_MCTL_ERR(base);
1968 }
1969
1970 /* Check HW error.*/
1971 if (0U != TRNG_RD_MCTL_ERR(base))
1972 {
1973 result = kStatus_Fail; /* TRNG module error occurred */
1974 /* Clear error.*/
1975 TRNG_WR_MCTL_ERR(base, 1);
1976 break; /* No sense stay here.*/
1977 }
1978
1979 /* Read Entropy.*/
1980 random_32 = trng_ReadEntropy(base, (uint32_t)index++);
1981
1982 random_p = (uint8_t *)&random_32;
1983
1984 if (dataSize < sizeof(random_32))
1985 {
1986 random_size = dataSize;
1987 }
1988 else
1989 {
1990 random_size = sizeof(random_32);
1991 }
1992
1993 for (i = 0U; i < random_size; i++)
1994 {
1995 *data_p++ = *random_p++;
1996 }
1997
1998 dataSize -= random_size;
1999 } while (dataSize > 0u);
2000
2001 /* Start a new entropy generation.
2002 It is done by reading of the last entropy register.*/
2003 if (((unsigned)index % TRNG_ENT_COUNT) != 0U)
2004 {
2005 (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u));
2006 }
2007 }
2008 else
2009 {
2010 result = kStatus_InvalidArgument;
2011 }
2012
2013 return result;
2014 }
2015
2016 #endif /* FSL_FEATURE_SOC_TRNG_COUNT */
2017
