1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017, 2020-2023 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #include "fsl_trng.h"
9
10 #if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT
11
12 /*******************************************************************************
13 * Definitions
14 *******************************************************************************/
15
16 /* Component ID definition, used by tools. */
17 #ifndef FSL_COMPONENT_ID
18 #define FSL_COMPONENT_ID "platform.drivers.trng"
19 #endif
20
21 /* Default values for user configuration structure.*/
22 #if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES) || \
23 defined(MCIMX7U5_M4_SERIES) || defined(KW36Z4_SERIES) || defined(KW37A4_SERIES) || defined(KW37Z4_SERIES) || \
24 defined(KW38A4_SERIES) || defined(KW38Z4_SERIES) || defined(KW39A4_SERIES) || defined(KW35Z4_SERIES) || \
25 defined(KW36A4_SERIES) || defined(KW35A4_SERIES) || defined(KW34A4_SERIES))
26 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8
27 #elif (defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \
28 defined(KL82Z7_SERIES) || defined(K32L2A41A_SERIES))
29 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4
30 #elif ( \
31 defined(K81F25615_SERIES) || defined(K32L3A60_cm4_SERIES) || defined(K32L3A60_cm0plus_SERIES) || \
32 defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || defined(MCXN548_cm33_core0_SERIES) || \
33 defined(MCXN548_cm33_core1_SERIES) || defined(MCXN945_cm33_core0_SERIES) || defined(MCXN945_cm33_core1_SERIES) || \
34 defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || defined(MCXN947_cm33_core0_SERIES) || \
35 defined(MCXN947_cm33_core1_SERIES) || defined(MCXN948_cm33_core0_SERIES) || defined(MCXN948_cm33_core1_SERIES))
36 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2
37 #else
38 /* Default value for the TRNG user configuration structure can be optionally
39 defined by device specific preprocessor macros. */
40 #if defined(FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_OSC_DIV) && \
41 (FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_OSC_DIV > 0)
42 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV (FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_OSC_DIV_VALUE)
43 #else
44 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv0
45 #endif
46 #endif
47
48 #if (defined(RW610_SERIES) || defined(RW612_SERIES))
49
50 /* RW610 specific settings for the TRNG */
51 #define TRNG_USER_CONFIG_DEFAULT_LOCK 0
52 #define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200
53 #define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 256
54 #define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63
55 #define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1
56 #define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 34
57
58 #define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 171
59 #define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 86)
60 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 63
61 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 56)
62 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 38
63 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 38)
64 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 26
65 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 26)
66 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 75
67 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 64)
68 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 47
69 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 46)
70 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 47
71 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 46)
72 #define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 26912
73 #define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 2467)
74
75 #else
76
77 #ifndef TRNG_ENT_COUNT
78 #define TRNG_ENT_COUNT TRNG_ENTA_ENT_COUNT
79 #endif
80
81 #define TRNG_USER_CONFIG_DEFAULT_LOCK 0
82 #define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200
83 #define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 512
84 #define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63
85 #define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1
86 #define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 32
87
88 #define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 317
89 #define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 122)
90 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 107
91 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 80)
92 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 62
93 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 55)
94 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 39
95 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 39)
96 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 26
97 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 26)
98 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 18
99 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 18)
100 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 17
101 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 17)
102 #define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 1600
103 #define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 570)
104
105 #endif
106
107 #if defined(FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM) && \
108 (FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM > 0)
109 #define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM (FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM_VALUE)
110 #else
111 #define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 30000
112 #endif
113
114 #if defined(FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM) && \
115 (FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM > 0)
116 #define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM (FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM_VALUE)
117 #else
118 #define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1600
119 #endif
120
121 /*! @brief TRNG work mode */
122 typedef enum _trng_work_mode
123 {
124 kTRNG_WorkModeRun = 0U, /*!< Run Mode. */
125 kTRNG_WorkModeProgram = 1U /*!< Program Mode. */
126 } trng_work_mode_t;
127
128 /*! @brief TRNG statistical check type*/
129 typedef enum _trng_statistical_check
130 {
131 kTRNG_StatisticalCheckMonobit =
132 1U, /*!< Statistical check of number of ones/zero detected during entropy generation. */
133 kTRNG_StatisticalCheckRunBit1, /*!< Statistical check of number of runs of length 1 detected during entropy
134 generation. */
135 kTRNG_StatisticalCheckRunBit2, /*!< Statistical check of number of runs of length 2 detected during entropy
136 generation. */
137 kTRNG_StatisticalCheckRunBit3, /*!< Statistical check of number of runs of length 3 detected during entropy
138 generation. */
139 kTRNG_StatisticalCheckRunBit4, /*!< Statistical check of number of runs of length 4 detected during entropy
140 generation. */
141 kTRNG_StatisticalCheckRunBit5, /*!< Statistical check of number of runs of length 5 detected during entropy
142 generation. */
143 kTRNG_StatisticalCheckRunBit6Plus, /*!< Statistical check of number of runs of length 6 or more detected during
144 entropy generation. */
145 kTRNG_StatisticalCheckPoker, /*!< Statistical check of "Poker Test". */
146 kTRNG_StatisticalCheckFrequencyCount /*!< Statistical check of entropy sample frequency count. */
147 } trng_statistical_check_t;
148
149 /*******************************************************************************
150 * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register
151 ******************************************************************************/
152 /*!
153 * @name Register TRNG_SCMISC, field RTY_CT[19:16] (RW)
154 *
155 * RETRY COUNT. If a statistical check fails during the TRNG Entropy Generation,
156 * the RTY_CT value indicates the number of times a retry should occur before
157 * generating an error. This field is writable only if MCTL[PRGM] bit is 1. This
158 * field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 1h by writing
159 * the MCTL[RST_DEF] bit to 1.
160 */
161 /*@{*/
162 /*! @brief Read current value of the TRNG_SCMISC_RTY_CT field. */
163 #define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMISC_RTY_CT_SHIFT)
164
165 /*! @brief Set the RTY_CT field to a new value. */
166 #define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCMISC_RTY_CT(value)))
167 /*@}*/
168
169 /*******************************************************************************
170 * TRNG_SCML - RNG Statistical Check Monobit Limit Register
171 ******************************************************************************/
172 /*!
173 * @brief TRNG_SCML - RNG Statistical Check Monobit Limit Register (RW)
174 *
175 * Reset value: 0x010C0568U
176 *
177 * The RNG Statistical Check Monobit Limit Register defines the allowable
178 * maximum and minimum number of ones/zero detected during entropy generation. To pass
179 * the test, the number of ones/zeroes generated must be less than the programmed
180 * maximum value, and the number of ones/zeroes generated must be greater than
181 * (maximum - range). If this test fails, the Retry Counter in SCMISC will be
182 * decremented, and a retry will occur if the Retry Count has not reached zero. If
183 * the Retry Count has reached zero, an error will be generated. Note that this
184 * offset (0xBASE_0620) is used as SCML only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0,
185 * this offset is used as SCMC readback register.
186 */
187 /*!
188 * @name Constants and macros for entire TRNG_SCML register
189 */
190 /*@{*/
191 #define TRNG_SCML_REG(base) ((base)->SCML)
192 #define TRNG_RD_SCML(base) (TRNG_SCML_REG(base))
193 #define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value))
194 #define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (value)))
195 /*@}*/
196 /*!
197 * @name Register TRNG_SCML, field MONO_MAX[15:0] (RW)
198 *
199 * Monobit Maximum Limit. Defines the maximum allowable count taken during
200 * entropy generation. The number of ones/zeroes detected during entropy generation
201 * must be less than MONO_MAX, else a retry or error will occur. This register is
202 * cleared to 00056Bh (decimal 1387) by writing the MCTL[RST_DEF] bit to 1.
203 */
204 /*@{*/
205 /*! @brief Read current value of the TRNG_SCML_MONO_MAX field. */
206 #define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_MONO_MAX_SHIFT)
207
208 /*! @brief Set the MONO_MAX field to a new value. */
209 #define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_MONO_MAX(value)))
210 /*@}*/
211 /*!
212 * @name Register TRNG_SCML, field MONO_RNG[31:16] (RW)
213 *
214 * Monobit Range. The number of ones/zeroes detected during entropy generation
215 * must be greater than MONO_MAX - MONO_RNG, else a retry or error will occur.
216 * This register is cleared to 000112h (decimal 274) by writing the MCTL[RST_DEF]
217 * bit to 1.
218 */
219 /*@{*/
220 /*! @brief Read current value of the TRNG_SCML_MONO_RNG field. */
221 #define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_MONO_RNG_SHIFT)
222
223 /*! @brief Set the MONO_RNG field to a new value. */
224 #define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_MONO_RNG(value)))
225 /*@}*/
226
227 /*******************************************************************************
228 * TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register
229 ******************************************************************************/
230
231 /*!
232 * @brief TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register (RW)
233 *
234 * Reset value: 0x00B20195U
235 *
236 * The RNG Statistical Check Run Length 1 Limit Register defines the allowable
237 * maximum and minimum number of runs of length 1 detected during entropy
238 * generation. To pass the test, the number of runs of length 1 (for samples of both 0
239 * and 1) must be less than the programmed maximum value, and the number of runs of
240 * length 1 must be greater than (maximum - range). If this test fails, the
241 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
242 * Count has not reached zero. If the Retry Count has reached zero, an error will
243 * be generated. Note that this address (0xBASE_0624) is used as SCR1L only if
244 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR1C readback
245 * register.
246 */
247 /*!
248 * @name Constants and macros for entire TRNG_SCR1L register
249 */
250 /*@{*/
251 #define TRNG_SCR1L_REG(base) ((base)->SCR1L)
252 #define TRNG_RD_SCR1L(base) (TRNG_SCR1L_REG(base))
253 #define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value))
254 #define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (value)))
255 /*@}*/
256
257 /*!
258 * @name Register TRNG_SCR1L, field RUN1_MAX[14:0] (RW)
259 *
260 * Run Length 1 Maximum Limit. Defines the maximum allowable runs of length 1
261 * (for both 0 and 1) detected during entropy generation. The number of runs of
262 * length 1 detected during entropy generation must be less than RUN1_MAX, else a
263 * retry or error will occur. This register is cleared to 01E5h (decimal 485) by
264 * writing the MCTL[RST_DEF] bit to 1.
265 */
266 /*@{*/
267 /*! @brief Read current value of the TRNG_SCR1L_RUN1_MAX field. */
268 #define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR1L_RUN1_MAX_SHIFT)
269
270 /*! @brief Set the RUN1_MAX field to a new value. */
271 #define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SCR1L_RUN1_MAX(value)))
272 /*@}*/
273
274 /*!
275 * @name Register TRNG_SCR1L, field RUN1_RNG[30:16] (RW)
276 *
277 * Run Length 1 Range. The number of runs of length 1 (for both 0 and 1)
278 * detected during entropy generation must be greater than RUN1_MAX - RUN1_RNG, else a
279 * retry or error will occur. This register is cleared to 0102h (decimal 258) by
280 * writing the MCTL[RST_DEF] bit to 1.
281 */
282 /*@{*/
283 /*! @brief Read current value of the TRNG_SCR1L_RUN1_RNG field. */
284 #define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR1L_RUN1_RNG_SHIFT)
285
286 /*! @brief Set the RUN1_RNG field to a new value. */
287 #define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SCR1L_RUN1_RNG(value)))
288 /*@}*/
289
290 /*******************************************************************************
291 * TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register
292 ******************************************************************************/
293
294 /*!
295 * @brief TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register (RW)
296 *
297 * Reset value: 0x007A00DCU
298 *
299 * The RNG Statistical Check Run Length 2 Limit Register defines the allowable
300 * maximum and minimum number of runs of length 2 detected during entropy
301 * generation. To pass the test, the number of runs of length 2 (for samples of both 0
302 * and 1) must be less than the programmed maximum value, and the number of runs of
303 * length 2 must be greater than (maximum - range). If this test fails, the
304 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
305 * Count has not reached zero. If the Retry Count has reached zero, an error will
306 * be generated. Note that this address (0xBASE_0628) is used as SCR2L only if
307 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR2C readback
308 * register.
309 */
310 /*!
311 * @name Constants and macros for entire TRNG_SCR2L register
312 */
313 /*@{*/
314 #define TRNG_SCR2L_REG(base) ((base)->SCR2L)
315 #define TRNG_RD_SCR2L(base) (TRNG_SCR2L_REG(base))
316 #define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value))
317 #define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (value)))
318 /*@}*/
319
320 /*
321 * Constants & macros for individual TRNG_SCR2L bitfields
322 */
323
324 /*!
325 * @name Register TRNG_SCR2L, field RUN2_MAX[13:0] (RW)
326 *
327 * Run Length 2 Maximum Limit. Defines the maximum allowable runs of length 2
328 * (for both 0 and 1) detected during entropy generation. The number of runs of
329 * length 2 detected during entropy generation must be less than RUN2_MAX, else a
330 * retry or error will occur. This register is cleared to 00DCh (decimal 220) by
331 * writing the MCTL[RST_DEF] bit to 1.
332 */
333 /*@{*/
334 /*! @brief Read current value of the TRNG_SCR2L_RUN2_MAX field. */
335 #define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR2L_RUN2_MAX_SHIFT)
336
337 /*! @brief Set the RUN2_MAX field to a new value. */
338 #define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SCR2L_RUN2_MAX(value)))
339 /*@}*/
340
341 /*!
342 * @name Register TRNG_SCR2L, field RUN2_RNG[29:16] (RW)
343 *
344 * Run Length 2 Range. The number of runs of length 2 (for both 0 and 1)
345 * detected during entropy generation must be greater than RUN2_MAX - RUN2_RNG, else a
346 * retry or error will occur. This register is cleared to 007Ah (decimal 122) by
347 * writing the MCTL[RST_DEF] bit to 1.
348 */
349 /*@{*/
350 /*! @brief Read current value of the TRNG_SCR2L_RUN2_RNG field. */
351 #define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR2L_RUN2_RNG_SHIFT)
352
353 /*! @brief Set the RUN2_RNG field to a new value. */
354 #define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SCR2L_RUN2_RNG(value)))
355 /*@}*/
356
357 /*******************************************************************************
358 * TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register
359 ******************************************************************************/
360
361 /*!
362 * @brief TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register (RW)
363 *
364 * Reset value: 0x0058007DU
365 *
366 * The RNG Statistical Check Run Length 3 Limit Register defines the allowable
367 * maximum and minimum number of runs of length 3 detected during entropy
368 * generation. To pass the test, the number of runs of length 3 (for samples of both 0
369 * and 1) must be less than the programmed maximum value, and the number of runs of
370 * length 3 must be greater than (maximum - range). If this test fails, the
371 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
372 * Count has not reached zero. If the Retry Count has reached zero, an error will
373 * be generated. Note that this address (0xBASE_062C) is used as SCR3L only if
374 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR3C readback
375 * register.
376 */
377 /*!
378 * @name Constants and macros for entire TRNG_SCR3L register
379 */
380 /*@{*/
381 #define TRNG_SCR3L_REG(base) ((base)->SCR3L)
382 #define TRNG_RD_SCR3L(base) (TRNG_SCR3L_REG(base))
383 #define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value))
384 #define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (value)))
385 /*@}*/
386
387 /*
388 * Constants & macros for individual TRNG_SCR3L bitfields
389 */
390
391 /*!
392 * @name Register TRNG_SCR3L, field RUN3_MAX[12:0] (RW)
393 *
394 * Run Length 3 Maximum Limit. Defines the maximum allowable runs of length 3
395 * (for both 0 and 1) detected during entropy generation. The number of runs of
396 * length 3 detected during entropy generation must be less than RUN3_MAX, else a
397 * retry or error will occur. This register is cleared to 007Dh (decimal 125) by
398 * writing the MCTL[RST_DEF] bit to 1.
399 */
400 /*@{*/
401 /*! @brief Read current value of the TRNG_SCR3L_RUN3_MAX field. */
402 #define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR3L_RUN3_MAX_SHIFT)
403
404 /*! @brief Set the RUN3_MAX field to a new value. */
405 #define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SCR3L_RUN3_MAX(value)))
406 /*@}*/
407
408 /*!
409 * @name Register TRNG_SCR3L, field RUN3_RNG[28:16] (RW)
410 *
411 * Run Length 3 Range. The number of runs of length 3 (for both 0 and 1)
412 * detected during entropy generation must be greater than RUN3_MAX - RUN3_RNG, else a
413 * retry or error will occur. This register is cleared to 0058h (decimal 88) by
414 * writing the MCTL[RST_DEF] bit to 1.
415 */
416 /*@{*/
417 /*! @brief Read current value of the TRNG_SCR3L_RUN3_RNG field. */
418 #define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR3L_RUN3_RNG_SHIFT)
419
420 /*! @brief Set the RUN3_RNG field to a new value. */
421 #define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SCR3L_RUN3_RNG(value)))
422 /*@}*/
423
424 /*******************************************************************************
425 * TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register
426 ******************************************************************************/
427
428 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L)
429 /*!
430 * @brief TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register (RW)
431 *
432 * Reset value: 0x0040004BU
433 *
434 * The RNG Statistical Check Run Length 4 Limit Register defines the allowable
435 * maximum and minimum number of runs of length 4 detected during entropy
436 * generation. To pass the test, the number of runs of length 4 (for samples of both 0
437 * and 1) must be less than the programmed maximum value, and the number of runs of
438 * length 4 must be greater than (maximum - range). If this test fails, the
439 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
440 * Count has not reached zero. If the Retry Count has reached zero, an error will
441 * be generated. Note that this address (0xBASE_0630) is used as SCR4L only if
442 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR4C readback
443 * register.
444 */
445 /*!
446 * @name Constants and macros for entire TRNG_SCR4L register
447 */
448 /*@{*/
449 #define TRNG_SCR4L_REG(base) ((base)->SCR4L)
450 #define TRNG_RD_SCR4L(base) (TRNG_SCR4L_REG(base))
451 #define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value))
452 #define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (value)))
453 /*@}*/
454
455 /*
456 * Constants & macros for individual TRNG_SCR4L bitfields
457 */
458
459 /*!
460 * @name Register TRNG_SCR4L, field RUN4_MAX[11:0] (RW)
461 *
462 * Run Length 4 Maximum Limit. Defines the maximum allowable runs of length 4
463 * (for both 0 and 1) detected during entropy generation. The number of runs of
464 * length 4 detected during entropy generation must be less than RUN4_MAX, else a
465 * retry or error will occur. This register is cleared to 004Bh (decimal 75) by
466 * writing the MCTL[RST_DEF] bit to 1.
467 */
468 /*@{*/
469 /*! @brief Read current value of the TRNG_SCR4L_RUN4_MAX field. */
470 #define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR4L_RUN4_MAX_SHIFT)
471
472 /*! @brief Set the RUN4_MAX field to a new value. */
473 #define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SCR4L_RUN4_MAX(value)))
474 /*@}*/
475
476 /*!
477 * @name Register TRNG_SCR4L, field RUN4_RNG[27:16] (RW)
478 *
479 * Run Length 4 Range. The number of runs of length 4 (for both 0 and 1)
480 * detected during entropy generation must be greater than RUN4_MAX - RUN4_RNG, else a
481 * retry or error will occur. This register is cleared to 0040h (decimal 64) by
482 * writing the MCTL[RST_DEF] bit to 1.
483 */
484 /*@{*/
485 /*! @brief Read current value of the TRNG_SCR4L_RUN4_RNG field. */
486 #define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR4L_RUN4_RNG_SHIFT)
487
488 /*! @brief Set the RUN4_RNG field to a new value. */
489 #define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SCR4L_RUN4_RNG(value)))
490 /*@}*/
491 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L */
492
493 /*******************************************************************************
494 * TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register
495 ******************************************************************************/
496
497 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L)
498 /*!
499 * @brief TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register (RW)
500 *
501 * Reset value: 0x002E002FU
502 *
503 * The RNG Statistical Check Run Length 5 Limit Register defines the allowable
504 * maximum and minimum number of runs of length 5 detected during entropy
505 * generation. To pass the test, the number of runs of length 5 (for samples of both 0
506 * and 1) must be less than the programmed maximum value, and the number of runs of
507 * length 5 must be greater than (maximum - range). If this test fails, the
508 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
509 * Count has not reached zero. If the Retry Count has reached zero, an error will
510 * be generated. Note that this address (0xBASE_0634) is used as SCR5L only if
511 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR5C readback
512 * register.
513 */
514 /*!
515 * @name Constants and macros for entire TRNG_SCR5L register
516 */
517 /*@{*/
518 #define TRNG_SCR5L_REG(base) ((base)->SCR5L)
519 #define TRNG_RD_SCR5L(base) (TRNG_SCR5L_REG(base))
520 #define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value))
521 #define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (value)))
522 /*@}*/
523
524 /*
525 * Constants & macros for individual TRNG_SCR5L bitfields
526 */
527
528 /*!
529 * @name Register TRNG_SCR5L, field RUN5_MAX[10:0] (RW)
530 *
531 * Run Length 5 Maximum Limit. Defines the maximum allowable runs of length 5
532 * (for both 0 and 1) detected during entropy generation. The number of runs of
533 * length 5 detected during entropy generation must be less than RUN5_MAX, else a
534 * retry or error will occur. This register is cleared to 002Fh (decimal 47) by
535 * writing the MCTL[RST_DEF] bit to 1.
536 */
537 /*@{*/
538 /*! @brief Read current value of the TRNG_SCR5L_RUN5_MAX field. */
539 #define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR5L_RUN5_MAX_SHIFT)
540
541 /*! @brief Set the RUN5_MAX field to a new value. */
542 #define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SCR5L_RUN5_MAX(value)))
543 /*@}*/
544
545 /*!
546 * @name Register TRNG_SCR5L, field RUN5_RNG[26:16] (RW)
547 *
548 * Run Length 5 Range. The number of runs of length 5 (for both 0 and 1)
549 * detected during entropy generation must be greater than RUN5_MAX - RUN5_RNG, else a
550 * retry or error will occur. This register is cleared to 002Eh (decimal 46) by
551 * writing the MCTL[RST_DEF] bit to 1.
552 */
553 /*@{*/
554 /*! @brief Read current value of the TRNG_SCR5L_RUN5_RNG field. */
555 #define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR5L_RUN5_RNG_SHIFT)
556
557 /*! @brief Set the RUN5_RNG field to a new value. */
558 #define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SCR5L_RUN5_RNG(value)))
559 /*@}*/
560 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L */
561
562 /*******************************************************************************
563 * TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register
564 ******************************************************************************/
565
566 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L)
567 /*!
568 * @brief TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register (RW)
569 *
570 * Reset value: 0x002E002FU
571 *
572 * The RNG Statistical Check Run Length 6+ Limit Register defines the allowable
573 * maximum and minimum number of runs of length 6 or more detected during entropy
574 * generation. To pass the test, the number of runs of length 6 or more (for
575 * samples of both 0 and 1) must be less than the programmed maximum value, and the
576 * number of runs of length 6 or more must be greater than (maximum - range). If
577 * this test fails, the Retry Counter in SCMISC will be decremented, and a retry
578 * will occur if the Retry Count has not reached zero. If the Retry Count has
579 * reached zero, an error will be generated. Note that this offset (0xBASE_0638) is
580 * used as SCR6PL only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is
581 * used as SCR6PC readback register.
582 */
583 /*!
584 * @name Constants and macros for entire TRNG_SCR6PL register
585 */
586 /*@{*/
587 #define TRNG_SCR6PL_REG(base) ((base)->SCR6PL)
588 #define TRNG_RD_SCR6PL(base) (TRNG_SCR6PL_REG(base))
589 #define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value))
590 #define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) | (value)))
591 /*@}*/
592
593 /*
594 * Constants & macros for individual TRNG_SCR6PL bitfields
595 */
596
597 /*!
598 * @name Register TRNG_SCR6PL, field RUN6P_MAX[10:0] (RW)
599 *
600 * Run Length 6+ Maximum Limit. Defines the maximum allowable runs of length 6
601 * or more (for both 0 and 1) detected during entropy generation. The number of
602 * runs of length 6 or more detected during entropy generation must be less than
603 * RUN6P_MAX, else a retry or error will occur. This register is cleared to 002Fh
604 * (decimal 47) by writing the MCTL[RST_DEF] bit to 1.
605 */
606 /*@{*/
607 /*! @brief Read current value of the TRNG_SCR6PL_RUN6P_MAX field. */
608 #define TRNG_RD_SCR6PL_RUN6P_MAX(base) \
609 ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRNG_SCR6PL_RUN6P_MAX_SHIFT)
610
611 /*! @brief Set the RUN6P_MAX field to a new value. */
612 #define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) \
613 (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TRNG_SCR6PL_RUN6P_MAX(value)))
614 /*@}*/
615
616 /*!
617 * @name Register TRNG_SCR6PL, field RUN6P_RNG[26:16] (RW)
618 *
619 * Run Length 6+ Range. The number of runs of length 6 or more (for both 0 and
620 * 1) detected during entropy generation must be greater than RUN6P_MAX -
621 * RUN6P_RNG, else a retry or error will occur. This register is cleared to 002Eh
622 * (decimal 46) by writing the MCTL[RST_DEF] bit to 1.
623 */
624 /*@{*/
625 /*! @brief Read current value of the TRNG_SCR6PL_RUN6P_RNG field. */
626 #define TRNG_RD_SCR6PL_RUN6P_RNG(base) \
627 ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRNG_SCR6PL_RUN6P_RNG_SHIFT)
628
629 /*! @brief Set the RUN6P_RNG field to a new value. */
630 #define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) \
631 (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TRNG_SCR6PL_RUN6P_RNG(value)))
632 /*@}*/
633 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L */
634
635 /*******************************************************************************
636 * TRNG_PKRMAX - RNG Poker Maximum Limit Register
637 ******************************************************************************/
638
639 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX) && FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX)
640 /*!
641 * @brief TRNG_PKRMAX - RNG Poker Maximum Limit Register (RW)
642 *
643 * Reset value: 0x00006920U
644 *
645 * The RNG Poker Maximum Limit Register defines Maximum Limit allowable during
646 * the TRNG Statistical Check Poker Test. Note that this offset (0xBASE_060C) is
647 * used as PKRMAX only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used
648 * as the PKRSQ readback register.
649 */
650 /*!
651 * @name Constants and macros for entire TRNG_PKRMAX register
652 */
653 /*@{*/
654 #define TRNG_PKRMAX_REG(base) ((base)->PKRMAX)
655 #define TRNG_RD_PKRMAX(base) (TRNG_PKRMAX_REG(base))
656 #define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value))
657 #define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) | (value)))
658 /*@}*/
659
660 /*
661 * Constants & macros for individual TRNG_PKRMAX bitfields
662 */
663
664 /*!
665 * @name Register TRNG_PKRMAX, field PKR_MAX[23:0] (RW)
666 *
667 * Poker Maximum Limit. During the TRNG Statistical Checks, a "Poker Test" is
668 * run which requires a maximum and minimum limit. The maximum allowable result is
669 * programmed in the PKRMAX[PKR_MAX] register. This field is writable only if
670 * MCTL[PRGM] bit is 1. This register is cleared to 006920h (decimal 26912) by
671 * writing the MCTL[RST_DEF] bit to 1. Note that the PKRMAX and PKRRNG registers
672 * combined are used to define the minimum allowable Poker result, which is PKR_MAX -
673 * PKR_RNG + 1. Note that if MCTL[PRGM] bit is 0, this register address is used
674 * to read the Poker Test Square Calculation result in register PKRSQ, as defined
675 * in the following section.
676 */
677 /*@{*/
678 /*! @brief Read current value of the TRNG_PKRMAX_PKR_MAX field. */
679 #define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PKRMAX_PKR_MAX_SHIFT)
680
681 /*! @brief Set the PKR_MAX field to a new value. */
682 #define TRNG_WR_PKRMAX_PKR_MAX(base, value) \
683 (TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_PKRMAX_PKR_MAX(value)))
684 /*@}*/
685 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX */
686
687 /*******************************************************************************
688 * TRNG_PKRRNG - RNG Poker Range Register
689 ******************************************************************************/
690
691 /*!
692 * @brief TRNG_PKRRNG - RNG Poker Range Register (RW)
693 *
694 * Reset value: 0x000009A3U
695 *
696 * The RNG Poker Range Register defines the difference between the TRNG Poker
697 * Maximum Limit and the minimum limit. These limits are used during the TRNG
698 * Statistical Check Poker Test.
699 */
700 /*!
701 * @name Constants and macros for entire TRNG_PKRRNG register
702 */
703 /*@{*/
704 #define TRNG_PKRRNG_REG(base) ((base)->PKRRNG)
705 #define TRNG_RD_PKRRNG(base) (TRNG_PKRRNG_REG(base))
706 #define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value))
707 #define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) | (value)))
708 /*@}*/
709
710 /*
711 * Constants & macros for individual TRNG_PKRRNG bitfields
712 */
713
714 /*!
715 * @name Register TRNG_PKRRNG, field PKR_RNG[15:0] (RW)
716 *
717 * Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which
718 * requires a maximum and minimum limit. The maximum is programmed in the
719 * RTPKRMAX[PKR_MAX] register, and the minimum is derived by subtracting the PKR_RNG
720 * value from the programmed maximum value. This field is writable only if
721 * MCTL[PRGM] bit is 1. This field will read zeroes if MCTL[PRGM] = 0. This field is
722 * cleared to 09A3h (decimal 2467) by writing the MCTL[RST_DEF] bit to 1. Note that
723 * the minimum allowable Poker result is PKR_MAX - PKR_RNG + 1.
724 */
725 /*@{*/
726 /*! @brief Read current value of the TRNG_PKRRNG_PKR_RNG field. */
727 #define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PKRRNG_PKR_RNG_SHIFT)
728
729 /*! @brief Set the PKR_RNG field to a new value. */
730 #define TRNG_WR_PKRRNG_PKR_RNG(base, value) \
731 (TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_PKRRNG_PKR_RNG(value)))
732 /*@}*/
733
734 /*******************************************************************************
735 * TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register
736 ******************************************************************************/
737
738 /*!
739 * @brief TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register (RW)
740 *
741 * Reset value: 0x00006400U
742 *
743 * The RNG Frequency Count Maximum Limit Register defines the maximum allowable
744 * count taken by the Entropy sample counter during each Entropy sample. During
745 * any sample period, if the count is greater than this programmed maximum, a
746 * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. Note
747 * that this address (061C) is used as FRQMAX only if MCTL[PRGM] is 1. If
748 * MCTL[PRGM] is 0, this address is used as FRQCNT readback register.
749 */
750 /*!
751 * @name Constants and macros for entire TRNG_FRQMAX register
752 */
753 /*@{*/
754 #define TRNG_FRQMAX_REG(base) ((base)->FRQMAX)
755 #define TRNG_RD_FRQMAX(base) (TRNG_FRQMAX_REG(base))
756 #define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value))
757 #define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) | (value)))
758 /*@}*/
759
760 /*
761 * Constants & macros for individual TRNG_FRQMAX bitfields
762 */
763
764 /*!
765 * @name Register TRNG_FRQMAX, field FRQ_MAX[21:0] (RW)
766 *
767 * Frequency Counter Maximum Limit. Defines the maximum allowable count taken
768 * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1.
769 * This register is cleared to 000640h by writing the MCTL[RST_DEF] bit to 1.
770 * Note that if MCTL[PRGM] bit is 0, this register address is used to read the
771 * Frequency Count result in register FRQCNT, as defined in the following section.
772 */
773 /*@{*/
774 /*! @brief Read current value of the TRNG_FRQMAX_FRQ_MAX field. */
775 #define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FRQMAX_FRQ_MAX_SHIFT)
776
777 /*! @brief Set the FRQ_MAX field to a new value. */
778 #define TRNG_WR_FRQMAX_FRQ_MAX(base, value) \
779 (TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_FRQMAX_FRQ_MAX(value)))
780 /*@}*/
781
782 /*******************************************************************************
783 * TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register
784 ******************************************************************************/
785
786 /*!
787 * @brief TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register (RW)
788 *
789 * Reset value: 0x00000640U
790 *
791 * The RNG Frequency Count Minimum Limit Register defines the minimum allowable
792 * count taken by the Entropy sample counter during each Entropy sample. During
793 * any sample period, if the count is less than this programmed minimum, a
794 * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated.
795 */
796 /*!
797 * @name Constants and macros for entire TRNG_FRQMIN register
798 */
799 /*@{*/
800 #define TRNG_FRQMIN_REG(base) ((base)->FRQMIN)
801 #define TRNG_RD_FRQMIN(base) (TRNG_FRQMIN_REG(base))
802 #define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value))
803 #define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) | (value)))
804 /*@}*/
805
806 /*
807 * Constants & macros for individual TRNG_FRQMIN bitfields
808 */
809
810 /*!
811 * @name Register TRNG_FRQMIN, field FRQ_MIN[21:0] (RW)
812 *
813 * Frequency Count Minimum Limit. Defines the minimum allowable count taken
814 * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1.
815 * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 0000h64
816 * by writing the MCTL[RST_DEF] bit to 1.
817 */
818 /*@{*/
819 /*! @brief Read current value of the TRNG_FRQMIN_FRQ_MIN field. */
820 #define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FRQMIN_FRQ_MIN_SHIFT)
821
822 /*! @brief Set the FRQ_MIN field to a new value. */
823 #define TRNG_WR_FRQMIN_FRQ_MIN(base, value) \
824 (TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_FRQMIN_FRQ_MIN(value)))
825 /*@}*/
826
827 /*******************************************************************************
828 * TRNG_MCTL - RNG Miscellaneous Control Register
829 ******************************************************************************/
830
831 /*!
832 * @brief TRNG_MCTL - RNG Miscellaneous Control Register (RW)
833 *
834 * Reset value: 0x00012001U
835 *
836 * This register is intended to be used for programming, configuring and testing
837 * the RNG. It is the main register to read/write, in order to enable Entropy
838 * generation, to stop entropy generation and to block access to entropy registers.
839 * This is done via the special TRNG_ACC and PRGM bits below. The RNG
840 * Miscellaneous Control Register is a read/write register used to control the RNG's True
841 * Random Number Generator (TRNG) access, operation and test. Note that in many
842 * cases two RNG registers share the same address, and a particular register at the
843 * shared address is selected based upon the value in the PRGM field of the MCTL
844 * register.
845 */
846 /*!
847 * @name Constants and macros for entire TRNG_MCTL register
848 */
849 /*@{*/
850 #define TRNG_MCTL_REG(base) ((base)->MCTL)
851 #define TRNG_RD_MCTL(base) (TRNG_MCTL_REG(base))
852 #define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value))
853 #define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (value)))
854 /*@}*/
855
856 /*!
857 * @name Register TRNG_MCTL, field FOR_SCLK[7] (RW)
858 *
859 * Force System Clock. If set, the system clock is used to operate the TRNG,
860 * instead of the ring oscillator. This is for test use only, and indeterminate
861 * results may occur. This bit is writable only if PRGM bit is 1, or PRGM bit is
862 * being written to 1 simultaneously to writing this bit. This bit is cleared by
863 * writing the RST_DEF bit to 1.
864 */
865 /*@{*/
866 /*! @brief Read current value of the TRNG_MCTL_FOR_SCLK field. */
867 #define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_FOR_SCLK_SHIFT)
868
869 /*! @brief Set the FOR_SCLK field to a new value. */
870 #define TRNG_WR_MCTL_FOR_SCLK(base, value) \
871 (TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_FOR_SCLK(value)))
872 /*@}*/
873
874 /*!
875 * @name Register TRNG_MCTL, field OSC_DIV[3:2] (RW)
876 *
877 * Oscillator Divide. Determines the amount of dividing done to the ring
878 * oscillator before it is used by the TRNG.This field is writable only if PRGM bit is
879 * 1, or PRGM bit is being written to 1 simultaneously to writing this field. This
880 * field is cleared to 00 by writing the RST_DEF bit to 1.
881 *
882 * Values:
883 * - 0b00 - use ring oscillator with no divide
884 * - 0b01 - use ring oscillator divided-by-2
885 * - 0b10 - use ring oscillator divided-by-4
886 * - 0b11 - use ring oscillator divided-by-8
887 */
888 /*@{*/
889 /*! @brief Read current value of the TRNG_MCTL_OSC_DIV field. */
890 #define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC_DIV_SHIFT)
891
892 /*! @brief Set the OSC_DIV field to a new value. */
893 #define TRNG_WR_MCTL_OSC_DIV(base, value) \
894 (TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_OSC_DIV(value)))
895 /*@}*/
896
897 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE) && FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE)
898 /*!
899 * @name Register TRNG_MCTL, field SAMP_MODE[1:0] (RW)
900 *
901 * Sample Mode. Determines the method of sampling the ring oscillator while
902 * generating the Entropy value:This field is writable only if PRGM bit is 1, or PRGM
903 * bit is being written to 1 simultaneously with writing this field. This field
904 * is cleared to 01 by writing the RST_DEF bit to 1.
905 *
906 * Values:
907 * - 0b00 - use Von Neumann data into both Entropy shifter and Statistical
908 * Checker
909 * - 0b01 - use raw data into both Entropy shifter and Statistical Checker
910 * - 0b10 - use Von Neumann data into Entropy shifter. Use raw data into
911 * Statistical Checker
912 * - 0b11 - reserved.
913 */
914 /*@{*/
915 /*! @brief Read current value of the TRNG_MCTL_SAMP_MODE field. */
916 #define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL_SAMP_MODE_SHIFT)
917
918 /*! @brief Set the SAMP_MODE field to a new value. */
919 #define TRNG_WR_MCTL_SAMP_MODE(base, value) \
920 (TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_SAMP_MODE(value)))
921 /*@}*/
922 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE */
923
924 /*!
925 * @name Register TRNG_MCTL, field PRGM[16] (RW)
926 *
927 * Programming Mode Select. When this bit is 1, the TRNG is in Program Mode,
928 * otherwise it is in Run Mode. No Entropy value will be generated while the TRNG is
929 * in Program Mode. Note that different RNG registers are accessible at the same
930 * address depending on whether PRGM is set to 1 or 0. This is noted in the RNG
931 * register descriptions.
932 */
933 /*@{*/
934 /*! @brief Read current value of the TRNG_MCTL_PRGM field. */
935 #define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIFT)
936
937 /*! @brief Set the PRGM field to a new value. */
938 #define TRNG_WR_MCTL_PRGM(base, value) \
939 (TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_PRGM(value)))
940 /*@}*/
941
942 /*!
943 * @name Register TRNG_MCTL, field RST_DEF[6] (WO)
944 *
945 * Reset Defaults. Writing a 1 to this bit clears various TRNG registers, and
946 * bits within registers, to their default state. This bit is writable only if PRGM
947 * bit is 1, or PRGM bit is being written to 1 simultaneously to writing this
948 * bit. Reading this bit always produces a 0.
949 */
950 /*@{*/
951 /*! @brief Set the RST_DEF field to a new value. */
952 #define TRNG_WR_MCTL_RST_DEF(base, value) \
953 (TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_RST_DEF(value)))
954 /*@}*/
955
956 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0))
957 /*!
958 * @name Register TRNG_MCTL, field TRNG_ACC[5] (RW)
959 *
960 * TRNG Access Mode. If this bit is set to 1, the TRNG will generate an Entropy
961 * value that can be read via the ENT0-ENT15 registers. The Entropy value may be
962 * read once the ENT VAL bit is asserted. Also see ENTa register descriptions
963 * (For a = 0 to 15).
964 */
965 /*@{*/
966 /*! @brief Read current value of the TRNG_MCTL_TRNG_ACC field. */
967 #define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_TRNG_ACC_SHIFT)
968
969 /*! @brief Set the TRNG_ACC field to a new value. */
970 #define TRNG_WR_MCTL_TRNG_ACC(base, value) \
971 (TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_TRNG_ACC(value)))
972 /*@}*/
973 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC */
974
975 /*!
976 * @name Register TRNG_MCTL, field TSTOP_OK[13] (RO)
977 *
978 * TRNG_OK_TO_STOP. Software should check that this bit is a 1 before
979 * transitioning RNG to low power mode (RNG clock stopped). RNG turns on the TRNG
980 * free-running ring oscillator whenever new entropy is being generated and turns off the
981 * ring oscillator when entropy generation is complete. If the RNG clock is
982 * stopped while the TRNG ring oscillator is running, the oscillator will continue
983 * running even though the RNG clock is stopped. TSTOP_OK is asserted when the TRNG
984 * ring oscillator is not running. and therefore it is ok to stop the RNG clock.
985 */
986 /*@{*/
987 /*! @brief Read current value of the TRNG_MCTL_TSTOP_OK field. */
988 #define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_TSTOP_OK_SHIFT)
989 /*@}*/
990
991 /*!
992 * @name Register TRNG_MCTL, field ENT_VAL[10] (RO)
993 *
994 * Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then
995 * after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0
996 * through ENT14 should be read before reading ENT15).
997 */
998 /*@{*/
999 /*! @brief Read current value of the TRNG_MCTL_ENT_VAL field. */
1000 #define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT_VAL_SHIFT)
1001 /*@}*/
1002
1003 /*!
1004 * @name Register TRNG_MCTL, field ERR[12] (W1C)
1005 *
1006 * Read: Error status. 1 = error detected. 0 = no error.Write: Write 1 to clear
1007 * errors. Writing 0 has no effect.
1008 */
1009 /*@{*/
1010 /*! @brief Read current value of the TRNG_MCTL_ERR field. */
1011 #define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT)
1012
1013 /*! @brief Set the ERR field to a new value. */
1014 #define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value)))
1015 /*@}*/
1016
1017 /*******************************************************************************
1018 * TRNG_SDCTL - RNG Seed Control Register
1019 ******************************************************************************/
1020
1021 /*!
1022 * @brief TRNG_SDCTL - RNG Seed Control Register (RW)
1023 *
1024 * Reset value: 0x0C8009C4U
1025 *
1026 * The RNG Seed Control Register contains two fields. One field defines the
1027 * length (in system clocks) of each Entropy sample (ENT_DLY), and the other field
1028 * indicates the number of samples that will taken during each TRNG Entropy
1029 * generation (SAMP_SIZE).
1030 */
1031 /*!
1032 * @name Constants and macros for entire TRNG_SDCTL register
1033 */
1034 /*@{*/
1035 #define TRNG_SDCTL_REG(base) ((base)->SDCTL)
1036 #define TRNG_RD_SDCTL(base) (TRNG_SDCTL_REG(base))
1037 #define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value))
1038 #define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (value)))
1039 /*@}*/
1040
1041 /*
1042 * Constants & macros for individual TRNG_SDCTL bitfields
1043 */
1044
1045 /*!
1046 * @name Register TRNG_SDCTL, field SAMP_SIZE[15:0] (RW)
1047 *
1048 * Sample Size. Defines the total number of Entropy samples that will be taken
1049 * during Entropy generation. This field is writable only if MCTL[PRGM] bit is 1.
1050 * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 09C4h
1051 * (decimal 2500) by writing the MCTL[RST_DEF] bit to 1.
1052 */
1053 /*@{*/
1054 /*! @brief Read current value of the TRNG_SDCTL_SAMP_SIZE field. */
1055 #define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_SDCTL_SAMP_SIZE_SHIFT)
1056
1057 /*! @brief Set the SAMP_SIZE field to a new value. */
1058 #define TRNG_WR_SDCTL_SAMP_SIZE(base, value) \
1059 (TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_SDCTL_SAMP_SIZE(value)))
1060 /*@}*/
1061
1062 /*!
1063 * @name Register TRNG_SDCTL, field ENT_DLY[31:16] (RW)
1064 *
1065 * Entropy Delay. Defines the length (in system clocks) of each Entropy sample
1066 * taken. This field is writable only if MCTL[PRGM] bit is 1. This field will read
1067 * zeroes if MCTL[PRGM] = 0. This field is cleared to 0C80h (decimal 3200) by
1068 * writing the MCTL[RST_DEF] bit to 1.
1069 */
1070 /*@{*/
1071 /*! @brief Read current value of the TRNG_SDCTL_ENT_DLY field. */
1072 #define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL_ENT_DLY_SHIFT)
1073
1074 /*! @brief Set the ENT_DLY field to a new value. */
1075 #define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCTL_ENT_DLY(value)))
1076 /*@}*/
1077
1078 /*******************************************************************************
1079 * TRNG_SBLIM - RNG Sparse Bit Limit Register
1080 ******************************************************************************/
1081
1082 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM > 0))
1083 /*!
1084 * @brief TRNG_SBLIM - RNG Sparse Bit Limit Register (RW)
1085 *
1086 * Reset value: 0x0000003FU
1087 *
1088 * The RNG Sparse Bit Limit Register is used when Von Neumann sampling is
1089 * selected during Entropy Generation. It defines the maximum number of consecutive Von
1090 * Neumann samples which may be discarded before an error is generated. Note
1091 * that this address (0xBASE_0614) is used as SBLIM only if MCTL[PRGM] is 1. If
1092 * MCTL[PRGM] is 0, this address is used as TOTSAM readback register.
1093 */
1094 /*!
1095 * @name Constants and macros for entire TRNG_SBLIM register
1096 */
1097 /*@{*/
1098 #define TRNG_SBLIM_REG(base) ((base)->SBLIM)
1099 #define TRNG_RD_SBLIM(base) (TRNG_SBLIM_REG(base))
1100 #define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value))
1101 #define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (value)))
1102 /*@}*/
1103
1104 /*
1105 * Constants & macros for individual TRNG_SBLIM bitfields
1106 */
1107
1108 /*!
1109 * @name Register TRNG_SBLIM, field SB_LIM[9:0] (RW)
1110 *
1111 * Sparse Bit Limit. During Von Neumann sampling (if enabled by MCTL[SAMP_MODE],
1112 * samples are discarded if two consecutive raw samples are both 0 or both 1. If
1113 * this discarding occurs for a long period of time, it indicates that there is
1114 * insufficient Entropy. The Sparse Bit Limit defines the maximum number of
1115 * consecutive samples that may be discarded before an error is generated. This field
1116 * is writable only if MCTL[PRGM] bit is 1. This register is cleared to 03hF by
1117 * writing the MCTL[RST_DEF] bit to 1. Note that if MCTL[PRGM] bit is 0, this
1118 * register address is used to read the Total Samples count in register TOTSAM, as
1119 * defined in the following section.
1120 */
1121 /*@{*/
1122 /*! @brief Read current value of the TRNG_SBLIM_SB_LIM field. */
1123 #define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_SB_LIM_SHIFT)
1124
1125 /*! @brief Set the SB_LIM field to a new value. */
1126 #define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_SB_LIM(value)))
1127 /*@}*/
1128 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM */
1129
1130 /*******************************************************************************
1131 * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register
1132 ******************************************************************************/
1133
1134 /*!
1135 * @brief TRNG_SCMISC - RNG Statistical Check Miscellaneous Register (RW)
1136 *
1137 * Reset value: 0x0001001FU
1138 *
1139 * The RNG Statistical Check Miscellaneous Register contains the Long Run
1140 * Maximum Limit value and the Retry Count value. This register is accessible only when
1141 * the MCTL[PRGM] bit is 1, otherwise this register will read zeroes, and cannot
1142 * be written.
1143 */
1144 /*!
1145 * @name Constants and macros for entire TRNG_SCMISC register
1146 */
1147 /*@{*/
1148 #define TRNG_SCMISC_REG(base) ((base)->SCMISC)
1149 #define TRNG_RD_SCMISC(base) (TRNG_SCMISC_REG(base))
1150 #define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value))
1151 #define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) | (value)))
1152 /*@}*/
1153
1154 /*
1155 * Constants & macros for individual TRNG_SCMISC bitfields
1156 */
1157
1158 /*!
1159 * @name Register TRNG_SCMISC, field LRUN_MAX[7:0] (RW)
1160 *
1161 * LONG RUN MAX LIMIT. This value is the largest allowable number of consecutive
1162 * samples of all 1, or all 0, that is allowed during the Entropy generation.
1163 * This field is writable only if MCTL[PRGM] bit is 1. This field will read zeroes
1164 * if MCTL[PRGM] = 0. This field is cleared to 22h by writing the MCTL[RST_DEF]
1165 * bit to 1.
1166 */
1167 /*@{*/
1168 /*! @brief Read current value of the TRNG_SCMISC_LRUN_MAX field. */
1169 #define TRNG_RD_SCMISC_LRUN_MAX(base) \
1170 ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_SCMISC_LRUN_MAX_SHIFT)
1171
1172 /*! @brief Set the LRUN_MAX field to a new value. */
1173 #define TRNG_WR_SCMISC_LRUN_MAX(base, value) \
1174 (TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG_SCMISC_LRUN_MAX(value)))
1175 /*@}*/
1176
1177 /*******************************************************************************
1178 * TRNG_ENT - RNG TRNG Entropy Read Register
1179 ******************************************************************************/
1180
1181 /*!
1182 * @brief TRNG_ENT - RNG TRNG Entropy Read Register (RO)
1183 *
1184 * Reset value: 0x00000000U
1185 *
1186 * The RNG TRNG can be programmed to generate an entropy value that is readable
1187 * via the SkyBlue bus. To do this, set the MCTL[TRNG_ACC] bit to 1. Once the
1188 * entropy value has been generated, the MCTL[ENT_VAL] bit will be set to 1. At this
1189 * point, ENT0 through ENT15 may be read to retrieve the 512-bit entropy value.
1190 * Note that once ENT15 is read, the entropy value will be cleared and a new
1191 * value will begin generation, so it is important that ENT15 be read last. These
1192 * registers are readable only when MCTL[PRGM] = 0 (Run Mode), MCTL[TRNG_ACC] = 1
1193 * (TRNG access mode) and MCTL[ENT_VAL] = 1, otherwise zeroes will be read.
1194 */
1195 /*!
1196 * @name Constants and macros for entire TRNG_ENT register
1197 */
1198 /*@{*/
1199 #define TRNG_ENT_REG(base, index) ((base)->ENT[index])
1200 #define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index))
1201 /*@}*/
1202
1203 /*******************************************************************************
1204 * TRNG_SEC_CFG - RNG Security Configuration Register
1205 ******************************************************************************/
1206
1207 /*!
1208 * @brief TRNG_SEC_CFG - RNG Security Configuration Register (RW)
1209 *
1210 * Reset value: 0x00000000U
1211 *
1212 * The RNG Security Configuration Register is a read/write register used to
1213 * control the test mode, programmability and state modes of the RNG. Many bits are
1214 * place holders for this version. More configurability will be added here. Clears
1215 * on asynchronous reset. For SA-TRNG releases before 2014/July/01, offsets 0xA0
1216 * to 0xAC used to be 0xB0 to 0xBC respectively. So, update newer tests that use
1217 * these registers, if hard coded.
1218 */
1219 /*!
1220 * @name Constants and macros for entire TRNG_SEC_CFG register
1221 */
1222 /*@{*/
1223 #define TRNG_SEC_CFG_REG(base) ((base)->SEC_CFG)
1224 #define TRNG_RD_SEC_CFG(base) (TRNG_SEC_CFG_REG(base))
1225 #define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value))
1226 #define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)) | (value)))
1227 /*@}*/
1228
1229 /*!
1230 * @name Register TRNG_SEC_CFG, field NO_PRGM[1] (RW)
1231 *
1232 * If set the TRNG registers cannot be programmed. That is, regardless of the
1233 * TRNG access mode in the SA-TRNG Miscellaneous Control Register.
1234 *
1235 * Values:
1236 * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous
1237 * Control Register's access mode bit.
1238 * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents
1239 * TRNG register programming.
1240 */
1241 /*@{*/
1242 /*! @brief Read current value of the TRNG_SEC_CFG_NO_PRGM field. */
1243 #define TRNG_RD_SEC_CFG_NO_PRGM(base) \
1244 ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG_SEC_CFG_NO_PRGM_SHIFT)
1245
1246 /*! @brief Set the NO_PRGM field to a new value. */
1247 #define TRNG_WR_SEC_CFG_NO_PRGM(base, value) \
1248 (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRNG_SEC_CFG_NO_PRGM(value)))
1249 /*@}*/
1250
1251 /*! @brief Array to map TRNG instance number to base pointer. */
1252 static TRNG_Type *const s_trngBases[] = TRNG_BASE_PTRS;
1253
1254 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1255 /*! @brief Clock array name */
1256 static const clock_ip_name_t s_trngClock[] = TRNG_CLOCKS;
1257 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1258
1259 #if defined(FSL_FEATURE_TRNG_HAS_RSTCTL) && (FSL_FEATURE_TRNG_HAS_RSTCTL > 0)
1260 static const reset_ip_name_t trng_reset = TRNG_RSTS;
1261 #endif /* FSL_FEATURE_TRNG_HAS_RSTCTL */
1262
1263 /*******************************************************************************
1264 * Prototypes
1265 *******************************************************************************/
1266 static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig);
1267 static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count);
1268 static status_t trng_SetMonobitLimit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1269 static status_t trng_SetRunBit1Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1270 static status_t trng_SetRunBit2Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1271 static status_t trng_SetRunBit3Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1272 static status_t trng_SetRunBit4Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1273 static status_t trng_SetRunBit5Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1274 static status_t trng_SetRunBit6Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1275 static status_t trng_SetPokerMaxLimit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum);
1276 static status_t trng_SetFrequencyCountMaxLimit(TRNG_Type *base, uint32_t limit_minimum, uint32_t limit_maximum);
1277 static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base,
1278 trng_statistical_check_t statistical_check,
1279 const trng_statistical_check_limit_t *limit);
1280 static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index);
1281 static uint32_t trng_GetInstance(TRNG_Type *base);
1282
1283 /*******************************************************************************
1284 * Code
1285 ******************************************************************************/
1286
trng_GetInstance(TRNG_Type * base)1287 static uint32_t trng_GetInstance(TRNG_Type *base)
1288 {
1289 uint32_t instance;
1290
1291 /* Find the instance index from base address mappings. */
1292 for (instance = 0; instance < ARRAY_SIZE(s_trngBases); instance++)
1293 {
1294 if (s_trngBases[instance] == base)
1295 {
1296 break;
1297 }
1298 }
1299
1300 assert(instance < ARRAY_SIZE(s_trngBases));
1301
1302 return instance;
1303 }
1304
1305 /*FUNCTION*********************************************************************
1306 *
1307 * Function Name : TRNG_InitUserConfigDefault
1308 * Description : Initializes user configuration structure to default settings.
1309 *
1310 *END*************************************************************************/
1311 /*!
1312 * brief Initializes the user configuration structure to default values.
1313 *
1314 * This function initializes the configuration structure to default values. The default
1315 * values are as follows.
1316 * code
1317 * userConfig->lock = 0;
1318 * userConfig->clockMode = kTRNG_ClockModeRingOscillator;
1319 * userConfig->ringOscDiv = kTRNG_RingOscDiv0; Or to other kTRNG_RingOscDiv[2|8] depending on the platform.
1320 * userConfig->sampleMode = kTRNG_SampleModeRaw;
1321 * userConfig->entropyDelay = 3200;
1322 * userConfig->sampleSize = 2500;
1323 * userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT;
1324 * userConfig->retryCount = 63;
1325 * userConfig->longRunMaxLimit = 34;
1326 * userConfig->monobitLimit.maximum = 1384;
1327 * userConfig->monobitLimit.minimum = 1116;
1328 * userConfig->runBit1Limit.maximum = 405;
1329 * userConfig->runBit1Limit.minimum = 227;
1330 * userConfig->runBit2Limit.maximum = 220;
1331 * userConfig->runBit2Limit.minimum = 98;
1332 * userConfig->runBit3Limit.maximum = 125;
1333 * userConfig->runBit3Limit.minimum = 37;
1334 * userConfig->runBit4Limit.maximum = 75;
1335 * userConfig->runBit4Limit.minimum = 11;
1336 * userConfig->runBit5Limit.maximum = 47;
1337 * userConfig->runBit5Limit.minimum = 1;
1338 * userConfig->runBit6PlusLimit.maximum = 47;
1339 * userConfig->runBit6PlusLimit.minimum = 1;
1340 * userConfig->pokerLimit.maximum = 26912;
1341 * userConfig->pokerLimit.minimum = 24445;
1342 * userConfig->frequencyCountLimit.maximum = 25600;
1343 * userConfig->frequencyCountLimit.minimum = 1600;
1344 * endcode
1345 *
1346 * param userConfig User configuration structure.
1347 * return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error.
1348 */
TRNG_GetDefaultConfig(trng_config_t * userConfig)1349 status_t TRNG_GetDefaultConfig(trng_config_t *userConfig)
1350 {
1351 status_t result;
1352
1353 if (userConfig != NULL)
1354 {
1355 /* Initializes the configuration structure to default values. */
1356
1357 /* Lock programmability of TRNG registers. */
1358 userConfig->lock = (bool)TRNG_USER_CONFIG_DEFAULT_LOCK;
1359 /* Clock settings */
1360 userConfig->clockMode = kTRNG_ClockModeRingOscillator;
1361 userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV;
1362 userConfig->sampleMode = kTRNG_SampleModeRaw;
1363 #if defined(FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS) && (FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS > 0)
1364 userConfig->oscillatorMode = kTRNG_SingleOscillatorModeOsc1;
1365 userConfig->ringOsc2Div = kTRNG_RingOscDiv4;
1366 #endif /* FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS */
1367 /* Seed control*/
1368 userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY;
1369 userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE;
1370 userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT;
1371
1372 /* Statistical Check Parameters.*/
1373 userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT;
1374 userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT;
1375
1376 userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM;
1377 userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM;
1378 userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM;
1379 userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM;
1380 userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM;
1381 userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM;
1382 userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM;
1383 userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM;
1384 userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM;
1385 userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM;
1386 userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM;
1387 userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM;
1388 userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM;
1389 userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM;
1390 /* Limits for statistical check of "Poker Test". */
1391 userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM;
1392 userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM;
1393 /* Limits for statistical check of entropy sample frequency count. */
1394 userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM;
1395 userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM;
1396
1397 result = kStatus_Success;
1398 }
1399 else
1400 {
1401 result = kStatus_InvalidArgument;
1402 }
1403
1404 return result;
1405 }
1406
1407 /*!
1408 * @brief Sets the TRNG retry count.
1409 *
1410 * This function sets the retry counter which defines the number of times a
1411 * statistical check may fails during the TRNG Entropy Generation before
1412 * generating an error.
1413 */
trng_SetRetryCount(TRNG_Type * base,uint8_t retry_count)1414 static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count)
1415 {
1416 status_t status;
1417
1418 if ((retry_count >= 1u) && (retry_count <= 15u))
1419 {
1420 /* Set retry count.*/
1421 TRNG_WR_SCMISC_RTY_CT(base, retry_count);
1422 status = kStatus_Success;
1423 }
1424 else
1425 {
1426 status = kStatus_InvalidArgument;
1427 }
1428 return status;
1429 }
1430
1431 /*!
1432 * @brief Sets statistical Check Monobit Limit Register .
1433 *
1434 * This function set register TRNG_SCML - Statistical Check Monobit Limit Register
1435 */
trng_SetMonobitLimit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1436 static status_t trng_SetMonobitLimit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1437 {
1438 status_t status;
1439
1440 /* Check input parameters*/
1441 if ((range <= 0xffffu) && (limit_maximum <= 0xffffu))
1442
1443 {
1444 /* Set TRNG_SCML register */
1445 TRNG_WR_SCML_MONO_MAX(base, limit_maximum);
1446 TRNG_WR_SCML_MONO_RNG(base, range);
1447 status = kStatus_Success;
1448 }
1449 else
1450 {
1451 status = kStatus_InvalidArgument;
1452 }
1453 return status;
1454 }
1455
1456 /*!
1457 * @brief Sets statistical Statistical Check Run Length 1 Limit Register .
1458 *
1459 * This function set register TRNG_SCR1L - Statistical Check Run Length 1 Limit Register
1460 */
trng_SetRunBit1Limit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1461 static status_t trng_SetRunBit1Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1462 {
1463 status_t status;
1464
1465 /* Check input parameters*/
1466 if ((range <= 0x7fffu) && (limit_maximum <= 0x7fffu))
1467 {
1468 /* Set TRNG_SCR1L register */
1469 TRNG_WR_SCR1L_RUN1_MAX(base, limit_maximum);
1470 TRNG_WR_SCR1L_RUN1_RNG(base, range);
1471 status = kStatus_Success;
1472 }
1473 else
1474 {
1475 status = kStatus_InvalidArgument;
1476 }
1477 return status;
1478 }
1479
1480 /*!
1481 * @brief Sets statistical Statistical Check Run Length 2 Limit Register .
1482 *
1483 * This function set register TRNG_SCR2L - Statistical Check Run Length 2 Limit Register
1484 */
trng_SetRunBit2Limit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1485 static status_t trng_SetRunBit2Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1486 {
1487 status_t status;
1488
1489 /* Check input parameters*/
1490 if ((range <= 0x3fffu) && (limit_maximum <= 0x3fffu))
1491 {
1492 /* Set TRNG_SCR2L register */
1493 TRNG_WR_SCR2L_RUN2_MAX(base, limit_maximum);
1494 TRNG_WR_SCR2L_RUN2_RNG(base, range);
1495 status = kStatus_Success;
1496 }
1497 else
1498 {
1499 status = kStatus_InvalidArgument;
1500 }
1501 return status;
1502 }
1503
1504 /*!
1505 * @brief Sets statistical Statistical Check Run Length 3 Limit Register .
1506 *
1507 * This function set register TRNG_SCR3L - Statistical Check Run Length 3 Limit Register
1508 */
trng_SetRunBit3Limit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1509 static status_t trng_SetRunBit3Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1510 {
1511 status_t status;
1512
1513 /* Check input parameters*/
1514 if ((range <= 0x1fffu) && (limit_maximum <= 0x1fffu))
1515 {
1516 /* Set TRNG_SCR3L register */
1517 TRNG_WR_SCR3L_RUN3_MAX(base, limit_maximum);
1518 TRNG_WR_SCR3L_RUN3_RNG(base, range);
1519 status = kStatus_Success;
1520 }
1521 else
1522 {
1523 status = kStatus_InvalidArgument;
1524 }
1525 return status;
1526 }
1527
1528 /*!
1529 * @brief Sets statistical Statistical Check Run Length 4 Limit Register .
1530 * This function set register TRNG_SCR4L - Statistical Check Run Length 4 Limit Register
1531 */
trng_SetRunBit4Limit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1532 static status_t trng_SetRunBit4Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1533 {
1534 status_t status;
1535
1536 /* Check input parameters*/
1537 if ((range <= 0xfffu) && (limit_maximum <= 0xfffu))
1538 {
1539 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L)
1540 /* Set TRNG_SCR4L register */
1541 TRNG_WR_SCR4L_RUN4_MAX(base, limit_maximum);
1542 TRNG_WR_SCR4L_RUN4_RNG(base, range);
1543 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L */
1544 status = kStatus_Success;
1545 }
1546 else
1547 {
1548 status = kStatus_InvalidArgument;
1549 }
1550 return status;
1551 }
1552
1553 /*!
1554 * @brief Sets statistical Statistical Check Run Length 5 Limit Register .
1555 * This function set register TRNG_SCR5L - Statistical Check Run Length 5 Limit Register
1556 */
trng_SetRunBit5Limit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1557 static status_t trng_SetRunBit5Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1558 {
1559 status_t status;
1560
1561 /* Check input parameters*/
1562 if ((range <= 0x7ffu) && (limit_maximum <= 0x7ffu))
1563 {
1564 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L)
1565 /* Set TRNG_SCR5L register */
1566 TRNG_WR_SCR5L_RUN5_MAX(base, limit_maximum);
1567 TRNG_WR_SCR5L_RUN5_RNG(base, range);
1568 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L */
1569 status = kStatus_Success;
1570 }
1571 else
1572 {
1573 status = kStatus_InvalidArgument;
1574 }
1575 return status;
1576 }
1577
1578 /*!
1579 * @brief Sets statistical Statistical Check Run Length 6 Limit Register .
1580 * This function set register TRNG_SCR6L - Statistical Check Run Length 6 Limit Register
1581 */
trng_SetRunBit6Limit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1582 static status_t trng_SetRunBit6Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1583 {
1584 status_t status;
1585
1586 /* Check input parameters*/
1587 if ((range <= 0x7ffu) && (limit_maximum <= 0x7ffu))
1588 {
1589 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L)
1590 /* Set TRNG_SCR6L register */
1591 TRNG_WR_SCR6PL_RUN6P_MAX(base, limit_maximum);
1592 TRNG_WR_SCR6PL_RUN6P_RNG(base, range);
1593 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L */
1594 status = kStatus_Success;
1595 }
1596 else
1597 {
1598 status = kStatus_InvalidArgument;
1599 }
1600 return status;
1601 }
1602
1603 /*!
1604 * @brief Sets statistical Poker Maximum Limit Register.
1605 * This function set register TRNG_PKRMAX - Poker Maximum Limit Register
1606 */
trng_SetPokerMaxLimit(TRNG_Type * base,uint32_t range,uint32_t limit_maximum)1607 static status_t trng_SetPokerMaxLimit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum)
1608 {
1609 status_t status;
1610
1611 /* Check input parameters*/
1612 if ((range <= 0xffffu) && (limit_maximum <= 0xffffffu))
1613 {
1614 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX) && FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX)
1615 /* Set TRNG_PKRMAX register */
1616 TRNG_WR_PKRMAX_PKR_MAX(base, limit_maximum);
1617 TRNG_WR_PKRRNG_PKR_RNG(base, range);
1618 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX */
1619 status = kStatus_Success;
1620 }
1621 else
1622 {
1623 status = kStatus_InvalidArgument;
1624 }
1625 return status;
1626 }
1627
1628 /*!
1629 * @brief Sets statistical Frequency Count Maximum Limit Register.
1630 * This function set register TRNG_FRQMAX - Frequency Count Maximum Limit Register
1631 */
trng_SetFrequencyCountMaxLimit(TRNG_Type * base,uint32_t limit_minimum,uint32_t limit_maximum)1632 static status_t trng_SetFrequencyCountMaxLimit(TRNG_Type *base, uint32_t limit_minimum, uint32_t limit_maximum)
1633 {
1634 status_t status;
1635
1636 /* Check input parameters*/
1637 if ((limit_minimum <= 0x3fffffu) && (limit_maximum <= 0x3fffffu))
1638 {
1639 /* Set FRQMAX register */
1640 TRNG_WR_FRQMAX_FRQ_MAX(base, limit_maximum);
1641 TRNG_WR_FRQMIN_FRQ_MIN(base, limit_minimum);
1642 status = kStatus_Success;
1643 }
1644 else
1645 {
1646 status = kStatus_InvalidArgument;
1647 }
1648 return status;
1649 }
1650
1651 /*!
1652 * @brief Sets statistical check limits.
1653 *
1654 * This function is used to set minimum and maximum limits of statistical checks.
1655 *
1656 */
trng_SetStatisticalCheckLimit(TRNG_Type * base,trng_statistical_check_t statistical_check,const trng_statistical_check_limit_t * limit)1657 static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base,
1658 trng_statistical_check_t statistical_check,
1659 const trng_statistical_check_limit_t *limit)
1660 {
1661 uint32_t range;
1662 status_t status = kStatus_Success;
1663
1664 if ((NULL != limit) && (limit->maximum > limit->minimum))
1665 {
1666 range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/
1667
1668 if (statistical_check == kTRNG_StatisticalCheckMonobit) /* Allowable maximum and minimum number of ones/zero
1669 detected during entropy generation. */
1670 {
1671 status = trng_SetMonobitLimit(base, range, limit->maximum);
1672 }
1673 else if (statistical_check == kTRNG_StatisticalCheckRunBit1) /* Allowable maximum and minimum number of runs of
1674 length 1 detected during entropy generation. */
1675 {
1676 status = trng_SetRunBit1Limit(base, range, limit->maximum);
1677 }
1678 else if (statistical_check == kTRNG_StatisticalCheckRunBit2) /* Allowable maximum and minimum number of runs of
1679 length 2 detected during entropy generation. */
1680 {
1681 status = trng_SetRunBit2Limit(base, range, limit->maximum);
1682 }
1683 else if (statistical_check == kTRNG_StatisticalCheckRunBit3) /* Allowable maximum and minimum number of runs of
1684 length 3 detected during entropy generation. */
1685 {
1686 status = trng_SetRunBit3Limit(base, range, limit->maximum);
1687 }
1688 else if (statistical_check == kTRNG_StatisticalCheckRunBit4) /* Allowable maximum and minimum number of runs of
1689 length 4 detected during entropy generation. */
1690 {
1691 status = trng_SetRunBit4Limit(base, range, limit->maximum);
1692 }
1693 else if (statistical_check == kTRNG_StatisticalCheckRunBit5) /* Allowable maximum and minimum number of runs of
1694 length 5 detected during entropy generation. */
1695 {
1696 status = trng_SetRunBit5Limit(base, range, limit->maximum);
1697 }
1698 else if (statistical_check == kTRNG_StatisticalCheckRunBit6Plus) /* Allowable maximum and minimum number of
1699 length 6 or more detected during entropy
1700 generation */
1701 {
1702 status = trng_SetRunBit6Limit(base, range, limit->maximum);
1703 }
1704 else if (statistical_check == kTRNG_StatisticalCheckPoker) /* Allowable maximum and minimum limit of "Poker
1705 Test" detected during entropy generation . */
1706 {
1707 status = trng_SetPokerMaxLimit(base, range, limit->maximum);
1708 }
1709 else if (statistical_check == kTRNG_StatisticalCheckFrequencyCount) /* Allowable maximum and minimum limit of
1710 entropy sample frquency count during
1711 entropy generation . */
1712 {
1713 status = trng_SetFrequencyCountMaxLimit(base, limit->minimum, limit->maximum);
1714 }
1715 else
1716 {
1717 status = kStatus_InvalidArgument;
1718 }
1719 }
1720
1721 return status;
1722 }
1723
1724 /*FUNCTION*********************************************************************
1725 *
1726 * Function Name : trng_ApplyUserConfig
1727 * Description : Apply user configuration settings to TRNG module.
1728 *
1729 *END*************************************************************************/
trng_ApplyUserConfig(TRNG_Type * base,const trng_config_t * userConfig)1730 static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig)
1731 {
1732 status_t status;
1733
1734 /* Set retry count */
1735 status = trng_SetRetryCount(base, userConfig->retryCount);
1736
1737 /* Set statistical check limit */
1738 if (kStatus_Success == status)
1739 {
1740 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit);
1741 }
1742
1743 if (kStatus_Success == status)
1744 {
1745 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit);
1746 }
1747
1748 if (kStatus_Success == status)
1749 {
1750 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit);
1751 }
1752
1753 if (kStatus_Success == status)
1754 {
1755 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit);
1756 }
1757
1758 if (kStatus_Success == status)
1759 {
1760 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit);
1761 }
1762
1763 if (kStatus_Success == status)
1764 {
1765 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit);
1766 }
1767
1768 if (kStatus_Success == status)
1769 {
1770 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus, &userConfig->runBit6PlusLimit);
1771 }
1772
1773 if (kStatus_Success == status)
1774 {
1775 status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit);
1776 }
1777
1778 if (kStatus_Success == status)
1779 {
1780 status =
1781 trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount, &userConfig->frequencyCountLimit);
1782 }
1783
1784 if (kStatus_Success == status)
1785 {
1786 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE) && FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE)
1787 /* Set clock mode used to operate TRNG */
1788 TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode);
1789 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE */
1790 /* Set ring oscillator divider used by TRNG */
1791 TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv);
1792 #if defined(FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS) && (FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS > 0)
1793 base->OSC2_CTL |= TRNG_OSC2_CTL_TRNG_ENT_CTL(userConfig->oscillatorMode);
1794 base->OSC2_CTL |= TRNG_OSC2_CTL_OSC2_DIV(userConfig->ringOsc2Div);
1795 #endif /* FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS */
1796 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE) && FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE)
1797 /* Set sample mode of the TRNG ring oscillator. */
1798 TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode);
1799 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE */
1800 /* Set length of each Entropy sample taken */
1801 TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay);
1802 /* Set number of entropy samples that will be taken during Entropy generation */
1803 TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize);
1804 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM > 0))
1805 /* Set Sparse Bit Limit */
1806 TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit);
1807 #endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM */
1808 TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit);
1809 }
1810
1811 return status;
1812 }
1813
1814 /*!
1815 * @brief Gets a entry data from the TRNG.
1816 *
1817 * This function gets an entropy data from TRNG.
1818 * Entropy data is spread over TRNG_ENT_COUNT registers.
1819 * Read register number is defined by index parameter.
1820 */
trng_ReadEntropy(TRNG_Type * base,uint32_t index)1821 static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index)
1822 {
1823 uint32_t data;
1824
1825 index = index % TRNG_ENT_COUNT; /* This way we can use incremental index without limit control from application.*/
1826
1827 data = TRNG_RD_ENT(base, index);
1828
1829 if (index == (TRNG_ENT_COUNT - 1u))
1830 {
1831 /* Dummy read. Defect workaround.
1832 * TRNG could not clear ENT_VAL flag automatically, application
1833 * had to do a dummy reading operation for anyone TRNG register
1834 * to clear it firstly, then to read the RTENT0 to RTENT15 again */
1835 index = TRNG_RD_ENT(base, 0);
1836 }
1837
1838 return data;
1839 }
1840
1841 /*!
1842 * brief Initializes the TRNG.
1843 *
1844 * This function initializes the TRNG.
1845 * When called, the TRNG entropy generation starts immediately.
1846 *
1847 * param base TRNG base address
1848 * param userConfig Pointer to the initialization configuration structure.
1849 * return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error.
1850 */
TRNG_Init(TRNG_Type * base,const trng_config_t * userConfig)1851 status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig)
1852 {
1853 status_t result;
1854
1855 /* Check input parameters.*/
1856 if ((base != NULL) && (userConfig != NULL))
1857 {
1858 #if defined(FSL_FEATURE_TRNG_HAS_RSTCTL) && (FSL_FEATURE_TRNG_HAS_RSTCTL > 0)
1859 /* Reset TRNG peripheral */
1860 #if (defined(RW610_SERIES) || defined(RW612_SERIES))
1861 SYSCTL2->TRNG_PIN_CTRL |= SYSCTL2_TRNG_PIN_CTRL_ENABLE_MASK;
1862 #endif /* RW610_SERIES RW612_SERIES */
1863 RESET_PeripheralReset(trng_reset);
1864 #endif /* FSL_FEATURE_TRNG_HAS_RSTCTL */
1865 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1866 /* Enable the clock gate. */
1867 CLOCK_EnableClock(s_trngClock[trng_GetInstance(base)]);
1868 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1869
1870 /* Clear pending errors, set program mode and reset the registers to default values.*/
1871 /* MCTL[PRGM] = 1 (kTRNG_WorkModeProgram); MCTL[ERR] = 1; MCTL[RST_DEF] = 1 */
1872 TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK | TRNG_MCTL_RST_DEF_MASK),
1873 TRNG_MCTL_PRGM(kTRNG_WorkModeProgram) | TRNG_MCTL_ERR(1) | TRNG_MCTL_RST_DEF(1));
1874
1875 /* Set configuration.*/
1876 if ((result = trng_ApplyUserConfig(base, userConfig)) == kStatus_Success)
1877 {
1878 /* Start entropy generation.*/
1879 /* Set to Run mode.*/
1880 TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun);
1881 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0))
1882 /* Enable TRNG Access Mode. To generate an Entropy
1883 * value that can be read via the true0-true15 registers.*/
1884 TRNG_WR_MCTL_TRNG_ACC(base, 1);
1885 #endif /* !FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC */
1886
1887 (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u));
1888
1889 if (true == userConfig->lock) /* Disable programmability of TRNG registers. */
1890 {
1891 TRNG_WR_SEC_CFG_NO_PRGM(base, 1);
1892 }
1893
1894 result = kStatus_Success;
1895 }
1896 }
1897 else
1898 {
1899 result = kStatus_InvalidArgument;
1900 }
1901
1902 return result;
1903 }
1904
1905 /*!
1906 * brief Shuts down the TRNG.
1907 *
1908 * This function shuts down the TRNG.
1909 *
1910 * param base TRNG base address.
1911 */
TRNG_Deinit(TRNG_Type * base)1912 void TRNG_Deinit(TRNG_Type *base)
1913 {
1914 /* Check input parameters.*/
1915 if (NULL != base)
1916 {
1917 /* Move to program mode. Stop entropy generation.*/
1918 TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram);
1919
1920 /* Check before clock stop.
1921 TRNG turns on the TRNG free-running ring oscillator whenever new entropy
1922 is being generated and turns off the ring oscillator when entropy generation
1923 is complete. If the TRNG clock is stopped while the TRNG ring oscillator
1924 is running, the oscillator continues running though the RNG clock.
1925 is stopped. */
1926 while (TRNG_RD_MCTL_TSTOP_OK(base) == 0u)
1927 {
1928 }
1929
1930 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1931 /* Disable Clock*/
1932 CLOCK_DisableClock(s_trngClock[trng_GetInstance(base)]);
1933 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1934 }
1935 }
1936
1937 /*!
1938 * brief Gets random data.
1939 *
1940 * This function gets random data from the TRNG.
1941 *
1942 * param base TRNG base address.
1943 * param data Pointer address used to store random data.
1944 * param dataSize Size of the buffer pointed by the data parameter.
1945 * return random data
1946 */
TRNG_GetRandomData(TRNG_Type * base,void * data,size_t dataSize)1947 status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize)
1948 {
1949 status_t result = kStatus_Success;
1950 uint32_t random_32;
1951 uint8_t *random_p;
1952 uint32_t random_size;
1953 uint8_t *data_p = (uint8_t *)data;
1954 uint32_t i;
1955 uint32_t tmpValidFlag;
1956 uint32_t tmpErrorFlag;
1957
1958 int index = 0;
1959
1960 /* Check input parameters.*/
1961 if ((NULL != base) && (NULL != data) && (0U != dataSize))
1962 {
1963 /* After a deepsleep exit some errors bits are set in MCTL and must be cleared before processing further.
1964 Also, trigger new 512 bits entropy generation to be sure we will have fresh bits.*/
1965 if (0U != TRNG_RD_MCTL_ERR(base))
1966 {
1967 /* clear errors bits */
1968 TRNG_WR_MCTL_ERR(base, 1);
1969 /* restart new entropy generation */
1970 (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u));
1971 }
1972
1973 do
1974 {
1975 /* Wait for Valid or Error flag*/
1976 tmpValidFlag = TRNG_RD_MCTL_ENT_VAL(base);
1977 tmpErrorFlag = TRNG_RD_MCTL_ERR(base);
1978 while ((tmpValidFlag == 0u) && (tmpErrorFlag == 0u))
1979 {
1980 tmpValidFlag = TRNG_RD_MCTL_ENT_VAL(base);
1981 tmpErrorFlag = TRNG_RD_MCTL_ERR(base);
1982 }
1983
1984 /* Check HW error.*/
1985 if (0U != TRNG_RD_MCTL_ERR(base))
1986 {
1987 result = kStatus_Fail; /* TRNG module error occurred */
1988 /* Clear error.*/
1989 TRNG_WR_MCTL_ERR(base, 1);
1990 break; /* No sense stay here.*/
1991 }
1992
1993 /* Read Entropy.*/
1994 random_32 = trng_ReadEntropy(base, (uint32_t)index++);
1995
1996 random_p = (uint8_t *)&random_32;
1997
1998 if (dataSize < sizeof(random_32))
1999 {
2000 random_size = dataSize;
2001 }
2002 else
2003 {
2004 random_size = sizeof(random_32);
2005 }
2006
2007 for (i = 0U; i < random_size; i++)
2008 {
2009 *data_p++ = *random_p++;
2010 }
2011
2012 dataSize -= random_size;
2013 } while (dataSize > 0u);
2014
2015 /* Start a new entropy generation.
2016 It is done by reading of the last entropy register.*/
2017 if (((unsigned)index % TRNG_ENT_COUNT) != 0U)
2018 {
2019 (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u));
2020 }
2021 }
2022 else
2023 {
2024 result = kStatus_InvalidArgument;
2025 }
2026
2027 return result;
2028 }
2029
2030 #endif /* FSL_FEATURE_SOC_TRNG_COUNT */
2031
