1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _BOARD_H_ 10 #define _BOARD_H_ 11 12 #include "clock_config.h" 13 #include "fsl_clock.h" 14 #include "fsl_rgpio.h" 15 #if defined(BOARD_USE_PCA6416A) && BOARD_USE_PCA6416A 16 #include "fsl_pca6416a.h" 17 #endif 18 /******************************************************************************* 19 * Definitions 20 ******************************************************************************/ 21 #define PFD_VALID_MASK (0x40404040U) 22 #ifndef BIT 23 #define BIT(n) (1U << (n)) 24 #endif 25 #define MHZ(X) ((X)*1000000UL) 26 27 /* SoC variable type */ 28 #define MPU_SOC_IMX8ULP 0xA1 /* dummy ID, full feature, iMX8ULP Dual core 7D/7C */ 29 #define MPU_SOC_IMX8ULPD5 0xA2 /* dummy ID, iMX8ULP Dual core 5D/5C, EPDC disabled */ 30 #define MPU_SOC_IMX8ULPS5 0xA3 /* dummy ID, iMX8ULP Single core 5D/5C, EPDC disabled */ 31 #define MPU_SOC_IMX8ULPD3 0xA4 /* dummy ID, iMX8ULP Dual core 3D/3C, EPDC + GPU disabled */ 32 #define MPU_SOC_IMX8ULPS3 0xA5 /* dummy ID, iMX8ULP Single core 3D/3C, EPDC + GPU disabled */ 33 #define MPU_SOC_IMX8ULPSC 0xA6 /* dummy ID, iMX8ULP SC part, 900 MHz + EPDC disabled */ 34 35 /*! @brief The board name */ 36 #define BOARD_NAME "MIMX8ULP-EVK" 37 #define MANUFACTURER_NAME "NXP" 38 39 /* SOC infomation*/ 40 #define IMX8ULP_SOC_REV_A0 0xA000 41 #define IMX8ULP_SOC_REV_A1 0xA100 42 #define IMX8ULP_SOC_ID 0x084D 43 44 /* The UART to use for debug messages. */ 45 #define BOARD_DEBUG_UART_TYPE kSerialPort_Uart 46 #define BOARD_DEBUG_UART_BAUDRATE 115200u 47 #define BOARD_DEBUG_UART_BASEADDR LPUART1_BASE 48 #define BOARD_DEBUG_UART_INSTANCE 1U 49 #define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetLpuartClkFreq(BOARD_DEBUG_UART_INSTANCE) 50 #define BOARD_DEBUG_UART_IP_NAME kCLOCK_Lpuart1 51 #define BOARD_DEBUG_UART_CLKSRC kCLOCK_Pcc1BusIpSrcSysOscDiv2 52 #define BOARD_DEBUG_UART_RESET kRESET_Lpuart1 53 #define BOARD_UART_IRQ LPUART1_IRQn 54 #define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler 55 56 /* Board accelerator sensor configuration */ 57 #define BOARD_ACCEL_I2C_BASEADDR LPI2C0 58 #define BOARD_ACCEL_I2C_CLOCK_FREQ CLOCK_GetLpi2cClkFreq(0) 59 60 #define BOARD_CODEC_I2C_BASEADDR LPI2C0 61 #define BOARD_CODEC_I2C_CLOCK_FREQ CLOCK_GetLpi2cClkFreq(0) 62 #define BOARD_CODEC_I2C_INSTANCE 0U 63 64 /* Board mipi to hdmi bridge ic(IT6161) */ 65 #define BOARD_DISPLAY_I2C_BASEADDR LPI2C0 66 #define BOARD_DISPLAY_I2C_CLOCK_FREQ CLOCK_GetLpi2cClkFreq(0) 67 68 #define BOARD_FLEXSPI_PSRAM FLEXSPI1 69 /* NOR FLASH */ 70 #define BOARD_NOR_FLASH_READ_MAXIMUM_FREQ (40000000U) /* READ NOR FLASH MAXIMUM FREQUENCY is 40 MHz */ 71 /* For NOR FLASH that connected to flexspi0 controller */ 72 #define BOARD_FLEXSPI_NOR_FLASH_PORT kFLEXSPI_PortA1 73 #define BOARD_FLEXSPI_CONNECT_TO_NOR_FLASH FLEXSPI0 74 /* For NOR FLASH GD25LX256E */ 75 #ifndef SPINOR_OP_DISABLE_4_BYTE_ADDR_MODE_GIGADEVICE 76 #define SPINOR_OP_DISABLE_4_BYTE_ADDR_MODE_GIGADEVICE \ 77 (0xE9) /* Disable 4-Byte Address Mode (from GigaDevice GD25LX256E) */ 78 #endif 79 80 #define BOARD_SW8_GPIO GPIOB 81 #define BOARD_SW8_GPIO_PIN 12U 82 #define BOARD_SW8_IRQ GPIOB_INT0_IRQn 83 #define BOARD_SW8_IRQ_HANDLER GPIOB_INT0_IRQHandler 84 #define BOARD_SW8_NAME "SW8" 85 86 #define BOARD_SW7_GPIO GPIOB 87 #define BOARD_SW7_GPIO_PIN 13U 88 #define BOARD_SW7_IRQ GPIOB_INT0_IRQn 89 #define BOARD_SW7_IRQ_HANDLER GPIOB_INT0_IRQHandler 90 #define BOARD_SW7_NAME "SW7" 91 92 #define LED_INIT() 93 #define LED_ON() 94 #define LED_TOGGLE() 95 96 #define VDEV0_VRING_BASE (0xAFF00000U) 97 #define VDEV1_VRING_BASE (0xAFF10000U) 98 99 /* MIPI panel. */ 100 /* RST pin. */ 101 #define BOARD_MIPI_RST_GPIO GPIOC 102 #define BOARD_MIPI_RST_PIN 23 103 /* Backlight pin. */ 104 #define BOARD_MIPI_BL_GPIO GPIOA 105 #define BOARD_MIPI_BL_PIN 3 106 /* TE pin. */ 107 #define BOARD_MIPI_TE_GPIO GPIOE 108 #define BOARD_MIPI_TE_PIN 17 109 110 #define BOARD_IS_XIP_FLEXSPI0() \ 111 ((((uint32_t)BOARD_InitDebugConsole >= 0x04000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x0C000000U)) || \ 112 (((uint32_t)BOARD_InitDebugConsole >= 0x14000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x1C000000U))) 113 114 /* PCA6416A (U27) */ 115 #define BOARD_PCA6416A_I2C LPI2C0 116 #define BOARD_PCA6416A_I2C_ADDR (0x20U) 117 #define BOARD_PCA6416A_I2C_CLOCK_FREQ (CLOCK_GetLpi2cClkFreq(0)) 118 119 #define BOARD_PCA6416A_CPU_POWER_MODE0 0U 120 #define BOARD_PCA6416A_CPU_POWER_MODE1 1U 121 #define BOARD_PCA6416A_CPU_POWER_MODE2 2U 122 #define BOARD_PCA6416A_CAN0_STDBY 4U 123 #define BOARD_PCA6416A_TOUCH_RESET 5U 124 #define BOARD_PCA6416A_CAMERA_RESET 7U 125 #define BOARD_PCA6416A_CAMERA_PWDN (8U + 0U) 126 #define BOARD_PCA6416A_MIPI_SWITCH (8U + 1U) 127 #define BOARD_PCA6416A_EPDC_SWITCH (8U + 2U) 128 #define BOARD_PCA6416A_BATT_ADC_ENABLE (8U + 3U) 129 #define BOARD_PCA6416A_CHG_OK (8U + 4U) 130 #define BOARD_PCA6416A_AC_OK (8U + 5U) 131 132 #define TPM0_CH2 (2UL) 133 /* 500 Hz */ 134 #define TPM0_CH2_PWM_FREQ (500UL) 135 #define FULL_DUTY_CYCLE (100UL) 136 137 /* IT6161(U10) */ 138 #define BOARD_IT6161_I2C LPI2C0 139 #define BOARD_IT6161_I2C_ADDR (0x6CU) 140 #define BOARD_IT6161_I2C_CLOCK_FREQ (CLOCK_GetLpi2cClkFreq(0)) 141 142 #define TRDC_MBC_ACCESS_CONTROL_POLICY_ALL_INDEX (0) 143 #define TRDC_MRC_ACCESS_CONTROL_POLICY_ALL_INDEX (0) 144 #define TRDC_M33_DOMAIN_ID (6) 145 #define TRDC_POWERQUAD_DOMAIN_ID (0) 146 #define TRDC_POWERQUAD_MASTER_ID (4) 147 #define TRDC_DMA0_DOMAIN_ID (0) 148 #define TRDC_DMA0_MASTER_ID (2) 149 #define TRDC_MDAC2_INDEX (2) /* T-MADC2 */ 150 #define TRDC_MDAC0_INDEX (0) /* T-MADC0 */ 151 #define TRDC_MRC0_INDEX (0) /* T-MRC0 */ 152 #define TRDC_MRC1_INDEX (1) /* T-MRC1 */ 153 #define TRDC_DCNANO_DOMAIN_ID (3) 154 155 #define TRDC_MBC3_INDEX (3) /* T-MBC3(controll access of DSP Domain) */ 156 #define TRDC_MBC_INDEX_NUM (4) 157 158 /* FSB */ 159 #define FUSE_BANKS (64) 160 #define FUSE_WORDS_PER_BANKS (8) 161 #define FSB_OTP_SHADOW (0x800) 162 #define FSB_BASE_ADDR (0x27010000) 163 164 /* handshake with uboot */ 165 /* Define the timeout ms to do handshake with uboot with mu flag */ 166 #define BOARD_HANDSHAKE_WITH_UBOOT_TIMEOUT_MS (10000U) 167 168 /* 169 * Get a proper sequence to recovery RCR of MU0_MUA from uboot(a35) 170 * at the same time, imply that io and pwm of mipi is ready for uboot 171 */ 172 #define BOARD_MU0_MUB_F0_INIT_SRTM_COMMUNICATION_FLG (0x1UL) 173 /* 1 ms */ 174 #define BOARD_WAIT_MU0_MUB_F0_FLG_FROM_UBOOT_MS (0x1U) 175 176 #define BOARD_FLEXSPI_DLL_LOCK_RETRY (10) 177 178 #define LPI_WAKEUP_EN_SHIFT (8U) 179 180 #define DENALI_CTL_137 (0x224U) 181 #define DENALI_CTL_143 (0x23CU) 182 #define DENALI_CTL_144 (0x240U) 183 #define DENALI_CTL_146 (0x248U) 184 #define DENALI_CTL_147 (0x24CU) 185 #define DENALI_CTL_148 (0x250U) 186 #define DENALI_CTL_153 (0x264U) 187 #define DENALI_CTL_266 (0x428U) 188 189 #define DENALI_PHY_1559 (0x585CU) 190 #define DENALI_PHY_1590 (0x58D8U) 191 192 #define DENALI_PI_52 (0x20D0U) 193 #define DENALI_PI_26 (0x2068U) 194 #define DENALI_PI_33 (0x2084U) 195 #define DENALI_PI_65 (0x2104U) 196 #define DENALI_PI_77 (0x2134U) 197 #define DENALI_PI_134 (0x2218U) 198 #define DENALI_PI_132 (0x2210U) 199 #define DENALI_PI_137 (0x2224U) 200 201 /* Set RTD_SEC_SIM_GPR1 as ddr state flag between AD and RTD, ddr active: 0, ddr in self refresh: 1 */ 202 #define DDR_IN_SELFREFRESH_BASE (0x2802B004u) 203 204 #define W32(addr, val) *((volatile uint32_t *)(addr)) = (val) 205 #define R32(addr) *((volatile uint32_t *)(addr)) 206 207 #define SETBIT32(addr, set) W32(addr, R32(addr) | set) 208 #define CLRBIT32(addr, clear) W32(addr, R32(addr) & ~clear) 209 210 #define LPDDR3_TYPE (0x7U) 211 #define LPDDR4_TYPE (0xBU) 212 #define SAVED_DRAM_DATA_BASE_ADDR_FROM_TFA (0x20055000) 213 #define SAVED_DRAM_TIMING_INFO_SIZE_FROM_TFA (0x58) 214 215 #define LPDDR_CTRL_LP_CMD_MASK (0x7F00U) 216 #define LPAV_LPDDR_CTRL_LP_CMD_SHIFT (8U) 217 #define LPAV_LPDDR_CTRL_LP_CMD(x) \ 218 (((uint32_t)(((uint32_t)(x)) << LPAV_LPDDR_CTRL_LP_CMD_SHIFT)) & LPDDR_CTRL_LP_CMD_MASK) 219 #define CTL_NUM 680 220 #define PI_NUM 298 221 #define PHY_NUM 1654 222 #define PHY_DIFF_NUM 49 223 224 #define LP_AUTO_ENTRY_EN (0x4U) 225 #define LP_AUTO_EXIT_EN (0xFU) 226 #define AUTO_LP_NUM (0x3) 227 228 /* For debugging */ 229 #define BOARD_ENABLE_DUMP_REGS (0) 230 #define LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_NUM (0xF) 231 232 extern struct dram_cfg *dram_timing_cfg; 233 extern uint32_t dram_class; 234 struct dram_cfg 235 { 236 uint32_t ctl_cfg[CTL_NUM]; 237 uint32_t pi_cfg[PI_NUM]; 238 uint32_t phy_full[PHY_NUM]; 239 uint32_t phy_diff[PHY_DIFF_NUM]; 240 uint32_t auto_lp_cfg[AUTO_LP_NUM]; 241 }; 242 243 struct dram_cfg_param 244 { 245 uint32_t reg; 246 uint32_t val; 247 }; 248 249 struct dram_timing_info 250 { 251 /* ddr controller config */ 252 struct dram_cfg_param *ctl_cfg; 253 unsigned int ctl_cfg_num; 254 /* pi config */ 255 struct dram_cfg_param *pi_cfg; 256 unsigned int pi_cfg_num; 257 /* phy freq1 config */ 258 struct dram_cfg_param *phy_f1_cfg; 259 unsigned int phy_f1_cfg_num; 260 /* phy freq2 config */ 261 struct dram_cfg_param *phy_f2_cfg; 262 unsigned int phy_f2_cfg_num; 263 struct dram_cfg_param *auto_lp_cfg; 264 unsigned int auto_lp_cfg_num; 265 /* initialized drate table */ 266 unsigned int fsp_table[3]; 267 }; 268 269 /* boot type */ 270 typedef enum 271 { 272 SINGLE_BOOT_TYPE, 273 DUAL_BOOT_TYPE, 274 LOW_POWER_BOOT_TYPE, 275 } boot_type_e; 276 277 typedef enum 278 { 279 IP_EPDC = 1, 280 IP_GPU = 2, 281 IP_MPU1 = 3, /* MPU1 - Cortex-A35 core 1 */ 282 } ip_type_e; 283 #if defined(__cplusplus) 284 extern "C" { 285 #endif /* __cplusplus */ 286 287 /******************************************************************************* 288 * API 289 ******************************************************************************/ 290 291 void BOARD_InitDebugConsole(void); 292 bool BOARD_IsLowPowerBootType(void); 293 bool BOARD_IsSingleBootType(void); 294 bool BOARD_IsLPAVOwnedByRTD(void); 295 const char *BOARD_GetBootTypeName(void); 296 297 /* TRDC */ 298 bool BOARD_GetReleaseFlagOfTrdc(void); 299 void BOARD_SetReleaseFlagOfTrdc(bool flag); 300 void BOARD_ReleaseTRDC(void); 301 void BOARD_SetTrdcGlobalConfig(void); 302 /* Setup TRDC configuration before executing rom code of A35(A35 rom will access FSB, S400 MUAP A-Side, SIM0-S with 303 * secure state, so m33 help a35 to configure TRDC) */ 304 void BOARD_SetTrdcAfterApdReset(void); 305 306 /* 307 * return the handshake result(fail or success): 308 * true: succeeded to handshake with uboot; false: failed to handshake with uboot 309 */ 310 bool BOARD_HandshakeWithUboot(void); 311 312 void BOARD_ConfigMPU(void); 313 status_t BOARD_InitPsRam(void); 314 void BOARD_FlexspiClockSafeConfig(void); 315 AT_QUICKACCESS_SECTION_CODE( 316 void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint32_t src, uint8_t divValue, uint8_t fracValue)); 317 AT_QUICKACCESS_SECTION_CODE(void BOARD_DeinitXip(FLEXSPI_Type *base)); 318 AT_QUICKACCESS_SECTION_CODE(void BOARD_InitXip(FLEXSPI_Type *base)); 319 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED 320 void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz); 321 status_t BOARD_LPI2C_Send(LPI2C_Type *base, 322 uint8_t deviceAddress, 323 uint32_t subAddress, 324 uint8_t subaddressSize, 325 uint8_t *txBuff, 326 uint16_t txBuffSize, 327 uint32_t flags); 328 status_t BOARD_LPI2C_Receive(LPI2C_Type *base, 329 uint8_t deviceAddress, 330 uint32_t subAddress, 331 uint8_t subaddressSize, 332 uint8_t *rxBuff, 333 uint16_t rxBuffSize, 334 uint32_t flags); 335 void BOARD_Accel_I2C_Init(void); 336 status_t BOARD_Accel_I2C_Send( 337 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff, uint32_t flags); 338 status_t BOARD_Accel_I2C_Receive(uint8_t deviceAddress, 339 uint32_t subAddress, 340 uint8_t subaddressSize, 341 uint8_t *rxBuff, 342 uint8_t rxBuffSize, 343 uint32_t flags); 344 void BOARD_Codec_I2C_Init(void); 345 status_t BOARD_Codec_I2C_Send(uint8_t deviceAddress, 346 uint32_t subAddress, 347 uint8_t subAddressSize, 348 const uint8_t *txBuff, 349 uint8_t txBuffSize, 350 uint32_t flags); 351 status_t BOARD_Codec_I2C_Receive(uint8_t deviceAddress, 352 uint32_t subAddress, 353 uint8_t subAddressSize, 354 uint8_t *rxBuff, 355 uint8_t rxBuffSize, 356 uint32_t flags); 357 358 void BOARD_Display_I2C_Init(void); 359 status_t BOARD_Display_I2C_Send( 360 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize); 361 status_t BOARD_Display_I2C_Receive( 362 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize); 363 364 #if defined(BOARD_USE_PCA6416A) && BOARD_USE_PCA6416A 365 void BOARD_PCA6416A_I2C_Init(void); 366 status_t BOARD_PCA6416A_I2C_Send(uint8_t deviceAddress, 367 uint32_t subAddress, 368 uint8_t subAddressSize, 369 const uint8_t *txBuff, 370 uint8_t txBuffSize, 371 uint32_t flags); 372 status_t BOARD_PCA6416A_I2C_Receive(uint8_t deviceAddress, 373 uint32_t subAddress, 374 uint8_t subAddressSize, 375 uint8_t *rxBuff, 376 uint8_t rxBuffSize, 377 uint32_t flags); 378 379 /* PCA6416A U27. */ 380 extern pca6416a_handle_t g_pca6416aHandle; 381 382 void BOARD_InitPCA6416A(pca6416a_handle_t *handle); 383 384 /* MIPI DSI */ 385 void BOARD_InitMipiDsiPins(void); 386 void BOARD_EnableMipiDsiBacklight(void); 387 #endif /* BOARD_USE_PCA6416A */ 388 389 #endif /* SDK_I2C_BASED_COMPONENT_USED */ 390 391 /* LPAV DDR */ 392 void BOARD_LpavInit(); 393 void BOARD_DdrSave(void); 394 void BOARD_LpavSave(void); 395 void BOARD_DramEnterRetention(void); 396 void BOARD_DramExitRetention(uint32_t dram_class, struct dram_cfg *dram_timing_cfg); 397 void BOARD_DDREnterSelfRefresh(); 398 void BOARD_DDRExitSelfRefresh(); 399 400 /* Use for debugging */ 401 void BOARD_DumpRegs(uint32_t start_reg_addr, uint32_t end_reg_addr); 402 void BOARD_DumpRTDRegs(void); 403 bool BOARD_IsIpDisabled(ip_type_e type); 404 uint32_t BOARD_GetSocVariantType(void); 405 #if defined(__cplusplus) 406 } 407 #endif /* __cplusplus */ 408 409 #endif /* _BOARD_H_ */ 410
