1 /* 2 * Trace Recorder for Tracealyzer v4.6.6 3 * Copyright 2021 Percepio AB 4 * www.percepio.com 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * 8 * Some common defines for the trace recorder. 9 */ 10 11 #ifndef TRC_DEFINES_H 12 #define TRC_DEFINES_H 13 14 #define TRC_SUCCESS (0) 15 #define TRC_FAIL (1) 16 17 #define TRC_FREE_RUNNING_32BIT_INCR 1 18 #define TRC_FREE_RUNNING_32BIT_DECR 2 19 #define TRC_OS_TIMER_INCR 3 20 #define TRC_OS_TIMER_DECR 4 21 #define TRC_CUSTOM_TIMER_INCR 5 22 #define TRC_CUSTOM_TIMER_DECR 6 23 24 #define TRC_STATE_IN_STARTUP 0 25 #define TRC_STATE_IN_TASKSWITCH 1 26 #define TRC_STATE_IN_APPLICATION 2 27 28 /* Start options for vTraceEnable. */ 29 #define TRC_START_FROM_HOST 0 30 #define TRC_START 1 31 #define TRC_START_AWAIT_HOST 2 32 33 #define TRC_ACKNOWLEDGED (0xABC99123) 34 35 /* Command codes for TzCtrl task */ 36 #define CMD_SET_ACTIVE 1 /* Start (param1 = 1) or Stop (param1 = 0) */ 37 38 /* The final command code, used to validate commands. */ 39 #define CMD_LAST_COMMAND 1 40 41 #define TRC_RECORDER_MODE_SNAPSHOT 0 42 #define TRC_RECORDER_MODE_STREAMING 1 43 44 #define TRC_SNAPSHOT_MODE_RING_BUFFER (0x01) 45 #define TRC_SNAPSHOT_MODE_STOP_WHEN_FULL (0x02) 46 47 #define TRC_RECORDER_BUFFER_ALLOCATION_STATIC (0x00) 48 #define TRC_RECORDER_BUFFER_ALLOCATION_DYNAMIC (0x01) 49 #define TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM (0x02) 50 51 #define TRC_OPTION_BIT_SHIFT_IRQ_ORDER 0 52 #define TRC_OPTION_BIT_SHIFT_BASE_SIZE 8 53 54 /******************************************************************************/ 55 /*** ERROR AND WARNING CODES (check using xTraceErrorGetLast) *****************/ 56 /******************************************************************************/ 57 58 #define TRC_ERROR_NONE 0x00 59 60 #define TRC_ERROR_ASSERT 0x01 61 #define TRC_ERROR_EVENT_CODE_TOO_LARGE 0x02 62 #define TRC_ERROR_ISR_NESTING_OVERFLOW 0x03 63 #define TRC_ERROR_DWT_NOT_SUPPORTED 0x04 64 #define TRC_ERROR_DWT_CYCCNT_NOT_SUPPORTED 0x05 65 #define TRC_ERROR_TZCTRLTASK_NOT_CREATED 0x06 66 #define TRC_ERROR_STREAM_PORT_WRITE 0x07 67 68 #define TRC_WARNING_ENTRY_TABLE_SLOTS 0x08 69 #define TRC_WARNING_ENTRY_SYMBOL_MAX_LENGTH 0x09 70 #define TRC_WARNING_EVENT_SIZE_TRUNCATED 0x0A 71 #define TRC_WARNING_STREAM_PORT_READ 0x0B 72 #define TRC_WARNING_STREAM_PORT_WRITE 0x0C 73 #define TRC_WARNING_STREAM_PORT_INITIAL_BLOCKING 0x0D 74 #define TRC_WARNING_STACKMON_NO_SLOTS 0x0E 75 76 /* Entry Option definitions */ 77 #define TRC_ENTRY_OPTION_EXCLUDED 0x00000001 78 #define TRC_ENTRY_OPTION_HEAP 0x80000000 79 #define TRC_ENTRY_OPTION_EXTENSION 0x40000000 80 #define TRC_ENTRY_OPTION_STATE_MACHINE 0x20000000 81 #define TRC_ENTRY_OPTION_STATE_MACHINE_STATE 0x10000000 82 #define TRC_ENTRY_OPTION_INTERVAL_CHANNEL 0x08000000 83 #define TRC_ENTRY_OPTION_COUNTER 0x04000000 84 #define TRC_ENTRY_OPTION_INTERVAL_CHANNEL_SET 0x02000000 85 86 #define TRC_RECORDER_COMPONENT_CORE 0x00000001 87 #define TRC_RECORDER_COMPONENT_ASSERT 0x00000002 88 #define TRC_RECORDER_COMPONENT_BLOB 0x00000004 89 #define TRC_RECORDER_COMPONENT_DIAGNOSTICS 0x00000008 90 #define TRC_RECORDER_COMPONENT_ENTRY 0x00000010 91 #define TRC_RECORDER_COMPONENT_ERROR 0x00000020 92 #define TRC_RECORDER_COMPONENT_EVENT 0x00000040 93 #define TRC_RECORDER_COMPONENT_EVENT_BUFFER 0x00000080 94 #define TRC_RECORDER_COMPONENT_EXTENSION 0x00000100 95 #define TRC_RECORDER_COMPONENT_HEAP 0x00000200 96 #define TRC_RECORDER_COMPONENT_INTERNAL_EVENT_BUFFER 0x00000400 97 #define TRC_RECORDER_COMPONENT_INTERVAL 0x00000800 98 #define TRC_RECORDER_COMPONENT_ISR 0x00001000 99 #define TRC_RECORDER_COMPONENT_MULTI_CORE_EVENT_BUFFER 0x00002000 100 #define TRC_RECORDER_COMPONENT_OBJECT 0x00004000 101 #define TRC_RECORDER_COMPONENT_PRINT 0x00008000 102 #define TRC_RECORDER_COMPONENT_STACK_MONITOR 0x00010000 103 #define TRC_RECORDER_COMPONENT_STATE_MACHINE 0x00020000 104 #define TRC_RECORDER_COMPONENT_STATIC_BUFFER 0x00040000 105 #define TRC_RECORDER_COMPONENT_STRING 0x00080000 106 #define TRC_RECORDER_COMPONENT_TASK 0x00100000 107 #define TRC_RECORDER_COMPONENT_TIMESTAMP 0x00200000 108 #define TRC_RECORDER_COMPONENT_COUNTER 0x00400000 109 110 /* Filter Groups */ 111 #define FilterGroup0 (uint16_t)0x0001 112 #define FilterGroup1 (uint16_t)0x0002 113 #define FilterGroup2 (uint16_t)0x0004 114 #define FilterGroup3 (uint16_t)0x0008 115 #define FilterGroup4 (uint16_t)0x0010 116 #define FilterGroup5 (uint16_t)0x0020 117 #define FilterGroup6 (uint16_t)0x0040 118 #define FilterGroup7 (uint16_t)0x0080 119 #define FilterGroup8 (uint16_t)0x0100 120 #define FilterGroup9 (uint16_t)0x0200 121 #define FilterGroup10 (uint16_t)0x0400 122 #define FilterGroup11 (uint16_t)0x0800 123 #define FilterGroup12 (uint16_t)0x1000 124 #define FilterGroup13 (uint16_t)0x2000 125 #define FilterGroup14 (uint16_t)0x4000 126 #define FilterGroup15 (uint16_t)0x8000 127 128 /****************************************************************************** 129 * Supported ports 130 * 131 * TRC_HARDWARE_PORT_HWIndependent 132 * A hardware independent fallback option for event timestamping. Provides low 133 * resolution timestamps based on the OS tick. 134 * This may be used on the Win32 port, but may also be used on embedded hardware 135 * platforms. All time durations will be truncated to the OS tick frequency, 136 * typically 1 KHz. This means that a task or ISR that executes in less than 137 * 1 ms get an execution time of zero. 138 * 139 * TRC_HARDWARE_PORT_APPLICATION_DEFINED 140 * Allows for defining the port macros in other source code files. 141 * 142 * TRC_HARDWARE_PORT_Win32 143 * "Accurate" timestamping based on the Windows performance counter for Win32 144 * builds. Note that this gives the host machine time, not the kernel time. 145 * 146 * Hardware specific ports 147 * To get accurate timestamping, a hardware timer is necessary. Below are the 148 * available ports. Some of these are "unofficial", meaning that 149 * they have not yet been verified by Percepio but have been contributed by 150 * external developers. They should work, otherwise let us know by emailing 151 * support@percepio.com. Some work on any OS platform, while other are specific 152 * to a certain operating system. 153 *****************************************************************************/ 154 155 /****** Port Name ************************************* Code ** Official ** OS Platform *********/ 156 #define TRC_HARDWARE_PORT_APPLICATION_DEFINED 98 /* - - */ 157 #define TRC_HARDWARE_PORT_NOT_SET 99 /* - - */ 158 #define TRC_HARDWARE_PORT_HWIndependent 0 /* Yes Any */ 159 #define TRC_HARDWARE_PORT_Win32 1 /* Yes FreeRTOS on Win32 */ 160 #define TRC_HARDWARE_PORT_Atmel_AT91SAM7 2 /* No Any */ 161 #define TRC_HARDWARE_PORT_Atmel_UC3A0 3 /* No Any */ 162 #define TRC_HARDWARE_PORT_ARM_Cortex_M 4 /* Yes Any */ 163 #define TRC_HARDWARE_PORT_Renesas_RX600 6 /* Yes Any */ 164 #define TRC_HARDWARE_PORT_MICROCHIP_PIC24_PIC32 7 /* Yes Any */ 165 #define TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48 8 /* Yes Any */ 166 #define TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_MSP430 9 /* No Any */ 167 #define TRC_HARDWARE_PORT_XILINX_PPC405 11 /* No FreeRTOS */ 168 #define TRC_HARDWARE_PORT_XILINX_PPC440 12 /* No FreeRTOS */ 169 #define TRC_HARDWARE_PORT_XILINX_MICROBLAZE 13 /* No Any */ 170 #define TRC_HARDWARE_PORT_XILINX_ZyncUltraScaleR5 14 /* No FreeRTOS */ 171 #define TRC_HARDWARE_PORT_NXP_LPC210X 15 /* No Any */ 172 #define TRC_HARDWARE_PORT_ARM_CORTEX_A9 16 /* Yes Any */ 173 #define TRC_HARDWARE_PORT_POWERPC_Z4 17 /* No FreeRTOS */ 174 #define TRC_HARDWARE_PORT_Altera_NiosII 18 /* Yes Any (Tested with FreeRTOS) */ 175 #define TRC_HARDWARE_PORT_ZEPHYR 19 /* Yes Zephyr */ 176 #define TRC_HARDWARE_PORT_XTensa_LX6 20 /* Yes ESP-IDF FreeRTOS */ 177 #define TRC_HARDWARE_PORT_XTensa_LX7 21 /* Yes ESP-IDF FreeRTOS */ 178 #define TRC_HARDWARE_PORT_Win64 22 /* Yes FreeRTOS on Win64 */ 179 #define TRC_HARDWARE_PORT_XMOS_XCOREAI 23 /* Yes FreeRTOS SMP */ 180 #define TRC_HARDWARE_PORT_RISCV_RV32I 24 /* Yes FreeRTOS */ 181 #define TRC_HARDWARE_PORT_CYCLONE_V_HPS 25 /* Yes FreeRTOS */ 182 183 #endif /* TRC_PORTDEFINES_H */ 184
