1 /* 2 * Trace Recorder for Tracealyzer v4.8.1 3 * Copyright 2023 Percepio AB 4 * www.percepio.com 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * 8 * The hardware abstraction layer for the trace recorder. 9 */ 10 11 #ifndef TRC_HARDWARE_PORT_H 12 #define TRC_HARDWARE_PORT_H 13 14 #include <trcDefines.h> 15 16 /* 17 * @brief 18 * This macro must be used as name for the variable in the critical section allocation. 19 * Example: #define TRACE_ALLOC_CRITICAL_SECION uint32_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 20 */ 21 #define TRACE_ALLOC_CRITICAL_SECTION_NAME xTraceCriticalSectionStatus 22 23 #if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET) 24 #error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h" 25 #endif 26 27 /******************************************************************************* 28 * TRC_IRQ_PRIORITY_ORDER 29 * 30 * Macro which should be defined as an integer of 0 or 1. 31 * 32 * This should be 0 if lower IRQ priority values implies higher priority 33 * levels, such as on ARM Cortex M. If the opposite scheme is used, i.e., 34 * if higher IRQ priority values means higher priority, this should be 1. 35 * 36 * This setting is not critical. It is used only to sort and colorize the 37 * interrupts in priority order, in case you record interrupts using 38 * the vTraceStoreISRBegin and vTraceStoreISREnd routines. 39 * 40 ****************************************************************************** 41 * 42 * HWTC Macros 43 * 44 * These macros provides a hardware isolation layer representing the 45 * hardware timer/counter used for the event timestamping. 46 * 47 * TRC_HWTC_COUNT: How to read the current value of the timer/counter. 48 * 49 * TRC_HWTC_TYPE: Tells the type of timer/counter used for TRC_HWTC_COUNT: 50 * 51 * - TRC_FREE_RUNNING_32BIT_INCR: 52 * Free-running 32-bit timer/counter, counting upwards from 0. 53 * 54 * - TRC_FREE_RUNNING_32BIT_DECR 55 * Free-running 32-bit timer/counter, counting downwards from 0xFFFFFFFF. 56 * 57 * - TRC_OS_TIMER_INCR 58 * Periodic timer that drives the OS tick interrupt, counting upwards 59 * from 0 until (TRC_HWTC_PERIOD-1). 60 * 61 * - TRC_OS_TIMER_DECR 62 * Periodic timer that drives the OS tick interrupt, counting downwards 63 * from TRC_HWTC_PERIOD-1 until 0. 64 * 65 * - TRC_CUSTOM_TIMER_INCR 66 * A custom timer or counter independent of the OS tick, counting 67 * downwards from TRC_HWTC_PERIOD-1 until 0. (Currently only supported 68 * in streaming mode). 69 * 70 * - TRC_CUSTOM_TIMER_DECR 71 * A custom timer independent of the OS tick, counting downwards 72 * from TRC_HWTC_PERIOD-1 until 0. (Currently only supported 73 * in streaming mode). 74 * 75 * TRC_HWTC_PERIOD: The number of HWTC_COUNT ticks until the timer wraps 76 * around. If using TRC_FREE_RUNNING_32BIT_INCR/DECR, this should be 0. 77 * 78 * TRC_HWTC_FREQ_HZ: The clock rate of the TRC_HWTC_COUNT counter in Hz. If using 79 * TRC_OS_TIMER_INCR/DECR, this is should be TRC_HWTC_PERIOD * TRC_TICK_RATE_HZ. 80 * If using a free-running timer, this is often TRACE_CPU_CLOCK_HZ (if running at 81 * the core clock rate). If using TRC_CUSTOM_TIMER_INCR/DECR, this should match 82 * the clock rate of your custom timer (i.e., TRC_HWTC_COUNT). If the default value 83 * of TRC_HWTC_FREQ_HZ is incorrect for your setup, you can override it by calling 84 * vTraceSetFrequency before calling vTraceEnable. 85 * 86 * TRC_HWTC_DIVISOR (used in snapshot mode only): 87 * In snapshot mode, the timestamp resolution is TRC_HWTC_FREQ_HZ/TRC_HWTC_DIVISOR. 88 * If the timer frequency is very high (hundreds of MHz), we recommend increasing 89 * the TRC_HWTC_DIVISOR prescaler, to reduce the bandwidth needed to store 90 * timestamps. This since extra "XTS" events are inserted if the time since the 91 * previous event exceeds a certain limit (255 or 65535 depending on event type). 92 * It is advised to keep the time between most events below 65535 native ticks 93 * (after division by TRC_HWTC_DIVISOR) to avoid frequent XTS events. 94 ******************************************************************************/ 95 96 #if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET) 97 #error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h" 98 #endif 99 100 #if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Win32) 101 /* This can be used as a template for any free-running 32-bit counter */ 102 void vTraceTimerReset(void); 103 uint32_t uiTraceTimerGetFrequency(void); 104 uint32_t uiTraceTimerGetValue(void); 105 106 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR 107 #define TRC_HWTC_COUNT ((TraceUnsignedBaseType_t)uiTraceTimerGetValue()) 108 #define TRC_HWTC_PERIOD 0 109 #define TRC_HWTC_DIVISOR 1 110 #define TRC_HWTC_FREQ_HZ ((TraceUnsignedBaseType_t)uiTraceTimerGetFrequency()) 111 112 #define TRC_IRQ_PRIORITY_ORDER 1 113 114 #define TRC_PORT_SPECIFIC_INIT() vTraceTimerReset() 115 116 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Win64) 117 /* This can be used as a template for any free-running 32-bit counter */ 118 void vTraceTimerReset(void); 119 uint32_t uiTraceTimerGetFrequency(void); 120 uint32_t uiTraceTimerGetValue(void); 121 122 #define TRC_BASE_TYPE int64_t 123 124 #define TRC_UNSIGNED_BASE_TYPE uint64_t 125 126 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR 127 #define TRC_HWTC_COUNT ((TraceUnsignedBaseType_t)uiTraceTimerGetValue()) 128 #define TRC_HWTC_PERIOD 0 129 #define TRC_HWTC_DIVISOR 1 130 #define TRC_HWTC_FREQ_HZ ((TraceUnsignedBaseType_t)uiTraceTimerGetFrequency()) 131 132 #define TRC_IRQ_PRIORITY_ORDER 1 133 134 #define TRC_PORT_SPECIFIC_INIT() vTraceTimerReset() 135 136 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_HWIndependent) 137 /* Timestamping by OS tick only (typically 1 ms resolution) */ 138 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR 139 #define TRC_HWTC_COUNT 0 140 #define TRC_HWTC_PERIOD 1 141 #define TRC_HWTC_DIVISOR 1 142 #define TRC_HWTC_FREQ_HZ TRC_TICK_RATE_HZ 143 144 /* Set the meaning of IRQ priorities in ISR tracing - see above */ 145 #define TRC_IRQ_PRIORITY_ORDER NOT_SET 146 147 #elif ((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M_NRF_SD)) 148 149 #ifndef __CORTEX_M 150 #error "Can't find the CMSIS API. Please include your processor's header file in trcConfig.h" 151 #endif 152 153 #if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M) 154 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 155 #define TRACE_ENTER_CRITICAL_SECTION() {TRACE_ALLOC_CRITICAL_SECTION_NAME = __get_PRIMASK(); __set_PRIMASK(1);} /* PRIMASK disables ALL interrupts - allows for tracing in any ISR */ 156 #define TRACE_EXIT_CRITICAL_SECTION() {__set_PRIMASK(TRACE_ALLOC_CRITICAL_SECTION_NAME);} 157 #else 158 #include "nrf_nvic.h" 159 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 160 #define TRACE_ENTER_CRITICAL_SECTION() {(void) sd_nvic_critical_region_enter((uint8_t*)&TRACE_ALLOC_CRITICAL_SECTION_NAME);} 161 #define TRACE_EXIT_CRITICAL_SECTION() {(void) sd_nvic_critical_region_exit((uint8_t)TRACE_ALLOC_CRITICAL_SECTION_NAME);} 162 #endif 163 164 /************************************************************************** 165 * For Cortex-M3, M4 and M7, the DWT cycle counter is used for timestamping. 166 * For Cortex-M0 and M0+, the SysTick timer is used since DWT is not 167 * available. Systick timestamping can also be forced on Cortex-M3, M4 and 168 * M7 by defining the preprocessor directive TRC_CFG_ARM_CM_USE_SYSTICK, 169 * either directly below or in trcConfig.h. 170 * 171 * #define TRC_CFG_ARM_CM_USE_SYSTICK 172 **************************************************************************/ 173 174 #if ((__CORTEX_M >= 0x03) && (! defined TRC_CFG_ARM_CM_USE_SYSTICK)) 175 176 void xTraceHardwarePortInitCortexM(void); 177 178 #define TRC_REG_DEMCR (*(volatile uint32_t*)0xE000EDFC) 179 #define TRC_REG_DWT_CTRL (*(volatile uint32_t*)0xE0001000) 180 #define TRC_REG_DWT_CYCCNT (*(volatile uint32_t*)0xE0001004) 181 #define TRC_REG_DWT_EXCCNT (*(volatile uint32_t*)0xE000100C) 182 183 #define TRC_REG_ITM_LOCKACCESS (*(volatile uint32_t*)0xE0001FB0) 184 #define TRC_ITM_LOCKACCESS_UNLOCK (0xC5ACCE55) 185 186 /* Bit mask for TRCENA bit in DEMCR - Global enable for DWT and ITM */ 187 #define TRC_DEMCR_TRCENA (1 << 24) 188 189 /* Bit mask for NOPRFCNT bit in DWT_CTRL. If 1, DWT_EXCCNT is not supported */ 190 #define TRC_DWT_CTRL_NOPRFCNT (1 << 24) 191 192 /* Bit mask for NOCYCCNT bit in DWT_CTRL. If 1, DWT_CYCCNT is not supported */ 193 #define TRC_DWT_CTRL_NOCYCCNT (1 << 25) 194 195 /* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_EXCCNT */ 196 #define TRC_DWT_CTRL_EXCEVTENA (1 << 18) 197 198 /* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_CYCCNT */ 199 #define TRC_DWT_CTRL_CYCCNTENA (1) 200 201 #define TRC_PORT_SPECIFIC_INIT() xTraceHardwarePortInitCortexM() 202 203 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR 204 #define TRC_HWTC_COUNT TRC_REG_DWT_CYCCNT 205 #define TRC_HWTC_PERIOD 0 206 #define TRC_HWTC_DIVISOR 4 207 #define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ 208 #define TRC_IRQ_PRIORITY_ORDER 0 209 210 #else 211 /* Uses the lower bits of the 64-bit free running timer in the RP2040. SysTick can not be used since it is different for both cores. */ 212 #ifdef _CMSIS_RP2040_H_ 213 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR 214 #define TRC_HWTC_COUNT (*((volatile uint32_t*)0x4005400c)) 215 #define TRC_HWTC_PERIOD 0 216 #define TRC_HWTC_DIVISOR 1 217 #define TRC_HWTC_FREQ_HZ 1000000 218 #define TRC_IRQ_PRIORITY_ORDER 0 219 #else 220 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR 221 #define TRC_HWTC_COUNT (*((volatile uint32_t*)0xE000E018)) 222 #define TRC_HWTC_PERIOD ((*((volatile uint32_t*)0xE000E014)) + 1) 223 #define TRC_HWTC_DIVISOR 4 224 #define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ 225 #define TRC_IRQ_PRIORITY_ORDER 0 226 #endif 227 228 #endif 229 230 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Renesas_RX600) 231 #define TRACE_ALLOC_CRITICAL_SECTION() TraceBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 232 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = TRC_KERNEL_PORT_SET_INTERRUPT_MASK(); } 233 #define TRACE_EXIT_CRITICAL_SECTION() { TRC_KERNEL_PORT_CLEAR_INTERRUPT_MASK(TRACE_ALLOC_CRITICAL_SECTION_NAME); } 234 235 #include <iodefine.h> 236 237 #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) 238 239 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR 240 #define TRC_HWTC_COUNT (CMT0.CMCNT) 241 242 #elif (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) 243 244 /* Decreasing counters better for Tickless Idle? */ 245 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR 246 #define TRC_HWTC_COUNT (CMT0.CMCOR - CMT0.CMCNT) 247 248 #endif 249 250 #define TRC_HWTC_PERIOD (CMT0.CMCOR + 1) 251 #define TRC_HWTC_DIVISOR 1 252 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD) 253 #define TRC_IRQ_PRIORITY_ORDER 1 254 255 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_MICROCHIP_PIC24_PIC32) 256 257 #define TRACE_ALLOC_CRITICAL_SECTION() TraceBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 258 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = TRC_KERNEL_PORT_SET_INTERRUPT_MASK(); } 259 #define TRACE_EXIT_CRITICAL_SECTION() { TRC_KERNEL_PORT_CLEAR_INTERRUPT_MASK(TRACE_ALLOC_CRITICAL_SECTION_NAME); } 260 261 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR 262 #define TRC_HWTC_COUNT (TMR1) 263 #define TRC_HWTC_PERIOD (PR1 + 1) 264 #define TRC_HWTC_DIVISOR 1 265 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD) 266 #define TRC_IRQ_PRIORITY_ORDER 1 267 268 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48) 269 270 #define TRC_RTIFRC0 *((uint32_t *)0xFFFFFC10) 271 #define TRC_RTICOMP0 *((uint32_t *)0xFFFFFC50) 272 #define TRC_RTIUDCP0 *((uint32_t *)0xFFFFFC54) 273 274 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR 275 #define TRC_HWTC_COUNT (TRC_RTIFRC0 - (TRC_RTICOMP0 - TRC_RTIUDCP0)) 276 #define TRC_HWTC_PERIOD (TRC_RTIUDCP0) 277 #define TRC_HWTC_DIVISOR 1 278 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD) 279 #define TRC_IRQ_PRIORITY_ORDER 0 280 281 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_AT91SAM7) 282 283 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */ 284 285 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR 286 #define TRC_HWTC_COUNT ((uint32_t)(AT91C_BASE_PITC->PITC_PIIR & 0xFFFFF)) 287 #define TRC_HWTC_PERIOD ((uint32_t)(AT91C_BASE_PITC->PITC_PIMR + 1)) 288 #define TRC_HWTC_DIVISOR 1 289 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD) 290 #define TRC_IRQ_PRIORITY_ORDER 1 291 292 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_UC3A0) 293 294 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO*/ 295 296 /* For Atmel AVR32 (AT32UC3A) */ 297 298 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR 299 #define TRC_HWTC_COUNT ((uint32_t)sysreg_read(AVR32_COUNT)) 300 #define TRC_HWTC_PERIOD ((uint32_t)(sysreg_read(AVR32_COMPARE) + 1)) 301 #define TRC_HWTC_DIVISOR 1 302 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD) 303 #define TRC_IRQ_PRIORITY_ORDER 1 304 305 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NXP_LPC210X) 306 307 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */ 308 309 /* Tested with LPC2106, but should work with most LPC21XX chips. */ 310 311 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR 312 #define TRC_HWTC_COUNT *((uint32_t *)0xE0004008 ) 313 #define TRC_HWTC_PERIOD *((uint32_t *)0xE0004018 ) 314 #define TRC_HWTC_DIVISOR 1 315 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD) 316 #define TRC_IRQ_PRIORITY_ORDER 0 317 318 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_MSP430) 319 320 /* UNOFFICIAL PORT - NOT YET VERIFIED */ 321 322 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR 323 #define TRC_HWTC_COUNT (TA0R) 324 #define TRC_HWTC_PERIOD (((uint16_t)TACCR0)+1) 325 #define TRC_HWTC_DIVISOR 1 326 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD) 327 #define TRC_IRQ_PRIORITY_ORDER 1 328 329 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC405) 330 331 /* UNOFFICIAL PORT - NOT YET VERIFIED */ 332 333 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR 334 #define TRC_HWTC_COUNT mfspr(0x3db) 335 #define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRC_TICK_RATE_HZ) 336 #define TRC_HWTC_DIVISOR 1 337 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD) 338 #define TRC_IRQ_PRIORITY_ORDER 0 339 340 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC440) 341 342 /* UNOFFICIAL PORT */ 343 344 /* This should work with most PowerPC chips */ 345 346 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR 347 #define TRC_HWTC_COUNT mfspr(0x016) 348 #define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRC_TICK_RATE_HZ) 349 #define TRC_HWTC_DIVISOR 1 350 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD) 351 #define TRC_IRQ_PRIORITY_ORDER 0 352 353 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_MICROBLAZE) 354 355 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */ 356 357 /* This should work with most Microblaze configurations. 358 * It uses the AXI Timer 0 - the tick interrupt source. 359 * If an AXI Timer 0 peripheral is available on your hardware platform, no modifications are required. 360 */ 361 #include <xtmrctr_l.h> 362 363 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR 364 #define TRC_HWTC_COUNT XTmrCtr_GetTimerCounterReg( XPAR_TMRCTR_0_BASEADDR, 0 ) 365 #define TRC_HWTC_PERIOD (XTmrCtr_GetLoadReg( XPAR_TMRCTR_0_BASEADDR, 0) + 1) 366 #define TRC_HWTC_DIVISOR 16 367 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD) 368 #define TRC_IRQ_PRIORITY_ORDER 0 369 370 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_ZyncUltraScaleR5) 371 372 extern TraceUnsignedBaseType_t cortex_a9_r5_enter_critical(void); 373 extern void cortex_a9_r5_exit_critical(TraceUnsignedBaseType_t irq_already_masked_at_enter); 374 375 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 376 377 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = cortex_a9_r5_enter_critical(); } 378 379 #define TRACE_EXIT_CRITICAL_SECTION() { cortex_a9_r5_exit_critical(TRACE_ALLOC_CRITICAL_SECTION_NAME); } 380 381 #include <xttcps_hw.h> 382 383 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR 384 #define TRC_HWTC_COUNT (*(volatile uint32_t *)(configTIMER_BASEADDR + XTTCPS_COUNT_VALUE_OFFSET)) 385 #define TRC_HWTC_PERIOD (*(volatile uint32_t *)(configTIMER_BASEADDR + XTTCPS_INTERVAL_VAL_OFFSET)) 386 #define TRC_HWTC_DIVISOR 16 387 #define TRC_HWTC_FREQ_HZ (TRC_HWTC_PERIOD * TRC_TICK_RATE_HZ) 388 #define TRC_IRQ_PRIORITY_ORDER 0 389 390 #ifdef __GNUC__ 391 prvGetCPSR(void)392 static inline uint32_t prvGetCPSR(void) 393 { 394 unsigned long ret; 395 /* GCC-style assembly for getting the CPSR/APSR register, where the system execution mode is found. */ 396 asm volatile (" mrs %0, cpsr" : "=r" (ret) : /* no inputs */ ); 397 return ret; 398 } 399 #else 400 #error "Only GCC Supported!" 401 #endif 402 403 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Altera_NiosII) 404 405 /* OFFICIAL PORT */ 406 407 #include <system.h> 408 #include <altera_avalon_timer_regs.h> 409 #include <sys/alt_irq.h> 410 411 #define TRACE_ALLOC_CRITICAL_SECTION() alt_irq_context TRACE_ALLOC_CRITICAL_SECTION_NAME; 412 #define TRACE_ENTER_CRITICAL_SECTION(){TRACE_ALLOC_CRITICAL_SECTION_NAME = alt_irq_disable_all();} 413 #define TRACE_EXIT_CRITICAL_SECTION() {alt_irq_enable_all(TRACE_ALLOC_CRITICAL_SECTION_NAME);} 414 415 #define NOT_SET 1 416 417 /* The base address for the sustem timer set. 418 * The name user for the system timer can be found in the BSP editor. 419 * If the name of the timer is sys_tmr SYSTEM_TIMER_BASE should be set to SYS_TMR_BASE. 420 */ 421 #define SYSTEM_TIMER_BASE NOT_SET 422 423 #if (SYSTEM_TIMER == NOT_SET) 424 #error "Set SYSTEM_TIMER_BASE to the timer base used for system ticks." 425 #endif 426 altera_nios2_GetTimerSnapReg(void)427 static inline uint32_t altera_nios2_GetTimerSnapReg(void) 428 { 429 /* A processor can read the current counter value by first writing to either snapl or snaph to request a coherent snapshot of the counter, 430 * and then reading snapl and snaph for the full 32-bit value. 431 */ 432 IOWR_ALTERA_AVALON_TIMER_SNAPL(SYSTEM_TIMER_BASE, 0); 433 return (IORD_ALTERA_AVALON_TIMER_SNAPH(SYSTEM_TIMER_BASE) << 16) | IORD_ALTERA_AVALON_TIMER_SNAPL(SYSTEM_TIMER_BASE); 434 } 435 436 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR 437 #define TRC_HWTC_COUNT altera_nios2_GetTimerSnapReg() 438 #define TRC_HWTC_PERIOD (configCPU_CLOCK_HZ / configTICK_RATE_HZ ) 439 #define TRC_HWTC_DIVISOR 16 440 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD) 441 #define TRC_IRQ_PRIORITY_ORDER 0 442 443 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9) 444 445 /************************************************************************** 446 * This hardware port only supports FreeRTOS and the GCC compiler at the 447 * moment, due to the implementation of critical sections (trcKernelPort.h). 448 * 449 * Assuming FreeRTOS is used: 450 * 451 * For critical sections, this uses vTaskEnterCritical is when called from 452 * task context and ulPortSetInterruptMask when called from ISR context. 453 * Thus, it does not disable all ISRs. This means that the trace recorder 454 * can only be called from ISRs with priority less or equal to 455 * configMAX_API_CALL_INTERRUPT_PRIORITY (like FreeRTOS fromISR functions). 456 * 457 * This hardware port has been tested on a Xilinx Zync 7000 (Cortex-A9). 458 459 **************************************************************************/ 460 461 extern TraceUnsignedBaseType_t cortex_a9_r5_enter_critical(void); 462 extern void cortex_a9_r5_exit_critical(TraceUnsignedBaseType_t irq_already_masked_at_enter); 463 464 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 465 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = cortex_a9_r5_enter_critical(); } 466 #define TRACE_EXIT_CRITICAL_SECTION() { cortex_a9_r5_exit_critical(TRACE_ALLOC_CRITICAL_SECTION_NAME); } 467 468 /* INPUT YOUR PERIPHERAL BASE ADDRESS HERE (0xF8F00000 for Xilinx Zynq 7000)*/ 469 #define TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS 0 470 471 #if (TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS == 0) 472 #error "Please specify TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS." 473 #endif 474 475 #define TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET 0x0600 476 #define TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x00)) 477 #define TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x04)) 478 #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x08)) 479 480 #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK 0x0000FF00 481 #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT 8 482 #define TRC_CA9_MPCORE_PRIVCTR_PRESCALER (((TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG & TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK) >> TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT) + 1) 483 484 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR 485 #define TRC_HWTC_COUNT TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG 486 #define TRC_HWTC_PERIOD (TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG + 1) 487 488 /**************************************************************************************** 489 NOTE: The private timer ticks with a very high frequency (half the core-clock usually), 490 depending on the prescaler used. If a low prescaler is used, the number of HW ticks between 491 the trace events gets large, and thereby inefficient to store (sometimes extra events are 492 needed). To improve efficiency, you may use the TRC_HWTC_DIVISOR as an additional prescaler. 493 *****************************************************************************************/ 494 #define TRC_HWTC_DIVISOR 1 495 496 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD) 497 #define TRC_IRQ_PRIORITY_ORDER 0 498 499 #ifdef __GNUC__ 500 prvGetCPSR(void)501 static inline uint32_t prvGetCPSR(void) 502 { 503 unsigned long ret; 504 /* GCC-style assembly for getting the CPSR/APSR register, where the system execution mode is found. */ 505 asm volatile (" mrs %0, cpsr" : "=r" (ret) : /* no inputs */ ); 506 return ret; 507 } 508 #else 509 #error "Only GCC Supported!" 510 #endif 511 512 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_CYCLONE_V_HPS) 513 #include "alt_clock_manager.h" 514 515 extern TraceUnsignedBaseType_t cortex_a9_r5_enter_critical(void); 516 extern void cortex_a9_r5_exit_critical(TraceUnsignedBaseType_t irq_already_masked_at_enter); 517 518 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 519 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = cortex_a9_r5_enter_critical(); } 520 #define TRACE_EXIT_CRITICAL_SECTION() { cortex_a9_r5_exit_critical(TRACE_ALLOC_CRITICAL_SECTION_NAME); } 521 522 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR 523 #define TRC_HWTC_COUNT *((uint32_t *)0xFFFEC200) 524 #define TRC_HWTC_PERIOD 0 525 #define TRC_HWTC_DIVISOR 1 526 #define TRC_HWTC_FREQ_HZ (({ \ 527 uint32_t __freq; \ 528 alt_clk_freq_get( ALT_CLK_MPU_PERIPH, &__freq ); \ 529 __freq; \ 530 })) 531 #define TRC_IRQ_PRIORITY_ORDER 0 532 533 #ifdef __GNUC__ 534 /* For Arm Cortex-A and Cortex-R in general. */ prvGetCPSR(void)535 static inline uint32_t prvGetCPSR(void) 536 { 537 unsigned long ret; 538 /* GCC-style assembly for getting the CPSR/APSR register, where the system execution mode is found. */ 539 __asm__ __volatile__(" mrs %0, cpsr" : "=r" (ret) : /* no inputs */ ); 540 return ret; 541 } 542 #else 543 #error "Only GCC Supported!" 544 #endif 545 546 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ZEPHYR) 547 #ifdef CONFIG_64BIT 548 #define TRC_BASE_TYPE int64_t 549 #define TRC_UNSIGNED_BASE_TYPE uint64_t 550 #else 551 #define TRC_BASE_TYPE int32_t 552 #define TRC_UNSIGNED_BASE_TYPE uint32_t 553 #endif 554 555 #define TRACE_ALLOC_CRITICAL_SECTION() TraceBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 556 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = irq_lock(); } 557 #define TRACE_EXIT_CRITICAL_SECTION() { irq_unlock(TRACE_ALLOC_CRITICAL_SECTION_NAME); } 558 559 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR 560 #define TRC_HWTC_COUNT k_cycle_get_32() 561 #define TRC_HWTC_PERIOD (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) 562 #define TRC_HWTC_DIVISOR 4 563 #define TRC_HWTC_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC 564 #define TRC_IRQ_PRIORITY_ORDER 0 // Lower IRQ priority values are more significant 565 566 #define TRC_PORT_SPECIFIC_INIT() 567 568 #elif ((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XTensa_LX6) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XTensa_LX7)) 569 /** 570 * @note When running with SMP FreeRTOS we cannot use the CCOUNT register for timestamping, 571 * instead we use the external 40MHz timer for synchronized timestamping between the cores. 572 */ 573 #if CONFIG_FREERTOS_UNICORE == 1 574 575 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 576 #define TRACE_ENTER_CRITICAL_SECTION() {TRACE_ALLOC_CRITICAL_SECTION_NAME = __extension__({ unsigned __tmp; \ 577 __asm__ __volatile__("rsil %0, 15\n" \ 578 : "=a" (__tmp) : : "memory" ); \ 579 __tmp;});} 580 #define TRACE_EXIT_CRITICAL_SECTION() {portCLEAR_INTERRUPT_MASK_FROM_ISR(TRACE_ALLOC_CRITICAL_SECTION_NAME);} 581 582 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR 583 #define TRC_HWTC_COUNT ({ unsigned int __ccount; \ 584 __asm__ __volatile__("rsr.ccount %0" : "=a"(__ccount)); \ 585 __ccount; }) 586 #ifdef CONFIG_IDF_TARGET_ESP32 587 #define TRC_HWTC_FREQ_HZ (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * 1000000) 588 #elif defined(CONFIG_IDF_TARGET_ESP32S2) 589 #define TRC_HWTC_FREQ_HZ (CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ * 1000000) 590 #else 591 #error "Invalid IDF target, check your sdkconfig." 592 #endif 593 #define TRC_HWTC_PERIOD 0 594 #define TRC_HWTC_DIVISOR 4 595 #define TRC_IRQ_PRIORITY_ORDER 0 596 #else 597 /** 598 * @brief Fetch core agnostic timestamp using the external boot timestamp timer used by ESP IDF. 599 * 600 * @return Ticks since the timer started 601 */ 602 uint32_t prvGetSMPTimestamp(); 603 604 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR 605 #define TRC_HWTC_COUNT prvGetSMPTimestamp() 606 #define TRC_HWTC_FREQ_HZ 1000000 607 #define TRC_HWTC_PERIOD 0 608 #define TRC_HWTC_DIVISOR 4 609 #define TRC_IRQ_PRIORITY_ORDER 0 610 #endif 611 612 #if !defined(TRC_HWTC_FREQ_HZ) 613 #error "The XTensa LX6/LX7 trace hardware clock frequency is not defined." 614 #endif 615 616 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_RISCV_RV32I) 617 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 618 #define TRACE_ENTER_CRITICAL_SECTION() __asm__ __volatile__("csrr %0, mstatus \n\t" \ 619 "csrci mstatus, 8 \n\t" \ 620 "andi %0, %0, 8 \n\t" \ 621 : "=r"(TRACE_ALLOC_CRITICAL_SECTION_NAME)) 622 #define TRACE_EXIT_CRITICAL_SECTION() __asm__ __volatile__("csrr a1, mstatus \n\t" \ 623 "or %0, %0, a1 \n\t" \ 624 "csrs mstatus, %0 \n\t" \ 625 : \ 626 : "r" (TRACE_ALLOC_CRITICAL_SECTION_NAME) \ 627 : "a1") 628 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR 629 #define TRC_HWTC_COUNT ({ unsigned int __count; \ 630 __asm__ __volatile__("rdcycle %0" : "=r"(__count)); \ 631 __count; }) 632 #define TRC_HWTC_PERIOD 0 633 #define TRC_HWTC_DIVISOR 1 634 #define TRC_HWTC_FREQ_HZ 16000000 635 #define TRC_IRQ_PRIORITY_ORDER 0 636 637 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XMOS_XCOREAI) 638 #define TRC_PORT_SPECIFIC_INIT() 639 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR 640 #define TRC_HWTC_COUNT xscope_gettime() 641 #define TRC_HWTC_PERIOD (configCPU_CLOCK_HZ / configTICK_RATE_HZ ) 642 #define TRC_HWTC_DIVISOR 4 643 #define TRC_HWTC_FREQ_HZ 100000000 644 #define TRC_IRQ_PRIORITY_ORDER 0 645 646 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_POWERPC_Z4) 647 648 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */ 649 650 #define TRACE_ALLOC_CRITICAL_SECTION() TraceBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 651 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = TRC_KERNEL_PORT_SET_INTERRUPT_MASK(); } 652 #define TRACE_EXIT_CRITICAL_SECTION() { TRC_KERNEL_PORT_CLEAR_INTERRUPT_MASK(TRACE_ALLOC_CRITICAL_SECTION_NAME); } 653 654 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR 655 //#define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING 656 #define TRC_HWTC_COUNT PIT.TIMER[configTICK_PIT_CHANNEL].CVAL.R // must be the PIT channel used for the systick 657 #define TRC_HWTC_PERIOD ((configPIT_CLOCK_HZ / configTICK_RATE_HZ) - 1U) // TODO FIXME or maybe not -1? what's the right "period" value? 658 #define TRC_HWTC_FREQ_HZ configPIT_CLOCK_HZ 659 #define TRC_HWTC_DIVISOR 1 660 #define TRC_IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant 661 662 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARMv8AR_A32) 663 extern TraceUnsignedBaseType_t cortex_a9_r5_enter_critical(void); 664 extern void cortex_a9_r5_exit_critical(TraceUnsignedBaseType_t irq_already_masked_at_enter); 665 666 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME; 667 668 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = cortex_a9_r5_enter_critical(); } 669 670 #define TRACE_EXIT_CRITICAL_SECTION() { cortex_a9_r5_exit_critical(TRACE_ALLOC_CRITICAL_SECTION_NAME); } 671 672 #include <cmsis_compiler.h> 673 674 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR 675 #define TRC_HWTC_COUNT ((uint32_t)__get_CNTPCT()) 676 #define TRC_HWTC_PERIOD 0 677 #define TRC_HWTC_DIVISOR 16 678 #define TRC_HWTC_FREQ_HZ (R_GSC->CNTFID0) 679 #define TRC_IRQ_PRIORITY_ORDER 0 680 681 #ifdef __GNUC__ 682 /* For Arm Cortex-A and Cortex-R in general. */ prvGetCPSR(void)683 static inline uint32_t prvGetCPSR(void) 684 { 685 unsigned long ret; 686 /* GCC-style assembly for getting the CPSR/APSR register, where the system execution mode is found. */ 687 __asm volatile (" mrs %0, cpsr" : "=r" (ret) : /* no inputs */ ); 688 return ret; 689 } 690 #else 691 #error "Only GCC Supported!" 692 #endif 693 694 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_APPLICATION_DEFINED) 695 696 #if !( defined (TRC_HWTC_TYPE) && defined (TRC_HWTC_COUNT) && defined (TRC_HWTC_PERIOD) && defined (TRC_HWTC_FREQ_HZ) && defined (TRC_IRQ_PRIORITY_ORDER) ) 697 #error "The hardware port is not completely defined!" 698 #endif 699 700 #elif (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET) 701 702 #error "TRC_CFG_HARDWARE_PORT had unsupported value!" 703 #define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_NOT_SET 704 705 #endif 706 707 #ifndef TRC_HWTC_DIVISOR 708 #define TRC_HWTC_DIVISOR 1 709 #endif 710 711 #ifndef TRC_PORT_SPECIFIC_INIT 712 #define TRC_PORT_SPECIFIC_INIT() 713 #endif 714 715 /* If Win32 port */ 716 #ifdef WIN32 717 718 #undef _WIN32_WINNT 719 #define _WIN32_WINNT 0x0600 720 721 /* Standard includes. */ 722 #include <stdio.h> 723 #include <windows.h> 724 #include <direct.h> 725 726 /*************************************************************************** 727 * The Win32 port by default saves the trace to file and then kills the 728 * program when the recorder is stopped, to facilitate quick, simple tests 729 * of the recorder. 730 ***************************************************************************/ 731 #define WIN32_PORT_SAVE_WHEN_STOPPED 1 732 #define WIN32_PORT_EXIT_WHEN_STOPPED 1 733 734 #endif 735 736 #if (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET) 737 738 #ifndef TRC_HWTC_TYPE 739 #error "TRC_HWTC_TYPE is not set!" 740 #endif 741 742 #ifndef TRC_HWTC_COUNT 743 #error "TRC_HWTC_COUNT is not set!" 744 #endif 745 746 #ifndef TRC_HWTC_PERIOD 747 #error "TRC_HWTC_PERIOD is not set!" 748 #endif 749 750 #ifndef TRC_HWTC_DIVISOR 751 #error "TRC_HWTC_DIVISOR is not set!" 752 #endif 753 754 #ifndef TRC_IRQ_PRIORITY_ORDER 755 #error "TRC_IRQ_PRIORITY_ORDER is not set!" 756 #elif (TRC_IRQ_PRIORITY_ORDER != 0) && (TRC_IRQ_PRIORITY_ORDER != 1) 757 #error "TRC_IRQ_PRIORITY_ORDER has bad value!" 758 #endif 759 760 #if (TRC_HWTC_DIVISOR < 1) 761 #error "TRC_HWTC_DIVISOR must be a non-zero positive value!" 762 #endif 763 764 #ifndef TRC_HWTC_FREQ_HZ 765 #error "TRC_HWTC_FREQ_HZ not defined!" 766 #endif 767 768 #endif 769 770 /* If a custom TRC_CFG_ALLOC_CRITICAL_SECTION is defined it will override the default definition */ 771 #ifdef TRC_CFG_ALLOC_CRITICAL_SECTION 772 #undef TRACE_ALLOC_CRITICAL_SECTION 773 #define TRACE_ALLOC_CRITICAL_SECTION() TRC_CFG_ALLOC_CRITICAL_SECTION() 774 #endif 775 776 /* If a custom TRC_CFG_ENTER_CRITICAL_SECTION is defined it will override the default definition */ 777 #ifdef TRC_CFG_ENTER_CRITICAL_SECTION 778 #undef TRACE_ENTER_CRITICAL_SECTION 779 #define TRACE_ENTER_CRITICAL_SECTION() TRC_CFG_ENTER_CRITICAL_SECTION() 780 #endif 781 782 /* If a custom TRC_CFG_EXIT_CRITICAL_SECTION is defined it will override the default definition */ 783 #ifdef TRC_CFG_EXIT_CRITICAL_SECTION 784 #undef TRACE_EXIT_CRITICAL_SECTION 785 #define TRACE_EXIT_CRITICAL_SECTION() TRC_CFG_EXIT_CRITICAL_SECTION() 786 #endif 787 788 #ifndef TRACE_ALLOC_CRITICAL_SECTION 789 #define TRACE_ALLOC_CRITICAL_SECTION() TRC_KERNEL_PORT_ALLOC_CRITICAL_SECTION() 790 #endif 791 #ifndef TRACE_ENTER_CRITICAL_SECTION 792 #define TRACE_ENTER_CRITICAL_SECTION() TRC_KERNEL_PORT_ENTER_CRITICAL_SECTION() 793 #endif 794 #ifndef TRACE_EXIT_CRITICAL_SECTION 795 #define TRACE_EXIT_CRITICAL_SECTION() TRC_KERNEL_PORT_EXIT_CRITICAL_SECTION() 796 #endif 797 798 #endif /*TRC_HARDWARE_PORT_H*/ 799
