1 #ifndef XTENSA_DEBUG_MODULE_H 2 #define XTENSA_DEBUG_MODULE_H 3 4 #include <xtensa/config/core-isa.h> 5 6 /* 7 ERI registers / OCD offsets and field definitions 8 */ 9 10 #define ERI_DEBUG_OFFSET 0x100000 11 12 #define ERI_TRAX_OFFSET (ERI_DEBUG_OFFSET+0) 13 #define ERI_PERFMON_OFFSET (ERI_DEBUG_OFFSET+0x1000) 14 #define ERI_OCDREG_OFFSET (ERI_DEBUG_OFFSET+0x2000) 15 #define ERI_MISCDBG_OFFSET (ERI_DEBUG_OFFSET+0x3000) 16 #define ERI_CORESIGHT_OFFSET (ERI_DEBUG_OFFSET+0x3F00) 17 18 #define ERI_TRAX_TRAXID (ERI_TRAX_OFFSET+0x00) 19 #define ERI_TRAX_TRAXCTRL (ERI_TRAX_OFFSET+0x04) 20 #define ERI_TRAX_TRAXSTAT (ERI_TRAX_OFFSET+0x08) 21 #define ERI_TRAX_TRAXDATA (ERI_TRAX_OFFSET+0x0C) 22 #define ERI_TRAX_TRAXADDR (ERI_TRAX_OFFSET+0x10) 23 #define ERI_TRAX_TRIGGERPC (ERI_TRAX_OFFSET+0x14) 24 #define ERI_TRAX_PCMATCHCTRL (ERI_TRAX_OFFSET+0x18) 25 #define ERI_TRAX_DELAYCNT (ERI_TRAX_OFFSET+0x1C) 26 #define ERI_TRAX_MEMADDRSTART (ERI_TRAX_OFFSET+0x20) 27 #define ERI_TRAX_MEMADDREND (ERI_TRAX_OFFSET+0x24) 28 29 #define TRAXCTRL_TREN (1<<0) //Trace enable. Tracing starts on 0->1 30 #define TRAXCTRL_TRSTP (1<<1) //Trace Stop. Make 1 to stop trace. 31 #define TRAXCTRL_PCMEN (1<<2) //PC match enable 32 #define TRAXCTRL_PTIEN (1<<4) //Processor-trigger enable 33 #define TRAXCTRL_CTIEN (1<<5) //Cross-trigger enable 34 #define TRAXCTRL_TMEN (1<<7) //Tracemem Enable. Always set. 35 #define TRAXCTRL_CNTU (1<<9) //Post-stop-trigger countdown units; selects when DelayCount-- happens. 36 //0 - every 32-bit word written to tracemem, 1 - every cpu instruction 37 #define TRAXCTRL_TSEN (1<<11) //Undocumented/deprecated? 38 #define TRAXCTRL_SMPER_SHIFT 12 //Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg 39 #define TRAXCTRL_SMPER_MASK 0x7 //Synchronization message period 40 #define TRAXCTRL_PTOWT (1<<16) //Processor Trigger Out (OCD halt) enabled when stop triggered 41 #define TRAXCTRL_PTOWS (1<<17) //Processor Trigger Out (OCD halt) enabled when trace stop completes 42 #define TRAXCTRL_CTOWT (1<<20) //Cross-trigger Out enabled when stop triggered 43 #define TRAXCTRL_CTOWS (1<<21) //Cross-trigger Out enabled when trace stop completes 44 #define TRAXCTRL_ITCTO (1<<22) //Integration mode: cross-trigger output 45 #define TRAXCTRL_ITCTIA (1<<23) //Integration mode: cross-trigger ack 46 #define TRAXCTRL_ITATV (1<<24) //replaces ATID when in integration mode: ATVALID output 47 #define TRAXCTRL_ATID_MASK 0x7F //ARB source ID 48 #define TRAXCTRL_ATID_SHIFT 24 49 #define TRAXCTRL_ATEN (1<<31) //ATB interface enable 50 51 #define TRAXSTAT_TRACT (1<<0) //Trace active flag. 52 #define TRAXSTAT_TRIG (1<<1) //Trace stop trigger. Clears on TREN 1->0 53 #define TRAXSTAT_PCMTG (1<<2) //Stop trigger caused by PC match. Clears on TREN 1->0 54 #define TRAXSTAT_PJTR (1<<3) //JTAG transaction result. 1=err in preceding jtag transaction. 55 #define TRAXSTAT_PTITG (1<<4) //Stop trigger caused by Processor Trigger Input. Clears on TREN 1->0 56 #define TRAXSTAT_CTITG (1<<5) //Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0 57 #define TRAXSTAT_MEMSZ_SHIFT 8 //Traceram size inducator. Usable trace ram is 2^MEMSZ bytes. 58 #define TRAXSTAT_MEMSZ_MASK 0x1F 59 #define TRAXSTAT_PTO (1<<16) //Processor Trigger Output: current value 60 #define TRAXSTAT_CTO (1<<17) //Cross-Trigger Output: current value 61 #define TRAXSTAT_ITCTOA (1<<22) //Cross-Trigger Out Ack: current value 62 #define TRAXSTAT_ITCTI (1<<23) //Cross-Trigger Input: current value 63 #define TRAXSTAT_ITATR (1<<24) //ATREADY Input: current value 64 65 #define TRAXADDR_TADDR_SHIFT 0 //Trax memory address, in 32-bit words. 66 #define TRAXADDR_TADDR_MASK 0x1FFFFF //Actually is only as big as the trace buffer size max addr. 67 #define TRAXADDR_TWRAP_SHIFT 21 //Amount of times TADDR has overflown 68 #define TRAXADDR_TWRAP_MASK 0x3FF 69 #define TRAXADDR_TWSAT (1<<31) //1 if TWRAP has overflown, clear by disabling tren. 70 71 #define PCMATCHCTRL_PCML_SHIFT 0 //Amount of lower bits to ignore in pc trigger register 72 #define PCMATCHCTRL_PCML_MASK 0x1F 73 #define PCMATCHCTRL_PCMS (1<<31) //PC Match Sense, 0 - match when procs PC is in-range, 1 - match when 74 //out-of-range 75 76 // Global control/status for all performance counters 77 #define ERI_PERFMON_PGM (ERI_PERFMON_OFFSET+0x0000) 78 //PC at the cycle of the event that caused PerfMonInt assertion 79 #define ERI_PERFMON_INTPC (ERI_PERFMON_OFFSET+0x0010) 80 81 // Maximum amount of counter (depends on chip) 82 #define ERI_PERFMON_MAX XCHAL_NUM_PERF_COUNTERS 83 84 // Performance counter value 85 #define ERI_PERFMON_PM0 (ERI_PERFMON_OFFSET+0x0080) 86 // Performance counter control register 87 #define ERI_PERFMON_PMCTRL0 (ERI_PERFMON_OFFSET+0x0100) 88 // Performance counter status register 89 #define ERI_PERFMON_PMSTAT0 (ERI_PERFMON_OFFSET+0x0180) 90 91 92 #define PMCTRL_INTEN (1<<0) // Enables assertion of PerfMonInt output when overflow happens 93 #define PMCTRL_KRNLCNT (1<<3) // Enables counting when CINTLEVEL* > 94 // TRACELEVEL (i.e. If this bit is set, this counter 95 // counts only when CINTLEVEL >TRACELEVEL; 96 // if this bit is cleared, this counter counts only when 97 // CINTLEVEL ≤ TRACELEVEL) 98 #define PMCTRL_KRNLCNT_SHIFT 3 99 #define PMCTRL_TRACELEVEL_SHIFT 4 // Compares this value to CINTLEVEL* when deciding whether to count 100 #define PMCTRL_TRACELEVEL_MASK 0xf 101 #define PMCTRL_SELECT_SHIFT 8 // Selects input to be counted by the counter 102 #define PMCTRL_SELECT_MASK 0x1f 103 #define PMCTRL_MASK_SHIFT 16 // Selects input subsets to be counted (counter will 104 // increment only once even if more than one condition 105 // corresponding to a mask bit occurs) 106 #define PMCTRL_MASK_MASK 0xffff 107 108 109 #define PMSTAT_OVFL (1<<0) // Counter Overflow. Sticky bit set when a counter rolls over 110 // from 0xffffffff to 0x0. 111 #define PMSTAT_INTSTART (1<<4) // This counter’s overflow caused PerfMonInt to be asserted. 112 113 114 #define PGM_PMEN (1<<0) // Overall enable for all performance counting 115 116 117 #endif 118
