1 /*! 2 \file gd32e50x_tmu.h 3 \brief definitions for the TMU 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 */ 9 10 /* 11 Copyright (c) 2021, GigaDevice Semiconductor Inc. 12 13 All rights reserved. 14 15 Redistribution and use in source and binary forms, with or without modification, 16 are permitted provided that the following conditions are met: 17 18 1. Redistributions of source code must retain the above copyright notice, this 19 list of conditions and the following disclaimer. 20 2. Redistributions in binary form must reproduce the above copyright notice, 21 this list of conditions and the following disclaimer in the documentation 22 and/or other materials provided with the distribution. 23 3. Neither the name of the copyright holder nor the names of its contributors 24 may be used to endorse or promote products derived from this software without 25 specific prior written permission. 26 27 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 29 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 31 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 34 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 36 OF SUCH DAMAGE. 37 */ 38 39 #ifndef GD32E50X_TMU_H 40 #define GD32E50X_TMU_H 41 42 #include "gd32e50x.h" 43 44 #if defined(GD32E50X_CL) || defined(GD32E508) 45 46 /* TMU definitions */ 47 #define TMU TMU_BASE 48 49 /* registers definitions */ 50 #define TMU_IDATA0 REG32((TMU) + 0x00000000U) /*!< input data0 register */ 51 #define TMU_IDATA1 REG32((TMU) + 0x00000004U) /*!< input data1 register */ 52 #define TMU_CTL REG32((TMU) + 0x00000008U) /*!< control register */ 53 #define TMU_DATA0 REG32((TMU) + 0x0000000CU) /*!< data0 register */ 54 #define TMU_DATA1 REG32((TMU) + 0x00000010U) /*!< data1 register */ 55 #define TMU_STAT REG32((TMU) + 0x00000014U) /*!< status register */ 56 57 /* bits definitions */ 58 /* TMU_IDATA0 */ 59 #define TMU_IDATA0_IDATA0 BITS(0,31) /*!< the value of input data0 register */ 60 61 /* TMU_IDATA1 */ 62 #define TMU_IDATA1_IDATA1 BITS(0,31) /*!< the value of input data1 register */ 63 64 /* TMU_CTL */ 65 #define TMU_CTL_TMUEN BIT(0) /*!< start TMU calculation */ 66 #define TMU_CTL_MODE BITS(1,4) /*!< the mode of TMU */ 67 #define TMU_CTL_CFIE BIT(5) /*!< enable calculation finishes interrupt */ 68 #define TMU_CTL_CFIF BIT(6) /*!< the flag of calculation finishes interrupt */ 69 70 /* TMU_DATA0 */ 71 #define TMU_DATA0_DATA0 BITS(0,31) /*!< the value of data0 register */ 72 73 /* TMU_DATA0 */ 74 #define TMU_DATA1_DATA1 BITS(0,31) /*!< the value of data1 register */ 75 76 /* TMU_STAT */ 77 #define TMU_STAT_OVRF BIT(0) /*!< the status of overflow */ 78 #define TMU_STAT_UDRF BIT(1) /*!< the status of underflow */ 79 80 /* constants definitions */ 81 /* TMU mode definitions */ 82 #define TMU_MODE(regval) (BITS(1,4) & ((uint32_t)(regval) << 1)) 83 #define TMU_MODE0 TMU_MODE(0) /*!< the mode0 of TMU */ 84 #define TMU_MODE1 TMU_MODE(1) /*!< the mode1 of TMU */ 85 #define TMU_MODE2 TMU_MODE(2) /*!< the mode2 of TMU */ 86 #define TMU_MODE3 TMU_MODE(3) /*!< the mode3 of TMU */ 87 #define TMU_MODE4 TMU_MODE(4) /*!< the mode4 of TMU */ 88 #define TMU_MODE5 TMU_MODE(5) /*!< the mode5 of TMU */ 89 #define TMU_MODE6 TMU_MODE(6) /*!< the mode6 of TMU */ 90 #define TMU_MODE7 TMU_MODE(7) /*!< the mode7 of TMU */ 91 #define TMU_MODE8 TMU_MODE(8) /*!< the mode8 of TMU */ 92 93 /* TMU interrupt flag definitions */ 94 #define TMU_INT_FLAG_CFIF TMU_CTL_CFIF /*!< the interrupt flag of calculation finished */ 95 96 /* TMU flag definitions */ 97 #define TMU_FLAG_OVRF TMU_STAT_OVRF /*!< the flag of TMU overflow */ 98 #define TMU_FLAG_UDRF TMU_STAT_UDRF /*!< the flag of TMU underflow */ 99 100 /* function declarations */ 101 /* TMU deinitialization and initialization functions */ 102 /* reset the TMU */ 103 void tmu_deinit(void); 104 /* enable the TMU */ 105 void tmu_enable(void); 106 107 /* configure the TMU calculation */ 108 /* configure the TMU mode */ 109 void tmu_mode_set(uint32_t modex); 110 /* write the data to TMU input data0 regisetr */ 111 void tmu_idata0_write(uint32_t idata0); 112 /* write the data to TMU input data1 regisetr */ 113 void tmu_idata1_write(uint32_t idata1); 114 /* read the data from TMU data0 regisetr */ 115 uint32_t tmu_data0_read(void); 116 /* read the data from TMU data1 regisetr */ 117 uint32_t tmu_data1_read(void); 118 119 /* flag and interrupt functions */ 120 /* enable TTMU interrupt */ 121 void tmu_interrupt_enable(void); 122 /* disable TTMU interrupt */ 123 void tmu_interrupt_disable(void); 124 /* check teh TMU status flag */ 125 FlagStatus tmu_flag_get(uint32_t flag); 126 /* check teh TMU interrupt flag */ 127 FlagStatus tmu_interrupt_flag_get(uint32_t int_flag); 128 129 #endif /* GD32E50x_CL and GD32E508 */ 130 131 #endif /* GD32E50X_TMU_H */ 132
