1 /* 2 * Copyright 2021-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CLOCK_IP_TYPES_H 8 #define CLOCK_IP_TYPES_H 9 10 /** 11 * @file Clock_Ip_Types.h 12 * @version 2.0.0 13 * 14 * @brief CLOCK IP type header file. 15 * @details CLOCK IP type header file. 16 17 * @addtogroup CLOCK_DRIVER Clock Ip Driver 18 * @{ 19 */ 20 21 #if defined(__cplusplus) 22 extern "C"{ 23 #endif 24 /*================================================================================================== 25 * INCLUDE FILES 26 * 1) system and project includes 27 * 2) needed interfaces from external units 28 * 3) internal and external interfaces from this unit 29 ==================================================================================================*/ 30 #include "Std_Types.h" 31 #include "Clock_Ip_Cfg_Defines.h" 32 #include "Mcal.h" 33 /*================================================================================================== 34 SOURCE FILE VERSION INFORMATION 35 ==================================================================================================*/ 36 #define CLOCK_IP_TYPES_VENDOR_ID 43 37 #define CLOCK_IP_TYPES_AR_RELEASE_MAJOR_VERSION 4 38 #define CLOCK_IP_TYPES_AR_RELEASE_MINOR_VERSION 7 39 #define CLOCK_IP_TYPES_AR_RELEASE_REVISION_VERSION 0 40 #define CLOCK_IP_TYPES_SW_MAJOR_VERSION 2 41 #define CLOCK_IP_TYPES_SW_MINOR_VERSION 0 42 #define CLOCK_IP_TYPES_SW_PATCH_VERSION 0 43 44 /*================================================================================================== 45 FILE VERSION CHECKS 46 ==================================================================================================*/ 47 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 48 /* Check if source file and Std_Types.h file are of the same Autosar version */ 49 #if ((CLOCK_IP_TYPES_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \ 50 (CLOCK_IP_TYPES_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION) \ 51 ) 52 #error "AutoSar Version Numbers of Clock_Ip_Types.h and Std_Types.h are different" 53 #endif 54 #endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */ 55 56 /* Check if Clock_Ip_Types.h file and Clock_Ip_Cfg_Defines.h file have same versions */ 57 #if (CLOCK_IP_TYPES_VENDOR_ID != CLOCK_IP_CFG_DEFINES_VENDOR_ID) 58 #error "Clock_Ip_Types.h and Clock_Ip_Cfg_Defines.h have different vendor IDs" 59 #endif 60 61 /* Check if Clock_Ip_Types.h file and Clock_Ip_Cfg_Defines.h file are of the same Autosar version */ 62 #if ((CLOCK_IP_TYPES_AR_RELEASE_MAJOR_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ 63 (CLOCK_IP_TYPES_AR_RELEASE_MINOR_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ 64 (CLOCK_IP_TYPES_AR_RELEASE_REVISION_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION)) 65 #error "AutoSar Version Numbers of Clock_Ip_Types.h and Clock_Ip_Cfg_Defines.h are different" 66 #endif 67 68 /* Check if Clock_Ip_Types.h file and Clock_Ip_Cfg_Defines.h file are of the same Software version */ 69 #if ((CLOCK_IP_TYPES_SW_MAJOR_VERSION != CLOCK_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ 70 (CLOCK_IP_TYPES_SW_MINOR_VERSION != CLOCK_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ 71 (CLOCK_IP_TYPES_SW_PATCH_VERSION != CLOCK_IP_CFG_DEFINES_SW_PATCH_VERSION)) 72 #error "Software Version Numbers of Clock_Ip_Types.h and Clock_Ip_Cfg_Defines.h are different" 73 #endif 74 75 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 76 /* Check if Clock_Ip_Types.h file and Mcal.h file are of the same Autosar version */ 77 #if ((CLOCK_IP_TYPES_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \ 78 (CLOCK_IP_TYPES_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION)) 79 #error "AutoSar Version Numbers of Clock_Ip_Types.h and Mcal.h are different" 80 #endif 81 #endif 82 /*================================================================================================== 83 * CONSTANTS 84 ==================================================================================================*/ 85 86 /*================================================================================================== 87 * DEFINES AND MACROS 88 ==================================================================================================*/ 89 90 /*================================================================================================== 91 * ENUMS 92 ==================================================================================================*/ 93 #if (defined(CLOCK_IP_POWER_NOTIFICATIONS)) 94 /** @brief Power modes. */ 95 typedef enum { 96 97 #if defined(CLOCK_IP_HAS_RUN_MODE) 98 RUN_MODE = CLOCK_IP_HAS_RUN_MODE, 99 VLPR_MODE = 1U, 100 VLPS_MODE = 2U, 101 HSRUN_MODE = 3U, 102 #endif 103 } Clock_Ip_PowerModesType; 104 105 /** @brief Power mode notification. */ 106 typedef enum { 107 108 BEFORE_POWER_MODE_CHANGE, /* Before power mode change command is sent */ 109 POWER_MODE_CHANGE_IN_PROGRESS, /* Power mode transition is in progress */ 110 POWER_MODE_CHANGED, /* Power mode transition completed */ 111 112 } Clock_Ip_PowerNotificationType; 113 #endif 114 115 /** @brief Clock names. */ 116 typedef enum { 117 118 CLOCK_IS_OFF = 0U, 119 120 #if defined(CLOCK_IP_HAS_FIRC_CLK) 121 FIRC_CLK = CLOCK_IP_HAS_FIRC_CLK, 122 #endif 123 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 124 FIRC_AE_CLK = CLOCK_IP_HAS_FIRC_AE_CLK, 125 #endif 126 #if defined(CLOCK_IP_HAS_FIRC_MUXED_CLK) 127 FIRC_MUXED_CLK = CLOCK_IP_HAS_FIRC_MUXED_CLK, 128 #endif 129 #if defined(CLOCK_IP_HAS_FIRC_VLP_CLK) 130 FIRC_VLP_CLK = CLOCK_IP_HAS_FIRC_VLP_CLK, 131 #endif 132 #if defined(CLOCK_IP_HAS_FIRC_STOP_CLK) 133 FIRC_STOP_CLK = CLOCK_IP_HAS_FIRC_STOP_CLK, 134 #endif 135 #if defined(CLOCK_IP_HAS_FIRC_STANDBY_CLK) 136 FIRC_STANDBY_CLK = CLOCK_IP_HAS_FIRC_STANDBY_CLK, 137 #endif 138 #if defined(CLOCK_IP_HAS_FIRC_POSTDIV_CLK) 139 FIRC_POSTDIV_CLK = CLOCK_IP_HAS_FIRC_POSTDIV_CLK, 140 #endif 141 #if defined(CLOCK_IP_HAS_FRO_CLK) 142 FRO_CLK = CLOCK_IP_HAS_FRO_CLK, 143 #endif 144 #if defined(CLOCK_IP_HAS_SAFE_CLK) 145 SAFE_CLK = CLOCK_IP_HAS_SAFE_CLK, 146 #endif 147 #if defined(CLOCK_IP_HAS_SIRC_CLK) 148 SIRC_CLK = CLOCK_IP_HAS_SIRC_CLK, 149 #endif 150 #if defined(CLOCK_IP_HAS_SIRC_VLP_CLK) 151 SIRC_VLP_CLK = CLOCK_IP_HAS_SIRC_VLP_CLK, 152 #endif 153 #if defined(CLOCK_IP_HAS_SIRC_STOP_CLK) 154 SIRC_STOP_CLK = CLOCK_IP_HAS_SIRC_STOP_CLK, 155 #endif 156 #if defined(CLOCK_IP_HAS_SIRC_STANDBY_CLK) 157 SIRC_STANDBY_CLK = CLOCK_IP_HAS_SIRC_STANDBY_CLK, 158 #endif 159 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 160 SYSTEM_CLK = CLOCK_IP_HAS_SYSTEM_CLK, 161 #endif 162 #if defined(CLOCK_IP_HAS_LPO_128K_CLK) 163 LPO_128K_CLK = CLOCK_IP_HAS_LPO_128K_CLK, 164 #endif 165 #if defined(CLOCK_IP_HAS_FXOSC_CLK) 166 FXOSC_CLK = CLOCK_IP_HAS_FXOSC_CLK, 167 #endif 168 #if defined(CLOCK_IP_HAS_SXOSC_CLK) 169 SXOSC_CLK = CLOCK_IP_HAS_SXOSC_CLK, 170 #endif 171 #if defined(CLOCK_IP_HAS_SOSC_CLK) 172 SOSC_CLK = CLOCK_IP_HAS_SOSC_CLK, 173 #endif 174 #if defined(CLOCK_IP_HAS_ACCELPLL_CLK) 175 ACCELPLL_CLK = CLOCK_IP_HAS_ACCELPLL_CLK, 176 #endif 177 #if defined(CLOCK_IP_HAS_COREPLL_CLK) 178 COREPLL_CLK = CLOCK_IP_HAS_COREPLL_CLK, 179 #endif 180 #if defined(CLOCK_IP_HAS_DDRPLL_CLK) 181 DDRPLL_CLK = CLOCK_IP_HAS_DDRPLL_CLK, 182 #endif 183 #if defined(CLOCK_IP_HAS_PERIPHPLL_CLK) 184 PERIPHPLL_CLK = CLOCK_IP_HAS_PERIPHPLL_CLK, 185 #endif 186 #if defined(CLOCK_IP_HAS_LFAST0_PLL_CLK) 187 LFAST0_PLL_CLK = CLOCK_IP_HAS_LFAST0_PLL_CLK, 188 #endif 189 #if defined(CLOCK_IP_HAS_LFAST1_PLL_CLK) 190 LFAST1_PLL_CLK = CLOCK_IP_HAS_LFAST1_PLL_CLK, 191 #endif 192 #if defined(CLOCK_IP_HAS_PLL_CLK) 193 PLL_CLK = CLOCK_IP_HAS_PLL_CLK, 194 #endif 195 #if defined(CLOCK_IP_HAS_PLL0_CLK) 196 PLL0_CLK = CLOCK_IP_HAS_PLL0_CLK, 197 #endif 198 #if defined(CLOCK_IP_HAS_PLL1_CLK) 199 PLL1_CLK = CLOCK_IP_HAS_PLL1_CLK, 200 #endif 201 #if defined(CLOCK_IP_HAS_PLLAUX_CLK) 202 PLLAUX_CLK = CLOCK_IP_HAS_PLLAUX_CLK, 203 #endif 204 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK) 205 PLLAUX_PHI0_CLK = CLOCK_IP_HAS_PLLAUX_PHI0_CLK, 206 #endif 207 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK) 208 PLLAUX_PHI1_CLK = CLOCK_IP_HAS_PLLAUX_PHI1_CLK, 209 #endif 210 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK) 211 PLLAUX_PHI2_CLK = CLOCK_IP_HAS_PLLAUX_PHI2_CLK, 212 #endif 213 #if defined(CLOCK_IP_HAS_SPLL_CLK) 214 SPLL_CLK = CLOCK_IP_HAS_SPLL_CLK, 215 #endif 216 #if defined(CLOCK_IP_HAS_AURORAPLL_CLK) 217 AURORAPLL_CLK = CLOCK_IP_HAS_AURORAPLL_CLK, 218 #endif 219 #if defined(CLOCK_IP_HAS_ACCEL_PLL_PHI0_CLK) 220 ACCEL_PLL_PHI0_CLK = CLOCK_IP_HAS_ACCEL_PLL_PHI0_CLK, 221 #endif 222 #if defined(CLOCK_IP_HAS_ACCEL_PLL_PHI1_CLK) 223 ACCEL_PLL_PHI1_CLK = CLOCK_IP_HAS_ACCEL_PLL_PHI1_CLK, 224 #endif 225 #if defined(CLOCK_IP_HAS_CORE_PLL_PHI0_CLK) 226 CORE_PLL_PHI0_CLK = CLOCK_IP_HAS_CORE_PLL_PHI0_CLK, 227 #endif 228 #if defined(CLOCK_IP_HAS_CORE_PLL_PHI1_CLK) 229 CORE_PLL_PHI1_CLK = CLOCK_IP_HAS_CORE_PLL_PHI1_CLK, 230 #endif 231 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS0_CLK) 232 CORE_PLL_DFS0_CLK = CLOCK_IP_HAS_CORE_PLL_DFS0_CLK, 233 #endif 234 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS1_CLK) 235 CORE_PLL_DFS1_CLK = CLOCK_IP_HAS_CORE_PLL_DFS1_CLK, 236 #endif 237 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS2_CLK) 238 CORE_PLL_DFS2_CLK = CLOCK_IP_HAS_CORE_PLL_DFS2_CLK, 239 #endif 240 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS3_CLK) 241 CORE_PLL_DFS3_CLK = CLOCK_IP_HAS_CORE_PLL_DFS3_CLK, 242 #endif 243 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS4_CLK) 244 CORE_PLL_DFS4_CLK = CLOCK_IP_HAS_CORE_PLL_DFS4_CLK, 245 #endif 246 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS5_CLK) 247 CORE_PLL_DFS5_CLK = CLOCK_IP_HAS_CORE_PLL_DFS5_CLK, 248 #endif 249 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS6_CLK) 250 CORE_PLL_DFS6_CLK = CLOCK_IP_HAS_CORE_PLL_DFS6_CLK, 251 #endif 252 #if defined(CLOCK_IP_HAS_DDR_PLL_PHI0_CLK) 253 DDR_PLL_PHI0_CLK = CLOCK_IP_HAS_DDR_PLL_PHI0_CLK, 254 #endif 255 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI0_CLK) 256 PERIPH_PLL_PHI0_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI0_CLK, 257 #endif 258 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI1_CLK) 259 PERIPH_PLL_PHI1_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI1_CLK, 260 #endif 261 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI2_CLK) 262 PERIPH_PLL_PHI2_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI2_CLK, 263 #endif 264 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI3_CLK) 265 PERIPH_PLL_PHI3_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI3_CLK, 266 #endif 267 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI4_CLK) 268 PERIPH_PLL_PHI4_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI4_CLK, 269 #endif 270 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI5_CLK) 271 PERIPH_PLL_PHI5_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI5_CLK, 272 #endif 273 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI6_CLK) 274 PERIPH_PLL_PHI6_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI6_CLK, 275 #endif 276 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI7_CLK) 277 PERIPH_PLL_PHI7_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI7_CLK, 278 #endif 279 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS0_CLK) 280 PERIPH_PLL_DFS0_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS0_CLK, 281 #endif 282 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS1_CLK) 283 PERIPH_PLL_DFS1_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS1_CLK, 284 #endif 285 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS2_CLK) 286 PERIPH_PLL_DFS2_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS2_CLK, 287 #endif 288 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS3_CLK) 289 PERIPH_PLL_DFS3_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS3_CLK, 290 #endif 291 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS4_CLK) 292 PERIPH_PLL_DFS4_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS4_CLK, 293 #endif 294 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS5_CLK) 295 PERIPH_PLL_DFS5_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS5_CLK, 296 #endif 297 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS6_CLK) 298 PERIPH_PLL_DFS6_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS6_CLK, 299 #endif 300 #if defined(CLOCK_IP_HAS_COREPLL_PHI0_CLK) 301 COREPLL_PHI0_CLK = CLOCK_IP_HAS_COREPLL_PHI0_CLK, 302 #endif 303 #if defined(CLOCK_IP_HAS_COREPLL_PHI1_CLK) 304 COREPLL_PHI1_CLK = CLOCK_IP_HAS_COREPLL_PHI1_CLK, 305 #endif 306 #if defined(CLOCK_IP_HAS_COREPLL_PHI2_CLK) 307 COREPLL_PHI2_CLK = CLOCK_IP_HAS_COREPLL_PHI2_CLK, 308 #endif 309 #if defined(CLOCK_IP_HAS_COREPLL_PHI3_CLK) 310 COREPLL_PHI3_CLK = CLOCK_IP_HAS_COREPLL_PHI3_CLK, 311 #endif 312 #if defined(CLOCK_IP_HAS_COREPLL_PHI4_CLK) 313 COREPLL_PHI4_CLK = CLOCK_IP_HAS_COREPLL_PHI4_CLK, 314 #endif 315 #if defined(CLOCK_IP_HAS_COREPLL_PHI5_CLK) 316 COREPLL_PHI5_CLK = CLOCK_IP_HAS_COREPLL_PHI5_CLK, 317 #endif 318 #if defined(CLOCK_IP_HAS_COREPLL_PHI6_CLK) 319 COREPLL_PHI6_CLK = CLOCK_IP_HAS_COREPLL_PHI6_CLK, 320 #endif 321 #if defined(CLOCK_IP_HAS_COREPLL_PHI7_CLK) 322 COREPLL_PHI7_CLK = CLOCK_IP_HAS_COREPLL_PHI7_CLK, 323 #endif 324 #if defined(CLOCK_IP_HAS_COREPLL_PHI8_CLK) 325 COREPLL_PHI8_CLK = CLOCK_IP_HAS_COREPLL_PHI8_CLK, 326 #endif 327 #if defined(CLOCK_IP_HAS_COREPLL_PHI9_CLK) 328 COREPLL_PHI9_CLK = CLOCK_IP_HAS_COREPLL_PHI9_CLK, 329 #endif 330 #if defined(CLOCK_IP_HAS_COREPLL_DFS0_CLK) 331 COREPLL_DFS0_CLK = CLOCK_IP_HAS_COREPLL_DFS0_CLK, 332 #endif 333 #if defined(CLOCK_IP_HAS_COREPLL_DFS1_CLK) 334 COREPLL_DFS1_CLK = CLOCK_IP_HAS_COREPLL_DFS1_CLK, 335 #endif 336 #if defined(CLOCK_IP_HAS_COREPLL_DFS2_CLK) 337 COREPLL_DFS2_CLK = CLOCK_IP_HAS_COREPLL_DFS2_CLK, 338 #endif 339 #if defined(CLOCK_IP_HAS_COREPLL_DFS3_CLK) 340 COREPLL_DFS3_CLK = CLOCK_IP_HAS_COREPLL_DFS3_CLK, 341 #endif 342 #if defined(CLOCK_IP_HAS_COREPLL_DFS4_CLK) 343 COREPLL_DFS4_CLK = CLOCK_IP_HAS_COREPLL_DFS4_CLK, 344 #endif 345 #if defined(CLOCK_IP_HAS_COREPLL_DFS5_CLK) 346 COREPLL_DFS5_CLK = CLOCK_IP_HAS_COREPLL_DFS5_CLK, 347 #endif 348 #if defined(CLOCK_IP_HAS_COREPLL_DFS6_CLK) 349 COREPLL_DFS6_CLK = CLOCK_IP_HAS_COREPLL_DFS6_CLK, 350 #endif 351 #if defined(CLOCK_IP_HAS_DDRPLL_PHI0_CLK) 352 DDRPLL_PHI0_CLK = CLOCK_IP_HAS_DDRPLL_PHI0_CLK, 353 #endif 354 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI0_CLK) 355 PERIPHPLL_PHI0_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI0_CLK, 356 #endif 357 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI1_CLK) 358 PERIPHPLL_PHI1_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI1_CLK, 359 #endif 360 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI2_CLK) 361 PERIPHPLL_PHI2_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI2_CLK, 362 #endif 363 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI3_CLK) 364 PERIPHPLL_PHI3_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI3_CLK, 365 #endif 366 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI4_CLK) 367 PERIPHPLL_PHI4_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI4_CLK, 368 #endif 369 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI5_CLK) 370 PERIPHPLL_PHI5_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI5_CLK, 371 #endif 372 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI6_CLK) 373 PERIPHPLL_PHI6_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI6_CLK, 374 #endif 375 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI7_CLK) 376 PERIPHPLL_PHI7_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI7_CLK, 377 #endif 378 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI8_CLK) 379 PERIPHPLL_PHI8_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI8_CLK, 380 #endif 381 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI9_CLK) 382 PERIPHPLL_PHI9_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI9_CLK, 383 #endif 384 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS0_CLK) 385 PERIPHPLL_DFS0_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS0_CLK, 386 #endif 387 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS1_CLK) 388 PERIPHPLL_DFS1_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS1_CLK, 389 #endif 390 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS2_CLK) 391 PERIPHPLL_DFS2_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS2_CLK, 392 #endif 393 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS3_CLK) 394 PERIPHPLL_DFS3_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS3_CLK, 395 #endif 396 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS4_CLK) 397 PERIPHPLL_DFS4_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS4_CLK, 398 #endif 399 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS5_CLK) 400 PERIPHPLL_DFS5_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS5_CLK, 401 #endif 402 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS6_CLK) 403 PERIPHPLL_DFS6_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS6_CLK, 404 #endif 405 #if defined(CLOCK_IP_HAS_PLL_PHI0_CLK) 406 PLL_PHI0_CLK = CLOCK_IP_HAS_PLL_PHI0_CLK, 407 #endif 408 #if defined(CLOCK_IP_HAS_PLL_PHI1_CLK) 409 PLL_PHI1_CLK = CLOCK_IP_HAS_PLL_PHI1_CLK, 410 #endif 411 #if defined(CLOCK_IP_HAS_AURORAPLL_PHI0_CLK) 412 AURORAPLL_PHI0_CLK = CLOCK_IP_HAS_AURORAPLL_PHI0_CLK, 413 #endif 414 #if defined(CLOCK_IP_HAS_AURORAPLL_PHI1_CLK) 415 AURORAPLL_PHI1_CLK = CLOCK_IP_HAS_AURORAPLL_PHI1_CLK, 416 #endif 417 #if defined(CLOCK_IP_HAS_AURORAPLL_PHI2_CLK) 418 AURORAPLL_PHI2_CLK = CLOCK_IP_HAS_AURORAPLL_PHI2_CLK, 419 #endif 420 #if defined(CLOCK_IP_HAS_LFAST0_PLL_PH0_CLK) 421 LFAST0_PLL_PH0_CLK = CLOCK_IP_HAS_LFAST0_PLL_PH0_CLK, 422 #endif 423 #if defined(CLOCK_IP_HAS_LFAST1_PLL_PH0_CLK) 424 LFAST1_PLL_PH0_CLK = CLOCK_IP_HAS_LFAST1_PLL_PH0_CLK, 425 #endif 426 #if defined(CLOCK_IP_HAS_PLL_POSTDIV_CLK) 427 PLL_POSTDIV_CLK = CLOCK_IP_HAS_PLL_POSTDIV_CLK, 428 #endif 429 #if defined(CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK) 430 PLLAUX_POSTDIV_CLK = CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK, 431 #endif 432 #if defined(CLOCK_IP_HAS_SIRCDIV1_CLK) 433 SIRCDIV1_CLK = CLOCK_IP_HAS_SIRCDIV1_CLK, 434 #endif 435 #if defined(CLOCK_IP_HAS_SIRCDIV2_CLK) 436 SIRCDIV2_CLK = CLOCK_IP_HAS_SIRCDIV2_CLK, 437 #endif 438 #if defined(CLOCK_IP_HAS_FDIV0_CLK) 439 FDIV0_CLK = CLOCK_IP_HAS_FDIV0_CLK, 440 #endif 441 #if defined(CLOCK_IP_HAS_FIRCDIV1_CLK) 442 FIRCDIV1_CLK = CLOCK_IP_HAS_FIRCDIV1_CLK, 443 #endif 444 #if defined(CLOCK_IP_HAS_FIRCDIV2_CLK) 445 FIRCDIV2_CLK = CLOCK_IP_HAS_FIRCDIV2_CLK, 446 #endif 447 #if defined(CLOCK_IP_HAS_SOSCDIV1_CLK) 448 SOSCDIV1_CLK = CLOCK_IP_HAS_SOSCDIV1_CLK, 449 #endif 450 #if defined(CLOCK_IP_HAS_SOSCDIV2_CLK) 451 SOSCDIV2_CLK = CLOCK_IP_HAS_SOSCDIV2_CLK, 452 #endif 453 #if defined(CLOCK_IP_HAS_SPLLDIV1_CLK) 454 SPLLDIV1_CLK = CLOCK_IP_HAS_SPLLDIV1_CLK, 455 #endif 456 #if defined(CLOCK_IP_HAS_SPLLDIV2_CLK) 457 SPLLDIV2_CLK = CLOCK_IP_HAS_SPLLDIV2_CLK, 458 #endif 459 #if defined(CLOCK_IP_HAS_LPO_32K_CLK) 460 LPO_32K_CLK = CLOCK_IP_HAS_LPO_32K_CLK, 461 #endif 462 #if defined(CLOCK_IP_HAS_LPO_1K_CLK) 463 LPO_1K_CLK = CLOCK_IP_HAS_LPO_1K_CLK, 464 #endif 465 #if defined(CLOCK_IP_HAS_SERDES_0_LANE_0_TX) 466 SERDES_0_LANE_0_TX = CLOCK_IP_HAS_SERDES_0_LANE_0_TX, 467 #endif 468 #if defined(CLOCK_IP_HAS_SERDES_0_LANE_0_CDR) 469 SERDES_0_LANE_0_CDR = CLOCK_IP_HAS_SERDES_0_LANE_0_CDR, 470 #endif 471 #if defined(CLOCK_IP_HAS_SERDES_0_LANE_1_TX) 472 SERDES_0_LANE_1_TX = CLOCK_IP_HAS_SERDES_0_LANE_1_TX, 473 #endif 474 #if defined(CLOCK_IP_HAS_SERDES_0_LANE_1_CDR) 475 SERDES_0_LANE_1_CDR = CLOCK_IP_HAS_SERDES_0_LANE_1_CDR, 476 #endif 477 #if defined(CLOCK_IP_HAS_SERDES_1_LANE_0_TX) 478 SERDES_1_LANE_0_TX = CLOCK_IP_HAS_SERDES_1_LANE_0_TX, 479 #endif 480 #if defined(CLOCK_IP_HAS_SERDES_1_LANE_0_CDR) 481 SERDES_1_LANE_0_CDR = CLOCK_IP_HAS_SERDES_1_LANE_0_CDR, 482 #endif 483 #if defined(CLOCK_IP_HAS_SERDES_1_LANE_1_TX) 484 SERDES_1_LANE_1_TX = CLOCK_IP_HAS_SERDES_1_LANE_1_TX, 485 #endif 486 #if defined(CLOCK_IP_HAS_SERDES_1_LANE_1_CDR) 487 SERDES_1_LANE_1_CDR = CLOCK_IP_HAS_SERDES_1_LANE_1_CDR, 488 #endif 489 #if defined(CLOCK_IP_HAS_SERDES_0_XPCS_0_TX) 490 SERDES_0_XPCS_0_TX = CLOCK_IP_HAS_SERDES_0_XPCS_0_TX, 491 #endif 492 #if defined(CLOCK_IP_HAS_SERDES_0_XPCS_0_CDR) 493 SERDES_0_XPCS_0_CDR = CLOCK_IP_HAS_SERDES_0_XPCS_0_CDR, 494 #endif 495 #if defined(CLOCK_IP_HAS_SERDES_0_XPCS_1_TX) 496 SERDES_0_XPCS_1_TX = CLOCK_IP_HAS_SERDES_0_XPCS_1_TX, 497 #endif 498 #if defined(CLOCK_IP_HAS_SERDES_0_XPCS_1_CDR) 499 SERDES_0_XPCS_1_CDR = CLOCK_IP_HAS_SERDES_0_XPCS_1_CDR, 500 #endif 501 #if defined(CLOCK_IP_HAS_SERDES_1_XPCS_0_TX) 502 SERDES_1_XPCS_0_TX = CLOCK_IP_HAS_SERDES_1_XPCS_0_TX, 503 #endif 504 #if defined(CLOCK_IP_HAS_SERDES_1_XPCS_0_CDR) 505 SERDES_1_XPCS_0_CDR = CLOCK_IP_HAS_SERDES_1_XPCS_0_CDR, 506 #endif 507 #if defined(CLOCK_IP_HAS_SERDES_1_XPCS_1_TX) 508 SERDES_1_XPCS_1_TX = CLOCK_IP_HAS_SERDES_1_XPCS_1_TX, 509 #endif 510 #if defined(CLOCK_IP_HAS_SERDES_1_XPCS_1_CDR) 511 SERDES_1_XPCS_1_CDR = CLOCK_IP_HAS_SERDES_1_XPCS_1_CDR, 512 #endif 513 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK) 514 EMAC_MII_RX_CLK = CLOCK_IP_HAS_EMAC_MII_RX_CLK, 515 #endif 516 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK) 517 EMAC_MII_RMII_TX_CLK = CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK, 518 #endif 519 #if defined(CLOCK_IP_HAS_ETH_RGMII_REF_CLK) 520 ETH_RGMII_REF_CLK = CLOCK_IP_HAS_ETH_RGMII_REF_CLK, 521 #endif 522 #if defined(CLOCK_IP_HAS_TMR_1588_CLK) 523 TMR_1588_CLK = CLOCK_IP_HAS_TMR_1588_CLK, 524 #endif 525 #if defined(CLOCK_IP_HAS_ETH_EXT_TS_CLK) 526 ETH_EXT_TS_CLK = CLOCK_IP_HAS_ETH_EXT_TS_CLK, 527 #endif 528 #if defined(CLOCK_IP_HAS_ETH0_EXT_RX_CLK) 529 ETH0_EXT_RX_CLK = CLOCK_IP_HAS_ETH0_EXT_RX_CLK, 530 #endif 531 #if defined(CLOCK_IP_HAS_ETH0_EXT_TX_CLK) 532 ETH0_EXT_TX_CLK = CLOCK_IP_HAS_ETH0_EXT_TX_CLK, 533 #endif 534 #if defined(CLOCK_IP_HAS_ETH1_EXT_RX_CLK) 535 ETH1_EXT_RX_CLK = CLOCK_IP_HAS_ETH1_EXT_RX_CLK, 536 #endif 537 #if defined(CLOCK_IP_HAS_ETH1_EXT_TX_CLK) 538 ETH1_EXT_TX_CLK = CLOCK_IP_HAS_ETH1_EXT_TX_CLK, 539 #endif 540 #if defined(CLOCK_IP_HAS_LFAST0_EXT_REF_CLK) 541 LFAST0_EXT_REF_CLK = CLOCK_IP_HAS_LFAST0_EXT_REF_CLK, 542 #endif 543 #if defined(CLOCK_IP_HAS_LFAST1_EXT_REF_CLK) 544 LFAST1_EXT_REF_CLK = CLOCK_IP_HAS_LFAST1_EXT_REF_CLK, 545 #endif 546 #if defined(CLOCK_IP_HAS_FTM_0_EXT_REF_CLK) 547 FTM_0_EXT_REF_CLK = CLOCK_IP_HAS_FTM_0_EXT_REF_CLK, 548 #endif 549 #if defined(CLOCK_IP_HAS_FTM_1_EXT_REF_CLK) 550 FTM_1_EXT_REF_CLK = CLOCK_IP_HAS_FTM_1_EXT_REF_CLK, 551 #endif 552 #if defined(CLOCK_IP_HAS_GMAC_MII_RGMII_RX_CLK) 553 GMAC_MII_RGMII_RX_CLK = CLOCK_IP_HAS_GMAC_MII_RGMII_RX_CLK, 554 #endif 555 #if defined(CLOCK_IP_HAS_GMAC_MII_RMII_RGMII_TX_CLK) 556 GMAC_MII_RMII_RGMII_TX_CLK = CLOCK_IP_HAS_GMAC_MII_RMII_RGMII_TX_CLK, 557 #endif 558 #if defined(CLOCK_IP_HAS_GMAC_0_EXT_REF_CLK) 559 GMAC_0_EXT_REF_CLK = CLOCK_IP_HAS_GMAC_0_EXT_REF_CLK, 560 #endif 561 #if defined(CLOCK_IP_HAS_GMAC_0_EXT_RX_CLK) 562 GMAC_0_EXT_RX_CLK = CLOCK_IP_HAS_GMAC_0_EXT_RX_CLK, 563 #endif 564 #if defined(CLOCK_IP_HAS_GMAC_0_EXT_TX_CLK) 565 GMAC_0_EXT_TX_CLK = CLOCK_IP_HAS_GMAC_0_EXT_TX_CLK, 566 #endif 567 #if defined(CLOCK_IP_HAS_GMAC_0_SGMII_REF_CLK) 568 GMAC_0_SGMII_REF_CLK = CLOCK_IP_HAS_GMAC_0_SGMII_REF_CLK, 569 #endif 570 #if defined(CLOCK_IP_HAS_GMAC_0_SGMII_RX_CLK) 571 GMAC_0_SGMII_RX_CLK = CLOCK_IP_HAS_GMAC_0_SGMII_RX_CLK, 572 #endif 573 #if defined(CLOCK_IP_HAS_GMAC_0_SGMII_TX_CLK) 574 GMAC_0_SGMII_TX_CLK = CLOCK_IP_HAS_GMAC_0_SGMII_TX_CLK, 575 #endif 576 #if defined(CLOCK_IP_HAS_GMAC_1_EXT_REF_CLK) 577 GMAC_1_EXT_REF_CLK = CLOCK_IP_HAS_GMAC_1_EXT_REF_CLK, 578 #endif 579 #if defined(CLOCK_IP_HAS_GMAC_1_EXT_RX_CLK) 580 GMAC_1_EXT_RX_CLK = CLOCK_IP_HAS_GMAC_1_EXT_RX_CLK, 581 #endif 582 #if defined(CLOCK_IP_HAS_GMAC_1_EXT_TX_CLK) 583 GMAC_1_EXT_TX_CLK = CLOCK_IP_HAS_GMAC_1_EXT_TX_CLK, 584 #endif 585 #if defined(CLOCK_IP_HAS_GMAC_EXT_TS_CLK) 586 GMAC_EXT_TS_CLK = CLOCK_IP_HAS_GMAC_EXT_TS_CLK, 587 #endif 588 #if defined(CLOCK_IP_HAS_GMAC_0_EXT_TS_CLK) 589 GMAC_0_EXT_TS_CLK = CLOCK_IP_HAS_GMAC_0_EXT_TS_CLK, 590 #endif 591 #if defined(CLOCK_IP_HAS_GMAC_1_EXT_TS_CLK) 592 GMAC_1_EXT_TS_CLK = CLOCK_IP_HAS_GMAC_1_EXT_TS_CLK, 593 #endif 594 #if defined(CLOCK_IP_HAS_GMAC_1_INT_REF_CLK) 595 GMAC_1_INT_REF_CLK = CLOCK_IP_HAS_GMAC_1_INT_REF_CLK, 596 #endif 597 #if defined(CLOCK_IP_HAS_PFE_MAC_0_EXT_REF_CLK) 598 PFE_MAC_0_EXT_REF_CLK = CLOCK_IP_HAS_PFE_MAC_0_EXT_REF_CLK, 599 #endif 600 #if defined(CLOCK_IP_HAS_PFE_MAC_0_EXT_RX_CLK) 601 PFE_MAC_0_EXT_RX_CLK = CLOCK_IP_HAS_PFE_MAC_0_EXT_RX_CLK, 602 #endif 603 #if defined(CLOCK_IP_HAS_PFE_MAC_0_EXT_TX_CLK) 604 PFE_MAC_0_EXT_TX_CLK = CLOCK_IP_HAS_PFE_MAC_0_EXT_TX_CLK, 605 #endif 606 #if defined(CLOCK_IP_HAS_PFE_MAC_1_EXT_REF_CLK) 607 PFE_MAC_1_EXT_REF_CLK = CLOCK_IP_HAS_PFE_MAC_1_EXT_REF_CLK, 608 #endif 609 #if defined(CLOCK_IP_HAS_PFE_MAC_1_EXT_RX_CLK) 610 PFE_MAC_1_EXT_RX_CLK = CLOCK_IP_HAS_PFE_MAC_1_EXT_RX_CLK, 611 #endif 612 #if defined(CLOCK_IP_HAS_PFE_MAC_1_EXT_TX_CLK) 613 PFE_MAC_1_EXT_TX_CLK = CLOCK_IP_HAS_PFE_MAC_1_EXT_TX_CLK, 614 #endif 615 #if defined(CLOCK_IP_HAS_PFE_MAC_2_EXT_REF_CLK) 616 PFE_MAC_2_EXT_REF_CLK = CLOCK_IP_HAS_PFE_MAC_2_EXT_REF_CLK, 617 #endif 618 #if defined(CLOCK_IP_HAS_PFE_MAC_2_EXT_RX_CLK) 619 PFE_MAC_2_EXT_RX_CLK = CLOCK_IP_HAS_PFE_MAC_2_EXT_RX_CLK, 620 #endif 621 #if defined(CLOCK_IP_HAS_PFE_MAC_2_EXT_TX_CLK) 622 PFE_MAC_2_EXT_TX_CLK = CLOCK_IP_HAS_PFE_MAC_2_EXT_TX_CLK, 623 #endif 624 #if defined(CLOCK_IP_HAS_TCLK0_REF_CLK) 625 TCLK0_REF_CLK = CLOCK_IP_HAS_TCLK0_REF_CLK, 626 #endif 627 #if defined(CLOCK_IP_HAS_TCLK1_REF_CLK) 628 TCLK1_REF_CLK = CLOCK_IP_HAS_TCLK1_REF_CLK, 629 #endif 630 #if defined(CLOCK_IP_HAS_TCLK2_REF_CLK) 631 TCLK2_REF_CLK = CLOCK_IP_HAS_TCLK2_REF_CLK, 632 #endif 633 #if defined(CLOCK_IP_HAS_TEST_CLK) 634 TEST_CLK = CLOCK_IP_HAS_TEST_CLK, 635 #endif 636 #if defined(CLOCK_IP_HAS_TPR_CLK) 637 TPR_CLK = CLOCK_IP_HAS_TPR_CLK, 638 #endif 639 #if defined(CLOCK_IP_HAS_RTC_CLKIN) 640 RTC_CLKIN = CLOCK_IP_HAS_RTC_CLKIN, 641 #endif 642 #if defined(CLOCK_IP_HAS_A53_CORE_CLK) 643 A53_CORE_CLK = CLOCK_IP_HAS_A53_CORE_CLK, 644 #endif 645 #if defined(CLOCK_IP_HAS_A53_CORE_DIV2_CLK) 646 A53_CORE_DIV2_CLK = CLOCK_IP_HAS_A53_CORE_DIV2_CLK, 647 #endif 648 #if defined(CLOCK_IP_HAS_A53_CORE_DIV4_CLK) 649 A53_CORE_DIV4_CLK = CLOCK_IP_HAS_A53_CORE_DIV4_CLK, 650 #endif 651 #if defined(CLOCK_IP_HAS_A53_CORE_DIV10_CLK) 652 A53_CORE_DIV10_CLK = CLOCK_IP_HAS_A53_CORE_DIV10_CLK, 653 #endif 654 #if defined(CLOCK_IP_HAS_AIPS_PLAT_CLK) 655 AIPS_PLAT_CLK = CLOCK_IP_HAS_AIPS_PLAT_CLK, 656 #endif 657 #if defined(CLOCK_IP_HAS_AIPS_SLOW_CLK) 658 AIPS_SLOW_CLK = CLOCK_IP_HAS_AIPS_SLOW_CLK, 659 #endif 660 #if defined(CLOCK_IP_HAS_ACCEL3_CLK) 661 ACCEL3_CLK = CLOCK_IP_HAS_ACCEL3_CLK, 662 #endif 663 #if defined(CLOCK_IP_HAS_ACCEL3_DIV3_CLK) 664 ACCEL3_DIV3_CLK = CLOCK_IP_HAS_ACCEL3_DIV3_CLK, 665 #endif 666 #if defined(CLOCK_IP_HAS_ACCEL4_CLK) 667 ACCEL4_CLK = CLOCK_IP_HAS_ACCEL4_CLK, 668 #endif 669 #if defined(CLOCK_IP_HAS_CLKOUT_RUN_CLK) 670 CLKOUT_RUN_CLK = CLOCK_IP_HAS_CLKOUT_RUN_CLK, 671 #endif 672 #if defined(CLOCK_IP_HAS_DCM_CLK) 673 DCM_CLK = CLOCK_IP_HAS_DCM_CLK, 674 #endif 675 #if defined(CLOCK_IP_HAS_DDR_CLK) 676 DDR_CLK = CLOCK_IP_HAS_DDR_CLK, 677 #endif 678 #if defined(CLOCK_IP_HAS_DDR0_CLK) 679 DDR0_CLK = CLOCK_IP_HAS_DDR0_CLK, 680 #endif 681 #if defined(CLOCK_IP_HAS_DMACRC0_CLK) 682 DMACRC0_CLK = CLOCK_IP_HAS_DMACRC0_CLK, 683 #endif 684 #if defined(CLOCK_IP_HAS_DMACRC1_CLK) 685 DMACRC1_CLK = CLOCK_IP_HAS_DMACRC1_CLK, 686 #endif 687 #if defined(CLOCK_IP_HAS_DMACRC4_CLK) 688 DMACRC4_CLK = CLOCK_IP_HAS_DMACRC4_CLK, 689 #endif 690 #if defined(CLOCK_IP_HAS_DMACRC5_CLK) 691 DMACRC5_CLK = CLOCK_IP_HAS_DMACRC5_CLK, 692 #endif 693 #if defined(CLOCK_IP_HAS_GMAC_REF_DIV_CLK) 694 GMAC_REF_DIV_CLK = CLOCK_IP_HAS_GMAC_REF_DIV_CLK, 695 #endif 696 #if defined(CLOCK_IP_HAS_GMAC0_REF_DIV_CLK) 697 GMAC0_REF_DIV_CLK = CLOCK_IP_HAS_GMAC0_REF_DIV_CLK, 698 #endif 699 #if defined(CLOCK_IP_HAS_GMAC0_REF_CLK) 700 GMAC0_REF_CLK = CLOCK_IP_HAS_GMAC0_REF_CLK, 701 #endif 702 #if defined(CLOCK_IP_HAS_GMAC1_REF_DIV_CLK) 703 GMAC1_REF_DIV_CLK = CLOCK_IP_HAS_GMAC1_REF_DIV_CLK, 704 #endif 705 #if defined(CLOCK_IP_HAS_GMAC1_REF_CLK) 706 GMAC1_REF_CLK = CLOCK_IP_HAS_GMAC1_REF_CLK, 707 #endif 708 #if defined(CLOCK_IP_HAS_GMAC1_INT_CLK) 709 GMAC1_INT_CLK = CLOCK_IP_HAS_GMAC1_INT_CLK, 710 #endif 711 #if defined(CLOCK_IP_HAS_AURORA_TRACE_TEST_CLK) 712 AURORA_TRACE_TEST_CLK = CLOCK_IP_HAS_AURORA_TRACE_TEST_CLK, 713 #endif 714 #if defined(CLOCK_IP_HAS_HSE_CLK) 715 HSE_CLK = CLOCK_IP_HAS_HSE_CLK, 716 #endif 717 #if defined(CLOCK_IP_HAS_LBIST_CLK) 718 LBIST_CLK = CLOCK_IP_HAS_LBIST_CLK, 719 #endif 720 #if defined(CLOCK_IP_HAS_PFE_PE_CLK) 721 PFE_PE_CLK = CLOCK_IP_HAS_PFE_PE_CLK, 722 #endif 723 #if defined(CLOCK_IP_HAS_PFE_SYS_CLK) 724 PFE_SYS_CLK = CLOCK_IP_HAS_PFE_SYS_CLK, 725 #endif 726 #if defined(CLOCK_IP_HAS_PER_CLK) 727 PER_CLK = CLOCK_IP_HAS_PER_CLK, 728 #endif 729 #if defined(CLOCK_IP_HAS_PFEMAC0_REF_DIV_CLK) 730 PFEMAC0_REF_DIV_CLK = CLOCK_IP_HAS_PFEMAC0_REF_DIV_CLK, 731 #endif 732 #if defined(CLOCK_IP_HAS_PFEMAC1_REF_DIV_CLK) 733 PFEMAC1_REF_DIV_CLK = CLOCK_IP_HAS_PFEMAC1_REF_DIV_CLK, 734 #endif 735 #if defined(CLOCK_IP_HAS_PFEMAC2_REF_DIV_CLK) 736 PFEMAC2_REF_DIV_CLK = CLOCK_IP_HAS_PFEMAC2_REF_DIV_CLK, 737 #endif 738 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK) 739 QSPI_MEM_CLK = CLOCK_IP_HAS_QSPI_MEM_CLK, 740 #endif 741 #if defined(CLOCK_IP_HAS_SCS_CLK) 742 SCS_CLK = CLOCK_IP_HAS_SCS_CLK, 743 #endif 744 #if defined(CLOCK_IP_HAS_XBAR_2X_CLK) 745 XBAR_2X_CLK = CLOCK_IP_HAS_XBAR_2X_CLK, 746 #endif 747 #if defined(CLOCK_IP_HAS_XBAR_CLK) 748 XBAR_CLK = CLOCK_IP_HAS_XBAR_CLK, 749 #endif 750 #if defined(CLOCK_IP_HAS_XBAR_DIV2_CLK) 751 XBAR_DIV2_CLK = CLOCK_IP_HAS_XBAR_DIV2_CLK, 752 #endif 753 #if defined(CLOCK_IP_HAS_XBAR_DIV3_CLK) 754 XBAR_DIV3_CLK = CLOCK_IP_HAS_XBAR_DIV3_CLK, 755 #endif 756 #if defined(CLOCK_IP_HAS_XBAR_DIV4_CLK) 757 XBAR_DIV4_CLK = CLOCK_IP_HAS_XBAR_DIV4_CLK, 758 #endif 759 #if defined(CLOCK_IP_HAS_XBAR_DIV6_CLK) 760 XBAR_DIV6_CLK = CLOCK_IP_HAS_XBAR_DIV6_CLK, 761 #endif 762 #if defined(CLOCK_IP_HAS_XMII_CLK_125MHZ) 763 XMII_CLK_125MHZ = CLOCK_IP_HAS_XMII_CLK_125MHZ, 764 #endif 765 #if defined(CLOCK_IP_HAS_XMII_CLK_2M5HZ) 766 XMII_CLK_2M5HZ = CLOCK_IP_HAS_XMII_CLK_2M5HZ, 767 #endif 768 #if defined(CLOCK_IP_HAS_XMII_CLK_25MHZ) 769 XMII_CLK_25MHZ = CLOCK_IP_HAS_XMII_CLK_25MHZ, 770 #endif 771 #if defined(CLOCK_IP_HAS_XMII_CLK_50MHZ) 772 XMII_CLK_50MHZ = CLOCK_IP_HAS_XMII_CLK_50MHZ, 773 #endif 774 #if defined(CLOCK_IP_HAS_XOSC_CLK) 775 XOSC_CLK = CLOCK_IP_HAS_XOSC_CLK, 776 #endif 777 #if defined(CLOCK_IP_HAS_SERDES_REF_CLK) 778 SERDES_REF_CLK = CLOCK_IP_HAS_SERDES_REF_CLK, 779 #endif 780 #if defined(CLOCK_IP_HAS_SERDES0_REF_CLK) 781 SERDES0_REF_CLK = CLOCK_IP_HAS_SERDES0_REF_CLK, 782 #endif 783 #if defined(CLOCK_IP_HAS_SERDES1_REF_CLK) 784 SERDES1_REF_CLK = CLOCK_IP_HAS_SERDES1_REF_CLK, 785 #endif 786 #if defined(CLOCK_IP_HAS_SCS_RUN_CLK) 787 SCS_RUN_CLK = CLOCK_IP_HAS_SCS_RUN_CLK, 788 #endif 789 #if defined(CLOCK_IP_HAS_SCS_VLPR_CLK) 790 SCS_VLPR_CLK = CLOCK_IP_HAS_SCS_VLPR_CLK, 791 #endif 792 #if defined(CLOCK_IP_HAS_SCS_HSRUN_CLK) 793 SCS_HSRUN_CLK = CLOCK_IP_HAS_SCS_HSRUN_CLK, 794 #endif 795 #if defined(CLOCK_IP_HAS_CORE_CLK) 796 CORE_CLK = CLOCK_IP_HAS_CORE_CLK, 797 #endif 798 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 799 CM7_CORE_CLK = CLOCK_IP_HAS_CM7_CORE_CLK, 800 #endif 801 #if defined(CLOCK_IP_HAS_CORE_RUN_CLK) 802 CORE_RUN_CLK = CLOCK_IP_HAS_CORE_RUN_CLK, 803 #endif 804 #if defined(CLOCK_IP_HAS_CORE_VLPR_CLK) 805 CORE_VLPR_CLK = CLOCK_IP_HAS_CORE_VLPR_CLK, 806 #endif 807 #if defined(CLOCK_IP_HAS_CORE_HSRUN_CLK) 808 CORE_HSRUN_CLK = CLOCK_IP_HAS_CORE_HSRUN_CLK, 809 #endif 810 #if defined(CLOCK_IP_HAS_BUS_CLK) 811 BUS_CLK = CLOCK_IP_HAS_BUS_CLK, 812 #endif 813 #if defined(CLOCK_IP_HAS_BUS_RUN_CLK) 814 BUS_RUN_CLK = CLOCK_IP_HAS_BUS_RUN_CLK, 815 #endif 816 #if defined(CLOCK_IP_HAS_BUS_VLPR_CLK) 817 BUS_VLPR_CLK = CLOCK_IP_HAS_BUS_VLPR_CLK, 818 #endif 819 #if defined(CLOCK_IP_HAS_BUS_HSRUN_CLK) 820 BUS_HSRUN_CLK = CLOCK_IP_HAS_BUS_HSRUN_CLK, 821 #endif 822 #if defined(CLOCK_IP_HAS_SLOW_CLK) 823 SLOW_CLK = CLOCK_IP_HAS_SLOW_CLK, 824 #endif 825 #if defined(CLOCK_IP_HAS_SLOW_RUN_CLK) 826 SLOW_RUN_CLK = CLOCK_IP_HAS_SLOW_RUN_CLK, 827 #endif 828 #if defined(CLOCK_IP_HAS_SLOW_VLPR_CLK) 829 SLOW_VLPR_CLK = CLOCK_IP_HAS_SLOW_VLPR_CLK, 830 #endif 831 #if defined(CLOCK_IP_HAS_SLOW_HSRUN_CLK) 832 SLOW_HSRUN_CLK = CLOCK_IP_HAS_SLOW_HSRUN_CLK, 833 #endif 834 #if defined(CLOCK_IP_HAS_LPO_CLK) 835 LPO_CLK = CLOCK_IP_HAS_LPO_CLK, 836 #endif 837 #if defined(CLOCK_IP_HAS_SCG_CLKOUT_CLK) 838 SCG_CLKOUT_CLK = CLOCK_IP_HAS_SCG_CLKOUT_CLK, 839 #endif 840 #if defined(CLOCK_IP_HAS_FTM0_EXT_CLK) 841 FTM0_EXT_CLK = CLOCK_IP_HAS_FTM0_EXT_CLK, 842 #endif 843 #if defined(CLOCK_IP_HAS_FTM1_EXT_CLK) 844 FTM1_EXT_CLK = CLOCK_IP_HAS_FTM1_EXT_CLK, 845 #endif 846 #if defined(CLOCK_IP_HAS_FTM2_EXT_CLK) 847 FTM2_EXT_CLK = CLOCK_IP_HAS_FTM2_EXT_CLK, 848 #endif 849 #if defined(CLOCK_IP_HAS_FTM3_EXT_CLK) 850 FTM3_EXT_CLK = CLOCK_IP_HAS_FTM3_EXT_CLK, 851 #endif 852 #if defined(CLOCK_IP_HAS_FTM4_EXT_CLK) 853 FTM4_EXT_CLK = CLOCK_IP_HAS_FTM4_EXT_CLK, 854 #endif 855 #if defined(CLOCK_IP_HAS_FTM5_EXT_CLK) 856 FTM5_EXT_CLK = CLOCK_IP_HAS_FTM5_EXT_CLK, 857 #endif 858 #if defined(CLOCK_IP_HAS_FTM6_EXT_CLK) 859 FTM6_EXT_CLK = CLOCK_IP_HAS_FTM6_EXT_CLK, 860 #endif 861 #if defined(CLOCK_IP_HAS_FTM7_EXT_CLK) 862 FTM7_EXT_CLK = CLOCK_IP_HAS_FTM7_EXT_CLK, 863 #endif 864 #if defined(CLOCK_IP_HAS_Px_CLKOUT_SRC_CLK) 865 Px_CLKOUT_SRC_CLK = CLOCK_IP_HAS_Px_CLKOUT_SRC_CLK, 866 #endif 867 #if defined(CLOCK_IP_HAS_Px_PSI5_S_UTIL_CLK) 868 Px_PSI5_S_UTIL_CLK = CLOCK_IP_HAS_Px_PSI5_S_UTIL_CLK, 869 #endif 870 #if defined(CLOCK_IP_HAS_SHIFT_LBIST_CLK) 871 SHIFT_LBIST_CLK = CLOCK_IP_HAS_SHIFT_LBIST_CLK, 872 #endif 873 #if defined(CLOCK_IP_HAS_P0_SYS_CLK) 874 P0_SYS_CLK = CLOCK_IP_HAS_P0_SYS_CLK, 875 #endif 876 #if defined(CLOCK_IP_HAS_P1_SYS_CLK) 877 P1_SYS_CLK = CLOCK_IP_HAS_P1_SYS_CLK, 878 #endif 879 #if defined(CLOCK_IP_HAS_P1_SYS_DIV2_CLK) 880 P1_SYS_DIV2_CLK = CLOCK_IP_HAS_P1_SYS_DIV2_CLK, 881 #endif 882 #if defined(CLOCK_IP_HAS_P1_SYS_DIV4_CLK) 883 P1_SYS_DIV4_CLK = CLOCK_IP_HAS_P1_SYS_DIV4_CLK, 884 #endif 885 #if defined(CLOCK_IP_HAS_P2_SYS_CLK) 886 P2_SYS_CLK = CLOCK_IP_HAS_P2_SYS_CLK, 887 #endif 888 #if defined(CLOCK_IP_HAS_CORE_M33_CLK) 889 CORE_M33_CLK = CLOCK_IP_HAS_CORE_M33_CLK, 890 #endif 891 #if defined(CLOCK_IP_HAS_P2_SYS_DIV2_CLK) 892 P2_SYS_DIV2_CLK = CLOCK_IP_HAS_P2_SYS_DIV2_CLK, 893 #endif 894 #if defined(CLOCK_IP_HAS_P2_SYS_DIV4_CLK) 895 P2_SYS_DIV4_CLK = CLOCK_IP_HAS_P2_SYS_DIV4_CLK, 896 #endif 897 #if defined(CLOCK_IP_HAS_P3_SYS_CLK) 898 P3_SYS_CLK = CLOCK_IP_HAS_P3_SYS_CLK, 899 #endif 900 #if defined(CLOCK_IP_HAS_CE_SYS_DIV2_CLK) 901 CE_SYS_DIV2_CLK = CLOCK_IP_HAS_CE_SYS_DIV2_CLK, 902 #endif 903 #if defined(CLOCK_IP_HAS_CE_SYS_DIV4_CLK) 904 CE_SYS_DIV4_CLK = CLOCK_IP_HAS_CE_SYS_DIV4_CLK, 905 #endif 906 #if defined(CLOCK_IP_HAS_P3_SYS_DIV2_NOC_CLK) 907 P3_SYS_DIV2_NOC_CLK = CLOCK_IP_HAS_P3_SYS_DIV2_NOC_CLK, 908 #endif 909 #if defined(CLOCK_IP_HAS_P3_SYS_DIV4_CLK) 910 P3_SYS_DIV4_CLK = CLOCK_IP_HAS_P3_SYS_DIV4_CLK, 911 #endif 912 #if defined(CLOCK_IP_HAS_P4_SYS_CLK) 913 P4_SYS_CLK = CLOCK_IP_HAS_P4_SYS_CLK, 914 #endif 915 #if defined(CLOCK_IP_HAS_P4_SYS_DIV2_CLK) 916 P4_SYS_DIV2_CLK = CLOCK_IP_HAS_P4_SYS_DIV2_CLK, 917 #endif 918 #if defined(CLOCK_IP_HAS_HSE_SYS_DIV2_CLK) 919 HSE_SYS_DIV2_CLK = CLOCK_IP_HAS_HSE_SYS_DIV2_CLK, 920 #endif 921 #if defined(CLOCK_IP_HAS_P5_SYS_CLK) 922 P5_SYS_CLK = CLOCK_IP_HAS_P5_SYS_CLK, 923 #endif 924 #if defined(CLOCK_IP_HAS_P5_SYS_DIV2_CLK) 925 P5_SYS_DIV2_CLK = CLOCK_IP_HAS_P5_SYS_DIV2_CLK, 926 #endif 927 #if defined(CLOCK_IP_HAS_P5_SYS_DIV4_CLK) 928 P5_SYS_DIV4_CLK = CLOCK_IP_HAS_P5_SYS_DIV4_CLK, 929 #endif 930 #if defined(CLOCK_IP_HAS_P2_MATH_CLK) 931 P2_MATH_CLK = CLOCK_IP_HAS_P2_MATH_CLK, 932 #endif 933 #if defined(CLOCK_IP_HAS_P2_MATH_DIV3_CLK) 934 P2_MATH_DIV3_CLK = CLOCK_IP_HAS_P2_MATH_DIV3_CLK, 935 #endif 936 #if defined(CLOCK_IP_HAS_RTU0_CORE_CLK) 937 RTU0_CORE_CLK = CLOCK_IP_HAS_RTU0_CORE_CLK, 938 #endif 939 #if defined(CLOCK_IP_HAS_RTU0_CORE_DIV2_CLK) 940 RTU0_CORE_DIV2_CLK = CLOCK_IP_HAS_RTU0_CORE_DIV2_CLK, 941 #endif 942 #if defined(CLOCK_IP_HAS_RTU1_CORE_CLK) 943 RTU1_CORE_CLK = CLOCK_IP_HAS_RTU1_CORE_CLK, 944 #endif 945 #if defined(CLOCK_IP_HAS_RTU1_CORE_DIV2_CLK) 946 RTU1_CORE_DIV2_CLK = CLOCK_IP_HAS_RTU1_CORE_DIV2_CLK, 947 #endif 948 #if defined(CLOCK_IP_HAS_P0_PSI5_S_UTIL_CLK) 949 P0_PSI5_S_UTIL_CLK = CLOCK_IP_HAS_P0_PSI5_S_UTIL_CLK, 950 #endif 951 #if defined(CLOCK_IP_HAS_P4_PSI5_S_UTIL_CLK) 952 P4_PSI5_S_UTIL_CLK = CLOCK_IP_HAS_P4_PSI5_S_UTIL_CLK, 953 #endif 954 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 955 SYSTEM_DRUN_CLK = CLOCK_IP_HAS_SYSTEM_DRUN_CLK, 956 #endif 957 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 958 SYSTEM_DIV2_CLK = CLOCK_IP_HAS_SYSTEM_DIV2_CLK, 959 #endif 960 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) 961 SYSTEM_DIV4_MON1_CLK = CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK, 962 #endif 963 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK) 964 SYSTEM_DIV4_MON2_CLK = CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK, 965 #endif 966 #if defined(CLOCK_IP_HAS_SYS_CLK) 967 SYS_CLK = CLOCK_IP_HAS_SYS_CLK, 968 #endif 969 #if defined(CLOCK_IP_HAS_SYS_DIV2_CLK) 970 SYS_DIV2_CLK = CLOCK_IP_HAS_SYS_DIV2_CLK, 971 #endif 972 #if defined(CLOCK_IP_HAS_SYS_DIV4_CLK) 973 SYS_DIV4_CLK = CLOCK_IP_HAS_SYS_DIV4_CLK, 974 #endif 975 #if defined(CLOCK_IP_HAS_SYS_DIV8_CLK) 976 SYS_DIV8_CLK = CLOCK_IP_HAS_SYS_DIV8_CLK, 977 #endif 978 #if defined(CLOCK_IP_HAS_RT_DAPB_CLK) 979 RT_DAPB_CLK = CLOCK_IP_HAS_RT_DAPB_CLK, 980 #endif 981 #if defined(CLOCK_IP_HAS_ACCEL_CLK) 982 ACCEL_CLK = CLOCK_IP_HAS_ACCEL_CLK, 983 #endif 984 #if defined(CLOCK_IP_HAS_ACCEL_DIV3_CLK) 985 ACCEL_DIV3_CLK = CLOCK_IP_HAS_ACCEL_DIV3_CLK, 986 #endif 987 #if defined(CLOCK_IP_HAS_ACCEL_DIV4_CLK) 988 ACCEL_DIV4_CLK = CLOCK_IP_HAS_ACCEL_DIV4_CLK, 989 #endif 990 #if defined(CLOCK_IP_HAS_ACCEL_XBAR_CLK) 991 ACCEL_XBAR_CLK = CLOCK_IP_HAS_ACCEL_XBAR_CLK, 992 #endif 993 #if defined(CLOCK_IP_HAS_ACCEL_XBAR_DIV2_CLK) 994 ACCEL_XBAR_DIV2_CLK = CLOCK_IP_HAS_ACCEL_XBAR_DIV2_CLK, 995 #endif 996 #if defined(CLOCK_IP_HAS_ACCEL_XBAR_DIV4_CLK) 997 ACCEL_XBAR_DIV4_CLK = CLOCK_IP_HAS_ACCEL_XBAR_DIV4_CLK, 998 #endif 999 #if defined(CLOCK_IP_HAS_ACCEL_XBAR_DIV8_CLK) 1000 ACCEL_XBAR_DIV8_CLK = CLOCK_IP_HAS_ACCEL_XBAR_DIV8_CLK, 1001 #endif 1002 #if defined(CLOCK_IP_HAS_AP_DAPB_CLK) 1003 AP_DAPB_CLK = CLOCK_IP_HAS_AP_DAPB_CLK, 1004 #endif 1005 THE_LAST_PRODUCER_CLK = CLOCK_IP_FEATURE_PRODUCERS_NO, /* Number of producers clocks */ 1006 #if defined(CLOCK_IP_HAS_ACCEL4_LAX0_CLK) 1007 ACCEL4_LAX0_CLK = CLOCK_IP_HAS_ACCEL4_LAX0_CLK, 1008 #endif 1009 #if defined(CLOCK_IP_HAS_ACCEL4_LAX1_CLK) 1010 ACCEL4_LAX1_CLK = CLOCK_IP_HAS_ACCEL4_LAX1_CLK, 1011 #endif 1012 #if defined(CLOCK_IP_HAS_ADC0_CLK) 1013 ADC0_CLK = CLOCK_IP_HAS_ADC0_CLK, 1014 #endif 1015 #if defined(CLOCK_IP_HAS_ADC1_CLK) 1016 ADC1_CLK = CLOCK_IP_HAS_ADC1_CLK, 1017 #endif 1018 #if defined(CLOCK_IP_HAS_ADC2_CLK) 1019 ADC2_CLK = CLOCK_IP_HAS_ADC2_CLK, 1020 #endif 1021 #if defined(CLOCK_IP_HAS_ADC3_CLK) 1022 ADC3_CLK = CLOCK_IP_HAS_ADC3_CLK, 1023 #endif 1024 #if defined(CLOCK_IP_HAS_ADC4_CLK) 1025 ADC4_CLK = CLOCK_IP_HAS_ADC4_CLK, 1026 #endif 1027 #if defined(CLOCK_IP_HAS_ADC5_CLK) 1028 ADC5_CLK = CLOCK_IP_HAS_ADC5_CLK, 1029 #endif 1030 #if defined(CLOCK_IP_HAS_ADC6_CLK) 1031 ADC6_CLK = CLOCK_IP_HAS_ADC6_CLK, 1032 #endif 1033 #if defined(CLOCK_IP_HAS_ADCBIST_CLK) 1034 ADCBIST_CLK = CLOCK_IP_HAS_ADCBIST_CLK, 1035 #endif 1036 #if defined(CLOCK_IP_HAS_AURORAPLL_DIFF_CLK) 1037 AURORAPLL_DIFF_CLK = CLOCK_IP_HAS_AURORAPLL_DIFF_CLK, 1038 #endif 1039 #if defined(CLOCK_IP_HAS_BCTU0_CLK) 1040 BCTU0_CLK = CLOCK_IP_HAS_BCTU0_CLK, 1041 #endif 1042 #if defined(CLOCK_IP_HAS_BCTU1_CLK) 1043 BCTU1_CLK = CLOCK_IP_HAS_BCTU1_CLK, 1044 #endif 1045 #if defined(CLOCK_IP_HAS_CE_SYS_DIV2_MON_CLK) 1046 CE_SYS_DIV2_MON_CLK = CLOCK_IP_HAS_CE_SYS_DIV2_MON_CLK, 1047 #endif 1048 #if defined(CLOCK_IP_HAS_CE_EDMA_CLK) 1049 CE_EDMA_CLK = CLOCK_IP_HAS_CE_EDMA_CLK, 1050 #endif 1051 #if defined(CLOCK_IP_HAS_CE_PIT0_CLK) 1052 CE_PIT0_CLK = CLOCK_IP_HAS_CE_PIT0_CLK, 1053 #endif 1054 #if defined(CLOCK_IP_HAS_CE_PIT1_CLK) 1055 CE_PIT1_CLK = CLOCK_IP_HAS_CE_PIT1_CLK, 1056 #endif 1057 #if defined(CLOCK_IP_HAS_CE_PIT2_CLK) 1058 CE_PIT2_CLK = CLOCK_IP_HAS_CE_PIT2_CLK, 1059 #endif 1060 #if defined(CLOCK_IP_HAS_CE_PIT3_CLK) 1061 CE_PIT3_CLK = CLOCK_IP_HAS_CE_PIT3_CLK, 1062 #endif 1063 #if defined(CLOCK_IP_HAS_CE_PIT4_CLK) 1064 CE_PIT4_CLK = CLOCK_IP_HAS_CE_PIT4_CLK, 1065 #endif 1066 #if defined(CLOCK_IP_HAS_CE_PIT5_CLK) 1067 CE_PIT5_CLK = CLOCK_IP_HAS_CE_PIT5_CLK, 1068 #endif 1069 #if defined(CLOCK_IP_HAS_CLKOUT_STANDBY_CLK) 1070 CLKOUT_STANDBY_CLK = CLOCK_IP_HAS_CLKOUT_STANDBY_CLK, 1071 #endif 1072 #if defined(CLOCK_IP_HAS_CLKOUT0_CLK) 1073 CLKOUT0_CLK = CLOCK_IP_HAS_CLKOUT0_CLK, 1074 #endif 1075 #if defined(CLOCK_IP_HAS_CLKOUT1_CLK) 1076 CLKOUT1_CLK = CLOCK_IP_HAS_CLKOUT1_CLK, 1077 #endif 1078 #if defined(CLOCK_IP_HAS_CLKOUT2_CLK) 1079 CLKOUT2_CLK = CLOCK_IP_HAS_CLKOUT2_CLK, 1080 #endif 1081 #if defined(CLOCK_IP_HAS_CLKOUT3_CLK) 1082 CLKOUT3_CLK = CLOCK_IP_HAS_CLKOUT3_CLK, 1083 #endif 1084 #if defined(CLOCK_IP_HAS_CLKOUT4_CLK) 1085 CLKOUT4_CLK = CLOCK_IP_HAS_CLKOUT4_CLK, 1086 #endif 1087 #if defined(CLOCK_IP_HAS_CLKOUT5_CLK) 1088 CLKOUT5_CLK = CLOCK_IP_HAS_CLKOUT5_CLK, 1089 #endif 1090 #if defined(CLOCK_IP_HAS_CMP0_CLK) 1091 CMP0_CLK = CLOCK_IP_HAS_CMP0_CLK, 1092 #endif 1093 #if defined(CLOCK_IP_HAS_CMP1_CLK) 1094 CMP1_CLK = CLOCK_IP_HAS_CMP1_CLK, 1095 #endif 1096 #if defined(CLOCK_IP_HAS_CMP2_CLK) 1097 CMP2_CLK = CLOCK_IP_HAS_CMP2_CLK, 1098 #endif 1099 #if defined(CLOCK_IP_HAS_CMU0_CLK) 1100 CMU0_CLK = CLOCK_IP_HAS_CMU0_CLK, 1101 #endif 1102 #if defined(CLOCK_IP_HAS_CMU1_CLK) 1103 CMU1_CLK = CLOCK_IP_HAS_CMU1_CLK, 1104 #endif 1105 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK) 1106 COOLFLUX_D_RAM0_CLK = CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK, 1107 #endif 1108 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK) 1109 COOLFLUX_D_RAM1_CLK = CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK, 1110 #endif 1111 #if defined(CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK) 1112 COOLFLUX_DSP16L_CLK = CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK, 1113 #endif 1114 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK) 1115 COOLFLUX_I_RAM0_CLK = CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK, 1116 #endif 1117 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK) 1118 COOLFLUX_I_RAM1_CLK = CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK, 1119 #endif 1120 #if defined(CLOCK_IP_HAS_CORE_A53_CLUSTER_0_CLK) 1121 CORE_A53_CLUSTER_0_CLK = CLOCK_IP_HAS_CORE_A53_CLUSTER_0_CLK, 1122 #endif 1123 #if defined(CLOCK_IP_HAS_CORE_A53_CLUSTER_1_CLK) 1124 CORE_A53_CLUSTER_1_CLK = CLOCK_IP_HAS_CORE_A53_CLUSTER_1_CLK, 1125 #endif 1126 #if defined(CLOCK_IP_HAS_CORE_M7_0_CLK) 1127 CORE_M7_0_CLK = CLOCK_IP_HAS_CORE_M7_0_CLK, 1128 #endif 1129 #if defined(CLOCK_IP_HAS_CORE_M7_1_CLK) 1130 CORE_M7_1_CLK = CLOCK_IP_HAS_CORE_M7_1_CLK, 1131 #endif 1132 #if defined(CLOCK_IP_HAS_CORE_M7_2_CLK) 1133 CORE_M7_2_CLK = CLOCK_IP_HAS_CORE_M7_2_CLK, 1134 #endif 1135 #if defined(CLOCK_IP_HAS_CORE_M7_3_CLK) 1136 CORE_M7_3_CLK = CLOCK_IP_HAS_CORE_M7_3_CLK, 1137 #endif 1138 #if defined(CLOCK_IP_HAS_CRC0_CLK) 1139 CRC0_CLK = CLOCK_IP_HAS_CRC0_CLK, 1140 #endif 1141 #if defined(CLOCK_IP_HAS_CTU0_CLK) 1142 CTU0_CLK = CLOCK_IP_HAS_CTU0_CLK, 1143 #endif 1144 #if defined(CLOCK_IP_HAS_CTU1_CLK) 1145 CTU1_CLK = CLOCK_IP_HAS_CTU1_CLK, 1146 #endif 1147 #if defined(CLOCK_IP_HAS_DAPB_CLK) 1148 DAPB_CLK = CLOCK_IP_HAS_DAPB_CLK, 1149 #endif 1150 #if defined(CLOCK_IP_HAS_DCM0_CLK) 1151 DCM0_CLK = CLOCK_IP_HAS_DCM0_CLK, 1152 #endif 1153 #if defined(CLOCK_IP_HAS_DMA_CRC0_CLK) 1154 DMA_CRC0_CLK = CLOCK_IP_HAS_DMA_CRC0_CLK, 1155 #endif 1156 #if defined(CLOCK_IP_HAS_DMA_CRC1_CLK) 1157 DMA_CRC1_CLK = CLOCK_IP_HAS_DMA_CRC1_CLK, 1158 #endif 1159 #if defined(CLOCK_IP_HAS_DMA0_CLK) 1160 DMA0_CLK = CLOCK_IP_HAS_DMA0_CLK, 1161 #endif 1162 #if defined(CLOCK_IP_HAS_DMA1_CLK) 1163 DMA1_CLK = CLOCK_IP_HAS_DMA1_CLK, 1164 #endif 1165 #if defined(CLOCK_IP_HAS_DMAMUX0_CLK) 1166 DMAMUX0_CLK = CLOCK_IP_HAS_DMAMUX0_CLK, 1167 #endif 1168 #if defined(CLOCK_IP_HAS_DMAMUX1_CLK) 1169 DMAMUX1_CLK = CLOCK_IP_HAS_DMAMUX1_CLK, 1170 #endif 1171 #if defined(CLOCK_IP_HAS_DMAMUX2_CLK) 1172 DMAMUX2_CLK = CLOCK_IP_HAS_DMAMUX2_CLK, 1173 #endif 1174 #if defined(CLOCK_IP_HAS_DMAMUX3_CLK) 1175 DMAMUX3_CLK = CLOCK_IP_HAS_DMAMUX3_CLK, 1176 #endif 1177 #if defined(CLOCK_IP_HAS_DMAMUX4_CLK) 1178 DMAMUX4_CLK = CLOCK_IP_HAS_DMAMUX4_CLK, 1179 #endif 1180 #if defined(CLOCK_IP_HAS_DMAMUX5_CLK) 1181 DMAMUX5_CLK = CLOCK_IP_HAS_DMAMUX5_CLK, 1182 #endif 1183 #if defined(CLOCK_IP_HAS_DSPI_MSC_CLK) 1184 DSPI_MSC_CLK = CLOCK_IP_HAS_DSPI_MSC_CLK, 1185 #endif 1186 #if defined(CLOCK_IP_HAS_EDMA_CLK) 1187 EDMA_CLK = CLOCK_IP_HAS_EDMA_CLK, 1188 #endif 1189 #if defined(CLOCK_IP_HAS_EDMA0_CLK) 1190 EDMA0_CLK = CLOCK_IP_HAS_EDMA0_CLK, 1191 #endif 1192 #if defined(CLOCK_IP_HAS_EDMA0_TCD0_CLK) 1193 EDMA0_TCD0_CLK = CLOCK_IP_HAS_EDMA0_TCD0_CLK, 1194 #endif 1195 #if defined(CLOCK_IP_HAS_EDMA0_TCD1_CLK) 1196 EDMA0_TCD1_CLK = CLOCK_IP_HAS_EDMA0_TCD1_CLK, 1197 #endif 1198 #if defined(CLOCK_IP_HAS_EDMA0_TCD2_CLK) 1199 EDMA0_TCD2_CLK = CLOCK_IP_HAS_EDMA0_TCD2_CLK, 1200 #endif 1201 #if defined(CLOCK_IP_HAS_EDMA0_TCD3_CLK) 1202 EDMA0_TCD3_CLK = CLOCK_IP_HAS_EDMA0_TCD3_CLK, 1203 #endif 1204 #if defined(CLOCK_IP_HAS_EDMA0_TCD4_CLK) 1205 EDMA0_TCD4_CLK = CLOCK_IP_HAS_EDMA0_TCD4_CLK, 1206 #endif 1207 #if defined(CLOCK_IP_HAS_EDMA0_TCD5_CLK) 1208 EDMA0_TCD5_CLK = CLOCK_IP_HAS_EDMA0_TCD5_CLK, 1209 #endif 1210 #if defined(CLOCK_IP_HAS_EDMA0_TCD6_CLK) 1211 EDMA0_TCD6_CLK = CLOCK_IP_HAS_EDMA0_TCD6_CLK, 1212 #endif 1213 #if defined(CLOCK_IP_HAS_EDMA0_TCD7_CLK) 1214 EDMA0_TCD7_CLK = CLOCK_IP_HAS_EDMA0_TCD7_CLK, 1215 #endif 1216 #if defined(CLOCK_IP_HAS_EDMA0_TCD8_CLK) 1217 EDMA0_TCD8_CLK = CLOCK_IP_HAS_EDMA0_TCD8_CLK, 1218 #endif 1219 #if defined(CLOCK_IP_HAS_EDMA0_TCD9_CLK) 1220 EDMA0_TCD9_CLK = CLOCK_IP_HAS_EDMA0_TCD9_CLK, 1221 #endif 1222 #if defined(CLOCK_IP_HAS_EDMA0_TCD10_CLK) 1223 EDMA0_TCD10_CLK = CLOCK_IP_HAS_EDMA0_TCD10_CLK, 1224 #endif 1225 #if defined(CLOCK_IP_HAS_EDMA0_TCD11_CLK) 1226 EDMA0_TCD11_CLK = CLOCK_IP_HAS_EDMA0_TCD11_CLK, 1227 #endif 1228 #if defined(CLOCK_IP_HAS_EDMA0_TCD12_CLK) 1229 EDMA0_TCD12_CLK = CLOCK_IP_HAS_EDMA0_TCD12_CLK, 1230 #endif 1231 #if defined(CLOCK_IP_HAS_EDMA0_TCD13_CLK) 1232 EDMA0_TCD13_CLK = CLOCK_IP_HAS_EDMA0_TCD13_CLK, 1233 #endif 1234 #if defined(CLOCK_IP_HAS_EDMA0_TCD14_CLK) 1235 EDMA0_TCD14_CLK = CLOCK_IP_HAS_EDMA0_TCD14_CLK, 1236 #endif 1237 #if defined(CLOCK_IP_HAS_EDMA0_TCD15_CLK) 1238 EDMA0_TCD15_CLK = CLOCK_IP_HAS_EDMA0_TCD15_CLK, 1239 #endif 1240 #if defined(CLOCK_IP_HAS_EDMA0_TCD16_CLK) 1241 EDMA0_TCD16_CLK = CLOCK_IP_HAS_EDMA0_TCD16_CLK, 1242 #endif 1243 #if defined(CLOCK_IP_HAS_EDMA0_TCD17_CLK) 1244 EDMA0_TCD17_CLK = CLOCK_IP_HAS_EDMA0_TCD17_CLK, 1245 #endif 1246 #if defined(CLOCK_IP_HAS_EDMA0_TCD18_CLK) 1247 EDMA0_TCD18_CLK = CLOCK_IP_HAS_EDMA0_TCD18_CLK, 1248 #endif 1249 #if defined(CLOCK_IP_HAS_EDMA0_TCD19_CLK) 1250 EDMA0_TCD19_CLK = CLOCK_IP_HAS_EDMA0_TCD19_CLK, 1251 #endif 1252 #if defined(CLOCK_IP_HAS_EDMA0_TCD20_CLK) 1253 EDMA0_TCD20_CLK = CLOCK_IP_HAS_EDMA0_TCD20_CLK, 1254 #endif 1255 #if defined(CLOCK_IP_HAS_EDMA0_TCD21_CLK) 1256 EDMA0_TCD21_CLK = CLOCK_IP_HAS_EDMA0_TCD21_CLK, 1257 #endif 1258 #if defined(CLOCK_IP_HAS_EDMA0_TCD22_CLK) 1259 EDMA0_TCD22_CLK = CLOCK_IP_HAS_EDMA0_TCD22_CLK, 1260 #endif 1261 #if defined(CLOCK_IP_HAS_EDMA0_TCD23_CLK) 1262 EDMA0_TCD23_CLK = CLOCK_IP_HAS_EDMA0_TCD23_CLK, 1263 #endif 1264 #if defined(CLOCK_IP_HAS_EDMA0_TCD24_CLK) 1265 EDMA0_TCD24_CLK = CLOCK_IP_HAS_EDMA0_TCD24_CLK, 1266 #endif 1267 #if defined(CLOCK_IP_HAS_EDMA0_TCD25_CLK) 1268 EDMA0_TCD25_CLK = CLOCK_IP_HAS_EDMA0_TCD25_CLK, 1269 #endif 1270 #if defined(CLOCK_IP_HAS_EDMA0_TCD26_CLK) 1271 EDMA0_TCD26_CLK = CLOCK_IP_HAS_EDMA0_TCD26_CLK, 1272 #endif 1273 #if defined(CLOCK_IP_HAS_EDMA0_TCD27_CLK) 1274 EDMA0_TCD27_CLK = CLOCK_IP_HAS_EDMA0_TCD27_CLK, 1275 #endif 1276 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 1277 EDMA0_TCD28_CLK = CLOCK_IP_HAS_EDMA0_TCD28_CLK, 1278 #endif 1279 #if defined(CLOCK_IP_HAS_EDMA0_TCD29_CLK) 1280 EDMA0_TCD29_CLK = CLOCK_IP_HAS_EDMA0_TCD29_CLK, 1281 #endif 1282 #if defined(CLOCK_IP_HAS_EDMA0_TCD30_CLK) 1283 EDMA0_TCD30_CLK = CLOCK_IP_HAS_EDMA0_TCD30_CLK, 1284 #endif 1285 #if defined(CLOCK_IP_HAS_EDMA0_TCD31_CLK) 1286 EDMA0_TCD31_CLK = CLOCK_IP_HAS_EDMA0_TCD31_CLK, 1287 #endif 1288 #if defined(CLOCK_IP_HAS_EDMA1_CLK) 1289 EDMA1_CLK = CLOCK_IP_HAS_EDMA1_CLK, 1290 #endif 1291 #if defined(CLOCK_IP_HAS_EDMA1_TCD0_CLK) 1292 EDMA1_TCD0_CLK = CLOCK_IP_HAS_EDMA1_TCD0_CLK, 1293 #endif 1294 #if defined(CLOCK_IP_HAS_EDMA1_TCD1_CLK) 1295 EDMA1_TCD1_CLK = CLOCK_IP_HAS_EDMA1_TCD1_CLK, 1296 #endif 1297 #if defined(CLOCK_IP_HAS_EDMA1_TCD2_CLK) 1298 EDMA1_TCD2_CLK = CLOCK_IP_HAS_EDMA1_TCD2_CLK, 1299 #endif 1300 #if defined(CLOCK_IP_HAS_EDMA1_TCD3_CLK) 1301 EDMA1_TCD3_CLK = CLOCK_IP_HAS_EDMA1_TCD3_CLK, 1302 #endif 1303 #if defined(CLOCK_IP_HAS_EDMA1_TCD4_CLK) 1304 EDMA1_TCD4_CLK = CLOCK_IP_HAS_EDMA1_TCD4_CLK, 1305 #endif 1306 #if defined(CLOCK_IP_HAS_EDMA1_TCD5_CLK) 1307 EDMA1_TCD5_CLK = CLOCK_IP_HAS_EDMA1_TCD5_CLK, 1308 #endif 1309 #if defined(CLOCK_IP_HAS_EDMA1_TCD6_CLK) 1310 EDMA1_TCD6_CLK = CLOCK_IP_HAS_EDMA1_TCD6_CLK, 1311 #endif 1312 #if defined(CLOCK_IP_HAS_EDMA1_TCD7_CLK) 1313 EDMA1_TCD7_CLK = CLOCK_IP_HAS_EDMA1_TCD7_CLK, 1314 #endif 1315 #if defined(CLOCK_IP_HAS_EDMA1_TCD8_CLK) 1316 EDMA1_TCD8_CLK = CLOCK_IP_HAS_EDMA1_TCD8_CLK, 1317 #endif 1318 #if defined(CLOCK_IP_HAS_EDMA1_TCD9_CLK) 1319 EDMA1_TCD9_CLK = CLOCK_IP_HAS_EDMA1_TCD9_CLK, 1320 #endif 1321 #if defined(CLOCK_IP_HAS_EDMA1_TCD10_CLK) 1322 EDMA1_TCD10_CLK = CLOCK_IP_HAS_EDMA1_TCD10_CLK, 1323 #endif 1324 #if defined(CLOCK_IP_HAS_EDMA1_TCD11_CLK) 1325 EDMA1_TCD11_CLK = CLOCK_IP_HAS_EDMA1_TCD11_CLK, 1326 #endif 1327 #if defined(CLOCK_IP_HAS_EDMA1_TCD12_CLK) 1328 EDMA1_TCD12_CLK = CLOCK_IP_HAS_EDMA1_TCD12_CLK, 1329 #endif 1330 #if defined(CLOCK_IP_HAS_EDMA1_TCD13_CLK) 1331 EDMA1_TCD13_CLK = CLOCK_IP_HAS_EDMA1_TCD13_CLK, 1332 #endif 1333 #if defined(CLOCK_IP_HAS_EDMA1_TCD14_CLK) 1334 EDMA1_TCD14_CLK = CLOCK_IP_HAS_EDMA1_TCD14_CLK, 1335 #endif 1336 #if defined(CLOCK_IP_HAS_EDMA1_TCD15_CLK) 1337 EDMA1_TCD15_CLK = CLOCK_IP_HAS_EDMA1_TCD15_CLK, 1338 #endif 1339 #if defined(CLOCK_IP_HAS_EDMA1_TCD16_CLK) 1340 EDMA1_TCD16_CLK = CLOCK_IP_HAS_EDMA1_TCD16_CLK, 1341 #endif 1342 #if defined(CLOCK_IP_HAS_EDMA1_TCD17_CLK) 1343 EDMA1_TCD17_CLK = CLOCK_IP_HAS_EDMA1_TCD17_CLK, 1344 #endif 1345 #if defined(CLOCK_IP_HAS_EDMA1_TCD18_CLK) 1346 EDMA1_TCD18_CLK = CLOCK_IP_HAS_EDMA1_TCD18_CLK, 1347 #endif 1348 #if defined(CLOCK_IP_HAS_EDMA1_TCD19_CLK) 1349 EDMA1_TCD19_CLK = CLOCK_IP_HAS_EDMA1_TCD19_CLK, 1350 #endif 1351 #if defined(CLOCK_IP_HAS_EDMA1_TCD20_CLK) 1352 EDMA1_TCD20_CLK = CLOCK_IP_HAS_EDMA1_TCD20_CLK, 1353 #endif 1354 #if defined(CLOCK_IP_HAS_EDMA1_TCD21_CLK) 1355 EDMA1_TCD21_CLK = CLOCK_IP_HAS_EDMA1_TCD21_CLK, 1356 #endif 1357 #if defined(CLOCK_IP_HAS_EDMA1_TCD22_CLK) 1358 EDMA1_TCD22_CLK = CLOCK_IP_HAS_EDMA1_TCD22_CLK, 1359 #endif 1360 #if defined(CLOCK_IP_HAS_EDMA1_TCD23_CLK) 1361 EDMA1_TCD23_CLK = CLOCK_IP_HAS_EDMA1_TCD23_CLK, 1362 #endif 1363 #if defined(CLOCK_IP_HAS_EDMA1_TCD24_CLK) 1364 EDMA1_TCD24_CLK = CLOCK_IP_HAS_EDMA1_TCD24_CLK, 1365 #endif 1366 #if defined(CLOCK_IP_HAS_EDMA1_TCD25_CLK) 1367 EDMA1_TCD25_CLK = CLOCK_IP_HAS_EDMA1_TCD25_CLK, 1368 #endif 1369 #if defined(CLOCK_IP_HAS_EDMA1_TCD26_CLK) 1370 EDMA1_TCD26_CLK = CLOCK_IP_HAS_EDMA1_TCD26_CLK, 1371 #endif 1372 #if defined(CLOCK_IP_HAS_EDMA1_TCD27_CLK) 1373 EDMA1_TCD27_CLK = CLOCK_IP_HAS_EDMA1_TCD27_CLK, 1374 #endif 1375 #if defined(CLOCK_IP_HAS_EDMA1_TCD28_CLK) 1376 EDMA1_TCD28_CLK = CLOCK_IP_HAS_EDMA1_TCD28_CLK, 1377 #endif 1378 #if defined(CLOCK_IP_HAS_EDMA1_TCD29_CLK) 1379 EDMA1_TCD29_CLK = CLOCK_IP_HAS_EDMA1_TCD29_CLK, 1380 #endif 1381 #if defined(CLOCK_IP_HAS_EDMA1_TCD30_CLK) 1382 EDMA1_TCD30_CLK = CLOCK_IP_HAS_EDMA1_TCD30_CLK, 1383 #endif 1384 #if defined(CLOCK_IP_HAS_EDMA1_TCD31_CLK) 1385 EDMA1_TCD31_CLK = CLOCK_IP_HAS_EDMA1_TCD31_CLK, 1386 #endif 1387 #if defined(CLOCK_IP_HAS_EDMA3_CLK) 1388 EDMA3_CLK = CLOCK_IP_HAS_EDMA3_CLK, 1389 #endif 1390 #if defined(CLOCK_IP_HAS_EDMA4_CLK) 1391 EDMA4_CLK = CLOCK_IP_HAS_EDMA4_CLK, 1392 #endif 1393 #if defined(CLOCK_IP_HAS_EDMA5_CLK) 1394 EDMA5_CLK = CLOCK_IP_HAS_EDMA5_CLK, 1395 #endif 1396 #if defined(CLOCK_IP_HAS_EFLEX_PWM0_CLK) 1397 EFLEX_PWM0_CLK = CLOCK_IP_HAS_EFLEX_PWM0_CLK, 1398 #endif 1399 #if defined(CLOCK_IP_HAS_EFLEX_PWM1_CLK) 1400 EFLEX_PWM1_CLK = CLOCK_IP_HAS_EFLEX_PWM1_CLK, 1401 #endif 1402 #if defined(CLOCK_IP_HAS_FDMA0_CLK) 1403 FDMA0_CLK = CLOCK_IP_HAS_FDMA0_CLK, 1404 #endif 1405 #if defined(CLOCK_IP_HAS_ENET_CLK) 1406 ENET_CLK = CLOCK_IP_HAS_ENET_CLK, 1407 #endif 1408 #if defined(CLOCK_IP_HAS_EIM_CLK) 1409 EIM_CLK = CLOCK_IP_HAS_EIM_CLK, 1410 #endif 1411 #if defined(CLOCK_IP_HAS_EIM0_CLK) 1412 EIM0_CLK = CLOCK_IP_HAS_EIM0_CLK, 1413 #endif 1414 #if defined(CLOCK_IP_HAS_EIM1_CLK) 1415 EIM1_CLK = CLOCK_IP_HAS_EIM1_CLK, 1416 #endif 1417 #if defined(CLOCK_IP_HAS_EIM2_CLK) 1418 EIM2_CLK = CLOCK_IP_HAS_EIM2_CLK, 1419 #endif 1420 #if defined(CLOCK_IP_HAS_EIM3_CLK) 1421 EIM3_CLK = CLOCK_IP_HAS_EIM3_CLK, 1422 #endif 1423 #if defined(CLOCK_IP_HAS_EIM_BBE32DSP_CLK) 1424 EIM_BBE32DSP_CLK = CLOCK_IP_HAS_EIM_BBE32DSP_CLK, 1425 #endif 1426 #if defined(CLOCK_IP_HAS_EIM_LAX0_CLK) 1427 EIM_LAX0_CLK = CLOCK_IP_HAS_EIM_LAX0_CLK, 1428 #endif 1429 #if defined(CLOCK_IP_HAS_EIM_LAX1_CLK) 1430 EIM_LAX1_CLK = CLOCK_IP_HAS_EIM_LAX1_CLK, 1431 #endif 1432 #if defined(CLOCK_IP_HAS_EIM_PER1_CLK) 1433 EIM_PER1_CLK = CLOCK_IP_HAS_EIM_PER1_CLK, 1434 #endif 1435 #if defined(CLOCK_IP_HAS_ENET0_CLK) 1436 ENET0_CLK = CLOCK_IP_HAS_ENET0_CLK, 1437 #endif 1438 #if defined(CLOCK_IP_HAS_ENET1_CLK) 1439 ENET1_CLK = CLOCK_IP_HAS_ENET1_CLK, 1440 #endif 1441 #if defined(CLOCK_IP_HAS_EMAC_RX_CLK) 1442 EMAC_RX_CLK = CLOCK_IP_HAS_EMAC_RX_CLK, 1443 #endif 1444 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK) 1445 EMAC_TS_CLK = CLOCK_IP_HAS_EMAC_TS_CLK, 1446 #endif 1447 #if defined(CLOCK_IP_HAS_EMAC_TX_CLK) 1448 EMAC_TX_CLK = CLOCK_IP_HAS_EMAC_TX_CLK, 1449 #endif 1450 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK) 1451 EMAC_TX_RMII_CLK = CLOCK_IP_HAS_EMAC_TX_RMII_CLK, 1452 #endif 1453 #if defined(CLOCK_IP_HAS_EMAC0_RX_CLK) 1454 EMAC0_RX_CLK = CLOCK_IP_HAS_EMAC0_RX_CLK, 1455 #endif 1456 #if defined(CLOCK_IP_HAS_EMAC0_TS_CLK) 1457 EMAC0_TS_CLK = CLOCK_IP_HAS_EMAC0_TS_CLK, 1458 #endif 1459 #if defined(CLOCK_IP_HAS_EMAC0_TX_CLK) 1460 EMAC0_TX_CLK = CLOCK_IP_HAS_EMAC0_TX_CLK, 1461 #endif 1462 #if defined(CLOCK_IP_HAS_EMIOS0_CLK) 1463 EMIOS0_CLK = CLOCK_IP_HAS_EMIOS0_CLK, 1464 #endif 1465 #if defined(CLOCK_IP_HAS_EMIOS1_CLK) 1466 EMIOS1_CLK = CLOCK_IP_HAS_EMIOS1_CLK, 1467 #endif 1468 #if defined(CLOCK_IP_HAS_EMIOS2_CLK) 1469 EMIOS2_CLK = CLOCK_IP_HAS_EMIOS2_CLK, 1470 #endif 1471 #if defined(CLOCK_IP_HAS_ERM0_CLK) 1472 ERM0_CLK = CLOCK_IP_HAS_ERM0_CLK, 1473 #endif 1474 #if defined(CLOCK_IP_HAS_ERM1_CLK) 1475 ERM1_CLK = CLOCK_IP_HAS_ERM1_CLK, 1476 #endif 1477 #if defined(CLOCK_IP_HAS_ERM_CPU0_CLK) 1478 ERM_CPU0_CLK = CLOCK_IP_HAS_ERM_CPU0_CLK, 1479 #endif 1480 #if defined(CLOCK_IP_HAS_ERM_CPU1_CLK) 1481 ERM_CPU1_CLK = CLOCK_IP_HAS_ERM_CPU1_CLK, 1482 #endif 1483 #if defined(CLOCK_IP_HAS_ERM_CPU2_CLK) 1484 ERM_CPU2_CLK = CLOCK_IP_HAS_ERM_CPU2_CLK, 1485 #endif 1486 #if defined(CLOCK_IP_HAS_ERM_EDMA0_CLK) 1487 ERM_EDMA0_CLK = CLOCK_IP_HAS_ERM_EDMA0_CLK, 1488 #endif 1489 #if defined(CLOCK_IP_HAS_ERM_EDMA1_CLK) 1490 ERM_EDMA1_CLK = CLOCK_IP_HAS_ERM_EDMA1_CLK, 1491 #endif 1492 #if defined(CLOCK_IP_HAS_ERM_LAX0_CLK) 1493 ERM_LAX0_CLK = CLOCK_IP_HAS_ERM_LAX0_CLK, 1494 #endif 1495 #if defined(CLOCK_IP_HAS_ERM_LAX1_CLK) 1496 ERM_LAX1_CLK = CLOCK_IP_HAS_ERM_LAX1_CLK, 1497 #endif 1498 #if defined(CLOCK_IP_HAS_ERM_PER_CLK) 1499 ERM_PER_CLK = CLOCK_IP_HAS_ERM_PER_CLK, 1500 #endif 1501 #if defined(CLOCK_IP_HAS_ERM_PER1_CLK) 1502 ERM_PER1_CLK = CLOCK_IP_HAS_ERM_PER1_CLK, 1503 #endif 1504 #if defined(CLOCK_IP_HAS_ERM_CLK) 1505 ERM_CLK = CLOCK_IP_HAS_ERM_CLK, 1506 #endif 1507 #if defined(CLOCK_IP_HAS_EWM0_CLK) 1508 EWM0_CLK = CLOCK_IP_HAS_EWM0_CLK, 1509 #endif 1510 #if defined(CLOCK_IP_HAS_FIRC_MON1_CLK) 1511 FIRC_MON1_CLK = CLOCK_IP_HAS_FIRC_MON1_CLK, 1512 #endif 1513 #if defined(CLOCK_IP_HAS_FIRC_MON2_CLK) 1514 FIRC_MON2_CLK = CLOCK_IP_HAS_FIRC_MON2_CLK, 1515 #endif 1516 #if defined(CLOCK_IP_HAS_FLASH0_CLK) 1517 FLASH0_CLK = CLOCK_IP_HAS_FLASH0_CLK, 1518 #endif 1519 #if defined(CLOCK_IP_HAS_CAN_PE_CLK) 1520 CAN_PE_CLK = CLOCK_IP_HAS_CAN_PE_CLK, 1521 #endif 1522 #if defined(CLOCK_IP_HAS_FLEXCAN_CLK) 1523 FLEXCAN_CLK = CLOCK_IP_HAS_FLEXCAN_CLK, 1524 #endif 1525 #if defined(CLOCK_IP_HAS_FLEXCAN0_CLK) 1526 FLEXCAN0_CLK = CLOCK_IP_HAS_FLEXCAN0_CLK, 1527 #endif 1528 #if defined(CLOCK_IP_HAS_FLEXCAN1_CLK) 1529 FLEXCAN1_CLK = CLOCK_IP_HAS_FLEXCAN1_CLK, 1530 #endif 1531 #if defined(CLOCK_IP_HAS_FLEXCAN2_CLK) 1532 FLEXCAN2_CLK = CLOCK_IP_HAS_FLEXCAN2_CLK, 1533 #endif 1534 #if defined(CLOCK_IP_HAS_FLEXCAN3_CLK) 1535 FLEXCAN3_CLK = CLOCK_IP_HAS_FLEXCAN3_CLK, 1536 #endif 1537 #if defined(CLOCK_IP_HAS_FLEXCAN4_CLK) 1538 FLEXCAN4_CLK = CLOCK_IP_HAS_FLEXCAN4_CLK, 1539 #endif 1540 #if defined(CLOCK_IP_HAS_FLEXCAN5_CLK) 1541 FLEXCAN5_CLK = CLOCK_IP_HAS_FLEXCAN5_CLK, 1542 #endif 1543 #if defined(CLOCK_IP_HAS_FLEXCAN6_CLK) 1544 FLEXCAN6_CLK = CLOCK_IP_HAS_FLEXCAN6_CLK, 1545 #endif 1546 #if defined(CLOCK_IP_HAS_FLEXCAN7_CLK) 1547 FLEXCAN7_CLK = CLOCK_IP_HAS_FLEXCAN7_CLK, 1548 #endif 1549 #if defined(CLOCK_IP_HAS_FLEXCAN8_CLK) 1550 FLEXCAN8_CLK = CLOCK_IP_HAS_FLEXCAN8_CLK, 1551 #endif 1552 #if defined(CLOCK_IP_HAS_FLEXCAN9_CLK) 1553 FLEXCAN9_CLK = CLOCK_IP_HAS_FLEXCAN9_CLK, 1554 #endif 1555 #if defined(CLOCK_IP_HAS_FLEXCAN10_CLK) 1556 FLEXCAN10_CLK = CLOCK_IP_HAS_FLEXCAN10_CLK, 1557 #endif 1558 #if defined(CLOCK_IP_HAS_FLEXCAN11_CLK) 1559 FLEXCAN11_CLK = CLOCK_IP_HAS_FLEXCAN11_CLK, 1560 #endif 1561 #if defined(CLOCK_IP_HAS_FLEXCAN12_CLK) 1562 FLEXCAN12_CLK = CLOCK_IP_HAS_FLEXCAN12_CLK, 1563 #endif 1564 #if defined(CLOCK_IP_HAS_FLEXCAN13_CLK) 1565 FLEXCAN13_CLK = CLOCK_IP_HAS_FLEXCAN13_CLK, 1566 #endif 1567 #if defined(CLOCK_IP_HAS_FLEXCAN14_CLK) 1568 FLEXCAN14_CLK = CLOCK_IP_HAS_FLEXCAN14_CLK, 1569 #endif 1570 #if defined(CLOCK_IP_HAS_FLEXCAN15_CLK) 1571 FLEXCAN15_CLK = CLOCK_IP_HAS_FLEXCAN15_CLK, 1572 #endif 1573 #if defined(CLOCK_IP_HAS_FLEXCAN16_CLK) 1574 FLEXCAN16_CLK = CLOCK_IP_HAS_FLEXCAN16_CLK, 1575 #endif 1576 #if defined(CLOCK_IP_HAS_FLEXCAN17_CLK) 1577 FLEXCAN17_CLK = CLOCK_IP_HAS_FLEXCAN17_CLK, 1578 #endif 1579 #if defined(CLOCK_IP_HAS_FLEXCAN18_CLK) 1580 FLEXCAN18_CLK = CLOCK_IP_HAS_FLEXCAN18_CLK, 1581 #endif 1582 #if defined(CLOCK_IP_HAS_FLEXCAN19_CLK) 1583 FLEXCAN19_CLK = CLOCK_IP_HAS_FLEXCAN19_CLK, 1584 #endif 1585 #if defined(CLOCK_IP_HAS_FLEXCAN20_CLK) 1586 FLEXCAN20_CLK = CLOCK_IP_HAS_FLEXCAN20_CLK, 1587 #endif 1588 #if defined(CLOCK_IP_HAS_FLEXCAN21_CLK) 1589 FLEXCAN21_CLK = CLOCK_IP_HAS_FLEXCAN21_CLK, 1590 #endif 1591 #if defined(CLOCK_IP_HAS_FLEXCAN22_CLK) 1592 FLEXCAN22_CLK = CLOCK_IP_HAS_FLEXCAN22_CLK, 1593 #endif 1594 #if defined(CLOCK_IP_HAS_FLEXCAN23_CLK) 1595 FLEXCAN23_CLK = CLOCK_IP_HAS_FLEXCAN23_CLK, 1596 #endif 1597 #if defined(CLOCK_IP_HAS_FLEXCANA_CLK) 1598 FLEXCANA_CLK = CLOCK_IP_HAS_FLEXCANA_CLK, 1599 #endif 1600 #if defined(CLOCK_IP_HAS_FLEXCANB_CLK) 1601 FLEXCANB_CLK = CLOCK_IP_HAS_FLEXCANB_CLK, 1602 #endif 1603 #if defined(CLOCK_IP_HAS_FlexIO_CLK) 1604 FlexIO_CLK = CLOCK_IP_HAS_FlexIO_CLK, 1605 #endif 1606 #if defined(CLOCK_IP_HAS_FlexIO0_CLK) 1607 FlexIO0_CLK = CLOCK_IP_HAS_FlexIO0_CLK, 1608 #endif 1609 #if defined(CLOCK_IP_HAS_FLEXIO0_CLK) 1610 FLEXIO0_CLK = CLOCK_IP_HAS_FLEXIO0_CLK, 1611 #endif 1612 #if defined(CLOCK_IP_HAS_FLEXRAY_CLK) 1613 FLEXRAY_CLK = CLOCK_IP_HAS_FLEXRAY_CLK, 1614 #endif 1615 #if defined(CLOCK_IP_HAS_FLEXTIMERA_CLK) 1616 FLEXTIMERA_CLK = CLOCK_IP_HAS_FLEXTIMERA_CLK, 1617 #endif 1618 #if defined(CLOCK_IP_HAS_FLEXTIMERB_CLK) 1619 FLEXTIMERB_CLK = CLOCK_IP_HAS_FLEXTIMERB_CLK, 1620 #endif 1621 #if defined(CLOCK_IP_HAS_FRAY0_CLK) 1622 FRAY0_CLK = CLOCK_IP_HAS_FRAY0_CLK, 1623 #endif 1624 #if defined(CLOCK_IP_HAS_FRAY1_CLK) 1625 FRAY1_CLK = CLOCK_IP_HAS_FRAY1_CLK, 1626 #endif 1627 #if defined(CLOCK_IP_HAS_FTFC_CLK) 1628 FTFC_CLK = CLOCK_IP_HAS_FTFC_CLK, 1629 #endif 1630 #if defined(CLOCK_IP_HAS_FTFM_CLK) 1631 FTFM_CLK = CLOCK_IP_HAS_FTFM_CLK, 1632 #endif 1633 #if defined(CLOCK_IP_HAS_FTIMER0_CLK) 1634 FTIMER0_CLK = CLOCK_IP_HAS_FTIMER0_CLK, 1635 #endif 1636 #if defined(CLOCK_IP_HAS_FTIMER1_CLK) 1637 FTIMER1_CLK = CLOCK_IP_HAS_FTIMER1_CLK, 1638 #endif 1639 #if defined(CLOCK_IP_HAS_FTM0_CLK) 1640 FTM0_CLK = CLOCK_IP_HAS_FTM0_CLK, 1641 #endif 1642 #if defined(CLOCK_IP_HAS_FTM1_CLK) 1643 FTM1_CLK = CLOCK_IP_HAS_FTM1_CLK, 1644 #endif 1645 #if defined(CLOCK_IP_HAS_FTM2_CLK) 1646 FTM2_CLK = CLOCK_IP_HAS_FTM2_CLK, 1647 #endif 1648 #if defined(CLOCK_IP_HAS_FTM3_CLK) 1649 FTM3_CLK = CLOCK_IP_HAS_FTM3_CLK, 1650 #endif 1651 #if defined(CLOCK_IP_HAS_FTM4_CLK) 1652 FTM4_CLK = CLOCK_IP_HAS_FTM4_CLK, 1653 #endif 1654 #if defined(CLOCK_IP_HAS_FTM5_CLK) 1655 FTM5_CLK = CLOCK_IP_HAS_FTM5_CLK, 1656 #endif 1657 #if defined(CLOCK_IP_HAS_FTM6_CLK) 1658 FTM6_CLK = CLOCK_IP_HAS_FTM6_CLK, 1659 #endif 1660 #if defined(CLOCK_IP_HAS_FTM7_CLK) 1661 FTM7_CLK = CLOCK_IP_HAS_FTM7_CLK, 1662 #endif 1663 #if defined(CLOCK_IP_HAS_GLB_LBIST_CLK) 1664 GLB_LBIST_CLK = CLOCK_IP_HAS_GLB_LBIST_CLK, 1665 #endif 1666 #if defined(CLOCK_IP_HAS_GMAC0_CLK) 1667 GMAC0_CLK = CLOCK_IP_HAS_GMAC0_CLK, 1668 #endif 1669 #if defined(CLOCK_IP_HAS_GMAC_TS_CLK) 1670 GMAC_TS_CLK = CLOCK_IP_HAS_GMAC_TS_CLK, 1671 #endif 1672 #if defined(CLOCK_IP_HAS_GMAC_RX_CLK) 1673 GMAC_RX_CLK = CLOCK_IP_HAS_GMAC_RX_CLK, 1674 #endif 1675 #if defined(CLOCK_IP_HAS_GMAC_TX_CLK) 1676 GMAC_TX_CLK = CLOCK_IP_HAS_GMAC_TX_CLK, 1677 #endif 1678 #if defined(CLOCK_IP_HAS_GMAC0_RX_CLK) 1679 GMAC0_RX_CLK = CLOCK_IP_HAS_GMAC0_RX_CLK, 1680 #endif 1681 #if defined(CLOCK_IP_HAS_GMAC0_TX_CLK) 1682 GMAC0_TX_CLK = CLOCK_IP_HAS_GMAC0_TX_CLK, 1683 #endif 1684 #if defined(CLOCK_IP_HAS_GMAC0_TS_CLK) 1685 GMAC0_TS_CLK = CLOCK_IP_HAS_GMAC0_TS_CLK, 1686 #endif 1687 #if defined(CLOCK_IP_HAS_GMAC0_TX_RMII_CLK) 1688 GMAC0_TX_RMII_CLK = CLOCK_IP_HAS_GMAC0_TX_RMII_CLK, 1689 #endif 1690 #if defined(CLOCK_IP_HAS_GMAC0_MII_RGMII_RX_CLK) 1691 GMAC0_MII_RGMII_RX_CLK = CLOCK_IP_HAS_GMAC0_MII_RGMII_RX_CLK, 1692 #endif 1693 #if defined(CLOCK_IP_HAS_GMAC0_MII_RMII_RGMII_TX_CLK) 1694 GMAC0_MII_RMII_RGMII_TX_CLK = CLOCK_IP_HAS_GMAC0_MII_RMII_RGMII_TX_CLK, 1695 #endif 1696 #if defined(CLOCK_IP_HAS_GMAC1_MII_RGMII_RX_CLK) 1697 GMAC1_MII_RGMII_RX_CLK = CLOCK_IP_HAS_GMAC1_MII_RGMII_RX_CLK, 1698 #endif 1699 #if defined(CLOCK_IP_HAS_GMAC1_RX_CLK) 1700 GMAC1_RX_CLK = CLOCK_IP_HAS_GMAC1_RX_CLK, 1701 #endif 1702 #if defined(CLOCK_IP_HAS_GMAC1_TX_CLK) 1703 GMAC1_TX_CLK = CLOCK_IP_HAS_GMAC1_TX_CLK, 1704 #endif 1705 #if defined(CLOCK_IP_HAS_GMAC1_TS_CLK) 1706 GMAC1_TS_CLK = CLOCK_IP_HAS_GMAC1_TS_CLK, 1707 #endif 1708 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK) 1709 GMAC1_RMII_CLK = CLOCK_IP_HAS_GMAC1_RMII_CLK, 1710 #endif 1711 #if defined(CLOCK_IP_HAS_GMAC1_MII_RMII_RGMII_TX_CLK) 1712 GMAC1_MII_RMII_RGMII_TX_CLK = CLOCK_IP_HAS_GMAC1_MII_RMII_RGMII_TX_CLK, 1713 #endif 1714 #if defined(CLOCK_IP_HAS_GPIO0_CLK) 1715 GPIO0_CLK = CLOCK_IP_HAS_GPIO0_CLK, 1716 #endif 1717 #if defined(CLOCK_IP_HAS_GTM_CLK) 1718 GTM_CLK = CLOCK_IP_HAS_GTM_CLK, 1719 #endif 1720 #if defined(CLOCK_IP_HAS_IDIV0_CLK) 1721 IDIV0_CLK = CLOCK_IP_HAS_IDIV0_CLK, 1722 #endif 1723 #if defined(CLOCK_IP_HAS_IDIV1_CLK) 1724 IDIV1_CLK = CLOCK_IP_HAS_IDIV1_CLK, 1725 #endif 1726 #if defined(CLOCK_IP_HAS_IDIV2_CLK) 1727 IDIV2_CLK = CLOCK_IP_HAS_IDIV2_CLK, 1728 #endif 1729 #if defined(CLOCK_IP_HAS_IDIV3_CLK) 1730 IDIV3_CLK = CLOCK_IP_HAS_IDIV3_CLK, 1731 #endif 1732 #if defined(CLOCK_IP_HAS_IDIV4_CLK) 1733 IDIV4_CLK = CLOCK_IP_HAS_IDIV4_CLK, 1734 #endif 1735 #if defined(CLOCK_IP_HAS_IGF0_CLK) 1736 IGF0_CLK = CLOCK_IP_HAS_IGF0_CLK, 1737 #endif 1738 #if defined(CLOCK_IP_HAS_IIIC0_CLK) 1739 IIIC0_CLK = CLOCK_IP_HAS_IIIC0_CLK, 1740 #endif 1741 #if defined(CLOCK_IP_HAS_IIIC1_CLK) 1742 IIIC1_CLK = CLOCK_IP_HAS_IIIC1_CLK, 1743 #endif 1744 #if defined(CLOCK_IP_HAS_IIIC2_CLK) 1745 IIIC2_CLK = CLOCK_IP_HAS_IIIC2_CLK, 1746 #endif 1747 #if defined(CLOCK_IP_HAS_IIC0_CLK) 1748 IIC0_CLK = CLOCK_IP_HAS_IIC0_CLK, 1749 #endif 1750 #if defined(CLOCK_IP_HAS_IIC1_CLK) 1751 IIC1_CLK = CLOCK_IP_HAS_IIC1_CLK, 1752 #endif 1753 #if defined(CLOCK_IP_HAS_IIC2_CLK) 1754 IIC2_CLK = CLOCK_IP_HAS_IIC2_CLK, 1755 #endif 1756 #if defined(CLOCK_IP_HAS_IIC3_CLK) 1757 IIC3_CLK = CLOCK_IP_HAS_IIC3_CLK, 1758 #endif 1759 #if defined(CLOCK_IP_HAS_IIC4_CLK) 1760 IIC4_CLK = CLOCK_IP_HAS_IIC4_CLK, 1761 #endif 1762 #if defined(CLOCK_IP_HAS_INTM_CLK) 1763 INTM_CLK = CLOCK_IP_HAS_INTM_CLK, 1764 #endif 1765 #if defined(CLOCK_IP_HAS_ISO_CLK) 1766 ISO_CLK = CLOCK_IP_HAS_ISO_CLK, 1767 #endif 1768 #if defined(CLOCK_IP_HAS_LBIST0_CLK) 1769 LBIST0_CLK = CLOCK_IP_HAS_LBIST0_CLK, 1770 #endif 1771 #if defined(CLOCK_IP_HAS_LBIST1_CLK) 1772 LBIST1_CLK = CLOCK_IP_HAS_LBIST1_CLK, 1773 #endif 1774 #if defined(CLOCK_IP_HAS_LBIST2_CLK) 1775 LBIST2_CLK = CLOCK_IP_HAS_LBIST2_CLK, 1776 #endif 1777 #if defined(CLOCK_IP_HAS_LBIST3_CLK) 1778 LBIST3_CLK = CLOCK_IP_HAS_LBIST3_CLK, 1779 #endif 1780 #if defined(CLOCK_IP_HAS_LBIST4_CLK) 1781 LBIST4_CLK = CLOCK_IP_HAS_LBIST4_CLK, 1782 #endif 1783 #if defined(CLOCK_IP_HAS_LBIST5_CLK) 1784 LBIST5_CLK = CLOCK_IP_HAS_LBIST5_CLK, 1785 #endif 1786 #if defined(CLOCK_IP_HAS_LBIST6_CLK) 1787 LBIST6_CLK = CLOCK_IP_HAS_LBIST6_CLK, 1788 #endif 1789 #if defined(CLOCK_IP_HAS_LBIST7_CLK) 1790 LBIST7_CLK = CLOCK_IP_HAS_LBIST7_CLK, 1791 #endif 1792 #if defined(CLOCK_IP_HAS_LCU0_CLK) 1793 LCU0_CLK = CLOCK_IP_HAS_LCU0_CLK, 1794 #endif 1795 #if defined(CLOCK_IP_HAS_LCU1_CLK) 1796 LCU1_CLK = CLOCK_IP_HAS_LCU1_CLK, 1797 #endif 1798 #if defined(CLOCK_IP_HAS_LIN_BAUD_CLK) 1799 LIN_BAUD_CLK = CLOCK_IP_HAS_LIN_BAUD_CLK, 1800 #endif 1801 #if defined(CLOCK_IP_HAS_LINFLEXD_CLK) 1802 LINFLEXD_CLK = CLOCK_IP_HAS_LINFLEXD_CLK, 1803 #endif 1804 #if defined(CLOCK_IP_HAS_LIN0_CLK) 1805 LIN0_CLK = CLOCK_IP_HAS_LIN0_CLK, 1806 #endif 1807 #if defined(CLOCK_IP_HAS_LIN1_CLK) 1808 LIN1_CLK = CLOCK_IP_HAS_LIN1_CLK, 1809 #endif 1810 #if defined(CLOCK_IP_HAS_LIN2_CLK) 1811 LIN2_CLK = CLOCK_IP_HAS_LIN2_CLK, 1812 #endif 1813 #if defined(CLOCK_IP_HAS_LIN3_CLK) 1814 LIN3_CLK = CLOCK_IP_HAS_LIN3_CLK, 1815 #endif 1816 #if defined(CLOCK_IP_HAS_LIN4_CLK) 1817 LIN4_CLK = CLOCK_IP_HAS_LIN4_CLK, 1818 #endif 1819 #if defined(CLOCK_IP_HAS_LIN5_CLK) 1820 LIN5_CLK = CLOCK_IP_HAS_LIN5_CLK, 1821 #endif 1822 #if defined(CLOCK_IP_HAS_LIN6_CLK) 1823 LIN6_CLK = CLOCK_IP_HAS_LIN6_CLK, 1824 #endif 1825 #if defined(CLOCK_IP_HAS_LIN7_CLK) 1826 LIN7_CLK = CLOCK_IP_HAS_LIN7_CLK, 1827 #endif 1828 #if defined(CLOCK_IP_HAS_LIN8_CLK) 1829 LIN8_CLK = CLOCK_IP_HAS_LIN8_CLK, 1830 #endif 1831 #if defined(CLOCK_IP_HAS_LIN9_CLK) 1832 LIN9_CLK = CLOCK_IP_HAS_LIN9_CLK, 1833 #endif 1834 #if defined(CLOCK_IP_HAS_LIN10_CLK) 1835 LIN10_CLK = CLOCK_IP_HAS_LIN10_CLK, 1836 #endif 1837 #if defined(CLOCK_IP_HAS_LIN11_CLK) 1838 LIN11_CLK = CLOCK_IP_HAS_LIN11_CLK, 1839 #endif 1840 #if defined(CLOCK_IP_HAS_LFAST_REF_CLK) 1841 LFAST_REF_CLK = CLOCK_IP_HAS_LFAST_REF_CLK, 1842 #endif 1843 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK) 1844 LFAST_REF_EXT_CLK = CLOCK_IP_HAS_LFAST_REF_EXT_CLK, 1845 #endif 1846 #if defined(CLOCK_IP_HAS_LPI2C0_CLK) 1847 LPI2C0_CLK = CLOCK_IP_HAS_LPI2C0_CLK, 1848 #endif 1849 #if defined(CLOCK_IP_HAS_LPI2C1_CLK) 1850 LPI2C1_CLK = CLOCK_IP_HAS_LPI2C1_CLK, 1851 #endif 1852 #if defined(CLOCK_IP_HAS_LPIT0_CLK) 1853 LPIT0_CLK = CLOCK_IP_HAS_LPIT0_CLK, 1854 #endif 1855 #if defined(CLOCK_IP_HAS_LPSPI_CLK) 1856 LPSPI_CLK = CLOCK_IP_HAS_LPSPI_CLK, 1857 #endif 1858 #if defined(CLOCK_IP_HAS_LPSPI0_CLK) 1859 LPSPI0_CLK = CLOCK_IP_HAS_LPSPI0_CLK, 1860 #endif 1861 #if defined(CLOCK_IP_HAS_LPSPI1_CLK) 1862 LPSPI1_CLK = CLOCK_IP_HAS_LPSPI1_CLK, 1863 #endif 1864 #if defined(CLOCK_IP_HAS_LPSPI2_CLK) 1865 LPSPI2_CLK = CLOCK_IP_HAS_LPSPI2_CLK, 1866 #endif 1867 #if defined(CLOCK_IP_HAS_LPSPI3_CLK) 1868 LPSPI3_CLK = CLOCK_IP_HAS_LPSPI3_CLK, 1869 #endif 1870 #if defined(CLOCK_IP_HAS_LPSPI4_CLK) 1871 LPSPI4_CLK = CLOCK_IP_HAS_LPSPI4_CLK, 1872 #endif 1873 #if defined(CLOCK_IP_HAS_LPSPI5_CLK) 1874 LPSPI5_CLK = CLOCK_IP_HAS_LPSPI5_CLK, 1875 #endif 1876 #if defined(CLOCK_IP_HAS_LPTMR0_CLK) 1877 LPTMR0_CLK = CLOCK_IP_HAS_LPTMR0_CLK, 1878 #endif 1879 #if defined(CLOCK_IP_HAS_LPUART0_CLK) 1880 LPUART0_CLK = CLOCK_IP_HAS_LPUART0_CLK, 1881 #endif 1882 #if defined(CLOCK_IP_HAS_LPUART1_CLK) 1883 LPUART1_CLK = CLOCK_IP_HAS_LPUART1_CLK, 1884 #endif 1885 #if defined(CLOCK_IP_HAS_LPUART2_CLK) 1886 LPUART2_CLK = CLOCK_IP_HAS_LPUART2_CLK, 1887 #endif 1888 #if defined(CLOCK_IP_HAS_LPUART3_CLK) 1889 LPUART3_CLK = CLOCK_IP_HAS_LPUART3_CLK, 1890 #endif 1891 #if defined(CLOCK_IP_HAS_LPUART4_CLK) 1892 LPUART4_CLK = CLOCK_IP_HAS_LPUART4_CLK, 1893 #endif 1894 #if defined(CLOCK_IP_HAS_LPUART5_CLK) 1895 LPUART5_CLK = CLOCK_IP_HAS_LPUART5_CLK, 1896 #endif 1897 #if defined(CLOCK_IP_HAS_LPUART6_CLK) 1898 LPUART6_CLK = CLOCK_IP_HAS_LPUART6_CLK, 1899 #endif 1900 #if defined(CLOCK_IP_HAS_LPUART7_CLK) 1901 LPUART7_CLK = CLOCK_IP_HAS_LPUART7_CLK, 1902 #endif 1903 #if defined(CLOCK_IP_HAS_LPUART8_CLK) 1904 LPUART8_CLK = CLOCK_IP_HAS_LPUART8_CLK, 1905 #endif 1906 #if defined(CLOCK_IP_HAS_LPUART9_CLK) 1907 LPUART9_CLK = CLOCK_IP_HAS_LPUART9_CLK, 1908 #endif 1909 #if defined(CLOCK_IP_HAS_LPUART10_CLK) 1910 LPUART10_CLK = CLOCK_IP_HAS_LPUART10_CLK, 1911 #endif 1912 #if defined(CLOCK_IP_HAS_LPUART11_CLK) 1913 LPUART11_CLK = CLOCK_IP_HAS_LPUART11_CLK, 1914 #endif 1915 #if defined(CLOCK_IP_HAS_LPUART12_CLK) 1916 LPUART12_CLK = CLOCK_IP_HAS_LPUART12_CLK, 1917 #endif 1918 #if defined(CLOCK_IP_HAS_LPUART13_CLK) 1919 LPUART13_CLK = CLOCK_IP_HAS_LPUART13_CLK, 1920 #endif 1921 #if defined(CLOCK_IP_HAS_LPUART14_CLK) 1922 LPUART14_CLK = CLOCK_IP_HAS_LPUART14_CLK, 1923 #endif 1924 #if defined(CLOCK_IP_HAS_LPUART15_CLK) 1925 LPUART15_CLK = CLOCK_IP_HAS_LPUART15_CLK, 1926 #endif 1927 #if defined(CLOCK_IP_HAS_LPUART_MSC_CLK) 1928 LPUART_MSC_CLK = CLOCK_IP_HAS_LPUART_MSC_CLK, 1929 #endif 1930 #if defined(CLOCK_IP_HAS_LVDS_CLK) 1931 LVDS_CLK = CLOCK_IP_HAS_LVDS_CLK, 1932 #endif 1933 #if defined(CLOCK_IP_HAS_MCSS_CLK) 1934 MCSS_CLK = CLOCK_IP_HAS_MCSS_CLK, 1935 #endif 1936 #if defined(CLOCK_IP_HAS_MPU0_CLK) 1937 MPU0_CLK = CLOCK_IP_HAS_MPU0_CLK, 1938 #endif 1939 #if defined(CLOCK_IP_HAS_MSCM_CLK) 1940 MSCM_CLK = CLOCK_IP_HAS_MSCM_CLK, 1941 #endif 1942 #if defined(CLOCK_IP_HAS_MSCM0_CLK) 1943 MSCM0_CLK = CLOCK_IP_HAS_MSCM0_CLK, 1944 #endif 1945 #if defined(CLOCK_IP_HAS_MUA_CLK) 1946 MUA_CLK = CLOCK_IP_HAS_MUA_CLK, 1947 #endif 1948 #if defined(CLOCK_IP_HAS_MUB_CLK) 1949 MUB_CLK = CLOCK_IP_HAS_MUB_CLK, 1950 #endif 1951 #if defined(CLOCK_IP_HAS_MU2A_CLK) 1952 MU2A_CLK = CLOCK_IP_HAS_MU2A_CLK, 1953 #endif 1954 #if defined(CLOCK_IP_HAS_MU2B_CLK) 1955 MU2B_CLK = CLOCK_IP_HAS_MU2B_CLK, 1956 #endif 1957 #if defined(CLOCK_IP_HAS_MU3A_CLK) 1958 MU3A_CLK = CLOCK_IP_HAS_MU3A_CLK, 1959 #endif 1960 #if defined(CLOCK_IP_HAS_MU3B_CLK) 1961 MU3B_CLK = CLOCK_IP_HAS_MU3B_CLK, 1962 #endif 1963 #if defined(CLOCK_IP_HAS_MU4A_CLK) 1964 MU4A_CLK = CLOCK_IP_HAS_MU4A_CLK, 1965 #endif 1966 #if defined(CLOCK_IP_HAS_MU4B_CLK) 1967 MU4B_CLK = CLOCK_IP_HAS_MU4B_CLK, 1968 #endif 1969 #if defined(CLOCK_IP_HAS_OCOTP_CLK) 1970 OCOTP_CLK = CLOCK_IP_HAS_OCOTP_CLK, 1971 #endif 1972 #if defined(CLOCK_IP_HAS_PDB0_CLK) 1973 PDB0_CLK = CLOCK_IP_HAS_PDB0_CLK, 1974 #endif 1975 #if defined(CLOCK_IP_HAS_PDB1_CLK) 1976 PDB1_CLK = CLOCK_IP_HAS_PDB1_CLK, 1977 #endif 1978 #if defined(CLOCK_IP_HAS_PFEMAC0_RX_CLK) 1979 PFEMAC0_RX_CLK = CLOCK_IP_HAS_PFEMAC0_RX_CLK, 1980 #endif 1981 #if defined(CLOCK_IP_HAS_PFEMAC0_TX_DIV_CLK) 1982 PFEMAC0_TX_DIV_CLK = CLOCK_IP_HAS_PFEMAC0_TX_DIV_CLK, 1983 #endif 1984 #if defined(CLOCK_IP_HAS_PFEMAC1_TX_DIV_CLK) 1985 PFEMAC1_TX_DIV_CLK = CLOCK_IP_HAS_PFEMAC1_TX_DIV_CLK, 1986 #endif 1987 #if defined(CLOCK_IP_HAS_PFEMAC2_TX_DIV_CLK) 1988 PFEMAC2_TX_DIV_CLK = CLOCK_IP_HAS_PFEMAC2_TX_DIV_CLK, 1989 #endif 1990 #if defined(CLOCK_IP_HAS_PFEMAC0_TX_CLK) 1991 PFEMAC0_TX_CLK = CLOCK_IP_HAS_PFEMAC0_TX_CLK, 1992 #endif 1993 #if defined(CLOCK_IP_HAS_PFEMAC1_RX_CLK) 1994 PFEMAC1_RX_CLK = CLOCK_IP_HAS_PFEMAC1_RX_CLK, 1995 #endif 1996 #if defined(CLOCK_IP_HAS_PFEMAC1_TX_CLK) 1997 PFEMAC1_TX_CLK = CLOCK_IP_HAS_PFEMAC1_TX_CLK, 1998 #endif 1999 #if defined(CLOCK_IP_HAS_PFEMAC2_RX_CLK) 2000 PFEMAC2_RX_CLK = CLOCK_IP_HAS_PFEMAC2_RX_CLK, 2001 #endif 2002 #if defined(CLOCK_IP_HAS_PFEMAC2_TX_CLK) 2003 PFEMAC2_TX_CLK = CLOCK_IP_HAS_PFEMAC2_TX_CLK, 2004 #endif 2005 #if defined(CLOCK_IP_HAS_PIT0_CLK) 2006 PIT0_CLK = CLOCK_IP_HAS_PIT0_CLK, 2007 #endif 2008 #if defined(CLOCK_IP_HAS_PIT1_CLK) 2009 PIT1_CLK = CLOCK_IP_HAS_PIT1_CLK, 2010 #endif 2011 #if defined(CLOCK_IP_HAS_PIT2_CLK) 2012 PIT2_CLK = CLOCK_IP_HAS_PIT2_CLK, 2013 #endif 2014 #if defined(CLOCK_IP_HAS_PIT3_CLK) 2015 PIT3_CLK = CLOCK_IP_HAS_PIT3_CLK, 2016 #endif 2017 #if defined(CLOCK_IP_HAS_PIT4_CLK) 2018 PIT4_CLK = CLOCK_IP_HAS_PIT4_CLK, 2019 #endif 2020 #if defined(CLOCK_IP_HAS_PIT5_CLK) 2021 PIT5_CLK = CLOCK_IP_HAS_PIT5_CLK, 2022 #endif 2023 #if defined(CLOCK_IP_HAS_PORTA_CLK) 2024 PORTA_CLK = CLOCK_IP_HAS_PORTA_CLK, 2025 #endif 2026 #if defined(CLOCK_IP_HAS_PORTB_CLK) 2027 PORTB_CLK = CLOCK_IP_HAS_PORTB_CLK, 2028 #endif 2029 #if defined(CLOCK_IP_HAS_PORTC_CLK) 2030 PORTC_CLK = CLOCK_IP_HAS_PORTC_CLK, 2031 #endif 2032 #if defined(CLOCK_IP_HAS_PORTD_CLK) 2033 PORTD_CLK = CLOCK_IP_HAS_PORTD_CLK, 2034 #endif 2035 #if defined(CLOCK_IP_HAS_PORTE_CLK) 2036 PORTE_CLK = CLOCK_IP_HAS_PORTE_CLK, 2037 #endif 2038 #if defined(CLOCK_IP_HAS_PSI5_0_CLK) 2039 PSI5_0_CLK = CLOCK_IP_HAS_PSI5_0_CLK, 2040 #endif 2041 #if defined(CLOCK_IP_HAS_PSI5_1_CLK) 2042 PSI5_1_CLK = CLOCK_IP_HAS_PSI5_1_CLK, 2043 #endif 2044 #if defined(CLOCK_IP_HAS_PSI5S_0_CLK) 2045 PSI5S_0_CLK = CLOCK_IP_HAS_PSI5S_0_CLK, 2046 #endif 2047 #if defined(CLOCK_IP_HAS_PSI5S_1_CLK) 2048 PSI5S_1_CLK = CLOCK_IP_HAS_PSI5S_1_CLK, 2049 #endif 2050 #if defined(CLOCK_IP_HAS_QSPI_CLK) 2051 QSPI_CLK = CLOCK_IP_HAS_QSPI_CLK, 2052 #endif 2053 #if defined(CLOCK_IP_HAS_QSPI_SFIF_CLK_HYP_PREMUX_CLK) 2054 QSPI_SFIF_CLK_HYP_PREMUX_CLK = CLOCK_IP_HAS_QSPI_SFIF_CLK_HYP_PREMUX_CLK, 2055 #endif 2056 #if defined(CLOCK_IP_HAS_QSPI_SFIF_CLK) 2057 QSPI_SFIF_CLK = CLOCK_IP_HAS_QSPI_SFIF_CLK, 2058 #endif 2059 #if defined(CLOCK_IP_HAS_QSPI_2xSFIF_CLK) 2060 QSPI_2xSFIF_CLK = CLOCK_IP_HAS_QSPI_2xSFIF_CLK, 2061 #endif 2062 #if defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK) 2063 QSPI_2XSFIF_CLK = CLOCK_IP_HAS_QSPI_2XSFIF_CLK, 2064 #endif 2065 #if defined(CLOCK_IP_HAS_QSPI_2X_CLK) 2066 QSPI_2X_CLK = CLOCK_IP_HAS_QSPI_2X_CLK, 2067 #endif 2068 #if defined(CLOCK_IP_HAS_QSPI_1X_CLK) 2069 QSPI_1X_CLK = CLOCK_IP_HAS_QSPI_1X_CLK, 2070 #endif 2071 #if defined(CLOCK_IP_HAS_QSPI_SFCK_CLK) 2072 QSPI_SFCK_CLK = CLOCK_IP_HAS_QSPI_SFCK_CLK, 2073 #endif 2074 #if defined(CLOCK_IP_HAS_QSPI0_CLK) 2075 QSPI0_CLK = CLOCK_IP_HAS_QSPI0_CLK, 2076 #endif 2077 #if defined(CLOCK_IP_HAS_QSPI0_RAM_CLK) 2078 QSPI0_RAM_CLK = CLOCK_IP_HAS_QSPI0_RAM_CLK, 2079 #endif 2080 #if defined(CLOCK_IP_HAS_QSPI0_SFCK_CLK) 2081 QSPI0_SFCK_CLK = CLOCK_IP_HAS_QSPI0_SFCK_CLK, 2082 #endif 2083 #if defined(CLOCK_IP_HAS_QSPI0_TX_MEM_CLK) 2084 QSPI0_TX_MEM_CLK = CLOCK_IP_HAS_QSPI0_TX_MEM_CLK, 2085 #endif 2086 #if defined(CLOCK_IP_HAS_QSPI1_CLK) 2087 QSPI1_CLK = CLOCK_IP_HAS_QSPI1_CLK, 2088 #endif 2089 #if defined(CLOCK_IP_HAS_P0_CLKOUT_SRC_CLK) 2090 P0_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P0_CLKOUT_SRC_CLK, 2091 #endif 2092 #if defined(CLOCK_IP_HAS_P0_CTU_PER_CLK) 2093 P0_CTU_PER_CLK = CLOCK_IP_HAS_P0_CTU_PER_CLK, 2094 #endif 2095 #if defined(CLOCK_IP_HAS_P0_DSPI_CLK) 2096 P0_DSPI_CLK = CLOCK_IP_HAS_P0_DSPI_CLK, 2097 #endif 2098 #if defined(CLOCK_IP_HAS_P0_DSPI_MSC_CLK) 2099 P0_DSPI_MSC_CLK = CLOCK_IP_HAS_P0_DSPI_MSC_CLK, 2100 #endif 2101 #if defined(CLOCK_IP_HAS_P0_EMIOS_LCU_CLK) 2102 P0_EMIOS_LCU_CLK = CLOCK_IP_HAS_P0_EMIOS_LCU_CLK, 2103 #endif 2104 #if defined(CLOCK_IP_HAS_P0_FR_PE_CLK) 2105 P0_FR_PE_CLK = CLOCK_IP_HAS_P0_FR_PE_CLK, 2106 #endif 2107 #if defined(CLOCK_IP_HAS_P0_GTM_CLK) 2108 P0_GTM_CLK = CLOCK_IP_HAS_P0_GTM_CLK, 2109 #endif 2110 #if defined(CLOCK_IP_HAS_P0_GTM_NOC_CLK) 2111 P0_GTM_NOC_CLK = CLOCK_IP_HAS_P0_GTM_NOC_CLK, 2112 #endif 2113 #if defined(CLOCK_IP_HAS_P0_GTM_TS_CLK) 2114 P0_GTM_TS_CLK = CLOCK_IP_HAS_P0_GTM_TS_CLK, 2115 #endif 2116 #if defined(CLOCK_IP_HAS_P0_LIN_BAUD_CLK) 2117 P0_LIN_BAUD_CLK = CLOCK_IP_HAS_P0_LIN_BAUD_CLK, 2118 #endif 2119 #if defined(CLOCK_IP_HAS_P0_LIN_CLK) 2120 P0_LIN_CLK = CLOCK_IP_HAS_P0_LIN_CLK, 2121 #endif 2122 #if defined(CLOCK_IP_HAS_P0_NANO_CLK) 2123 P0_NANO_CLK = CLOCK_IP_HAS_P0_NANO_CLK, 2124 #endif 2125 #if defined(CLOCK_IP_HAS_P0_PSI5_125K_CLK) 2126 P0_PSI5_125K_CLK = CLOCK_IP_HAS_P0_PSI5_125K_CLK, 2127 #endif 2128 #if defined(CLOCK_IP_HAS_P0_PSI5_189K_CLK) 2129 P0_PSI5_189K_CLK = CLOCK_IP_HAS_P0_PSI5_189K_CLK, 2130 #endif 2131 #if defined(CLOCK_IP_HAS_P0_PSI5_1US_CLK) 2132 P0_PSI5_1US_CLK = CLOCK_IP_HAS_P0_PSI5_1US_CLK, 2133 #endif 2134 #if defined(CLOCK_IP_HAS_P0_PSI5_S_BAUD_CLK) 2135 P0_PSI5_S_BAUD_CLK = CLOCK_IP_HAS_P0_PSI5_S_BAUD_CLK, 2136 #endif 2137 #if defined(CLOCK_IP_HAS_P0_PSI5_S_CORE_CLK) 2138 P0_PSI5_S_CORE_CLK = CLOCK_IP_HAS_P0_PSI5_S_CORE_CLK, 2139 #endif 2140 #if defined(CLOCK_IP_HAS_P0_PSI5_S_TRIG0_CLK) 2141 P0_PSI5_S_TRIG0_CLK = CLOCK_IP_HAS_P0_PSI5_S_TRIG0_CLK, 2142 #endif 2143 #if defined(CLOCK_IP_HAS_P0_PSI5_S_TRIG1_CLK) 2144 P0_PSI5_S_TRIG1_CLK = CLOCK_IP_HAS_P0_PSI5_S_TRIG1_CLK, 2145 #endif 2146 #if defined(CLOCK_IP_HAS_P0_PSI5_S_TRIG2_CLK) 2147 P0_PSI5_S_TRIG2_CLK = CLOCK_IP_HAS_P0_PSI5_S_TRIG2_CLK, 2148 #endif 2149 #if defined(CLOCK_IP_HAS_P0_PSI5_S_TRIG3_CLK) 2150 P0_PSI5_S_TRIG3_CLK = CLOCK_IP_HAS_P0_PSI5_S_TRIG3_CLK, 2151 #endif 2152 #if defined(CLOCK_IP_HAS_P0_PSI5_S_UART_CLK) 2153 P0_PSI5_S_UART_CLK = CLOCK_IP_HAS_P0_PSI5_S_UART_CLK, 2154 #endif 2155 #if defined(CLOCK_IP_HAS_P0_PSI5_S_WDOG0_CLK) 2156 P0_PSI5_S_WDOG0_CLK = CLOCK_IP_HAS_P0_PSI5_S_WDOG0_CLK, 2157 #endif 2158 #if defined(CLOCK_IP_HAS_P0_PSI5_S_WDOG1_CLK) 2159 P0_PSI5_S_WDOG1_CLK = CLOCK_IP_HAS_P0_PSI5_S_WDOG1_CLK, 2160 #endif 2161 #if defined(CLOCK_IP_HAS_P0_PSI5_S_WDOG2_CLK) 2162 P0_PSI5_S_WDOG2_CLK = CLOCK_IP_HAS_P0_PSI5_S_WDOG2_CLK, 2163 #endif 2164 #if defined(CLOCK_IP_HAS_P0_PSI5_S_WDOG3_CLK) 2165 P0_PSI5_S_WDOG3_CLK = CLOCK_IP_HAS_P0_PSI5_S_WDOG3_CLK, 2166 #endif 2167 #if defined(CLOCK_IP_HAS_P0_REG_INTF_2X_CLK) 2168 P0_REG_INTF_2X_CLK = CLOCK_IP_HAS_P0_REG_INTF_2X_CLK, 2169 #endif 2170 #if defined(CLOCK_IP_HAS_P0_REG_INTF_CLK) 2171 P0_REG_INTF_CLK = CLOCK_IP_HAS_P0_REG_INTF_CLK, 2172 #endif 2173 #if defined(CLOCK_IP_HAS_P1_CLKOUT_SRC_CLK) 2174 P1_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P1_CLKOUT_SRC_CLK, 2175 #endif 2176 #if defined(CLOCK_IP_HAS_P1_DSPI_CLK) 2177 P1_DSPI_CLK = CLOCK_IP_HAS_P1_DSPI_CLK, 2178 #endif 2179 #if defined(CLOCK_IP_HAS_P1_DSPI60_CLK) 2180 P1_DSPI60_CLK = CLOCK_IP_HAS_P1_DSPI60_CLK, 2181 #endif 2182 #if defined(CLOCK_IP_HAS_P1_LFAST0_REF_CLK) 2183 P1_LFAST0_REF_CLK = CLOCK_IP_HAS_P1_LFAST0_REF_CLK, 2184 #endif 2185 #if defined(CLOCK_IP_HAS_P1_LFAST1_REF_CLK) 2186 P1_LFAST1_REF_CLK = CLOCK_IP_HAS_P1_LFAST1_REF_CLK, 2187 #endif 2188 #if defined(CLOCK_IP_HAS_P1_LFAST_DFT_CLK) 2189 P1_LFAST_DFT_CLK = CLOCK_IP_HAS_P1_LFAST_DFT_CLK, 2190 #endif 2191 #if defined(CLOCK_IP_HAS_P1_NETC_AXI_CLK) 2192 P1_NETC_AXI_CLK = CLOCK_IP_HAS_P1_NETC_AXI_CLK, 2193 #endif 2194 #if defined(CLOCK_IP_HAS_P1_LIN_BAUD_CLK) 2195 P1_LIN_BAUD_CLK = CLOCK_IP_HAS_P1_LIN_BAUD_CLK, 2196 #endif 2197 #if defined(CLOCK_IP_HAS_P1_LIN_CLK) 2198 P1_LIN_CLK = CLOCK_IP_HAS_P1_LIN_CLK, 2199 #endif 2200 #if defined(CLOCK_IP_HAS_ETH_TS_CLK) 2201 ETH_TS_CLK = CLOCK_IP_HAS_ETH_TS_CLK, 2202 #endif 2203 #if defined(CLOCK_IP_HAS_ETH_TS_DIV4_CLK) 2204 ETH_TS_DIV4_CLK = CLOCK_IP_HAS_ETH_TS_DIV4_CLK, 2205 #endif 2206 #if defined(CLOCK_IP_HAS_ETH0_REF_RMII_CLK) 2207 ETH0_REF_RMII_CLK = CLOCK_IP_HAS_ETH0_REF_RMII_CLK, 2208 #endif 2209 #if defined(CLOCK_IP_HAS_ETH0_RX_MII_CLK) 2210 ETH0_RX_MII_CLK = CLOCK_IP_HAS_ETH0_RX_MII_CLK, 2211 #endif 2212 #if defined(CLOCK_IP_HAS_ETH0_RX_RGMII_CLK) 2213 ETH0_RX_RGMII_CLK = CLOCK_IP_HAS_ETH0_RX_RGMII_CLK, 2214 #endif 2215 #if defined(CLOCK_IP_HAS_ETH0_TX_MII_CLK) 2216 ETH0_TX_MII_CLK = CLOCK_IP_HAS_ETH0_TX_MII_CLK, 2217 #endif 2218 #if defined(CLOCK_IP_HAS_ETH0_TX_RGMII_CLK) 2219 ETH0_TX_RGMII_CLK = CLOCK_IP_HAS_ETH0_TX_RGMII_CLK, 2220 #endif 2221 #if defined(CLOCK_IP_HAS_ETH0_TX_RGMII_LPBK_CLK) 2222 ETH0_TX_RGMII_LPBK_CLK = CLOCK_IP_HAS_ETH0_TX_RGMII_LPBK_CLK, 2223 #endif 2224 #if defined(CLOCK_IP_HAS_ETH0_PS_TX_CLK) 2225 ETH0_PS_TX_CLK = CLOCK_IP_HAS_ETH0_PS_TX_CLK, 2226 #endif 2227 #if defined(CLOCK_IP_HAS_ETH1_REF_RMII_CLK) 2228 ETH1_REF_RMII_CLK = CLOCK_IP_HAS_ETH1_REF_RMII_CLK, 2229 #endif 2230 #if defined(CLOCK_IP_HAS_ETH1_RX_MII_CLK) 2231 ETH1_RX_MII_CLK = CLOCK_IP_HAS_ETH1_RX_MII_CLK, 2232 #endif 2233 #if defined(CLOCK_IP_HAS_ETH1_RX_RGMII_CLK) 2234 ETH1_RX_RGMII_CLK = CLOCK_IP_HAS_ETH1_RX_RGMII_CLK, 2235 #endif 2236 #if defined(CLOCK_IP_HAS_ETH1_TX_MII_CLK) 2237 ETH1_TX_MII_CLK = CLOCK_IP_HAS_ETH1_TX_MII_CLK, 2238 #endif 2239 #if defined(CLOCK_IP_HAS_ETH1_TX_RGMII_CLK) 2240 ETH1_TX_RGMII_CLK = CLOCK_IP_HAS_ETH1_TX_RGMII_CLK, 2241 #endif 2242 #if defined(CLOCK_IP_HAS_ETH1_TX_RGMII_LPBK_CLK) 2243 ETH1_TX_RGMII_LPBK_CLK = CLOCK_IP_HAS_ETH1_TX_RGMII_LPBK_CLK, 2244 #endif 2245 #if defined(CLOCK_IP_HAS_ETH1_PS_TX_CLK) 2246 ETH1_PS_TX_CLK = CLOCK_IP_HAS_ETH1_PS_TX_CLK, 2247 #endif 2248 #if defined(CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK) 2249 ETPU_AB_REGISTERS_CLK = CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK, 2250 #endif 2251 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK) 2252 ETPU_CODE_RAM1_CLK = CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK, 2253 #endif 2254 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK) 2255 ETPU_CODE_RAM2_CLK = CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK, 2256 #endif 2257 #if defined(CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK) 2258 ETPU_RAM_MIRROR_CLK = CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK, 2259 #endif 2260 #if defined(CLOCK_IP_HAS_ETPU_RAM_SDM_CLK) 2261 ETPU_RAM_SDM_CLK = CLOCK_IP_HAS_ETPU_RAM_SDM_CLK, 2262 #endif 2263 #if defined(CLOCK_IP_HAS_P1_REG_INTF_CLK) 2264 P1_REG_INTF_CLK = CLOCK_IP_HAS_P1_REG_INTF_CLK, 2265 #endif 2266 #if defined(CLOCK_IP_HAS_P2_DBG_ATB_CLK) 2267 P2_DBG_ATB_CLK = CLOCK_IP_HAS_P2_DBG_ATB_CLK, 2268 #endif 2269 #if defined(CLOCK_IP_HAS_P2_REG_INTF_CLK) 2270 P2_REG_INTF_CLK = CLOCK_IP_HAS_P2_REG_INTF_CLK, 2271 #endif 2272 #if defined(CLOCK_IP_HAS_P3_AES_CLK) 2273 P3_AES_CLK = CLOCK_IP_HAS_P3_AES_CLK, 2274 #endif 2275 #if defined(CLOCK_IP_HAS_P3_CAN_PE_CLK) 2276 P3_CAN_PE_CLK = CLOCK_IP_HAS_P3_CAN_PE_CLK, 2277 #endif 2278 #if defined(CLOCK_IP_HAS_P3_CLKOUT_SRC_CLK) 2279 P3_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P3_CLKOUT_SRC_CLK, 2280 #endif 2281 #if defined(CLOCK_IP_HAS_P3_DBG_TS_CLK) 2282 P3_DBG_TS_CLK = CLOCK_IP_HAS_P3_DBG_TS_CLK, 2283 #endif 2284 #if defined(CLOCK_IP_HAS_P3_REG_INTF_CLK) 2285 P3_REG_INTF_CLK = CLOCK_IP_HAS_P3_REG_INTF_CLK, 2286 #endif 2287 #if defined(CLOCK_IP_HAS_P3_SYS_MON1_CLK) 2288 P3_SYS_MON1_CLK = CLOCK_IP_HAS_P3_SYS_MON1_CLK, 2289 #endif 2290 #if defined(CLOCK_IP_HAS_P3_SYS_MON2_CLK) 2291 P3_SYS_MON2_CLK = CLOCK_IP_HAS_P3_SYS_MON2_CLK, 2292 #endif 2293 #if defined(CLOCK_IP_HAS_P3_SYS_MON3_CLK) 2294 P3_SYS_MON3_CLK = CLOCK_IP_HAS_P3_SYS_MON3_CLK, 2295 #endif 2296 #if defined(CLOCK_IP_HAS_P4_CLKOUT_SRC_CLK) 2297 P4_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P4_CLKOUT_SRC_CLK, 2298 #endif 2299 #if defined(CLOCK_IP_HAS_P4_DSPI_CLK) 2300 P4_DSPI_CLK = CLOCK_IP_HAS_P4_DSPI_CLK, 2301 #endif 2302 #if defined(CLOCK_IP_HAS_P4_DSPI60_CLK) 2303 P4_DSPI60_CLK = CLOCK_IP_HAS_P4_DSPI60_CLK, 2304 #endif 2305 #if defined(CLOCK_IP_HAS_P4_EMIOS_LCU_CLK) 2306 P4_EMIOS_LCU_CLK = CLOCK_IP_HAS_P4_EMIOS_LCU_CLK, 2307 #endif 2308 #if defined(CLOCK_IP_HAS_P4_LIN_BAUD_CLK) 2309 P4_LIN_BAUD_CLK = CLOCK_IP_HAS_P4_LIN_BAUD_CLK, 2310 #endif 2311 #if defined(CLOCK_IP_HAS_P4_LIN_CLK) 2312 P4_LIN_CLK = CLOCK_IP_HAS_P4_LIN_CLK, 2313 #endif 2314 #if defined(CLOCK_IP_HAS_P4_PSI5_125K_CLK) 2315 P4_PSI5_125K_CLK = CLOCK_IP_HAS_P4_PSI5_125K_CLK, 2316 #endif 2317 #if defined(CLOCK_IP_HAS_P4_PSI5_189K_CLK) 2318 P4_PSI5_189K_CLK = CLOCK_IP_HAS_P4_PSI5_189K_CLK, 2319 #endif 2320 #if defined(CLOCK_IP_HAS_P4_PSI5_1US_CLK) 2321 P4_PSI5_1US_CLK = CLOCK_IP_HAS_P4_PSI5_1US_CLK, 2322 #endif 2323 #if defined(CLOCK_IP_HAS_P4_PSI5_S_BAUD_CLK) 2324 P4_PSI5_S_BAUD_CLK = CLOCK_IP_HAS_P4_PSI5_S_BAUD_CLK, 2325 #endif 2326 #if defined(CLOCK_IP_HAS_P4_PSI5_S_CORE_CLK) 2327 P4_PSI5_S_CORE_CLK = CLOCK_IP_HAS_P4_PSI5_S_CORE_CLK, 2328 #endif 2329 #if defined(CLOCK_IP_HAS_P4_PSI5_S_TRIG0_CLK) 2330 P4_PSI5_S_TRIG0_CLK = CLOCK_IP_HAS_P4_PSI5_S_TRIG0_CLK, 2331 #endif 2332 #if defined(CLOCK_IP_HAS_P4_PSI5_S_TRIG1_CLK) 2333 P4_PSI5_S_TRIG1_CLK = CLOCK_IP_HAS_P4_PSI5_S_TRIG1_CLK, 2334 #endif 2335 #if defined(CLOCK_IP_HAS_P4_PSI5_S_TRIG2_CLK) 2336 P4_PSI5_S_TRIG2_CLK = CLOCK_IP_HAS_P4_PSI5_S_TRIG2_CLK, 2337 #endif 2338 #if defined(CLOCK_IP_HAS_P4_PSI5_S_TRIG3_CLK) 2339 P4_PSI5_S_TRIG3_CLK = CLOCK_IP_HAS_P4_PSI5_S_TRIG3_CLK, 2340 #endif 2341 #if defined(CLOCK_IP_HAS_P4_PSI5_S_UART_CLK) 2342 P4_PSI5_S_UART_CLK = CLOCK_IP_HAS_P4_PSI5_S_UART_CLK, 2343 #endif 2344 #if defined(CLOCK_IP_HAS_P4_PSI5_S_WDOG0_CLK) 2345 P4_PSI5_S_WDOG0_CLK = CLOCK_IP_HAS_P4_PSI5_S_WDOG0_CLK, 2346 #endif 2347 #if defined(CLOCK_IP_HAS_P4_PSI5_S_WDOG1_CLK) 2348 P4_PSI5_S_WDOG1_CLK = CLOCK_IP_HAS_P4_PSI5_S_WDOG1_CLK, 2349 #endif 2350 #if defined(CLOCK_IP_HAS_P4_PSI5_S_WDOG2_CLK) 2351 P4_PSI5_S_WDOG2_CLK = CLOCK_IP_HAS_P4_PSI5_S_WDOG2_CLK, 2352 #endif 2353 #if defined(CLOCK_IP_HAS_P4_PSI5_S_WDOG3_CLK) 2354 P4_PSI5_S_WDOG3_CLK = CLOCK_IP_HAS_P4_PSI5_S_WDOG3_CLK, 2355 #endif 2356 #if defined(CLOCK_IP_HAS_P4_QSPI0_2X_CLK) 2357 P4_QSPI0_2X_CLK = CLOCK_IP_HAS_P4_QSPI0_2X_CLK, 2358 #endif 2359 #if defined(CLOCK_IP_HAS_P4_QSPI0_1X_CLK) 2360 P4_QSPI0_1X_CLK = CLOCK_IP_HAS_P4_QSPI0_1X_CLK, 2361 #endif 2362 #if defined(CLOCK_IP_HAS_P4_QSPI1_2X_CLK) 2363 P4_QSPI1_2X_CLK = CLOCK_IP_HAS_P4_QSPI1_2X_CLK, 2364 #endif 2365 #if defined(CLOCK_IP_HAS_P4_QSPI1_1X_CLK) 2366 P4_QSPI1_1X_CLK = CLOCK_IP_HAS_P4_QSPI1_1X_CLK, 2367 #endif 2368 #if defined(CLOCK_IP_HAS_P4_REG_INTF_2X_CLK) 2369 P4_REG_INTF_2X_CLK = CLOCK_IP_HAS_P4_REG_INTF_2X_CLK, 2370 #endif 2371 #if defined(CLOCK_IP_HAS_P4_REG_INTF_CLK) 2372 P4_REG_INTF_CLK = CLOCK_IP_HAS_P4_REG_INTF_CLK, 2373 #endif 2374 #if defined(CLOCK_IP_HAS_P4_SDHC_CLK) 2375 P4_SDHC_CLK = CLOCK_IP_HAS_P4_SDHC_CLK, 2376 #endif 2377 #if defined(CLOCK_IP_HAS_P4_SDHC_IP_CLK) 2378 P4_SDHC_IP_CLK = CLOCK_IP_HAS_P4_SDHC_IP_CLK, 2379 #endif 2380 #if defined(CLOCK_IP_HAS_P4_SDHC_IP_DIV2_CLK) 2381 P4_SDHC_IP_DIV2_CLK = CLOCK_IP_HAS_P4_SDHC_IP_DIV2_CLK, 2382 #endif 2383 #if defined(CLOCK_IP_HAS_P5_AE_CLK) 2384 P5_AE_CLK = CLOCK_IP_HAS_P5_AE_CLK, 2385 #endif 2386 #if defined(CLOCK_IP_HAS_P5_CANXL_PE_CLK) 2387 P5_CANXL_PE_CLK = CLOCK_IP_HAS_P5_CANXL_PE_CLK, 2388 #endif 2389 #if defined(CLOCK_IP_HAS_P5_CANXL_CHI_CLK) 2390 P5_CANXL_CHI_CLK = CLOCK_IP_HAS_P5_CANXL_CHI_CLK, 2391 #endif 2392 #if defined(CLOCK_IP_HAS_P5_CLKOUT_SRC_CLK) 2393 P5_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P5_CLKOUT_SRC_CLK, 2394 #endif 2395 #if defined(CLOCK_IP_HAS_P5_DSPI_CLK) 2396 P5_DSPI_CLK = CLOCK_IP_HAS_P5_DSPI_CLK, 2397 #endif 2398 #if defined(CLOCK_IP_HAS_P5_DIPORT_CLK) 2399 P5_DIPORT_CLK = CLOCK_IP_HAS_P5_DIPORT_CLK, 2400 #endif 2401 #if defined(CLOCK_IP_HAS_P5_LIN_BAUD_CLK) 2402 P5_LIN_BAUD_CLK = CLOCK_IP_HAS_P5_LIN_BAUD_CLK, 2403 #endif 2404 #if defined(CLOCK_IP_HAS_P5_LIN_CLK) 2405 P5_LIN_CLK = CLOCK_IP_HAS_P5_LIN_CLK, 2406 #endif 2407 #if defined(CLOCK_IP_HAS_P5_REG_INTF_CLK) 2408 P5_REG_INTF_CLK = CLOCK_IP_HAS_P5_REG_INTF_CLK, 2409 #endif 2410 #if defined(CLOCK_IP_HAS_P6_REG_INTF_CLK) 2411 P6_REG_INTF_CLK = CLOCK_IP_HAS_P6_REG_INTF_CLK, 2412 #endif 2413 #if defined(CLOCK_IP_HAS_RTU0_REG_INTF_CLK) 2414 RTU0_REG_INTF_CLK = CLOCK_IP_HAS_RTU0_REG_INTF_CLK, 2415 #endif 2416 #if defined(CLOCK_IP_HAS_RTU0_CORE_MON1_CLK) 2417 RTU0_CORE_MON1_CLK = CLOCK_IP_HAS_RTU0_CORE_MON1_CLK, 2418 #endif 2419 #if defined(CLOCK_IP_HAS_RTU0_CORE_MON2_CLK) 2420 RTU0_CORE_MON2_CLK = CLOCK_IP_HAS_RTU0_CORE_MON2_CLK, 2421 #endif 2422 #if defined(CLOCK_IP_HAS_RTU0_CORE_DIV2_MON1_CLK) 2423 RTU0_CORE_DIV2_MON1_CLK = CLOCK_IP_HAS_RTU0_CORE_DIV2_MON1_CLK, 2424 #endif 2425 #if defined(CLOCK_IP_HAS_RTU0_CORE_DIV2_MON2_CLK) 2426 RTU0_CORE_DIV2_MON2_CLK = CLOCK_IP_HAS_RTU0_CORE_DIV2_MON2_CLK, 2427 #endif 2428 #if defined(CLOCK_IP_HAS_RTU0_CORE_DIV2_MON3_CLK) 2429 RTU0_CORE_DIV2_MON3_CLK = CLOCK_IP_HAS_RTU0_CORE_DIV2_MON3_CLK, 2430 #endif 2431 #if defined(CLOCK_IP_HAS_RTU1_REG_INTF_CLK) 2432 RTU1_REG_INTF_CLK = CLOCK_IP_HAS_RTU1_REG_INTF_CLK, 2433 #endif 2434 #if defined(CLOCK_IP_HAS_RTU1_CORE_MON1_CLK) 2435 RTU1_CORE_MON1_CLK = CLOCK_IP_HAS_RTU1_CORE_MON1_CLK, 2436 #endif 2437 #if defined(CLOCK_IP_HAS_RTU1_CORE_MON2_CLK) 2438 RTU1_CORE_MON2_CLK = CLOCK_IP_HAS_RTU1_CORE_MON2_CLK, 2439 #endif 2440 #if defined(CLOCK_IP_HAS_RTU1_CORE_DIV2_MON1_CLK) 2441 RTU1_CORE_DIV2_MON1_CLK = CLOCK_IP_HAS_RTU1_CORE_DIV2_MON1_CLK, 2442 #endif 2443 #if defined(CLOCK_IP_HAS_RTU1_CORE_DIV2_MON2_CLK) 2444 RTU1_CORE_DIV2_MON2_CLK = CLOCK_IP_HAS_RTU1_CORE_DIV2_MON2_CLK, 2445 #endif 2446 #if defined(CLOCK_IP_HAS_RTU1_CORE_DIV2_MON3_CLK) 2447 RTU1_CORE_DIV2_MON3_CLK = CLOCK_IP_HAS_RTU1_CORE_DIV2_MON3_CLK, 2448 #endif 2449 #if defined(CLOCK_IP_HAS_RFE_PLL_CLK) 2450 RFE_PLL_CLK = CLOCK_IP_HAS_RFE_PLL_CLK, 2451 #endif 2452 #if defined(CLOCK_IP_HAS_RTC_CLK) 2453 RTC_CLK = CLOCK_IP_HAS_RTC_CLK, 2454 #endif 2455 #if defined(CLOCK_IP_HAS_RTC0_CLK) 2456 RTC0_CLK = CLOCK_IP_HAS_RTC0_CLK, 2457 #endif 2458 #if defined(CLOCK_IP_HAS_RTC_EXT_REF_CLK) 2459 RTC_EXT_REF_CLK = CLOCK_IP_HAS_RTC_EXT_REF_CLK, 2460 #endif 2461 #if defined(CLOCK_IP_HAS_RXLUT_CLK) 2462 RXLUT_CLK = CLOCK_IP_HAS_RXLUT_CLK, 2463 #endif 2464 #if defined(CLOCK_IP_HAS_SAI0_CLK) 2465 SAI0_CLK = CLOCK_IP_HAS_SAI0_CLK, 2466 #endif 2467 #if defined(CLOCK_IP_HAS_SAI1_CLK) 2468 SAI1_CLK = CLOCK_IP_HAS_SAI1_CLK, 2469 #endif 2470 #if defined(CLOCK_IP_HAS_SDHC0_CLK) 2471 SDHC0_CLK = CLOCK_IP_HAS_SDHC0_CLK, 2472 #endif 2473 #if defined(CLOCK_IP_HAS_SEMA42_CLK) 2474 SEMA42_CLK = CLOCK_IP_HAS_SEMA42_CLK, 2475 #endif 2476 #if defined(CLOCK_IP_HAS_SIPI0_CLK) 2477 SIPI0_CLK = CLOCK_IP_HAS_SIPI0_CLK, 2478 #endif 2479 #if defined(CLOCK_IP_HAS_SIPI1_CLK) 2480 SIPI1_CLK = CLOCK_IP_HAS_SIPI1_CLK, 2481 #endif 2482 #if defined(CLOCK_IP_HAS_SINC_CLK) 2483 SINC_CLK = CLOCK_IP_HAS_SINC_CLK, 2484 #endif 2485 #if defined(CLOCK_IP_HAS_SIUL0_CLK) 2486 SIUL0_CLK = CLOCK_IP_HAS_SIUL0_CLK, 2487 #endif 2488 #if defined(CLOCK_IP_HAS_SIUL1_CLK) 2489 SIUL1_CLK = CLOCK_IP_HAS_SIUL1_CLK, 2490 #endif 2491 #if defined(CLOCK_IP_HAS_SIUL2_0_CLK) 2492 SIUL2_0_CLK = CLOCK_IP_HAS_SIUL2_0_CLK, 2493 #endif 2494 #if defined(CLOCK_IP_HAS_SIUL2_1_CLK) 2495 SIUL2_1_CLK = CLOCK_IP_HAS_SIUL2_1_CLK, 2496 #endif 2497 #if defined(CLOCK_IP_HAS_SIUL2_4_CLK) 2498 SIUL2_4_CLK = CLOCK_IP_HAS_SIUL2_4_CLK, 2499 #endif 2500 #if defined(CLOCK_IP_HAS_SIUL2_5_CLK) 2501 SIUL2_5_CLK = CLOCK_IP_HAS_SIUL2_5_CLK, 2502 #endif 2503 #if defined(CLOCK_IP_HAS_SPI_CLK) 2504 SPI_CLK = CLOCK_IP_HAS_SPI_CLK, 2505 #endif 2506 #if defined(CLOCK_IP_HAS_SPI0_CLK) 2507 SPI0_CLK = CLOCK_IP_HAS_SPI0_CLK, 2508 #endif 2509 #if defined(CLOCK_IP_HAS_SPI1_CLK) 2510 SPI1_CLK = CLOCK_IP_HAS_SPI1_CLK, 2511 #endif 2512 #if defined(CLOCK_IP_HAS_SPI2_CLK) 2513 SPI2_CLK = CLOCK_IP_HAS_SPI2_CLK, 2514 #endif 2515 #if defined(CLOCK_IP_HAS_SPI3_CLK) 2516 SPI3_CLK = CLOCK_IP_HAS_SPI3_CLK, 2517 #endif 2518 #if defined(CLOCK_IP_HAS_SPI4_CLK) 2519 SPI4_CLK = CLOCK_IP_HAS_SPI4_CLK, 2520 #endif 2521 #if defined(CLOCK_IP_HAS_SPI5_CLK) 2522 SPI5_CLK = CLOCK_IP_HAS_SPI5_CLK, 2523 #endif 2524 #if defined(CLOCK_IP_HAS_SPI6_CLK) 2525 SPI6_CLK = CLOCK_IP_HAS_SPI6_CLK, 2526 #endif 2527 #if defined(CLOCK_IP_HAS_SPI7_CLK) 2528 SPI7_CLK = CLOCK_IP_HAS_SPI7_CLK, 2529 #endif 2530 #if defined(CLOCK_IP_HAS_SPI8_CLK) 2531 SPI8_CLK = CLOCK_IP_HAS_SPI8_CLK, 2532 #endif 2533 #if defined(CLOCK_IP_HAS_SPI9_CLK) 2534 SPI9_CLK = CLOCK_IP_HAS_SPI9_CLK, 2535 #endif 2536 #if defined(CLOCK_IP_HAS_SRX0_CLK) 2537 SRX0_CLK = CLOCK_IP_HAS_SRX0_CLK, 2538 #endif 2539 #if defined(CLOCK_IP_HAS_SRX1_CLK) 2540 SRX1_CLK = CLOCK_IP_HAS_SRX1_CLK, 2541 #endif 2542 #if defined(CLOCK_IP_HAS_STCU0_CLK) 2543 STCU0_CLK = CLOCK_IP_HAS_STCU0_CLK, 2544 #endif 2545 #if defined(CLOCK_IP_HAS_STM0_CLK) 2546 STM0_CLK = CLOCK_IP_HAS_STM0_CLK, 2547 #endif 2548 #if defined(CLOCK_IP_HAS_STM1_CLK) 2549 STM1_CLK = CLOCK_IP_HAS_STM1_CLK, 2550 #endif 2551 #if defined(CLOCK_IP_HAS_STM2_CLK) 2552 STM2_CLK = CLOCK_IP_HAS_STM2_CLK, 2553 #endif 2554 #if defined(CLOCK_IP_HAS_STM3_CLK) 2555 STM3_CLK = CLOCK_IP_HAS_STM3_CLK, 2556 #endif 2557 #if defined(CLOCK_IP_HAS_STM4_CLK) 2558 STM4_CLK = CLOCK_IP_HAS_STM4_CLK, 2559 #endif 2560 #if defined(CLOCK_IP_HAS_STM5_CLK) 2561 STM5_CLK = CLOCK_IP_HAS_STM5_CLK, 2562 #endif 2563 #if defined(CLOCK_IP_HAS_STM6_CLK) 2564 STM6_CLK = CLOCK_IP_HAS_STM6_CLK, 2565 #endif 2566 #if defined(CLOCK_IP_HAS_STM7_CLK) 2567 STM7_CLK = CLOCK_IP_HAS_STM7_CLK, 2568 #endif 2569 #if defined(CLOCK_IP_HAS_STMA_CLK) 2570 STMA_CLK = CLOCK_IP_HAS_STMA_CLK, 2571 #endif 2572 #if defined(CLOCK_IP_HAS_STMB_CLK) 2573 STMB_CLK = CLOCK_IP_HAS_STMB_CLK, 2574 #endif 2575 #if defined(CLOCK_IP_HAS_STMC_CLK) 2576 STMC_CLK = CLOCK_IP_HAS_STMC_CLK, 2577 #endif 2578 #if defined(CLOCK_IP_HAS_STMD_CLK) 2579 STMD_CLK = CLOCK_IP_HAS_STMD_CLK, 2580 #endif 2581 #if defined(CLOCK_IP_HAS_SWG_CLK) 2582 SWG_CLK = CLOCK_IP_HAS_SWG_CLK, 2583 #endif 2584 #if defined(CLOCK_IP_HAS_SWG0_CLK) 2585 SWG0_CLK = CLOCK_IP_HAS_SWG0_CLK, 2586 #endif 2587 #if defined(CLOCK_IP_HAS_SWG1_CLK) 2588 SWG1_CLK = CLOCK_IP_HAS_SWG1_CLK, 2589 #endif 2590 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK) 2591 SWG_PAD_CLK = CLOCK_IP_HAS_SWG_PAD_CLK, 2592 #endif 2593 #if defined(CLOCK_IP_HAS_SWT0_CLK) 2594 SWT0_CLK = CLOCK_IP_HAS_SWT0_CLK, 2595 #endif 2596 #if defined(CLOCK_IP_HAS_SWT1_CLK) 2597 SWT1_CLK = CLOCK_IP_HAS_SWT1_CLK, 2598 #endif 2599 #if defined(CLOCK_IP_HAS_SWT2_CLK) 2600 SWT2_CLK = CLOCK_IP_HAS_SWT2_CLK, 2601 #endif 2602 #if defined(CLOCK_IP_HAS_SWT3_CLK) 2603 SWT3_CLK = CLOCK_IP_HAS_SWT3_CLK, 2604 #endif 2605 #if defined(CLOCK_IP_HAS_SWT4_CLK) 2606 SWT4_CLK = CLOCK_IP_HAS_SWT4_CLK, 2607 #endif 2608 #if defined(CLOCK_IP_HAS_SWT5_CLK) 2609 SWT5_CLK = CLOCK_IP_HAS_SWT5_CLK, 2610 #endif 2611 #if defined(CLOCK_IP_HAS_SWT6_CLK) 2612 SWT6_CLK = CLOCK_IP_HAS_SWT6_CLK, 2613 #endif 2614 #if defined(CLOCK_IP_HAS_TCM_CM7_0_CLK) 2615 TCM_CM7_0_CLK = CLOCK_IP_HAS_TCM_CM7_0_CLK, 2616 #endif 2617 #if defined(CLOCK_IP_HAS_TCM_CM7_1_CLK) 2618 TCM_CM7_1_CLK = CLOCK_IP_HAS_TCM_CM7_1_CLK, 2619 #endif 2620 #if defined(CLOCK_IP_HAS_TEMPSENSE_CLK) 2621 TEMPSENSE_CLK = CLOCK_IP_HAS_TEMPSENSE_CLK, 2622 #endif 2623 #if defined(CLOCK_IP_HAS_TIMER_CLK) 2624 TIMER_CLK = CLOCK_IP_HAS_TIMER_CLK, 2625 #endif 2626 #if defined(CLOCK_IP_HAS_ENET0_TIME_CLK) 2627 ENET0_TIME_CLK = CLOCK_IP_HAS_ENET0_TIME_CLK, 2628 #endif 2629 #if defined(CLOCK_IP_HAS_TRACE_CLK) 2630 TRACE_CLK = CLOCK_IP_HAS_TRACE_CLK, 2631 #endif 2632 #if defined(CLOCK_IP_HAS_TRGMUX0_CLK) 2633 TRGMUX0_CLK = CLOCK_IP_HAS_TRGMUX0_CLK, 2634 #endif 2635 #if defined(CLOCK_IP_HAS_TRGMUX1_CLK) 2636 TRGMUX1_CLK = CLOCK_IP_HAS_TRGMUX1_CLK, 2637 #endif 2638 #if defined(CLOCK_IP_HAS_TSENSE0_CLK) 2639 TSENSE0_CLK = CLOCK_IP_HAS_TSENSE0_CLK, 2640 #endif 2641 #if defined(CLOCK_IP_HAS_SDHC_CLK) 2642 SDHC_CLK = CLOCK_IP_HAS_SDHC_CLK, 2643 #endif 2644 #if defined(CLOCK_IP_HAS_USDHC_CLK) 2645 USDHC_CLK = CLOCK_IP_HAS_USDHC_CLK, 2646 #endif 2647 #if defined(CLOCK_IP_HAS_USDHC_PER_CLK) 2648 USDHC_PER_CLK = CLOCK_IP_HAS_USDHC_PER_CLK, 2649 #endif 2650 #if defined(CLOCK_IP_HAS_USDHC0_CLK) 2651 USDHC0_CLK = CLOCK_IP_HAS_USDHC0_CLK, 2652 #endif 2653 #if defined(CLOCK_IP_HAS_WKPU0_CLK) 2654 WKPU0_CLK = CLOCK_IP_HAS_WKPU0_CLK, 2655 #endif 2656 #if defined(CLOCK_IP_HAS_XBAR_DIV3_FAIL_CLK) 2657 XBAR_DIV3_FAIL_CLK = CLOCK_IP_HAS_XBAR_DIV3_FAIL_CLK, 2658 #endif 2659 #if defined(CLOCK_IP_HAS_XBAR_MIPICSI201_CLK) 2660 XBAR_MIPICSI201_CLK = CLOCK_IP_HAS_XBAR_MIPICSI201_CLK, 2661 #endif 2662 #if defined(CLOCK_IP_HAS_XBAR_MIPICSI223_CLK) 2663 XBAR_MIPICSI223_CLK = CLOCK_IP_HAS_XBAR_MIPICSI223_CLK, 2664 #endif 2665 #if defined(CLOCK_IP_HAS_BBE32EP_DSP_CLK) 2666 BBE32EP_DSP_CLK = CLOCK_IP_HAS_BBE32EP_DSP_CLK, 2667 #endif 2668 #if defined(CLOCK_IP_HAS_CAN_CHI_CLK) 2669 CAN_CHI_CLK = CLOCK_IP_HAS_CAN_CHI_CLK, 2670 #endif 2671 #if defined(CLOCK_IP_HAS_CAN_TS_CLK) 2672 CAN_TS_CLK = CLOCK_IP_HAS_CAN_TS_CLK, 2673 #endif 2674 #if defined(CLOCK_IP_HAS_CAN0_CLK) 2675 CAN0_CLK = CLOCK_IP_HAS_CAN0_CLK, 2676 #endif 2677 #if defined(CLOCK_IP_HAS_CAN1_CLK) 2678 CAN1_CLK = CLOCK_IP_HAS_CAN1_CLK, 2679 #endif 2680 #if defined(CLOCK_IP_HAS_CRC_CLK) 2681 CRC_CLK = CLOCK_IP_HAS_CRC_CLK, 2682 #endif 2683 #if defined(CLOCK_IP_HAS_CSI_CFG_CLK) 2684 CSI_CLK = CLOCK_IP_HAS_CSI_CLK, 2685 #endif 2686 #if defined(CLOCK_IP_HAS_CSI_CFG_CLK) 2687 CSI_CFG_CLK = CLOCK_IP_HAS_CSI_CFG_CLK, 2688 #endif 2689 #if defined(CLOCK_IP_HAS_CSI_IPS_CLK) 2690 CSI_IPS_CLK = CLOCK_IP_HAS_CSI_IPS_CLK, 2691 #endif 2692 #if defined(CLOCK_IP_HAS_CSI_TXCLK_CLK) 2693 CSI_TXCLK_CLK = CLOCK_IP_HAS_CSI_TXCLK_CLK, 2694 #endif 2695 #if defined(CLOCK_IP_HAS_CTE_CLK) 2696 CTE_CLK = CLOCK_IP_HAS_CTE_CLK, 2697 #endif 2698 #if defined(CLOCK_IP_HAS_CTU_CLK) 2699 CTU_CLK = CLOCK_IP_HAS_CTU_CLK, 2700 #endif 2701 #if defined(CLOCK_IP_HAS_CTU_IPS_CLK) 2702 CTU_IPS_CLK = CLOCK_IP_HAS_CTU_IPS_CLK, 2703 #endif 2704 #if defined(CLOCK_IP_HAS_DMA_CLK) 2705 DMA_CLK = CLOCK_IP_HAS_DMA_CLK, 2706 #endif 2707 #if defined(CLOCK_IP_HAS_DMA_CRC_CLK) 2708 DMA_CRC_CLK = CLOCK_IP_HAS_DMA_CRC_CLK, 2709 #endif 2710 #if defined(CLOCK_IP_HAS_DMA_TCD_CLK) 2711 DMA_TCD_CLK = CLOCK_IP_HAS_DMA_TCD_CLK, 2712 #endif 2713 #if defined(CLOCK_IP_HAS_EIM_AP1_CLK) 2714 EIM_AP1_CLK = CLOCK_IP_HAS_EIM_AP1_CLK, 2715 #endif 2716 #if defined(CLOCK_IP_HAS_EIM_CM70_CLK) 2717 EIM_CM70_CLK = CLOCK_IP_HAS_EIM_CM70_CLK, 2718 #endif 2719 #if defined(CLOCK_IP_HAS_EIM_CM71_CLK) 2720 EIM_CM71_CLK = CLOCK_IP_HAS_EIM_CM71_CLK, 2721 #endif 2722 #if defined(CLOCK_IP_HAS_EIM_DSP_CLK) 2723 EIM_DSP_CLK = CLOCK_IP_HAS_EIM_DSP_CLK, 2724 #endif 2725 #if defined(CLOCK_IP_HAS_EIM_RT0_CLK) 2726 EIM_RT0_CLK = CLOCK_IP_HAS_EIM_RT0_CLK, 2727 #endif 2728 #if defined(CLOCK_IP_HAS_EIM_RT2_CLK) 2729 EIM_RT2_CLK = CLOCK_IP_HAS_EIM_RT2_CLK, 2730 #endif 2731 #if defined(CLOCK_IP_HAS_ERM_AP1_CLK) 2732 ERM_AP1_CLK = CLOCK_IP_HAS_ERM_AP1_CLK, 2733 #endif 2734 #if defined(CLOCK_IP_HAS_ERM_RT0_CLK) 2735 ERM_RT0_CLK = CLOCK_IP_HAS_ERM_RT0_CLK, 2736 #endif 2737 #if defined(CLOCK_IP_HAS_ERM_RT1_CLK) 2738 ERM_RT1_CLK = CLOCK_IP_HAS_ERM_RT1_CLK, 2739 #endif 2740 #if defined(CLOCK_IP_HAS_ERM_RT2_CLK) 2741 ERM_RT2_CLK = CLOCK_IP_HAS_ERM_RT2_CLK, 2742 #endif 2743 #if defined(CLOCK_IP_HAS_FCCU_IPS_CLK) 2744 FCCU_IPS_CLK = CLOCK_IP_HAS_FCCU_IPS_CLK, 2745 #endif 2746 #if defined(CLOCK_IP_HAS_SYS_M7_0_CLK) 2747 SYS_M7_0_CLK = CLOCK_IP_HAS_SYS_M7_0_CLK, 2748 #endif 2749 #if defined(CLOCK_IP_HAS_SYS_M7_1_CLK) 2750 SYS_M7_1_CLK = CLOCK_IP_HAS_SYS_M7_1_CLK, 2751 #endif 2752 #if defined(CLOCK_IP_HAS_SYS_HSE_CLK) 2753 SYS_HSE_CLK = CLOCK_IP_HAS_SYS_HSE_CLK, 2754 #endif 2755 #if defined(CLOCK_IP_HAS_MC_CLK) 2756 MC_CLK = CLOCK_IP_HAS_MC_CLK, 2757 #endif 2758 #if defined(CLOCK_IP_HAS_MIPICSI2_0_CLK) 2759 MIPICSI2_0_CLK = CLOCK_IP_HAS_MIPICSI2_0_CLK, 2760 #endif 2761 #if defined(CLOCK_IP_HAS_MIPICSI2_1_CLK) 2762 MIPICSI2_1_CLK = CLOCK_IP_HAS_MIPICSI2_1_CLK, 2763 #endif 2764 #if defined(CLOCK_IP_HAS_MSCDSPI_CLK) 2765 MSCDSPI_CLK = CLOCK_IP_HAS_MSCDSPI_CLK, 2766 #endif 2767 #if defined(CLOCK_IP_HAS_MSCLIN_CLK) 2768 MSCLIN_CLK = CLOCK_IP_HAS_MSCLIN_CLK, 2769 #endif 2770 #if defined(CLOCK_IP_HAS_NOC_TRACE_CLK) 2771 NOC_TRACE_CLK = CLOCK_IP_HAS_NOC_TRACE_CLK, 2772 #endif 2773 #if defined(CLOCK_IP_HAS_NANO_CLK) 2774 NANO_CLK = CLOCK_IP_HAS_NANO_CLK, 2775 #endif 2776 #if defined(CLOCK_IP_HAS_SAR_ADC_CLK) 2777 SAR_ADC_CLK = CLOCK_IP_HAS_SAR_ADC_CLK, 2778 #endif 2779 #if defined(CLOCK_IP_HAS_SDA_AP_CLK) 2780 SDA_AP_CLK = CLOCK_IP_HAS_SDA_AP_CLK, 2781 #endif 2782 #if defined(CLOCK_IP_HAS_SDADC0_CLK) 2783 SDADC0_CLK = CLOCK_IP_HAS_SDADC0_CLK, 2784 #endif 2785 #if defined(CLOCK_IP_HAS_SDADC1_CLK) 2786 SDADC1_CLK = CLOCK_IP_HAS_SDADC1_CLK, 2787 #endif 2788 #if defined(CLOCK_IP_HAS_SDADC2_CLK) 2789 SDADC2_CLK = CLOCK_IP_HAS_SDADC2_CLK, 2790 #endif 2791 #if defined(CLOCK_IP_HAS_SDADC3_CLK) 2792 SDADC3_CLK = CLOCK_IP_HAS_SDADC3_CLK, 2793 #endif 2794 #if defined(CLOCK_IP_HAS_SEMA42_1_CLK) 2795 SEMA42_1_CLK = CLOCK_IP_HAS_SEMA42_1_CLK, 2796 #endif 2797 #if defined(CLOCK_IP_HAS_SIUL2_CLK) 2798 SIUL2_CLK = CLOCK_IP_HAS_SIUL2_CLK, 2799 #endif 2800 #if defined(CLOCK_IP_HAS_SPT_CLK) 2801 SPT_CLK = CLOCK_IP_HAS_SPT_CLK, 2802 #endif 2803 #if defined(CLOCK_IP_HAS_SRAM_CLK) 2804 SRAM_CLK = CLOCK_IP_HAS_SRAM_CLK, 2805 #endif 2806 #if defined(CLOCK_IP_HAS_STCU_CLK) 2807 STCU_CLK = CLOCK_IP_HAS_STCU_CLK, 2808 #endif 2809 #if defined(CLOCK_IP_HAS_TMU_CLK) 2810 TMU_CLK = CLOCK_IP_HAS_TMU_CLK, 2811 #endif 2812 #if defined(CLOCK_IP_HAS_WKPU_CLK) 2813 WKPU_CLK = CLOCK_IP_HAS_WKPU_CLK, 2814 #endif 2815 #if defined(CLOCK_IP_HAS_XRDC0_CLK) 2816 XRDC0_CLK = CLOCK_IP_HAS_XRDC0_CLK, 2817 #endif 2818 #if defined(CLOCK_IP_HAS_XRDC1_CLK) 2819 XRDC1_CLK = CLOCK_IP_HAS_XRDC1_CLK, 2820 #endif 2821 #if defined(CLOCK_IP_HAS_CORE_PLL_REFCLKOUT) 2822 CORE_PLL_REFCLKOUT = CLOCK_IP_HAS_CORE_PLL_REFCLKOUT, 2823 #endif 2824 #if defined(CLOCK_IP_HAS_CORE_PLL_FBCLKOUT) 2825 CORE_PLL_FBCLKOUT = CLOCK_IP_HAS_CORE_PLL_FBCLKOUT, 2826 #endif 2827 #if defined(CLOCK_IP_HAS_PERIPH_PLL_REFCLKOUT) 2828 PERIPH_PLL_REFCLKOUT = CLOCK_IP_HAS_PERIPH_PLL_REFCLKOUT, 2829 #endif 2830 #if defined(CLOCK_IP_HAS_PERIPH_PLL_FBCLKOUT) 2831 PERIPH_PLL_FBCLKOUT = CLOCK_IP_HAS_PERIPH_PLL_FBCLKOUT, 2832 #endif 2833 #if defined(CLOCK_IP_HAS_TCLK_CLK) 2834 TCLK_CLK = CLOCK_IP_HAS_TCLK_CLK, 2835 #endif 2836 #if defined(CLOCK_IP_HAS_TCK_CLK) 2837 TCK_CLK = CLOCK_IP_HAS_TCK_CLK, 2838 #endif 2839 #if defined(CLOCK_IP_HAS_AES_CLK) 2840 AES_CLK = CLOCK_IP_HAS_AES_CLK, 2841 #endif 2842 #if defined(CLOCK_IP_HAS_AES_ACCEL_CLK) 2843 AES_ACCEL_CLK = CLOCK_IP_HAS_AES_ACCEL_CLK, 2844 #endif 2845 #if defined(CLOCK_IP_HAS_AES_APP0_CLK) 2846 AES_APP0_CLK = CLOCK_IP_HAS_AES_APP0_CLK, 2847 #endif 2848 #if defined(CLOCK_IP_HAS_AES_APP1_CLK) 2849 AES_APP1_CLK = CLOCK_IP_HAS_AES_APP1_CLK, 2850 #endif 2851 #if defined(CLOCK_IP_HAS_AES_APP2_CLK) 2852 AES_APP2_CLK = CLOCK_IP_HAS_AES_APP2_CLK, 2853 #endif 2854 #if defined(CLOCK_IP_HAS_AES_APP3_CLK) 2855 AES_APP3_CLK = CLOCK_IP_HAS_AES_APP3_CLK, 2856 #endif 2857 #if defined(CLOCK_IP_HAS_AES_APP4_CLK) 2858 AES_APP4_CLK = CLOCK_IP_HAS_AES_APP4_CLK, 2859 #endif 2860 #if defined(CLOCK_IP_HAS_AES_APP5_CLK) 2861 AES_APP5_CLK = CLOCK_IP_HAS_AES_APP5_CLK, 2862 #endif 2863 #if defined(CLOCK_IP_HAS_AES_APP6_CLK) 2864 AES_APP6_CLK = CLOCK_IP_HAS_AES_APP6_CLK, 2865 #endif 2866 #if defined(CLOCK_IP_HAS_AES_APP7_CLK) 2867 AES_APP7_CLK = CLOCK_IP_HAS_AES_APP7_CLK, 2868 #endif 2869 #if defined(CLOCK_IP_HAS_DSPI_SCK_TST_CLK) 2870 DSPI_SCK_TST_CLK = CLOCK_IP_HAS_DSPI_SCK_TST_CLK, 2871 #endif 2872 RESERVED_CLK = CLOCK_IP_FEATURE_NAMES_NO, /* Invalid clock name */ 2873 } Clock_Ip_NameType; 2874 2875 /** @brief Clock ip status return codes. */ 2876 typedef enum 2877 { 2878 CLOCK_IP_SUCCESS = 0x00U, /**< Clock tree was initialized successfully. */ 2879 CLOCK_IP_ERROR = 0x01U, /**< One of the elements timeout, clock tree couldn't be initialized. */ 2880 2881 } Clock_Ip_StatusType; 2882 2883 /** @brief Clock ip pll status return codes. */ 2884 typedef enum 2885 { 2886 CLOCK_IP_PLL_LOCKED = 0x00U, /**< PLL is locked */ 2887 CLOCK_IP_PLL_UNLOCKED = 0x01U, /**< PLL is unlocked */ 2888 CLOCK_IP_PLL_STATUS_UNDEFINED = 0x02U, /**< PLL Status is unknown */ 2889 2890 } Clock_Ip_PllStatusType; 2891 2892 /** @brief Clock ip report error types. */ 2893 typedef enum 2894 { 2895 CLOCK_IP_CMU_ERROR = 0U, /**< @brief Cmu Fccu notification. */ 2896 CLOCK_IP_REPORT_TIMEOUT_ERROR = 1U, /**< @brief Report Timeout Error. */ 2897 CLOCK_IP_REPORT_FXOSC_CONFIGURATION_ERROR = 2U, /**< @brief Report Fxosc Configuration Error. */ 2898 CLOCK_IP_REPORT_CLOCK_MUX_SWITCH_ERROR = 3U, /**< @brief Report Clock Mux Switch Error. */ 2899 CLOCK_IP_RAM_MEMORY_CONFIG_ENTRY = 4U, /**< @brief Ram config entry point. */ 2900 CLOCK_IP_RAM_MEMORY_CONFIG_EXIT = 5U, /**< @brief Ram config exit point. */ 2901 CLOCK_IP_FLASH_MEMORY_CONFIG_ENTRY = 6U, /**< @brief Flash config entry point. */ 2902 CLOCK_IP_FLASH_MEMORY_CONFIG_EXIT = 7U, /**< @brief Flash config exit point. */ 2903 CLOCK_IP_ACTIVE = 8U, /**< @brief Report Clock Active. */ 2904 CLOCK_IP_INACTIVE = 9U, /**< @brief Report Clock Inactive. */ 2905 CLOCK_IP_REPORT_WRITE_PROTECTION_ERROR = 10U, /**< @brief Report Write Protection Error. */ 2906 CLOCK_IP_SET_RAM_WAIT_STATES_ERROR = 11U, /**< @brief Set Ram Wait States Error. */ 2907 } Clock_Ip_NotificationType; 2908 2909 /** @brief Clock ip trigger divider type. */ 2910 typedef enum 2911 { 2912 IMMEDIATE_DIVIDER_UPDATE, /**< @brief Immediate divider update. */ 2913 COMMON_TRIGGER_DIVIDER_UPDATE, /**< @brief Common trigger divider update. */ 2914 2915 } Clock_Ip_TriggerDividerType; 2916 2917 /*================================================================================================== 2918 * STRUCTURES AND OTHER TYPEDEFS 2919 ==================================================================================================*/ 2920 /*! 2921 * @brief Clock notifications callback type. 2922 * Implements ClockNotificationsCallbackType_Class 2923 */ 2924 typedef void (*Clock_Ip_NotificationsCallbackType)(Clock_Ip_NotificationType Error, Clock_Ip_NameType ClockName); 2925 2926 /*! 2927 * @brief Register value structure. 2928 * Implements Clock_Ip_RegisterValueType_Class 2929 */ 2930 typedef struct 2931 { 2932 uint32* RegisterAddr; /**< Register address. */ 2933 uint32 RegisterData; /**< Register value. */ 2934 2935 } Clock_Ip_RegisterValueType; 2936 2937 /*! 2938 * @brief Register index structure. 2939 * Implements Clock_Ip_RegisterIndexType_Class 2940 */ 2941 typedef struct 2942 { 2943 uint16 StartIndex; /**< Start index in register array. */ 2944 uint16 EndIndex; /**< End index in register array. */ 2945 2946 } Clock_Ip_RegisterIndexType; 2947 2948 2949 2950 /*! 2951 * @brief Clock Source IRCOSC configuration structure. 2952 * Implements Clock_Ip_IrcoscConfigType_Class 2953 */ 2954 typedef struct 2955 { 2956 Clock_Ip_NameType Name; /**< Clock name associated to ircosc */ 2957 uint16 Enable; /**< Enable ircosc. */ 2958 2959 uint8 Regulator; /**< Enable regulator. */ 2960 uint8 Range; /**< Ircosc range. */ 2961 uint8 LowPowerModeEnable; /**< Ircosc enable in VLP mode */ 2962 uint8 StopModeEnable; /**< Ircosc enable in STOP mode */ 2963 2964 } Clock_Ip_IrcoscConfigType; 2965 2966 /*! 2967 * @brief CGM Clock Source XOSC configuration structure. 2968 * Implements Clock_Ip_XoscConfigType_Class 2969 */ 2970 typedef struct 2971 { 2972 Clock_Ip_NameType Name; /**< Clock name associated to xosc */ 2973 2974 uint32 Freq; /**< External oscillator frequency. */ 2975 2976 uint16 Enable; /**< Enable xosc. */ 2977 2978 uint16 StartupDelay; /**< Startup stabilization time. */ 2979 uint8 BypassOption; /**< XOSC bypass option */ 2980 uint8 CompEn; /**< Comparator enable */ 2981 uint8 TransConductance; /**< Crystal overdrive protection */ 2982 2983 uint8 Gain; /**< Gain value */ 2984 uint8 Monitor; /**< Monitor type */ 2985 uint8 AutoLevelController; /**< Automatic level controller */ 2986 2987 } Clock_Ip_XoscConfigType; 2988 2989 /*! 2990 * @brief CGM Clock Source PLLDIG configuration structure. 2991 * Implements Clock_Ip_PllConfigType_Class 2992 */ 2993 typedef struct 2994 { 2995 Clock_Ip_NameType Name; /**< Clock name associated to pll */ 2996 2997 uint16 Enable; /**< Enable pll. */ 2998 2999 Clock_Ip_NameType InputReference; /**< Input reference. */ 3000 3001 uint8 Bypass; /**< Bypass pll. */ 3002 3003 uint8 Predivider; /**< Input clock predivider. */ 3004 uint16 Multiplier; /**< Clock multiplier. */ 3005 uint8 Postdivider; /**< Clock postidivder.*/ 3006 3007 uint16 NumeratorFracLoopDiv; /**< Numerator of fractional loop division factor (MFN) */ 3008 uint8 MulFactorDiv; /**< Multiplication factor divider (MFD) */ 3009 3010 uint8 FrequencyModulationBypass; /**< Enable/disable modulation */ 3011 uint8 ModulationType; /**< Modulation type */ 3012 uint16 ModulationPeriod; /**< Stepsize - modulation period */ 3013 uint16 IncrementStep; /**< Stepno - step no */ 3014 3015 uint8 SigmaDelta; /**< Sigma Delta Modulation Enable */ 3016 3017 uint8 DitherControl; /**< Dither control enable */ 3018 uint8 DitherControlValue; /**< Dither control value */ 3019 3020 uint8 Monitor; /**< Monitor type */ 3021 3022 uint16 Dividers[3U]; /**< Dividers values */ 3023 3024 uint8 SoftwareDisable; /**< Software Disable */ 3025 } Clock_Ip_PllConfigType; 3026 3027 /*! 3028 * @brief Clock selector configuration structure. 3029 * Implements Clock_Ip_SelectorConfigType_Class 3030 */ 3031 typedef struct 3032 { 3033 Clock_Ip_NameType Name; /**< Clock name associated to selector */ 3034 Clock_Ip_NameType Value; /**< Name of the selected input source */ 3035 3036 } Clock_Ip_SelectorConfigType; 3037 3038 /*! 3039 * @brief Clock divider configuration structure. 3040 * Implements Clock_Ip_DividerConfigType_Class 3041 */ 3042 typedef struct 3043 { 3044 Clock_Ip_NameType Name; /**< Clock name associated to divider. */ 3045 uint32 Value; /**< Divider value - if value is zero then divider is disabled. */ 3046 uint8 Options[1U]; /**< Option divider value - this value depend hardware information. */ 3047 } Clock_Ip_DividerConfigType; 3048 3049 /*! 3050 * @brief Clock divider trigger configuration structure. 3051 * Implements Clock_Ip_DividerTriggerConfigType_Class 3052 */ 3053 typedef struct 3054 { 3055 Clock_Ip_NameType Name; /**< Clock name associated to divider for which trigger is configured. */ 3056 Clock_Ip_TriggerDividerType TriggerType; /**< Trigger value - if value is zero then divider is updated immediately, divider is not triggered. */ 3057 Clock_Ip_NameType Source; /**< Clock name of the common input source of all dividers from the same group that support a common update */ 3058 3059 } Clock_Ip_DividerTriggerConfigType; 3060 3061 3062 3063 /*! 3064 * @brief Clock fractional divider configuration structure. 3065 * Implements Clock_Ip_FracDivConfigType_Class 3066 */ 3067 typedef struct 3068 { 3069 Clock_Ip_NameType Name; /**< Clock name associated to fractional divider. */ 3070 uint8 Enable; /**< Enable control for port n */ 3071 uint32 Value[2U]; /**< Fractional dividers */ 3072 3073 } Clock_Ip_FracDivConfigType; 3074 3075 /*! 3076 * @brief Clock external clock configuration structure. 3077 * Implements Clock_Ip_ExtClkConfigType_Class 3078 */ 3079 typedef struct 3080 { 3081 Clock_Ip_NameType Name; /**< Clock name of the external clock. */ 3082 uint64 Value; /**< Enable value - if value is zero then clock is gated, otherwise is enabled in different modes. */ 3083 3084 } Clock_Ip_ExtClkConfigType; 3085 3086 /*! 3087 * @brief Clock Source PCFS configuration structure. 3088 * Implements Clock_Ip_PcfsConfigType_Class 3089 */ 3090 typedef struct 3091 { 3092 Clock_Ip_NameType Name; /**< Clock source from which ramp-down and to which ramp-up are processed. */ 3093 uint32 MaxAllowableIDDchange; /**< Maximum variation of current per time (mA/microsec) - max allowable IDD change is determined by the user's power supply design. */ 3094 uint32 StepDuration; /**< Step duration of each PCFS step */ 3095 Clock_Ip_NameType SelectorName; /**< Name of the selector that supports PCFS and name is one the inputs that can be selected */ 3096 uint32 ClockSourceFrequency; /**< Frequency of the clock source from which ramp-down and to which ramp-up are processed. */ 3097 3098 } Clock_Ip_PcfsConfigType; 3099 3100 /*! 3101 * @brief Clock gate clock configuration structure. 3102 * Implements Clock_Ip_GateConfigType_Class 3103 */ 3104 typedef struct 3105 { 3106 Clock_Ip_NameType Name; /**< Clock name associated to clock gate. */ 3107 uint16 Enable; /**< Enable or disable clock */ 3108 3109 } Clock_Ip_GateConfigType; 3110 3111 /*! 3112 * @brief Clock cmu configuration structure. 3113 * Implements Clock_Ip_CmuConfigType_Class 3114 */ 3115 typedef struct 3116 { 3117 Clock_Ip_NameType Name; /**< Clock name associated to clock monitor. */ 3118 uint8 Enable; /**< Enable/disable clock monitor */ 3119 uint32 Interrupt; /**< Enable/disable interrupt */ 3120 uint32 MonitoredClockFrequency; /**< Frequency of the clock source from which ramp-down and to which ramp-up are processed. */ 3121 Clock_Ip_RegisterIndexType Indexes; /**< Register index if register value optimization is enabled. */ 3122 } Clock_Ip_CmuConfigType; 3123 3124 /*! 3125 * @brief Configured frequency structure. 3126 * Implements Clock_Ip_ConfiguredFrequencyType_Class 3127 */ 3128 typedef struct 3129 { 3130 Clock_Ip_NameType Name; /**< Clock name of the configured frequency value */ 3131 uint32 ConfiguredFrequencyValue; /**< Configured frequency value */ 3132 } Clock_Ip_ConfiguredFrequencyType; 3133 3134 /*! 3135 * @brief Clock configuration structure. 3136 * Implements Clock_Ip_ClockConfigType_Class 3137 */ 3138 typedef struct 3139 { 3140 uint32 ClkConfigId; /**< The ID for Clock configuration */ 3141 3142 const Clock_Ip_RegisterValueType (*RegValues)[]; /**< Pointer to register values array */ 3143 3144 uint8 IrcoscsCount; /**< IRCOSCs count */ 3145 uint8 XoscsCount; /**< XOSCs count */ 3146 uint8 PllsCount; /**< PLLs count */ 3147 uint8 SelectorsCount; /**< Selectors count */ 3148 uint8 DividersCount; /**< Dividers count */ 3149 uint8 DividerTriggersCount; /**< Divider triggers count */ 3150 uint8 FracDivsCount; /**< Fractional dividers count */ 3151 uint8 ExtClksCount; /**< External clocks count */ 3152 uint8 GatesCount; /**< Clock gates count */ 3153 uint8 PcfsCount; /**< Clock pcfs count */ 3154 uint8 CmusCount; /**< Clock cmus count */ 3155 uint8 ConfigureFrequenciesCount; /**< Configured frequencies count */ 3156 3157 const Clock_Ip_IrcoscConfigType (*Ircoscs)[]; /**< IRCOSCs */ 3158 const Clock_Ip_XoscConfigType (*Xoscs)[]; /**< XOSCs */ 3159 const Clock_Ip_PllConfigType (*Plls)[]; /**< PLLs */ 3160 const Clock_Ip_SelectorConfigType (*Selectors)[]; /**< Selectors */ 3161 const Clock_Ip_DividerConfigType (*Dividers)[]; /**< Dividers */ 3162 const Clock_Ip_DividerTriggerConfigType (*DividerTriggers)[]; /**< Divider triggers */ 3163 const Clock_Ip_FracDivConfigType (*FracDivs)[]; /**< Fractional dividers */ 3164 const Clock_Ip_ExtClkConfigType (*ExtClks)[]; /**< External clocks */ 3165 const Clock_Ip_GateConfigType (*Gates)[]; /**< Clock gates */ 3166 const Clock_Ip_PcfsConfigType (*Pcfs)[]; /**< Progressive clock switching */ 3167 const Clock_Ip_CmuConfigType (*Cmus)[]; /**< Clock cmus */ 3168 const Clock_Ip_ConfiguredFrequencyType (*ConfiguredFrequencies)[]; /**< Configured frequency values */ 3169 3170 } Clock_Ip_ClockConfigType; 3171 3172 /*================================================================================================== 3173 * GLOBAL VARIABLE DECLARATIONS 3174 ==================================================================================================*/ 3175 3176 /*================================================================================================== 3177 * FUNCTION PROTOTYPES 3178 ==================================================================================================*/ 3179 3180 /*================================================================================================== 3181 CONFIGURATION STRUCTURE 3182 ==================================================================================================*/ 3183 3184 3185 #if defined(__cplusplus) 3186 } 3187 #endif /* __cplusplus*/ 3188 3189 /*! @}*/ 3190 3191 #endif /* CLOCK_IP_TYPES_H */ 3192 3193 3194
