1 /* 2 * Copyright (c) 2024 Intel Corporation 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_REGIONS_H_ 7 #define ZEPHYR_SOC_INTEL_ADSP_MEMORY_REGIONS_H_ 8 9 /* Define amount of regions other than core heaps that virtual memory will be split to 10 * currently includes shared heap and oma region and one regions set to 0 as for table 11 * iterator end value. 12 */ 13 #define VIRTUAL_REGION_COUNT 3 14 15 #define CORE_HEAP_SIZE 0x100000 16 #define SHARED_HEAP_SIZE 0x100000 17 #define OPPORTUNISTIC_REGION_SIZE 0x100000 18 19 /* size of TLB table */ 20 #define TLB_SIZE DT_REG_SIZE_BY_IDX(DT_INST(0, intel_adsp_mtl_tlb), 0) 21 22 /* Attribiutes for memory regions */ 23 #define MEM_REG_ATTR_CORE_HEAP 1U 24 #define MEM_REG_ATTR_SHARED_HEAP 2U 25 #define MEM_REG_ATTR_OPPORTUNISTIC_MEMORY 4U 26 27 #endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_REGIONS_H_ */ 28
