1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + Time Base Initialization
9 * + Time Base Start
10 * + Time Base Start Interruption
11 * + Time Base Start DMA
12 * + Time Output Compare/PWM Initialization
13 * + Time Output Compare/PWM Channel Configuration
14 * + Time Output Compare/PWM Start
15 * + Time Output Compare/PWM Start Interruption
16 * + Time Output Compare/PWM Start DMA
17 * + Time Input Capture Initialization
18 * + Time Input Capture Channel Configuration
19 * + Time Input Capture Start
20 * + Time Input Capture Start Interruption
21 * + Time Input Capture Start DMA
22 * + Time One Pulse Initialization
23 * + Time One Pulse Channel Configuration
24 * + Time One Pulse Start
25 * + Time Encoder Interface Initialization
26 * + Time Encoder Interface Start
27 * + Time Encoder Interface Start Interruption
28 * + Time Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + Time OCRef clear configuration
31 * + Time External Clock configuration
32 @verbatim
33 ==============================================================================
34 ##### TIMER Generic features #####
35 ==============================================================================
36 [..] The Timer features include:
37 (#) 16-bit up, down, up/down auto-reload counter.
38 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
39 counter clock frequency either by any factor between 1 and 65536.
40 (#) Up to 4 independent channels for:
41 (++) Input Capture
42 (++) Output Compare
43 (++) PWM generation (Edge and Center-aligned Mode)
44 (++) One-pulse mode output
45 (#) Synchronization circuit to control the timer with external signals and to interconnect
46 several timers together.
47 (#) Supports incremental encoder for positioning purposes
48
49 ##### How to use this driver #####
50 ==============================================================================
51 [..]
52 (#) Initialize the TIM low level resources by implementing the following functions
53 depending on the selected feature:
54 (++) Time Base : HAL_TIM_Base_MspInit()
55 (++) Input Capture : HAL_TIM_IC_MspInit()
56 (++) Output Compare : HAL_TIM_OC_MspInit()
57 (++) PWM generation : HAL_TIM_PWM_MspInit()
58 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
59 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
60
61 (#) Initialize the TIM low level resources :
62 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
63 (##) TIM pins configuration
64 (+++) Enable the clock for the TIM GPIOs using the following function:
65 __HAL_RCC_GPIOx_CLK_ENABLE();
66 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
67
68 (#) The external Clock can be configured, if needed (the default clock is the
69 internal clock from the APBx), using the following function:
70 HAL_TIM_ConfigClockSource, the clock configuration should be done before
71 any start function.
72
73 (#) Configure the TIM in the desired functioning mode using one of the
74 Initialization function of this driver:
75 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
76 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
77 Output Compare signal.
78 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
79 PWM signal.
80 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
81 external signal.
82 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
83 in One Pulse Mode.
84 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
85
86 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
87 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
88 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
89 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
90 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
91 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
92 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
93
94 (#) The DMA Burst is managed with the two following functions:
95 HAL_TIM_DMABurst_WriteStart()
96 HAL_TIM_DMABurst_ReadStart()
97
98 *** Callback registration ***
99 =============================================
100
101 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
102 allows the user to configure dynamically the driver callbacks.
103
104 Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
105 @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
106 the Callback ID and a pointer to the user callback function.
107
108 Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
109 weak function.
110 @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
111 and the Callback ID.
112
113 These functions allow to register/unregister following callbacks:
114 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
115 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
116 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
117 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
118 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
119 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
120 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
121 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
122 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
123 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
124 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
125 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
126 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
127 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
128 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
129 (+) TriggerCallback : TIM Trigger Callback.
130 (+) IC_CaptureCallback : TIM Input Capture Callback.
131 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
132 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
133 (+) ErrorCallback : TIM Error Callback.
134 (+) CommutationCallback : TIM Commutation Callback.
135 (+) BreakCallback : TIM Break Callback.
136
137 By default, after the Init and when the state is HAL_TIM_STATE_RESET
138 all interrupt callbacks are set to the corresponding weak functions:
139 examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
140
141 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
142 functionalities in the Init / DeInit only when these callbacks are null
143 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
144 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
145
146 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
147 Exception done MspInit / MspDeInit that can be registered / unregistered
148 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
149 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
150 In that case first register the MspInit/MspDeInit user callbacks
151 using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
152
153 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
154 not defined, the callback registration feature is not available and all callbacks
155 are set to the corresponding weak functions.
156
157 @endverbatim
158 ******************************************************************************
159 * @attention
160 *
161 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
162 *
163 * Redistribution and use in source and binary forms, with or without modification,
164 * are permitted provided that the following conditions are met:
165 * 1. Redistributions of source code must retain the above copyright notice,
166 * this list of conditions and the following disclaimer.
167 * 2. Redistributions in binary form must reproduce the above copyright notice,
168 * this list of conditions and the following disclaimer in the documentation
169 * and/or other materials provided with the distribution.
170 * 3. Neither the name of STMicroelectronics nor the names of its contributors
171 * may be used to endorse or promote products derived from this software
172 * without specific prior written permission.
173 *
174 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
175 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
176 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
177 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
178 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
179 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
180 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
181 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
182 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
183 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
184 *
185 ******************************************************************************
186 */
187
188 /* Includes ------------------------------------------------------------------*/
189 #include "stm32l4xx_hal.h"
190
191 /** @addtogroup STM32L4xx_HAL_Driver
192 * @{
193 */
194
195 /** @defgroup TIM TIM
196 * @brief TIM HAL module driver
197 * @{
198 */
199
200 #ifdef HAL_TIM_MODULE_ENABLED
201
202 /* Private typedef -----------------------------------------------------------*/
203 /* Private define ------------------------------------------------------------*/
204 /* Private macro -------------------------------------------------------------*/
205 /* Private variables ---------------------------------------------------------*/
206 /* Private function prototypes -----------------------------------------------*/
207 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
208 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
209 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
210 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
211 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
212 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
213 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
214 uint32_t TIM_ICFilter);
215 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
216 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
217 uint32_t TIM_ICFilter);
218 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
219 uint32_t TIM_ICFilter);
220 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
221 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
222 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
223 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
224 TIM_SlaveConfigTypeDef *sSlaveConfig);
225 /* Exported functions --------------------------------------------------------*/
226
227 /** @defgroup TIM_Exported_Functions TIM Exported Functions
228 * @{
229 */
230
231 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
232 * @brief Time Base functions
233 *
234 @verbatim
235 ==============================================================================
236 ##### Time Base functions #####
237 ==============================================================================
238 [..]
239 This section provides functions allowing to:
240 (+) Initialize and configure the TIM base.
241 (+) De-initialize the TIM base.
242 (+) Start the Time Base.
243 (+) Stop the Time Base.
244 (+) Start the Time Base and enable interrupt.
245 (+) Stop the Time Base and disable interrupt.
246 (+) Start the Time Base and enable DMA transfer.
247 (+) Stop the Time Base and disable DMA transfer.
248
249 @endverbatim
250 * @{
251 */
252 /**
253 * @brief Initializes the TIM Time base Unit according to the specified
254 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
255 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
256 * requires a timer reset to avoid unexpected direction
257 * due to DIR bit readonly in center aligned mode.
258 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
259 * @param htim TIM Base handle
260 * @retval HAL status
261 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)262 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
263 {
264 /* Check the TIM handle allocation */
265 if (htim == NULL)
266 {
267 return HAL_ERROR;
268 }
269
270 /* Check the parameters */
271 assert_param(IS_TIM_INSTANCE(htim->Instance));
272 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
273 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
274 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
275
276 if (htim->State == HAL_TIM_STATE_RESET)
277 {
278 /* Allocate lock resource and initialize it */
279 htim->Lock = HAL_UNLOCKED;
280
281 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
282 /* Reset interrupt callbacks to legacy week callbacks */
283 TIM_ResetCallback(htim);
284
285 if (htim->Base_MspInitCallback == NULL)
286 {
287 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
288 }
289 /* Init the low level hardware : GPIO, CLOCK, NVIC */
290 htim->Base_MspInitCallback(htim);
291 #else
292 /* Init the low level hardware : GPIO, CLOCK, NVIC */
293 HAL_TIM_Base_MspInit(htim);
294 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
295 }
296
297 /* Set the TIM state */
298 htim->State = HAL_TIM_STATE_BUSY;
299
300 /* Set the Time Base configuration */
301 TIM_Base_SetConfig(htim->Instance, &htim->Init);
302
303 /* Initialize the TIM state*/
304 htim->State = HAL_TIM_STATE_READY;
305
306 return HAL_OK;
307 }
308
309 /**
310 * @brief DeInitializes the TIM Base peripheral
311 * @param htim TIM Base handle
312 * @retval HAL status
313 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)314 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
315 {
316 /* Check the parameters */
317 assert_param(IS_TIM_INSTANCE(htim->Instance));
318
319 htim->State = HAL_TIM_STATE_BUSY;
320
321 /* Disable the TIM Peripheral Clock */
322 __HAL_TIM_DISABLE(htim);
323
324 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
325 if (htim->Base_MspDeInitCallback == NULL)
326 {
327 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
328 }
329 /* DeInit the low level hardware */
330 htim->Base_MspDeInitCallback(htim);
331 #else
332 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
333 HAL_TIM_Base_MspDeInit(htim);
334 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
335
336 /* Change TIM state */
337 htim->State = HAL_TIM_STATE_RESET;
338
339 /* Release Lock */
340 __HAL_UNLOCK(htim);
341
342 return HAL_OK;
343 }
344
345 /**
346 * @brief Initializes the TIM Base MSP.
347 * @param htim TIM Base handle
348 * @retval None
349 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)350 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
351 {
352 /* Prevent unused argument(s) compilation warning */
353 UNUSED(htim);
354
355 /* NOTE : This function should not be modified, when the callback is needed,
356 the HAL_TIM_Base_MspInit could be implemented in the user file
357 */
358 }
359
360 /**
361 * @brief DeInitializes TIM Base MSP.
362 * @param htim TIM Base handle
363 * @retval None
364 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)365 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
366 {
367 /* Prevent unused argument(s) compilation warning */
368 UNUSED(htim);
369
370 /* NOTE : This function should not be modified, when the callback is needed,
371 the HAL_TIM_Base_MspDeInit could be implemented in the user file
372 */
373 }
374
375
376 /**
377 * @brief Starts the TIM Base generation.
378 * @param htim TIM Base handle
379 * @retval HAL status
380 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)381 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
382 {
383 /* Check the parameters */
384 assert_param(IS_TIM_INSTANCE(htim->Instance));
385
386 /* Set the TIM state */
387 htim->State = HAL_TIM_STATE_BUSY;
388
389 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
390 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim))
391 {
392 __HAL_TIM_ENABLE(htim);
393 }
394
395 /* Change the TIM state*/
396 htim->State = HAL_TIM_STATE_READY;
397
398 /* Return function status */
399 return HAL_OK;
400 }
401
402 /**
403 * @brief Stops the TIM Base generation.
404 * @param htim TIM Base handle
405 * @retval HAL status
406 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)407 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
408 {
409 /* Check the parameters */
410 assert_param(IS_TIM_INSTANCE(htim->Instance));
411
412 /* Set the TIM state */
413 htim->State = HAL_TIM_STATE_BUSY;
414
415 /* Disable the Peripheral */
416 __HAL_TIM_DISABLE(htim);
417
418 /* Change the TIM state*/
419 htim->State = HAL_TIM_STATE_READY;
420
421 /* Return function status */
422 return HAL_OK;
423 }
424
425 /**
426 * @brief Starts the TIM Base generation in interrupt mode.
427 * @param htim TIM Base handle
428 * @retval HAL status
429 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)430 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
431 {
432 /* Check the parameters */
433 assert_param(IS_TIM_INSTANCE(htim->Instance));
434
435 /* Enable the TIM Update interrupt */
436 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
437
438 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
439 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim))
440 {
441 __HAL_TIM_ENABLE(htim);
442 }
443
444 /* Return function status */
445 return HAL_OK;
446 }
447
448 /**
449 * @brief Stops the TIM Base generation in interrupt mode.
450 * @param htim TIM Base handle
451 * @retval HAL status
452 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)453 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
454 {
455 /* Check the parameters */
456 assert_param(IS_TIM_INSTANCE(htim->Instance));
457 /* Disable the TIM Update interrupt */
458 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
459
460 /* Disable the Peripheral */
461 __HAL_TIM_DISABLE(htim);
462
463 /* Return function status */
464 return HAL_OK;
465 }
466
467 /**
468 * @brief Starts the TIM Base generation in DMA mode.
469 * @param htim TIM Base handle
470 * @param pData The source Buffer address.
471 * @param Length The length of data to be transferred from memory to peripheral.
472 * @retval HAL status
473 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)474 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
475 {
476 /* Check the parameters */
477 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
478
479 if ((htim->State == HAL_TIM_STATE_BUSY))
480 {
481 return HAL_BUSY;
482 }
483 else if ((htim->State == HAL_TIM_STATE_READY))
484 {
485 if ((pData == NULL) && (Length > 0U))
486 {
487 return HAL_ERROR;
488 }
489 else
490 {
491 htim->State = HAL_TIM_STATE_BUSY;
492 }
493 }
494 else
495 {
496 /* nothing to do */
497 }
498
499 /* Set the DMA Period elapsed callback */
500 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
501
502 /* Set the DMA error callback */
503 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
504
505 /* Enable the DMA channel */
506 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
507 {
508 return HAL_ERROR;
509 }
510
511 /* Enable the TIM Update DMA request */
512 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
513
514 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
515 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim))
516 {
517 __HAL_TIM_ENABLE(htim);
518 }
519
520 /* Return function status */
521 return HAL_OK;
522 }
523
524 /**
525 * @brief Stops the TIM Base generation in DMA mode.
526 * @param htim TIM Base handle
527 * @retval HAL status
528 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)529 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
530 {
531 /* Check the parameters */
532 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
533
534 /* Disable the TIM Update DMA request */
535 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
536
537 /* Disable the Peripheral */
538 __HAL_TIM_DISABLE(htim);
539
540 /* Change the htim state */
541 htim->State = HAL_TIM_STATE_READY;
542
543 /* Return function status */
544 return HAL_OK;
545 }
546
547 /**
548 * @}
549 */
550
551 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
552 * @brief Time Output Compare functions
553 *
554 @verbatim
555 ==============================================================================
556 ##### Time Output Compare functions #####
557 ==============================================================================
558 [..]
559 This section provides functions allowing to:
560 (+) Initialize and configure the TIM Output Compare.
561 (+) De-initialize the TIM Output Compare.
562 (+) Start the Time Output Compare.
563 (+) Stop the Time Output Compare.
564 (+) Start the Time Output Compare and enable interrupt.
565 (+) Stop the Time Output Compare and disable interrupt.
566 (+) Start the Time Output Compare and enable DMA transfer.
567 (+) Stop the Time Output Compare and disable DMA transfer.
568
569 @endverbatim
570 * @{
571 */
572 /**
573 * @brief Initializes the TIM Output Compare according to the specified
574 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
575 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
576 * requires a timer reset to avoid unexpected direction
577 * due to DIR bit readonly in center aligned mode.
578 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
579 * @param htim TIM Output Compare handle
580 * @retval HAL status
581 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)582 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
583 {
584 /* Check the TIM handle allocation */
585 if (htim == NULL)
586 {
587 return HAL_ERROR;
588 }
589
590 /* Check the parameters */
591 assert_param(IS_TIM_INSTANCE(htim->Instance));
592 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
593 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
594 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
595
596 if (htim->State == HAL_TIM_STATE_RESET)
597 {
598 /* Allocate lock resource and initialize it */
599 htim->Lock = HAL_UNLOCKED;
600
601 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
602 /* Reset interrupt callbacks to legacy week callbacks */
603 TIM_ResetCallback(htim);
604
605 if (htim->OC_MspInitCallback == NULL)
606 {
607 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
608 }
609 /* Init the low level hardware : GPIO, CLOCK, NVIC */
610 htim->OC_MspInitCallback(htim);
611 #else
612 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
613 HAL_TIM_OC_MspInit(htim);
614 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
615 }
616
617 /* Set the TIM state */
618 htim->State = HAL_TIM_STATE_BUSY;
619
620 /* Init the base time for the Output Compare */
621 TIM_Base_SetConfig(htim->Instance, &htim->Init);
622
623 /* Initialize the TIM state*/
624 htim->State = HAL_TIM_STATE_READY;
625
626 return HAL_OK;
627 }
628
629 /**
630 * @brief DeInitializes the TIM peripheral
631 * @param htim TIM Output Compare handle
632 * @retval HAL status
633 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)634 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
635 {
636 /* Check the parameters */
637 assert_param(IS_TIM_INSTANCE(htim->Instance));
638
639 htim->State = HAL_TIM_STATE_BUSY;
640
641 /* Disable the TIM Peripheral Clock */
642 __HAL_TIM_DISABLE(htim);
643
644 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
645 if (htim->OC_MspDeInitCallback == NULL)
646 {
647 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
648 }
649 /* DeInit the low level hardware */
650 htim->OC_MspDeInitCallback(htim);
651 #else
652 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
653 HAL_TIM_OC_MspDeInit(htim);
654 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
655
656 /* Change TIM state */
657 htim->State = HAL_TIM_STATE_RESET;
658
659 /* Release Lock */
660 __HAL_UNLOCK(htim);
661
662 return HAL_OK;
663 }
664
665 /**
666 * @brief Initializes the TIM Output Compare MSP.
667 * @param htim TIM Output Compare handle
668 * @retval None
669 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)670 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
671 {
672 /* Prevent unused argument(s) compilation warning */
673 UNUSED(htim);
674
675 /* NOTE : This function should not be modified, when the callback is needed,
676 the HAL_TIM_OC_MspInit could be implemented in the user file
677 */
678 }
679
680 /**
681 * @brief DeInitializes TIM Output Compare MSP.
682 * @param htim TIM Output Compare handle
683 * @retval None
684 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)685 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
686 {
687 /* Prevent unused argument(s) compilation warning */
688 UNUSED(htim);
689
690 /* NOTE : This function should not be modified, when the callback is needed,
691 the HAL_TIM_OC_MspDeInit could be implemented in the user file
692 */
693 }
694
695 /**
696 * @brief Starts the TIM Output Compare signal generation.
697 * @param htim TIM Output Compare handle
698 * @param Channel TIM Channel to be enabled
699 * This parameter can be one of the following values:
700 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
701 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
702 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
703 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
704 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
705 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
706 * @retval HAL status
707 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)708 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
709 {
710 /* Check the parameters */
711 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
712
713 /* Enable the Output compare channel */
714 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
715
716 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
717 {
718 /* Enable the main output */
719 __HAL_TIM_MOE_ENABLE(htim);
720 }
721
722 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
723 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim))
724 {
725 __HAL_TIM_ENABLE(htim);
726 }
727
728 /* Return function status */
729 return HAL_OK;
730 }
731
732 /**
733 * @brief Stops the TIM Output Compare signal generation.
734 * @param htim TIM Output Compare handle
735 * @param Channel TIM Channel to be disabled
736 * This parameter can be one of the following values:
737 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
738 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
739 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
740 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
741 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
742 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
743 * @retval HAL status
744 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)745 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
746 {
747 /* Check the parameters */
748 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
749
750 /* Disable the Output compare channel */
751 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
752
753 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
754 {
755 /* Disable the Main Output */
756 __HAL_TIM_MOE_DISABLE(htim);
757 }
758
759 /* Disable the Peripheral */
760 __HAL_TIM_DISABLE(htim);
761
762 /* Return function status */
763 return HAL_OK;
764 }
765
766 /**
767 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
768 * @param htim TIM Output Compare handle
769 * @param Channel TIM Channel to be enabled
770 * This parameter can be one of the following values:
771 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
772 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
773 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
774 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
775 * @retval HAL status
776 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)777 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
778 {
779 /* Check the parameters */
780 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
781
782 switch (Channel)
783 {
784 case TIM_CHANNEL_1:
785 {
786 /* Enable the TIM Capture/Compare 1 interrupt */
787 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
788 break;
789 }
790
791 case TIM_CHANNEL_2:
792 {
793 /* Enable the TIM Capture/Compare 2 interrupt */
794 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
795 break;
796 }
797
798 case TIM_CHANNEL_3:
799 {
800 /* Enable the TIM Capture/Compare 3 interrupt */
801 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
802 break;
803 }
804
805 case TIM_CHANNEL_4:
806 {
807 /* Enable the TIM Capture/Compare 4 interrupt */
808 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
809 break;
810 }
811
812 default:
813 break;
814 }
815
816 /* Enable the Output compare channel */
817 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
818
819 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
820 {
821 /* Enable the main output */
822 __HAL_TIM_MOE_ENABLE(htim);
823 }
824
825 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
826 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim))
827 {
828 __HAL_TIM_ENABLE(htim);
829 }
830
831 /* Return function status */
832 return HAL_OK;
833 }
834
835 /**
836 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
837 * @param htim TIM Output Compare handle
838 * @param Channel TIM Channel to be disabled
839 * This parameter can be one of the following values:
840 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
841 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
842 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
843 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
844 * @retval HAL status
845 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)846 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
847 {
848 /* Check the parameters */
849 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
850
851 switch (Channel)
852 {
853 case TIM_CHANNEL_1:
854 {
855 /* Disable the TIM Capture/Compare 1 interrupt */
856 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
857 break;
858 }
859
860 case TIM_CHANNEL_2:
861 {
862 /* Disable the TIM Capture/Compare 2 interrupt */
863 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
864 break;
865 }
866
867 case TIM_CHANNEL_3:
868 {
869 /* Disable the TIM Capture/Compare 3 interrupt */
870 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
871 break;
872 }
873
874 case TIM_CHANNEL_4:
875 {
876 /* Disable the TIM Capture/Compare 4 interrupt */
877 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
878 break;
879 }
880
881 default:
882 break;
883 }
884
885 /* Disable the Output compare channel */
886 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
887
888 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
889 {
890 /* Disable the Main Output */
891 __HAL_TIM_MOE_DISABLE(htim);
892 }
893
894 /* Disable the Peripheral */
895 __HAL_TIM_DISABLE(htim);
896
897 /* Return function status */
898 return HAL_OK;
899 }
900
901 /**
902 * @brief Starts the TIM Output Compare signal generation in DMA mode.
903 * @param htim TIM Output Compare handle
904 * @param Channel TIM Channel to be enabled
905 * This parameter can be one of the following values:
906 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
907 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
908 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
909 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
910 * @param pData The source Buffer address.
911 * @param Length The length of data to be transferred from memory to TIM peripheral
912 * @retval HAL status
913 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)914 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
915 {
916 /* Check the parameters */
917 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
918
919 if ((htim->State == HAL_TIM_STATE_BUSY))
920 {
921 return HAL_BUSY;
922 }
923 else if ((htim->State == HAL_TIM_STATE_READY))
924 {
925 if ((pData == NULL) && (Length > 0U))
926 {
927 return HAL_ERROR;
928 }
929 else
930 {
931 htim->State = HAL_TIM_STATE_BUSY;
932 }
933 }
934 else
935 {
936 /* nothing to do */
937 }
938
939 switch (Channel)
940 {
941 case TIM_CHANNEL_1:
942 {
943 /* Set the DMA Period elapsed callback */
944 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
945
946 /* Set the DMA error callback */
947 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
948
949 /* Enable the DMA channel */
950 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
951 {
952 return HAL_ERROR;
953 }
954
955 /* Enable the TIM Capture/Compare 1 DMA request */
956 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
957 break;
958 }
959
960 case TIM_CHANNEL_2:
961 {
962 /* Set the DMA Period elapsed callback */
963 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
964
965 /* Set the DMA error callback */
966 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
967
968 /* Enable the DMA channel */
969 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
970 {
971 return HAL_ERROR;
972 }
973
974 /* Enable the TIM Capture/Compare 2 DMA request */
975 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
976 break;
977 }
978
979 case TIM_CHANNEL_3:
980 {
981 /* Set the DMA Period elapsed callback */
982 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
983
984 /* Set the DMA error callback */
985 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
986
987 /* Enable the DMA channel */
988 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
989 {
990 return HAL_ERROR;
991 }
992 /* Enable the TIM Capture/Compare 3 DMA request */
993 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
994 break;
995 }
996
997 case TIM_CHANNEL_4:
998 {
999 /* Set the DMA Period elapsed callback */
1000 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1001
1002 /* Set the DMA error callback */
1003 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1004
1005 /* Enable the DMA channel */
1006 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1007 {
1008 return HAL_ERROR;
1009 }
1010 /* Enable the TIM Capture/Compare 4 DMA request */
1011 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1012 break;
1013 }
1014
1015 default:
1016 break;
1017 }
1018
1019 /* Enable the Output compare channel */
1020 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1021
1022 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1023 {
1024 /* Enable the main output */
1025 __HAL_TIM_MOE_ENABLE(htim);
1026 }
1027
1028 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1029 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim))
1030 {
1031 __HAL_TIM_ENABLE(htim);
1032 }
1033
1034 /* Return function status */
1035 return HAL_OK;
1036 }
1037
1038 /**
1039 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1040 * @param htim TIM Output Compare handle
1041 * @param Channel TIM Channel to be disabled
1042 * This parameter can be one of the following values:
1043 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1044 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1045 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1046 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1047 * @retval HAL status
1048 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1049 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1050 {
1051 /* Check the parameters */
1052 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1053
1054 switch (Channel)
1055 {
1056 case TIM_CHANNEL_1:
1057 {
1058 /* Disable the TIM Capture/Compare 1 DMA request */
1059 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1060 break;
1061 }
1062
1063 case TIM_CHANNEL_2:
1064 {
1065 /* Disable the TIM Capture/Compare 2 DMA request */
1066 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1067 break;
1068 }
1069
1070 case TIM_CHANNEL_3:
1071 {
1072 /* Disable the TIM Capture/Compare 3 DMA request */
1073 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1074 break;
1075 }
1076
1077 case TIM_CHANNEL_4:
1078 {
1079 /* Disable the TIM Capture/Compare 4 interrupt */
1080 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1081 break;
1082 }
1083
1084 default:
1085 break;
1086 }
1087
1088 /* Disable the Output compare channel */
1089 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1090
1091 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1092 {
1093 /* Disable the Main Output */
1094 __HAL_TIM_MOE_DISABLE(htim);
1095 }
1096
1097 /* Disable the Peripheral */
1098 __HAL_TIM_DISABLE(htim);
1099
1100 /* Change the htim state */
1101 htim->State = HAL_TIM_STATE_READY;
1102
1103 /* Return function status */
1104 return HAL_OK;
1105 }
1106
1107 /**
1108 * @}
1109 */
1110
1111 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
1112 * @brief Time PWM functions
1113 *
1114 @verbatim
1115 ==============================================================================
1116 ##### Time PWM functions #####
1117 ==============================================================================
1118 [..]
1119 This section provides functions allowing to:
1120 (+) Initialize and configure the TIM PWM.
1121 (+) De-initialize the TIM PWM.
1122 (+) Start the Time PWM.
1123 (+) Stop the Time PWM.
1124 (+) Start the Time PWM and enable interrupt.
1125 (+) Stop the Time PWM and disable interrupt.
1126 (+) Start the Time PWM and enable DMA transfer.
1127 (+) Stop the Time PWM and disable DMA transfer.
1128
1129 @endverbatim
1130 * @{
1131 */
1132 /**
1133 * @brief Initializes the TIM PWM Time Base according to the specified
1134 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1135 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1136 * requires a timer reset to avoid unexpected direction
1137 * due to DIR bit readonly in center aligned mode.
1138 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1139 * @param htim TIM PWM handle
1140 * @retval HAL status
1141 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1142 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1143 {
1144 /* Check the TIM handle allocation */
1145 if (htim == NULL)
1146 {
1147 return HAL_ERROR;
1148 }
1149
1150 /* Check the parameters */
1151 assert_param(IS_TIM_INSTANCE(htim->Instance));
1152 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1153 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1154 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1155
1156 if (htim->State == HAL_TIM_STATE_RESET)
1157 {
1158 /* Allocate lock resource and initialize it */
1159 htim->Lock = HAL_UNLOCKED;
1160
1161 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1162 /* Reset interrupt callbacks to legacy week callbacks */
1163 TIM_ResetCallback(htim);
1164
1165 if (htim->PWM_MspInitCallback == NULL)
1166 {
1167 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1168 }
1169 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1170 htim->PWM_MspInitCallback(htim);
1171 #else
1172 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1173 HAL_TIM_PWM_MspInit(htim);
1174 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1175 }
1176
1177 /* Set the TIM state */
1178 htim->State = HAL_TIM_STATE_BUSY;
1179
1180 /* Init the base time for the PWM */
1181 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1182
1183 /* Initialize the TIM state*/
1184 htim->State = HAL_TIM_STATE_READY;
1185
1186 return HAL_OK;
1187 }
1188
1189 /**
1190 * @brief DeInitializes the TIM peripheral
1191 * @param htim TIM PWM handle
1192 * @retval HAL status
1193 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1194 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1195 {
1196 /* Check the parameters */
1197 assert_param(IS_TIM_INSTANCE(htim->Instance));
1198
1199 htim->State = HAL_TIM_STATE_BUSY;
1200
1201 /* Disable the TIM Peripheral Clock */
1202 __HAL_TIM_DISABLE(htim);
1203
1204 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1205 if (htim->PWM_MspDeInitCallback == NULL)
1206 {
1207 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1208 }
1209 /* DeInit the low level hardware */
1210 htim->PWM_MspDeInitCallback(htim);
1211 #else
1212 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1213 HAL_TIM_PWM_MspDeInit(htim);
1214 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1215
1216 /* Change TIM state */
1217 htim->State = HAL_TIM_STATE_RESET;
1218
1219 /* Release Lock */
1220 __HAL_UNLOCK(htim);
1221
1222 return HAL_OK;
1223 }
1224
1225 /**
1226 * @brief Initializes the TIM PWM MSP.
1227 * @param htim TIM PWM handle
1228 * @retval None
1229 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1230 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1231 {
1232 /* Prevent unused argument(s) compilation warning */
1233 UNUSED(htim);
1234
1235 /* NOTE : This function should not be modified, when the callback is needed,
1236 the HAL_TIM_PWM_MspInit could be implemented in the user file
1237 */
1238 }
1239
1240 /**
1241 * @brief DeInitializes TIM PWM MSP.
1242 * @param htim TIM PWM handle
1243 * @retval None
1244 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1245 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1246 {
1247 /* Prevent unused argument(s) compilation warning */
1248 UNUSED(htim);
1249
1250 /* NOTE : This function should not be modified, when the callback is needed,
1251 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1252 */
1253 }
1254
1255 /**
1256 * @brief Starts the PWM signal generation.
1257 * @param htim TIM handle
1258 * @param Channel TIM Channels to be enabled
1259 * This parameter can be one of the following values:
1260 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1261 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1262 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1263 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1264 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1265 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1266 * @retval HAL status
1267 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1268 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1269 {
1270 /* Check the parameters */
1271 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1272
1273 /* Enable the Capture compare channel */
1274 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1275
1276 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1277 {
1278 /* Enable the main output */
1279 __HAL_TIM_MOE_ENABLE(htim);
1280 }
1281
1282 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1283 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim))
1284 {
1285 __HAL_TIM_ENABLE(htim);
1286 }
1287
1288 /* Return function status */
1289 return HAL_OK;
1290 }
1291
1292 /**
1293 * @brief Stops the PWM signal generation.
1294 * @param htim TIM PWM handle
1295 * @param Channel TIM Channels to be disabled
1296 * This parameter can be one of the following values:
1297 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1298 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1299 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1300 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1301 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1302 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1303 * @retval HAL status
1304 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1305 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1306 {
1307 /* Check the parameters */
1308 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1309
1310 /* Disable the Capture compare channel */
1311 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1312
1313 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1314 {
1315 /* Disable the Main Output */
1316 __HAL_TIM_MOE_DISABLE(htim);
1317 }
1318
1319 /* Disable the Peripheral */
1320 __HAL_TIM_DISABLE(htim);
1321
1322 /* Change the htim state */
1323 htim->State = HAL_TIM_STATE_READY;
1324
1325 /* Return function status */
1326 return HAL_OK;
1327 }
1328
1329 /**
1330 * @brief Starts the PWM signal generation in interrupt mode.
1331 * @param htim TIM PWM handle
1332 * @param Channel TIM Channel to be enabled
1333 * This parameter can be one of the following values:
1334 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1335 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1336 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1337 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1338 * @retval HAL status
1339 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1340 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1341 {
1342 /* Check the parameters */
1343 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1344
1345 switch (Channel)
1346 {
1347 case TIM_CHANNEL_1:
1348 {
1349 /* Enable the TIM Capture/Compare 1 interrupt */
1350 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1351 break;
1352 }
1353
1354 case TIM_CHANNEL_2:
1355 {
1356 /* Enable the TIM Capture/Compare 2 interrupt */
1357 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1358 break;
1359 }
1360
1361 case TIM_CHANNEL_3:
1362 {
1363 /* Enable the TIM Capture/Compare 3 interrupt */
1364 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1365 break;
1366 }
1367
1368 case TIM_CHANNEL_4:
1369 {
1370 /* Enable the TIM Capture/Compare 4 interrupt */
1371 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1372 break;
1373 }
1374
1375 default:
1376 break;
1377 }
1378
1379 /* Enable the Capture compare channel */
1380 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1381
1382 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1383 {
1384 /* Enable the main output */
1385 __HAL_TIM_MOE_ENABLE(htim);
1386 }
1387
1388 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1389 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim))
1390 {
1391 __HAL_TIM_ENABLE(htim);
1392 }
1393
1394 /* Return function status */
1395 return HAL_OK;
1396 }
1397
1398 /**
1399 * @brief Stops the PWM signal generation in interrupt mode.
1400 * @param htim TIM PWM handle
1401 * @param Channel TIM Channels to be disabled
1402 * This parameter can be one of the following values:
1403 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1404 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1405 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1406 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1407 * @retval HAL status
1408 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1409 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1410 {
1411 /* Check the parameters */
1412 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1413
1414 switch (Channel)
1415 {
1416 case TIM_CHANNEL_1:
1417 {
1418 /* Disable the TIM Capture/Compare 1 interrupt */
1419 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1420 break;
1421 }
1422
1423 case TIM_CHANNEL_2:
1424 {
1425 /* Disable the TIM Capture/Compare 2 interrupt */
1426 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1427 break;
1428 }
1429
1430 case TIM_CHANNEL_3:
1431 {
1432 /* Disable the TIM Capture/Compare 3 interrupt */
1433 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1434 break;
1435 }
1436
1437 case TIM_CHANNEL_4:
1438 {
1439 /* Disable the TIM Capture/Compare 4 interrupt */
1440 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1441 break;
1442 }
1443
1444 default:
1445 break;
1446 }
1447
1448 /* Disable the Capture compare channel */
1449 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1450
1451 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1452 {
1453 /* Disable the Main Output */
1454 __HAL_TIM_MOE_DISABLE(htim);
1455 }
1456
1457 /* Disable the Peripheral */
1458 __HAL_TIM_DISABLE(htim);
1459
1460 /* Return function status */
1461 return HAL_OK;
1462 }
1463
1464 /**
1465 * @brief Starts the TIM PWM signal generation in DMA mode.
1466 * @param htim TIM PWM handle
1467 * @param Channel TIM Channels to be enabled
1468 * This parameter can be one of the following values:
1469 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1470 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1471 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1472 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1473 * @param pData The source Buffer address.
1474 * @param Length The length of data to be transferred from memory to TIM peripheral
1475 * @retval HAL status
1476 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1477 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1478 {
1479 /* Check the parameters */
1480 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1481
1482 if ((htim->State == HAL_TIM_STATE_BUSY))
1483 {
1484 return HAL_BUSY;
1485 }
1486 else if ((htim->State == HAL_TIM_STATE_READY))
1487 {
1488 if ((pData == NULL) && (Length > 0U))
1489 {
1490 return HAL_ERROR;
1491 }
1492 else
1493 {
1494 htim->State = HAL_TIM_STATE_BUSY;
1495 }
1496 }
1497 else
1498 {
1499 /* nothing to do */
1500 }
1501
1502 switch (Channel)
1503 {
1504 case TIM_CHANNEL_1:
1505 {
1506 /* Set the DMA Period elapsed callback */
1507 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1508
1509 /* Set the DMA error callback */
1510 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1511
1512 /* Enable the DMA channel */
1513 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
1514 {
1515 return HAL_ERROR;
1516 }
1517
1518 /* Enable the TIM Capture/Compare 1 DMA request */
1519 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1520 break;
1521 }
1522
1523 case TIM_CHANNEL_2:
1524 {
1525 /* Set the DMA Period elapsed callback */
1526 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1527
1528 /* Set the DMA error callback */
1529 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1530
1531 /* Enable the DMA channel */
1532 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1533 {
1534 return HAL_ERROR;
1535 }
1536 /* Enable the TIM Capture/Compare 2 DMA request */
1537 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1538 break;
1539 }
1540
1541 case TIM_CHANNEL_3:
1542 {
1543 /* Set the DMA Period elapsed callback */
1544 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1545
1546 /* Set the DMA error callback */
1547 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1548
1549 /* Enable the DMA channel */
1550 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1551 {
1552 return HAL_ERROR;
1553 }
1554 /* Enable the TIM Output Capture/Compare 3 request */
1555 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1556 break;
1557 }
1558
1559 case TIM_CHANNEL_4:
1560 {
1561 /* Set the DMA Period elapsed callback */
1562 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1563
1564 /* Set the DMA error callback */
1565 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1566
1567 /* Enable the DMA channel */
1568 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1569 {
1570 return HAL_ERROR;
1571 }
1572 /* Enable the TIM Capture/Compare 4 DMA request */
1573 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1574 break;
1575 }
1576
1577 default:
1578 break;
1579 }
1580
1581 /* Enable the Capture compare channel */
1582 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1583
1584 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1585 {
1586 /* Enable the main output */
1587 __HAL_TIM_MOE_ENABLE(htim);
1588 }
1589
1590 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1591 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim))
1592 {
1593 __HAL_TIM_ENABLE(htim);
1594 }
1595
1596 /* Return function status */
1597 return HAL_OK;
1598 }
1599
1600 /**
1601 * @brief Stops the TIM PWM signal generation in DMA mode.
1602 * @param htim TIM PWM handle
1603 * @param Channel TIM Channels to be disabled
1604 * This parameter can be one of the following values:
1605 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1606 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1607 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1608 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1609 * @retval HAL status
1610 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1611 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1612 {
1613 /* Check the parameters */
1614 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1615
1616 switch (Channel)
1617 {
1618 case TIM_CHANNEL_1:
1619 {
1620 /* Disable the TIM Capture/Compare 1 DMA request */
1621 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1622 break;
1623 }
1624
1625 case TIM_CHANNEL_2:
1626 {
1627 /* Disable the TIM Capture/Compare 2 DMA request */
1628 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1629 break;
1630 }
1631
1632 case TIM_CHANNEL_3:
1633 {
1634 /* Disable the TIM Capture/Compare 3 DMA request */
1635 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1636 break;
1637 }
1638
1639 case TIM_CHANNEL_4:
1640 {
1641 /* Disable the TIM Capture/Compare 4 interrupt */
1642 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1643 break;
1644 }
1645
1646 default:
1647 break;
1648 }
1649
1650 /* Disable the Capture compare channel */
1651 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1652
1653 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1654 {
1655 /* Disable the Main Output */
1656 __HAL_TIM_MOE_DISABLE(htim);
1657 }
1658
1659 /* Disable the Peripheral */
1660 __HAL_TIM_DISABLE(htim);
1661
1662 /* Change the htim state */
1663 htim->State = HAL_TIM_STATE_READY;
1664
1665 /* Return function status */
1666 return HAL_OK;
1667 }
1668
1669 /**
1670 * @}
1671 */
1672
1673 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
1674 * @brief Time Input Capture functions
1675 *
1676 @verbatim
1677 ==============================================================================
1678 ##### TIM Input Capture functions #####
1679 ==============================================================================
1680 [..]
1681 This section provides functions allowing to:
1682 (+) Initialize and configure the TIM Input Capture.
1683 (+) De-initialize the TIM Input Capture.
1684 (+) Start the TIM Input Capture.
1685 (+) Stop the TIM Input Capture.
1686 (+) Start the TIM Input Capture and enable interrupt.
1687 (+) Stop the TIM Input Capture and disable interrupt.
1688 (+) Start the TIM Input Capture and enable DMA transfer.
1689 (+) Stop the TIM Input Capture and disable DMA transfer.
1690
1691 @endverbatim
1692 * @{
1693 */
1694 /**
1695 * @brief Initializes the TIM Input Capture Time base according to the specified
1696 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1697 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1698 * requires a timer reset to avoid unexpected direction
1699 * due to DIR bit readonly in center aligned mode.
1700 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1701 * @param htim TIM Input Capture handle
1702 * @retval HAL status
1703 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1704 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1705 {
1706 /* Check the TIM handle allocation */
1707 if (htim == NULL)
1708 {
1709 return HAL_ERROR;
1710 }
1711
1712 /* Check the parameters */
1713 assert_param(IS_TIM_INSTANCE(htim->Instance));
1714 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1715 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1716 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1717
1718 if (htim->State == HAL_TIM_STATE_RESET)
1719 {
1720 /* Allocate lock resource and initialize it */
1721 htim->Lock = HAL_UNLOCKED;
1722
1723 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1724 /* Reset interrupt callbacks to legacy week callbacks */
1725 TIM_ResetCallback(htim);
1726
1727 if (htim->IC_MspInitCallback == NULL)
1728 {
1729 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
1730 }
1731 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1732 htim->IC_MspInitCallback(htim);
1733 #else
1734 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1735 HAL_TIM_IC_MspInit(htim);
1736 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1737 }
1738
1739 /* Set the TIM state */
1740 htim->State = HAL_TIM_STATE_BUSY;
1741
1742 /* Init the base time for the input capture */
1743 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1744
1745 /* Initialize the TIM state*/
1746 htim->State = HAL_TIM_STATE_READY;
1747
1748 return HAL_OK;
1749 }
1750
1751 /**
1752 * @brief DeInitializes the TIM peripheral
1753 * @param htim TIM Input Capture handle
1754 * @retval HAL status
1755 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)1756 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1757 {
1758 /* Check the parameters */
1759 assert_param(IS_TIM_INSTANCE(htim->Instance));
1760
1761 htim->State = HAL_TIM_STATE_BUSY;
1762
1763 /* Disable the TIM Peripheral Clock */
1764 __HAL_TIM_DISABLE(htim);
1765
1766 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1767 if (htim->IC_MspDeInitCallback == NULL)
1768 {
1769 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
1770 }
1771 /* DeInit the low level hardware */
1772 htim->IC_MspDeInitCallback(htim);
1773 #else
1774 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1775 HAL_TIM_IC_MspDeInit(htim);
1776 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1777
1778 /* Change TIM state */
1779 htim->State = HAL_TIM_STATE_RESET;
1780
1781 /* Release Lock */
1782 __HAL_UNLOCK(htim);
1783
1784 return HAL_OK;
1785 }
1786
1787 /**
1788 * @brief Initializes the TIM Input Capture MSP.
1789 * @param htim TIM Input Capture handle
1790 * @retval None
1791 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)1792 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1793 {
1794 /* Prevent unused argument(s) compilation warning */
1795 UNUSED(htim);
1796
1797 /* NOTE : This function should not be modified, when the callback is needed,
1798 the HAL_TIM_IC_MspInit could be implemented in the user file
1799 */
1800 }
1801
1802 /**
1803 * @brief DeInitializes TIM Input Capture MSP.
1804 * @param htim TIM handle
1805 * @retval None
1806 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)1807 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1808 {
1809 /* Prevent unused argument(s) compilation warning */
1810 UNUSED(htim);
1811
1812 /* NOTE : This function should not be modified, when the callback is needed,
1813 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1814 */
1815 }
1816
1817 /**
1818 * @brief Starts the TIM Input Capture measurement.
1819 * @param htim TIM Input Capture handle
1820 * @param Channel TIM Channels to be enabled
1821 * This parameter can be one of the following values:
1822 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1823 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1824 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1825 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1826 * @retval HAL status
1827 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1828 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1829 {
1830 /* Check the parameters */
1831 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1832
1833 /* Enable the Input Capture channel */
1834 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1835
1836 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1837 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim))
1838 {
1839 __HAL_TIM_ENABLE(htim);
1840 }
1841
1842 /* Return function status */
1843 return HAL_OK;
1844 }
1845
1846 /**
1847 * @brief Stops the TIM Input Capture measurement.
1848 * @param htim TIM Input Capture handle
1849 * @param Channel TIM Channels to be disabled
1850 * This parameter can be one of the following values:
1851 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1852 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1853 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1854 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1855 * @retval HAL status
1856 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1857 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1858 {
1859 /* Check the parameters */
1860 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1861
1862 /* Disable the Input Capture channel */
1863 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1864
1865 /* Disable the Peripheral */
1866 __HAL_TIM_DISABLE(htim);
1867
1868 /* Return function status */
1869 return HAL_OK;
1870 }
1871
1872 /**
1873 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1874 * @param htim TIM Input Capture handle
1875 * @param Channel TIM Channels to be enabled
1876 * This parameter can be one of the following values:
1877 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1878 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1879 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1880 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1881 * @retval HAL status
1882 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1883 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1884 {
1885 /* Check the parameters */
1886 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1887
1888 switch (Channel)
1889 {
1890 case TIM_CHANNEL_1:
1891 {
1892 /* Enable the TIM Capture/Compare 1 interrupt */
1893 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1894 break;
1895 }
1896
1897 case TIM_CHANNEL_2:
1898 {
1899 /* Enable the TIM Capture/Compare 2 interrupt */
1900 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1901 break;
1902 }
1903
1904 case TIM_CHANNEL_3:
1905 {
1906 /* Enable the TIM Capture/Compare 3 interrupt */
1907 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1908 break;
1909 }
1910
1911 case TIM_CHANNEL_4:
1912 {
1913 /* Enable the TIM Capture/Compare 4 interrupt */
1914 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1915 break;
1916 }
1917
1918 default:
1919 break;
1920 }
1921 /* Enable the Input Capture channel */
1922 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1923
1924 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1925 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim))
1926 {
1927 __HAL_TIM_ENABLE(htim);
1928 }
1929
1930 /* Return function status */
1931 return HAL_OK;
1932 }
1933
1934 /**
1935 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1936 * @param htim TIM Input Capture handle
1937 * @param Channel TIM Channels to be disabled
1938 * This parameter can be one of the following values:
1939 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1940 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1941 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1942 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1943 * @retval HAL status
1944 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1945 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1946 {
1947 /* Check the parameters */
1948 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1949
1950 switch (Channel)
1951 {
1952 case TIM_CHANNEL_1:
1953 {
1954 /* Disable the TIM Capture/Compare 1 interrupt */
1955 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1956 break;
1957 }
1958
1959 case TIM_CHANNEL_2:
1960 {
1961 /* Disable the TIM Capture/Compare 2 interrupt */
1962 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1963 break;
1964 }
1965
1966 case TIM_CHANNEL_3:
1967 {
1968 /* Disable the TIM Capture/Compare 3 interrupt */
1969 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1970 break;
1971 }
1972
1973 case TIM_CHANNEL_4:
1974 {
1975 /* Disable the TIM Capture/Compare 4 interrupt */
1976 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1977 break;
1978 }
1979
1980 default:
1981 break;
1982 }
1983
1984 /* Disable the Input Capture channel */
1985 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1986
1987 /* Disable the Peripheral */
1988 __HAL_TIM_DISABLE(htim);
1989
1990 /* Return function status */
1991 return HAL_OK;
1992 }
1993
1994 /**
1995 * @brief Starts the TIM Input Capture measurement in DMA mode.
1996 * @param htim TIM Input Capture handle
1997 * @param Channel TIM Channels to be enabled
1998 * This parameter can be one of the following values:
1999 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2000 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2001 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2002 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2003 * @param pData The destination Buffer address.
2004 * @param Length The length of data to be transferred from TIM peripheral to memory.
2005 * @retval HAL status
2006 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2007 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2008 {
2009 /* Check the parameters */
2010 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2011 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2012
2013 if ((htim->State == HAL_TIM_STATE_BUSY))
2014 {
2015 return HAL_BUSY;
2016 }
2017 else if ((htim->State == HAL_TIM_STATE_READY))
2018 {
2019 if ((pData == NULL) && (Length > 0U))
2020 {
2021 return HAL_ERROR;
2022 }
2023 else
2024 {
2025 htim->State = HAL_TIM_STATE_BUSY;
2026 }
2027 }
2028 else
2029 {
2030 /* nothing to do */
2031 }
2032
2033 switch (Channel)
2034 {
2035 case TIM_CHANNEL_1:
2036 {
2037 /* Set the DMA Period elapsed callback */
2038 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2039
2040 /* Set the DMA error callback */
2041 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2042
2043 /* Enable the DMA channel */
2044 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2045 {
2046 return HAL_ERROR;
2047 }
2048 /* Enable the TIM Capture/Compare 1 DMA request */
2049 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2050 break;
2051 }
2052
2053 case TIM_CHANNEL_2:
2054 {
2055 /* Set the DMA Period elapsed callback */
2056 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2057
2058 /* Set the DMA error callback */
2059 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2060
2061 /* Enable the DMA channel */
2062 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2063 {
2064 return HAL_ERROR;
2065 }
2066 /* Enable the TIM Capture/Compare 2 DMA request */
2067 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2068 break;
2069 }
2070
2071 case TIM_CHANNEL_3:
2072 {
2073 /* Set the DMA Period elapsed callback */
2074 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2075
2076 /* Set the DMA error callback */
2077 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2078
2079 /* Enable the DMA channel */
2080 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
2081 {
2082 return HAL_ERROR;
2083 }
2084 /* Enable the TIM Capture/Compare 3 DMA request */
2085 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2086 break;
2087 }
2088
2089 case TIM_CHANNEL_4:
2090 {
2091 /* Set the DMA Period elapsed callback */
2092 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2093
2094 /* Set the DMA error callback */
2095 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2096
2097 /* Enable the DMA channel */
2098 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
2099 {
2100 return HAL_ERROR;
2101 }
2102 /* Enable the TIM Capture/Compare 4 DMA request */
2103 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2104 break;
2105 }
2106
2107 default:
2108 break;
2109 }
2110
2111 /* Enable the Input Capture channel */
2112 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2113
2114 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2115 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim))
2116 {
2117 __HAL_TIM_ENABLE(htim);
2118 }
2119
2120 /* Return function status */
2121 return HAL_OK;
2122 }
2123
2124 /**
2125 * @brief Stops the TIM Input Capture measurement in DMA mode.
2126 * @param htim TIM Input Capture handle
2127 * @param Channel TIM Channels to be disabled
2128 * This parameter can be one of the following values:
2129 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2130 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2131 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2132 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2133 * @retval HAL status
2134 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2135 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2136 {
2137 /* Check the parameters */
2138 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2139 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2140
2141 switch (Channel)
2142 {
2143 case TIM_CHANNEL_1:
2144 {
2145 /* Disable the TIM Capture/Compare 1 DMA request */
2146 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2147 break;
2148 }
2149
2150 case TIM_CHANNEL_2:
2151 {
2152 /* Disable the TIM Capture/Compare 2 DMA request */
2153 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2154 break;
2155 }
2156
2157 case TIM_CHANNEL_3:
2158 {
2159 /* Disable the TIM Capture/Compare 3 DMA request */
2160 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2161 break;
2162 }
2163
2164 case TIM_CHANNEL_4:
2165 {
2166 /* Disable the TIM Capture/Compare 4 DMA request */
2167 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2168 break;
2169 }
2170
2171 default:
2172 break;
2173 }
2174
2175 /* Disable the Input Capture channel */
2176 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2177
2178 /* Disable the Peripheral */
2179 __HAL_TIM_DISABLE(htim);
2180
2181 /* Change the htim state */
2182 htim->State = HAL_TIM_STATE_READY;
2183
2184 /* Return function status */
2185 return HAL_OK;
2186 }
2187 /**
2188 * @}
2189 */
2190
2191 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
2192 * @brief Time One Pulse functions
2193 *
2194 @verbatim
2195 ==============================================================================
2196 ##### Time One Pulse functions #####
2197 ==============================================================================
2198 [..]
2199 This section provides functions allowing to:
2200 (+) Initialize and configure the TIM One Pulse.
2201 (+) De-initialize the TIM One Pulse.
2202 (+) Start the TIM One Pulse.
2203 (+) Stop the TIM One Pulse.
2204 (+) Start the TIM One Pulse and enable interrupt.
2205 (+) Stop the TIM One Pulse and disable interrupt.
2206 (+) Start the TIM One Pulse and enable DMA transfer.
2207 (+) Stop the TIM One Pulse and disable DMA transfer.
2208
2209 @endverbatim
2210 * @{
2211 */
2212 /**
2213 * @brief Initializes the TIM One Pulse Time Base according to the specified
2214 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2215 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2216 * requires a timer reset to avoid unexpected direction
2217 * due to DIR bit readonly in center aligned mode.
2218 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2219 * @param htim TIM One Pulse handle
2220 * @param OnePulseMode Select the One pulse mode.
2221 * This parameter can be one of the following values:
2222 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2223 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2224 * @retval HAL status
2225 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2226 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2227 {
2228 /* Check the TIM handle allocation */
2229 if (htim == NULL)
2230 {
2231 return HAL_ERROR;
2232 }
2233
2234 /* Check the parameters */
2235 assert_param(IS_TIM_INSTANCE(htim->Instance));
2236 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2237 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2238 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2239 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2240
2241 if (htim->State == HAL_TIM_STATE_RESET)
2242 {
2243 /* Allocate lock resource and initialize it */
2244 htim->Lock = HAL_UNLOCKED;
2245
2246 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2247 /* Reset interrupt callbacks to legacy week callbacks */
2248 TIM_ResetCallback(htim);
2249
2250 if (htim->OnePulse_MspInitCallback == NULL)
2251 {
2252 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2253 }
2254 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2255 htim->OnePulse_MspInitCallback(htim);
2256 #else
2257 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2258 HAL_TIM_OnePulse_MspInit(htim);
2259 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2260 }
2261
2262 /* Set the TIM state */
2263 htim->State = HAL_TIM_STATE_BUSY;
2264
2265 /* Configure the Time base in the One Pulse Mode */
2266 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2267
2268 /* Reset the OPM Bit */
2269 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2270
2271 /* Configure the OPM Mode */
2272 htim->Instance->CR1 |= OnePulseMode;
2273
2274 /* Initialize the TIM state*/
2275 htim->State = HAL_TIM_STATE_READY;
2276
2277 return HAL_OK;
2278 }
2279
2280 /**
2281 * @brief DeInitializes the TIM One Pulse
2282 * @param htim TIM One Pulse handle
2283 * @retval HAL status
2284 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2285 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2286 {
2287 /* Check the parameters */
2288 assert_param(IS_TIM_INSTANCE(htim->Instance));
2289
2290 htim->State = HAL_TIM_STATE_BUSY;
2291
2292 /* Disable the TIM Peripheral Clock */
2293 __HAL_TIM_DISABLE(htim);
2294
2295 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2296 if (htim->OnePulse_MspDeInitCallback == NULL)
2297 {
2298 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2299 }
2300 /* DeInit the low level hardware */
2301 htim->OnePulse_MspDeInitCallback(htim);
2302 #else
2303 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2304 HAL_TIM_OnePulse_MspDeInit(htim);
2305 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2306
2307 /* Change TIM state */
2308 htim->State = HAL_TIM_STATE_RESET;
2309
2310 /* Release Lock */
2311 __HAL_UNLOCK(htim);
2312
2313 return HAL_OK;
2314 }
2315
2316 /**
2317 * @brief Initializes the TIM One Pulse MSP.
2318 * @param htim TIM One Pulse handle
2319 * @retval None
2320 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2321 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2322 {
2323 /* Prevent unused argument(s) compilation warning */
2324 UNUSED(htim);
2325
2326 /* NOTE : This function should not be modified, when the callback is needed,
2327 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2328 */
2329 }
2330
2331 /**
2332 * @brief DeInitializes TIM One Pulse MSP.
2333 * @param htim TIM One Pulse handle
2334 * @retval None
2335 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2336 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2337 {
2338 /* Prevent unused argument(s) compilation warning */
2339 UNUSED(htim);
2340
2341 /* NOTE : This function should not be modified, when the callback is needed,
2342 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2343 */
2344 }
2345
2346 /**
2347 * @brief Starts the TIM One Pulse signal generation.
2348 * @param htim TIM One Pulse handle
2349 * @param OutputChannel TIM Channels to be enabled
2350 * This parameter can be one of the following values:
2351 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2352 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2353 * @retval HAL status
2354 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2355 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2356 {
2357 /* Prevent unused argument(s) compilation warning */
2358 UNUSED(OutputChannel);
2359
2360 /* Enable the Capture compare and the Input Capture channels
2361 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2362 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2363 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2364 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2365
2366 No need to enable the counter, it's enabled automatically by hardware
2367 (the counter starts in response to a stimulus and generate a pulse */
2368
2369 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2370 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2371
2372 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2373 {
2374 /* Enable the main output */
2375 __HAL_TIM_MOE_ENABLE(htim);
2376 }
2377
2378 /* Return function status */
2379 return HAL_OK;
2380 }
2381
2382 /**
2383 * @brief Stops the TIM One Pulse signal generation.
2384 * @param htim TIM One Pulse handle
2385 * @param OutputChannel TIM Channels to be disable
2386 * This parameter can be one of the following values:
2387 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2388 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2389 * @retval HAL status
2390 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2391 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2392 {
2393 /* Prevent unused argument(s) compilation warning */
2394 UNUSED(OutputChannel);
2395
2396 /* Disable the Capture compare and the Input Capture channels
2397 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2398 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2399 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2400 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2401
2402 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2403 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2404
2405 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2406 {
2407 /* Disable the Main Output */
2408 __HAL_TIM_MOE_DISABLE(htim);
2409 }
2410
2411 /* Disable the Peripheral */
2412 __HAL_TIM_DISABLE(htim);
2413
2414 /* Return function status */
2415 return HAL_OK;
2416 }
2417
2418 /**
2419 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2420 * @param htim TIM One Pulse handle
2421 * @param OutputChannel TIM Channels to be enabled
2422 * This parameter can be one of the following values:
2423 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2424 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2425 * @retval HAL status
2426 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2427 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2428 {
2429 /* Prevent unused argument(s) compilation warning */
2430 UNUSED(OutputChannel);
2431
2432 /* Enable the Capture compare and the Input Capture channels
2433 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2434 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2435 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2436 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2437
2438 No need to enable the counter, it's enabled automatically by hardware
2439 (the counter starts in response to a stimulus and generate a pulse */
2440
2441 /* Enable the TIM Capture/Compare 1 interrupt */
2442 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2443
2444 /* Enable the TIM Capture/Compare 2 interrupt */
2445 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2446
2447 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2448 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2449
2450 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2451 {
2452 /* Enable the main output */
2453 __HAL_TIM_MOE_ENABLE(htim);
2454 }
2455
2456 /* Return function status */
2457 return HAL_OK;
2458 }
2459
2460 /**
2461 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2462 * @param htim TIM One Pulse handle
2463 * @param OutputChannel TIM Channels to be enabled
2464 * This parameter can be one of the following values:
2465 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2466 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2467 * @retval HAL status
2468 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2469 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2470 {
2471 /* Prevent unused argument(s) compilation warning */
2472 UNUSED(OutputChannel);
2473
2474 /* Disable the TIM Capture/Compare 1 interrupt */
2475 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2476
2477 /* Disable the TIM Capture/Compare 2 interrupt */
2478 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2479
2480 /* Disable the Capture compare and the Input Capture channels
2481 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2482 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2483 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2484 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2485 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2486 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2487
2488 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2489 {
2490 /* Disable the Main Output */
2491 __HAL_TIM_MOE_DISABLE(htim);
2492 }
2493
2494 /* Disable the Peripheral */
2495 __HAL_TIM_DISABLE(htim);
2496
2497 /* Return function status */
2498 return HAL_OK;
2499 }
2500
2501 /**
2502 * @}
2503 */
2504
2505 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
2506 * @brief Time Encoder functions
2507 *
2508 @verbatim
2509 ==============================================================================
2510 ##### TIM Encoder functions #####
2511 ==============================================================================
2512 [..]
2513 This section provides functions allowing to:
2514 (+) Initialize and configure the TIM Encoder.
2515 (+) De-initialize the TIM Encoder.
2516 (+) Start the TIM Encoder.
2517 (+) Stop the TIM Encoder.
2518 (+) Start the TIM Encoder and enable interrupt.
2519 (+) Stop the TIM Encoder and disable interrupt.
2520 (+) Start the TIM Encoder and enable DMA transfer.
2521 (+) Stop the TIM Encoder and disable DMA transfer.
2522
2523 @endverbatim
2524 * @{
2525 */
2526 /**
2527 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
2528 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2529 * requires a timer reset to avoid unexpected direction
2530 * due to DIR bit readonly in center aligned mode.
2531 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
2532 * @param htim TIM Encoder Interface handle
2533 * @param sConfig TIM Encoder Interface configuration structure
2534 * @retval HAL status
2535 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,TIM_Encoder_InitTypeDef * sConfig)2536 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
2537 {
2538 uint32_t tmpsmcr;
2539 uint32_t tmpccmr1;
2540 uint32_t tmpccer;
2541
2542 /* Check the TIM handle allocation */
2543 if (htim == NULL)
2544 {
2545 return HAL_ERROR;
2546 }
2547
2548 /* Check the parameters */
2549 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2550 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2551 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2552 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2553 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2554 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2555 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2556 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2557 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2558 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2559 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2560 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2561 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2562 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2563 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2564 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2565
2566 if (htim->State == HAL_TIM_STATE_RESET)
2567 {
2568 /* Allocate lock resource and initialize it */
2569 htim->Lock = HAL_UNLOCKED;
2570
2571 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2572 /* Reset interrupt callbacks to legacy week callbacks */
2573 TIM_ResetCallback(htim);
2574
2575 if (htim->Encoder_MspInitCallback == NULL)
2576 {
2577 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
2578 }
2579 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2580 htim->Encoder_MspInitCallback(htim);
2581 #else
2582 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2583 HAL_TIM_Encoder_MspInit(htim);
2584 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2585 }
2586
2587 /* Set the TIM state */
2588 htim->State = HAL_TIM_STATE_BUSY;
2589
2590 /* Reset the SMS bits */
2591 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
2592
2593 /* Configure the Time base in the Encoder Mode */
2594 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2595
2596 /* Get the TIMx SMCR register value */
2597 tmpsmcr = htim->Instance->SMCR;
2598
2599 /* Get the TIMx CCMR1 register value */
2600 tmpccmr1 = htim->Instance->CCMR1;
2601
2602 /* Get the TIMx CCER register value */
2603 tmpccer = htim->Instance->CCER;
2604
2605 /* Set the encoder Mode */
2606 tmpsmcr |= sConfig->EncoderMode;
2607
2608 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2609 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2610 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
2611
2612 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2613 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2614 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2615 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
2616 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
2617
2618 /* Set the TI1 and the TI2 Polarities */
2619 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2620 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2621 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
2622
2623 /* Write to TIMx SMCR */
2624 htim->Instance->SMCR = tmpsmcr;
2625
2626 /* Write to TIMx CCMR1 */
2627 htim->Instance->CCMR1 = tmpccmr1;
2628
2629 /* Write to TIMx CCER */
2630 htim->Instance->CCER = tmpccer;
2631
2632 /* Initialize the TIM state*/
2633 htim->State = HAL_TIM_STATE_READY;
2634
2635 return HAL_OK;
2636 }
2637
2638
2639 /**
2640 * @brief DeInitializes the TIM Encoder interface
2641 * @param htim TIM Encoder Interface handle
2642 * @retval HAL status
2643 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)2644 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2645 {
2646 /* Check the parameters */
2647 assert_param(IS_TIM_INSTANCE(htim->Instance));
2648
2649 htim->State = HAL_TIM_STATE_BUSY;
2650
2651 /* Disable the TIM Peripheral Clock */
2652 __HAL_TIM_DISABLE(htim);
2653
2654 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2655 if (htim->Encoder_MspDeInitCallback == NULL)
2656 {
2657 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
2658 }
2659 /* DeInit the low level hardware */
2660 htim->Encoder_MspDeInitCallback(htim);
2661 #else
2662 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2663 HAL_TIM_Encoder_MspDeInit(htim);
2664 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2665
2666 /* Change TIM state */
2667 htim->State = HAL_TIM_STATE_RESET;
2668
2669 /* Release Lock */
2670 __HAL_UNLOCK(htim);
2671
2672 return HAL_OK;
2673 }
2674
2675 /**
2676 * @brief Initializes the TIM Encoder Interface MSP.
2677 * @param htim TIM Encoder Interface handle
2678 * @retval None
2679 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)2680 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2681 {
2682 /* Prevent unused argument(s) compilation warning */
2683 UNUSED(htim);
2684
2685 /* NOTE : This function should not be modified, when the callback is needed,
2686 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2687 */
2688 }
2689
2690 /**
2691 * @brief DeInitializes TIM Encoder Interface MSP.
2692 * @param htim TIM Encoder Interface handle
2693 * @retval None
2694 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)2695 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2696 {
2697 /* Prevent unused argument(s) compilation warning */
2698 UNUSED(htim);
2699
2700 /* NOTE : This function should not be modified, when the callback is needed,
2701 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2702 */
2703 }
2704
2705 /**
2706 * @brief Starts the TIM Encoder Interface.
2707 * @param htim TIM Encoder Interface handle
2708 * @param Channel TIM Channels to be enabled
2709 * This parameter can be one of the following values:
2710 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2711 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2712 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2713 * @retval HAL status
2714 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2715 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2716 {
2717 /* Check the parameters */
2718 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2719
2720 /* Enable the encoder interface channels */
2721 switch (Channel)
2722 {
2723 case TIM_CHANNEL_1:
2724 {
2725 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2726 break;
2727 }
2728
2729 case TIM_CHANNEL_2:
2730 {
2731 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2732 break;
2733 }
2734
2735 default :
2736 {
2737 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2738 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2739 break;
2740 }
2741 }
2742 /* Enable the Peripheral */
2743 __HAL_TIM_ENABLE(htim);
2744
2745 /* Return function status */
2746 return HAL_OK;
2747 }
2748
2749 /**
2750 * @brief Stops the TIM Encoder Interface.
2751 * @param htim TIM Encoder Interface handle
2752 * @param Channel TIM Channels to be disabled
2753 * This parameter can be one of the following values:
2754 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2755 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2756 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2757 * @retval HAL status
2758 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2759 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2760 {
2761 /* Check the parameters */
2762 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2763
2764 /* Disable the Input Capture channels 1 and 2
2765 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2766 switch (Channel)
2767 {
2768 case TIM_CHANNEL_1:
2769 {
2770 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2771 break;
2772 }
2773
2774 case TIM_CHANNEL_2:
2775 {
2776 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2777 break;
2778 }
2779
2780 default :
2781 {
2782 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2783 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2784 break;
2785 }
2786 }
2787
2788 /* Disable the Peripheral */
2789 __HAL_TIM_DISABLE(htim);
2790
2791 /* Return function status */
2792 return HAL_OK;
2793 }
2794
2795 /**
2796 * @brief Starts the TIM Encoder Interface in interrupt mode.
2797 * @param htim TIM Encoder Interface handle
2798 * @param Channel TIM Channels to be enabled
2799 * This parameter can be one of the following values:
2800 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2801 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2802 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2803 * @retval HAL status
2804 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2805 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2806 {
2807 /* Check the parameters */
2808 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2809
2810 /* Enable the encoder interface channels */
2811 /* Enable the capture compare Interrupts 1 and/or 2 */
2812 switch (Channel)
2813 {
2814 case TIM_CHANNEL_1:
2815 {
2816 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2817 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2818 break;
2819 }
2820
2821 case TIM_CHANNEL_2:
2822 {
2823 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2824 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2825 break;
2826 }
2827
2828 default :
2829 {
2830 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2831 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2832 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2833 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2834 break;
2835 }
2836 }
2837
2838 /* Enable the Peripheral */
2839 __HAL_TIM_ENABLE(htim);
2840
2841 /* Return function status */
2842 return HAL_OK;
2843 }
2844
2845 /**
2846 * @brief Stops the TIM Encoder Interface in interrupt mode.
2847 * @param htim TIM Encoder Interface handle
2848 * @param Channel TIM Channels to be disabled
2849 * This parameter can be one of the following values:
2850 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2851 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2852 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2853 * @retval HAL status
2854 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2855 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2856 {
2857 /* Check the parameters */
2858 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2859
2860 /* Disable the Input Capture channels 1 and 2
2861 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2862 if (Channel == TIM_CHANNEL_1)
2863 {
2864 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2865
2866 /* Disable the capture compare Interrupts 1 */
2867 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2868 }
2869 else if (Channel == TIM_CHANNEL_2)
2870 {
2871 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2872
2873 /* Disable the capture compare Interrupts 2 */
2874 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2875 }
2876 else
2877 {
2878 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2879 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2880
2881 /* Disable the capture compare Interrupts 1 and 2 */
2882 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2883 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2884 }
2885
2886 /* Disable the Peripheral */
2887 __HAL_TIM_DISABLE(htim);
2888
2889 /* Change the htim state */
2890 htim->State = HAL_TIM_STATE_READY;
2891
2892 /* Return function status */
2893 return HAL_OK;
2894 }
2895
2896 /**
2897 * @brief Starts the TIM Encoder Interface in DMA mode.
2898 * @param htim TIM Encoder Interface handle
2899 * @param Channel TIM Channels to be enabled
2900 * This parameter can be one of the following values:
2901 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2902 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2903 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2904 * @param pData1 The destination Buffer address for IC1.
2905 * @param pData2 The destination Buffer address for IC2.
2906 * @param Length The length of data to be transferred from TIM peripheral to memory.
2907 * @retval HAL status
2908 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)2909 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
2910 {
2911 /* Check the parameters */
2912 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2913
2914 if ((htim->State == HAL_TIM_STATE_BUSY))
2915 {
2916 return HAL_BUSY;
2917 }
2918 else if ((htim->State == HAL_TIM_STATE_READY))
2919 {
2920 if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
2921 {
2922 return HAL_ERROR;
2923 }
2924 else
2925 {
2926 htim->State = HAL_TIM_STATE_BUSY;
2927 }
2928 }
2929 else
2930 {
2931 /* nothing to do */
2932 }
2933
2934 switch (Channel)
2935 {
2936 case TIM_CHANNEL_1:
2937 {
2938 /* Set the DMA Period elapsed callback */
2939 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2940
2941 /* Set the DMA error callback */
2942 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2943
2944 /* Enable the DMA channel */
2945 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
2946 {
2947 return HAL_ERROR;
2948 }
2949 /* Enable the TIM Input Capture DMA request */
2950 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2951
2952 /* Enable the Peripheral */
2953 __HAL_TIM_ENABLE(htim);
2954
2955 /* Enable the Capture compare channel */
2956 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2957 break;
2958 }
2959
2960 case TIM_CHANNEL_2:
2961 {
2962 /* Set the DMA Period elapsed callback */
2963 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2964
2965 /* Set the DMA error callback */
2966 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
2967 /* Enable the DMA channel */
2968 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
2969 {
2970 return HAL_ERROR;
2971 }
2972 /* Enable the TIM Input Capture DMA request */
2973 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2974
2975 /* Enable the Peripheral */
2976 __HAL_TIM_ENABLE(htim);
2977
2978 /* Enable the Capture compare channel */
2979 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2980 break;
2981 }
2982
2983 case TIM_CHANNEL_ALL:
2984 {
2985 /* Set the DMA Period elapsed callback */
2986 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2987
2988 /* Set the DMA error callback */
2989 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2990
2991 /* Enable the DMA channel */
2992 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
2993 {
2994 return HAL_ERROR;
2995 }
2996
2997 /* Set the DMA Period elapsed callback */
2998 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2999
3000 /* Set the DMA error callback */
3001 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3002
3003 /* Enable the DMA channel */
3004 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3005 {
3006 return HAL_ERROR;
3007 }
3008 /* Enable the Peripheral */
3009 __HAL_TIM_ENABLE(htim);
3010
3011 /* Enable the Capture compare channel */
3012 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3013 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3014
3015 /* Enable the TIM Input Capture DMA request */
3016 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3017 /* Enable the TIM Input Capture DMA request */
3018 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3019 break;
3020 }
3021
3022 default:
3023 break;
3024 }
3025 /* Return function status */
3026 return HAL_OK;
3027 }
3028
3029 /**
3030 * @brief Stops the TIM Encoder Interface in DMA mode.
3031 * @param htim TIM Encoder Interface handle
3032 * @param Channel TIM Channels to be enabled
3033 * This parameter can be one of the following values:
3034 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3035 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3036 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3037 * @retval HAL status
3038 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3039 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3040 {
3041 /* Check the parameters */
3042 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
3043
3044 /* Disable the Input Capture channels 1 and 2
3045 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3046 if (Channel == TIM_CHANNEL_1)
3047 {
3048 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3049
3050 /* Disable the capture compare DMA Request 1 */
3051 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3052 }
3053 else if (Channel == TIM_CHANNEL_2)
3054 {
3055 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3056
3057 /* Disable the capture compare DMA Request 2 */
3058 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3059 }
3060 else
3061 {
3062 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3063 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3064
3065 /* Disable the capture compare DMA Request 1 and 2 */
3066 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3067 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3068 }
3069
3070 /* Disable the Peripheral */
3071 __HAL_TIM_DISABLE(htim);
3072
3073 /* Change the htim state */
3074 htim->State = HAL_TIM_STATE_READY;
3075
3076 /* Return function status */
3077 return HAL_OK;
3078 }
3079
3080 /**
3081 * @}
3082 */
3083 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3084 * @brief IRQ handler management
3085 *
3086 @verbatim
3087 ==============================================================================
3088 ##### IRQ handler management #####
3089 ==============================================================================
3090 [..]
3091 This section provides Timer IRQ handler function.
3092
3093 @endverbatim
3094 * @{
3095 */
3096 /**
3097 * @brief This function handles TIM interrupts requests.
3098 * @param htim TIM handle
3099 * @retval None
3100 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3101 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3102 {
3103 /* Capture compare 1 event */
3104 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3105 {
3106 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3107 {
3108 {
3109 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3110 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3111
3112 /* Input capture event */
3113 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3114 {
3115 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3116 htim->IC_CaptureCallback(htim);
3117 #else
3118 HAL_TIM_IC_CaptureCallback(htim);
3119 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3120 }
3121 /* Output compare event */
3122 else
3123 {
3124 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3125 htim->OC_DelayElapsedCallback(htim);
3126 htim->PWM_PulseFinishedCallback(htim);
3127 #else
3128 HAL_TIM_OC_DelayElapsedCallback(htim);
3129 HAL_TIM_PWM_PulseFinishedCallback(htim);
3130 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3131 }
3132 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3133 }
3134 }
3135 }
3136 /* Capture compare 2 event */
3137 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3138 {
3139 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3140 {
3141 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3142 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3143 /* Input capture event */
3144 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3145 {
3146 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3147 htim->IC_CaptureCallback(htim);
3148 #else
3149 HAL_TIM_IC_CaptureCallback(htim);
3150 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3151 }
3152 /* Output compare event */
3153 else
3154 {
3155 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3156 htim->OC_DelayElapsedCallback(htim);
3157 htim->PWM_PulseFinishedCallback(htim);
3158 #else
3159 HAL_TIM_OC_DelayElapsedCallback(htim);
3160 HAL_TIM_PWM_PulseFinishedCallback(htim);
3161 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3162 }
3163 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3164 }
3165 }
3166 /* Capture compare 3 event */
3167 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3168 {
3169 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3170 {
3171 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3172 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3173 /* Input capture event */
3174 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3175 {
3176 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3177 htim->IC_CaptureCallback(htim);
3178 #else
3179 HAL_TIM_IC_CaptureCallback(htim);
3180 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3181 }
3182 /* Output compare event */
3183 else
3184 {
3185 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3186 htim->OC_DelayElapsedCallback(htim);
3187 htim->PWM_PulseFinishedCallback(htim);
3188 #else
3189 HAL_TIM_OC_DelayElapsedCallback(htim);
3190 HAL_TIM_PWM_PulseFinishedCallback(htim);
3191 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3192 }
3193 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3194 }
3195 }
3196 /* Capture compare 4 event */
3197 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3198 {
3199 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3200 {
3201 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3202 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3203 /* Input capture event */
3204 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3205 {
3206 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3207 htim->IC_CaptureCallback(htim);
3208 #else
3209 HAL_TIM_IC_CaptureCallback(htim);
3210 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3211 }
3212 /* Output compare event */
3213 else
3214 {
3215 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3216 htim->OC_DelayElapsedCallback(htim);
3217 htim->PWM_PulseFinishedCallback(htim);
3218 #else
3219 HAL_TIM_OC_DelayElapsedCallback(htim);
3220 HAL_TIM_PWM_PulseFinishedCallback(htim);
3221 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3222 }
3223 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3224 }
3225 }
3226 /* TIM Update event */
3227 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3228 {
3229 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3230 {
3231 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3232 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3233 htim->PeriodElapsedCallback(htim);
3234 #else
3235 HAL_TIM_PeriodElapsedCallback(htim);
3236 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3237 }
3238 }
3239 /* TIM Break input event */
3240 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3241 {
3242 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3243 {
3244 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3245 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3246 htim->BreakCallback(htim);
3247 #else
3248 HAL_TIMEx_BreakCallback(htim);
3249 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3250 }
3251 }
3252 /* TIM Break2 input event */
3253 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
3254 {
3255 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3256 {
3257 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
3258 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3259 htim->Break2Callback(htim);
3260 #else
3261 HAL_TIMEx_Break2Callback(htim);
3262 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3263 }
3264 }
3265 /* TIM Trigger detection event */
3266 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3267 {
3268 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3269 {
3270 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3271 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3272 htim->TriggerCallback(htim);
3273 #else
3274 HAL_TIM_TriggerCallback(htim);
3275 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3276 }
3277 }
3278 /* TIM commutation event */
3279 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
3280 {
3281 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
3282 {
3283 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
3284 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3285 htim->CommutationCallback(htim);
3286 #else
3287 HAL_TIMEx_CommutationCallback(htim);
3288 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3289 }
3290 }
3291 }
3292
3293 /**
3294 * @}
3295 */
3296
3297 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
3298 * @brief Peripheral Control functions
3299 *
3300 @verbatim
3301 ==============================================================================
3302 ##### Peripheral Control functions #####
3303 ==============================================================================
3304 [..]
3305 This section provides functions allowing to:
3306 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
3307 (+) Configure External Clock source.
3308 (+) Configure Complementary channels, break features and dead time.
3309 (+) Configure Master and the Slave synchronization.
3310 (+) Configure the DMA Burst Mode.
3311
3312 @endverbatim
3313 * @{
3314 */
3315
3316 /**
3317 * @brief Initializes the TIM Output Compare Channels according to the specified
3318 * parameters in the TIM_OC_InitTypeDef.
3319 * @param htim TIM Output Compare handle
3320 * @param sConfig TIM Output Compare configuration structure
3321 * @param Channel TIM Channels to configure
3322 * This parameter can be one of the following values:
3323 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3324 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3325 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3326 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3327 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
3328 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
3329 * @retval HAL status
3330 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3331 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
3332 TIM_OC_InitTypeDef *sConfig,
3333 uint32_t Channel)
3334 {
3335 /* Check the parameters */
3336 assert_param(IS_TIM_CHANNELS(Channel));
3337 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
3338 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3339
3340 /* Process Locked */
3341 __HAL_LOCK(htim);
3342
3343 htim->State = HAL_TIM_STATE_BUSY;
3344
3345 switch (Channel)
3346 {
3347 case TIM_CHANNEL_1:
3348 {
3349 /* Check the parameters */
3350 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3351
3352 /* Configure the TIM Channel 1 in Output Compare */
3353 TIM_OC1_SetConfig(htim->Instance, sConfig);
3354 break;
3355 }
3356
3357 case TIM_CHANNEL_2:
3358 {
3359 /* Check the parameters */
3360 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3361
3362 /* Configure the TIM Channel 2 in Output Compare */
3363 TIM_OC2_SetConfig(htim->Instance, sConfig);
3364 break;
3365 }
3366
3367 case TIM_CHANNEL_3:
3368 {
3369 /* Check the parameters */
3370 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3371
3372 /* Configure the TIM Channel 3 in Output Compare */
3373 TIM_OC3_SetConfig(htim->Instance, sConfig);
3374 break;
3375 }
3376
3377 case TIM_CHANNEL_4:
3378 {
3379 /* Check the parameters */
3380 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3381
3382 /* Configure the TIM Channel 4 in Output Compare */
3383 TIM_OC4_SetConfig(htim->Instance, sConfig);
3384 break;
3385 }
3386
3387 case TIM_CHANNEL_5:
3388 {
3389 /* Check the parameters */
3390 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
3391
3392 /* Configure the TIM Channel 5 in Output Compare */
3393 TIM_OC5_SetConfig(htim->Instance, sConfig);
3394 break;
3395 }
3396
3397 case TIM_CHANNEL_6:
3398 {
3399 /* Check the parameters */
3400 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
3401
3402 /* Configure the TIM Channel 6 in Output Compare */
3403 TIM_OC6_SetConfig(htim->Instance, sConfig);
3404 break;
3405 }
3406
3407 default:
3408 break;
3409 }
3410
3411 htim->State = HAL_TIM_STATE_READY;
3412
3413 __HAL_UNLOCK(htim);
3414
3415 return HAL_OK;
3416 }
3417
3418 /**
3419 * @brief Initializes the TIM Input Capture Channels according to the specified
3420 * parameters in the TIM_IC_InitTypeDef.
3421 * @param htim TIM IC handle
3422 * @param sConfig TIM Input Capture configuration structure
3423 * @param Channel TIM Channel to configure
3424 * This parameter can be one of the following values:
3425 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3426 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3427 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3428 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3429 * @retval HAL status
3430 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_IC_InitTypeDef * sConfig,uint32_t Channel)3431 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
3432 {
3433 /* Check the parameters */
3434 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3435 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
3436 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
3437 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
3438 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
3439
3440 /* Process Locked */
3441 __HAL_LOCK(htim);
3442
3443 htim->State = HAL_TIM_STATE_BUSY;
3444
3445 if (Channel == TIM_CHANNEL_1)
3446 {
3447 /* TI1 Configuration */
3448 TIM_TI1_SetConfig(htim->Instance,
3449 sConfig->ICPolarity,
3450 sConfig->ICSelection,
3451 sConfig->ICFilter);
3452
3453 /* Reset the IC1PSC Bits */
3454 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3455
3456 /* Set the IC1PSC value */
3457 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
3458 }
3459 else if (Channel == TIM_CHANNEL_2)
3460 {
3461 /* TI2 Configuration */
3462 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3463
3464 TIM_TI2_SetConfig(htim->Instance,
3465 sConfig->ICPolarity,
3466 sConfig->ICSelection,
3467 sConfig->ICFilter);
3468
3469 /* Reset the IC2PSC Bits */
3470 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3471
3472 /* Set the IC2PSC value */
3473 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
3474 }
3475 else if (Channel == TIM_CHANNEL_3)
3476 {
3477 /* TI3 Configuration */
3478 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3479
3480 TIM_TI3_SetConfig(htim->Instance,
3481 sConfig->ICPolarity,
3482 sConfig->ICSelection,
3483 sConfig->ICFilter);
3484
3485 /* Reset the IC3PSC Bits */
3486 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
3487
3488 /* Set the IC3PSC value */
3489 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3490 }
3491 else
3492 {
3493 /* TI4 Configuration */
3494 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3495
3496 TIM_TI4_SetConfig(htim->Instance,
3497 sConfig->ICPolarity,
3498 sConfig->ICSelection,
3499 sConfig->ICFilter);
3500
3501 /* Reset the IC4PSC Bits */
3502 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
3503
3504 /* Set the IC4PSC value */
3505 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
3506 }
3507
3508 htim->State = HAL_TIM_STATE_READY;
3509
3510 __HAL_UNLOCK(htim);
3511
3512 return HAL_OK;
3513 }
3514
3515 /**
3516 * @brief Initializes the TIM PWM channels according to the specified
3517 * parameters in the TIM_OC_InitTypeDef.
3518 * @param htim TIM PWM handle
3519 * @param sConfig TIM PWM configuration structure
3520 * @param Channel TIM Channels to be configured
3521 * This parameter can be one of the following values:
3522 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3523 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3524 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3525 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3526 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
3527 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
3528 * @retval HAL status
3529 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3530 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
3531 TIM_OC_InitTypeDef *sConfig,
3532 uint32_t Channel)
3533 {
3534 /* Check the parameters */
3535 assert_param(IS_TIM_CHANNELS(Channel));
3536 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
3537 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3538 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
3539
3540 /* Process Locked */
3541 __HAL_LOCK(htim);
3542
3543 htim->State = HAL_TIM_STATE_BUSY;
3544
3545 switch (Channel)
3546 {
3547 case TIM_CHANNEL_1:
3548 {
3549 /* Check the parameters */
3550 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3551
3552 /* Configure the Channel 1 in PWM mode */
3553 TIM_OC1_SetConfig(htim->Instance, sConfig);
3554
3555 /* Set the Preload enable bit for channel1 */
3556 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
3557
3558 /* Configure the Output Fast mode */
3559 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
3560 htim->Instance->CCMR1 |= sConfig->OCFastMode;
3561 break;
3562 }
3563
3564 case TIM_CHANNEL_2:
3565 {
3566 /* Check the parameters */
3567 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3568
3569 /* Configure the Channel 2 in PWM mode */
3570 TIM_OC2_SetConfig(htim->Instance, sConfig);
3571
3572 /* Set the Preload enable bit for channel2 */
3573 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
3574
3575 /* Configure the Output Fast mode */
3576 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
3577 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
3578 break;
3579 }
3580
3581 case TIM_CHANNEL_3:
3582 {
3583 /* Check the parameters */
3584 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3585
3586 /* Configure the Channel 3 in PWM mode */
3587 TIM_OC3_SetConfig(htim->Instance, sConfig);
3588
3589 /* Set the Preload enable bit for channel3 */
3590 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
3591
3592 /* Configure the Output Fast mode */
3593 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
3594 htim->Instance->CCMR2 |= sConfig->OCFastMode;
3595 break;
3596 }
3597
3598 case TIM_CHANNEL_4:
3599 {
3600 /* Check the parameters */
3601 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3602
3603 /* Configure the Channel 4 in PWM mode */
3604 TIM_OC4_SetConfig(htim->Instance, sConfig);
3605
3606 /* Set the Preload enable bit for channel4 */
3607 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3608
3609 /* Configure the Output Fast mode */
3610 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3611 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
3612 break;
3613 }
3614
3615 case TIM_CHANNEL_5:
3616 {
3617 /* Check the parameters */
3618 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
3619
3620 /* Configure the Channel 5 in PWM mode */
3621 TIM_OC5_SetConfig(htim->Instance, sConfig);
3622
3623 /* Set the Preload enable bit for channel5*/
3624 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
3625
3626 /* Configure the Output Fast mode */
3627 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
3628 htim->Instance->CCMR3 |= sConfig->OCFastMode;
3629 break;
3630 }
3631
3632 case TIM_CHANNEL_6:
3633 {
3634 /* Check the parameters */
3635 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
3636
3637 /* Configure the Channel 6 in PWM mode */
3638 TIM_OC6_SetConfig(htim->Instance, sConfig);
3639
3640 /* Set the Preload enable bit for channel6 */
3641 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
3642
3643 /* Configure the Output Fast mode */
3644 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
3645 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
3646 break;
3647 }
3648
3649 default:
3650 break;
3651 }
3652
3653 htim->State = HAL_TIM_STATE_READY;
3654
3655 __HAL_UNLOCK(htim);
3656
3657 return HAL_OK;
3658 }
3659
3660 /**
3661 * @brief Initializes the TIM One Pulse Channels according to the specified
3662 * parameters in the TIM_OnePulse_InitTypeDef.
3663 * @param htim TIM One Pulse handle
3664 * @param sConfig TIM One Pulse configuration structure
3665 * @param OutputChannel TIM output channel to configure
3666 * This parameter can be one of the following values:
3667 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3668 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3669 * @param InputChannel TIM input Channel to configure
3670 * This parameter can be one of the following values:
3671 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3672 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3673 * @retval HAL status
3674 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)3675 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
3676 {
3677 TIM_OC_InitTypeDef temp1;
3678
3679 /* Check the parameters */
3680 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3681 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3682
3683 if (OutputChannel != InputChannel)
3684 {
3685 /* Process Locked */
3686 __HAL_LOCK(htim);
3687
3688 htim->State = HAL_TIM_STATE_BUSY;
3689
3690 /* Extract the Output compare configuration from sConfig structure */
3691 temp1.OCMode = sConfig->OCMode;
3692 temp1.Pulse = sConfig->Pulse;
3693 temp1.OCPolarity = sConfig->OCPolarity;
3694 temp1.OCNPolarity = sConfig->OCNPolarity;
3695 temp1.OCIdleState = sConfig->OCIdleState;
3696 temp1.OCNIdleState = sConfig->OCNIdleState;
3697
3698 switch (OutputChannel)
3699 {
3700 case TIM_CHANNEL_1:
3701 {
3702 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3703
3704 TIM_OC1_SetConfig(htim->Instance, &temp1);
3705 break;
3706 }
3707 case TIM_CHANNEL_2:
3708 {
3709 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3710
3711 TIM_OC2_SetConfig(htim->Instance, &temp1);
3712 break;
3713 }
3714 default:
3715 break;
3716 }
3717
3718 switch (InputChannel)
3719 {
3720 case TIM_CHANNEL_1:
3721 {
3722 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3723
3724 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3725 sConfig->ICSelection, sConfig->ICFilter);
3726
3727 /* Reset the IC1PSC Bits */
3728 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3729
3730 /* Select the Trigger source */
3731 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3732 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3733
3734 /* Select the Slave Mode */
3735 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3736 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3737 break;
3738 }
3739 case TIM_CHANNEL_2:
3740 {
3741 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3742
3743 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3744 sConfig->ICSelection, sConfig->ICFilter);
3745
3746 /* Reset the IC2PSC Bits */
3747 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3748
3749 /* Select the Trigger source */
3750 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3751 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3752
3753 /* Select the Slave Mode */
3754 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3755 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3756 break;
3757 }
3758
3759 default:
3760 break;
3761 }
3762
3763 htim->State = HAL_TIM_STATE_READY;
3764
3765 __HAL_UNLOCK(htim);
3766
3767 return HAL_OK;
3768 }
3769 else
3770 {
3771 return HAL_ERROR;
3772 }
3773 }
3774
3775 /**
3776 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3777 * @param htim TIM handle
3778 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
3779 * This parameter can be one of the following values:
3780 * @arg TIM_DMABASE_CR1
3781 * @arg TIM_DMABASE_CR2
3782 * @arg TIM_DMABASE_SMCR
3783 * @arg TIM_DMABASE_DIER
3784 * @arg TIM_DMABASE_SR
3785 * @arg TIM_DMABASE_EGR
3786 * @arg TIM_DMABASE_CCMR1
3787 * @arg TIM_DMABASE_CCMR2
3788 * @arg TIM_DMABASE_CCER
3789 * @arg TIM_DMABASE_CNT
3790 * @arg TIM_DMABASE_PSC
3791 * @arg TIM_DMABASE_ARR
3792 * @arg TIM_DMABASE_RCR
3793 * @arg TIM_DMABASE_CCR1
3794 * @arg TIM_DMABASE_CCR2
3795 * @arg TIM_DMABASE_CCR3
3796 * @arg TIM_DMABASE_CCR4
3797 * @arg TIM_DMABASE_BDTR
3798 * @arg TIM_DMABASE_DCR
3799 * @param BurstRequestSrc TIM DMA Request sources
3800 * This parameter can be one of the following values:
3801 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3802 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3803 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3804 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3805 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3806 * @arg TIM_DMA_COM: TIM Commutation DMA source
3807 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3808 * @param BurstBuffer The Buffer address.
3809 * @param BurstLength DMA Burst length. This parameter can be one value
3810 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3811 * @retval HAL status
3812 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)3813 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3814 uint32_t *BurstBuffer, uint32_t BurstLength)
3815 {
3816 /* Check the parameters */
3817 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3818 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3819 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3820 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3821
3822 if ((htim->State == HAL_TIM_STATE_BUSY))
3823 {
3824 return HAL_BUSY;
3825 }
3826 else if ((htim->State == HAL_TIM_STATE_READY))
3827 {
3828 if ((BurstBuffer == NULL) && (BurstLength > 0U))
3829 {
3830 return HAL_ERROR;
3831 }
3832 else
3833 {
3834 htim->State = HAL_TIM_STATE_BUSY;
3835 }
3836 }
3837 else
3838 {
3839 /* nothing to do */
3840 }
3841 switch (BurstRequestSrc)
3842 {
3843 case TIM_DMA_UPDATE:
3844 {
3845 /* Set the DMA Period elapsed callback */
3846 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3847
3848 /* Set the DMA error callback */
3849 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3850
3851 /* Enable the DMA channel */
3852 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3853 {
3854 return HAL_ERROR;
3855 }
3856 break;
3857 }
3858 case TIM_DMA_CC1:
3859 {
3860 /* Set the DMA Period elapsed callback */
3861 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
3862
3863 /* Set the DMA error callback */
3864 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3865
3866 /* Enable the DMA channel */
3867 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3868 {
3869 return HAL_ERROR;
3870 }
3871 break;
3872 }
3873 case TIM_DMA_CC2:
3874 {
3875 /* Set the DMA Period elapsed callback */
3876 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
3877
3878 /* Set the DMA error callback */
3879 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3880
3881 /* Enable the DMA channel */
3882 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3883 {
3884 return HAL_ERROR;
3885 }
3886 break;
3887 }
3888 case TIM_DMA_CC3:
3889 {
3890 /* Set the DMA Period elapsed callback */
3891 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
3892
3893 /* Set the DMA error callback */
3894 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3895
3896 /* Enable the DMA channel */
3897 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3898 {
3899 return HAL_ERROR;
3900 }
3901 break;
3902 }
3903 case TIM_DMA_CC4:
3904 {
3905 /* Set the DMA Period elapsed callback */
3906 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
3907
3908 /* Set the DMA error callback */
3909 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3910
3911 /* Enable the DMA channel */
3912 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3913 {
3914 return HAL_ERROR;
3915 }
3916 break;
3917 }
3918 case TIM_DMA_COM:
3919 {
3920 /* Set the DMA Period elapsed callback */
3921 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
3922
3923 /* Set the DMA error callback */
3924 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
3925
3926 /* Enable the DMA channel */
3927 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3928 {
3929 return HAL_ERROR;
3930 }
3931 break;
3932 }
3933 case TIM_DMA_TRIGGER:
3934 {
3935 /* Set the DMA Period elapsed callback */
3936 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3937
3938 /* Set the DMA error callback */
3939 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3940
3941 /* Enable the DMA channel */
3942 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3943 {
3944 return HAL_ERROR;
3945 }
3946 break;
3947 }
3948 default:
3949 break;
3950 }
3951 /* configure the DMA Burst Mode */
3952 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
3953
3954 /* Enable the TIM DMA Request */
3955 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3956
3957 htim->State = HAL_TIM_STATE_READY;
3958
3959 /* Return function status */
3960 return HAL_OK;
3961 }
3962
3963 /**
3964 * @brief Stops the TIM DMA Burst mode
3965 * @param htim TIM handle
3966 * @param BurstRequestSrc TIM DMA Request sources to disable
3967 * @retval HAL status
3968 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)3969 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3970 {
3971 HAL_StatusTypeDef status = HAL_OK;
3972 /* Check the parameters */
3973 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3974
3975 /* Abort the DMA transfer (at least disable the DMA channel) */
3976 switch (BurstRequestSrc)
3977 {
3978 case TIM_DMA_UPDATE:
3979 {
3980 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3981 break;
3982 }
3983 case TIM_DMA_CC1:
3984 {
3985 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3986 break;
3987 }
3988 case TIM_DMA_CC2:
3989 {
3990 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3991 break;
3992 }
3993 case TIM_DMA_CC3:
3994 {
3995 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3996 break;
3997 }
3998 case TIM_DMA_CC4:
3999 {
4000 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
4001 break;
4002 }
4003 case TIM_DMA_COM:
4004 {
4005 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4006 break;
4007 }
4008 case TIM_DMA_TRIGGER:
4009 {
4010 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
4011 break;
4012 }
4013 default:
4014 break;
4015 }
4016
4017 if (HAL_OK == status)
4018 {
4019 /* Disable the TIM Update DMA request */
4020 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4021 }
4022
4023 /* Return function status */
4024 return status;
4025 }
4026
4027 /**
4028 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4029 * @param htim TIM handle
4030 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4031 * This parameter can be one of the following values:
4032 * @arg TIM_DMABASE_CR1
4033 * @arg TIM_DMABASE_CR2
4034 * @arg TIM_DMABASE_SMCR
4035 * @arg TIM_DMABASE_DIER
4036 * @arg TIM_DMABASE_SR
4037 * @arg TIM_DMABASE_EGR
4038 * @arg TIM_DMABASE_CCMR1
4039 * @arg TIM_DMABASE_CCMR2
4040 * @arg TIM_DMABASE_CCER
4041 * @arg TIM_DMABASE_CNT
4042 * @arg TIM_DMABASE_PSC
4043 * @arg TIM_DMABASE_ARR
4044 * @arg TIM_DMABASE_RCR
4045 * @arg TIM_DMABASE_CCR1
4046 * @arg TIM_DMABASE_CCR2
4047 * @arg TIM_DMABASE_CCR3
4048 * @arg TIM_DMABASE_CCR4
4049 * @arg TIM_DMABASE_BDTR
4050 * @arg TIM_DMABASE_DCR
4051 * @param BurstRequestSrc TIM DMA Request sources
4052 * This parameter can be one of the following values:
4053 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4054 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4055 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4056 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4057 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4058 * @arg TIM_DMA_COM: TIM Commutation DMA source
4059 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4060 * @param BurstBuffer The Buffer address.
4061 * @param BurstLength DMA Burst length. This parameter can be one value
4062 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4063 * @retval HAL status
4064 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4065 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
4066 uint32_t *BurstBuffer, uint32_t BurstLength)
4067 {
4068 /* Check the parameters */
4069 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4070 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4071 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4072 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4073
4074 if ((htim->State == HAL_TIM_STATE_BUSY))
4075 {
4076 return HAL_BUSY;
4077 }
4078 else if ((htim->State == HAL_TIM_STATE_READY))
4079 {
4080 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4081 {
4082 return HAL_ERROR;
4083 }
4084 else
4085 {
4086 htim->State = HAL_TIM_STATE_BUSY;
4087 }
4088 }
4089 else
4090 {
4091 /* nothing to do */
4092 }
4093 switch (BurstRequestSrc)
4094 {
4095 case TIM_DMA_UPDATE:
4096 {
4097 /* Set the DMA Period elapsed callback */
4098 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4099
4100 /* Set the DMA error callback */
4101 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4102
4103 /* Enable the DMA channel */
4104 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4105 {
4106 return HAL_ERROR;
4107 }
4108 break;
4109 }
4110 case TIM_DMA_CC1:
4111 {
4112 /* Set the DMA Period elapsed callback */
4113 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4114
4115 /* Set the DMA error callback */
4116 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4117
4118 /* Enable the DMA channel */
4119 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4120 {
4121 return HAL_ERROR;
4122 }
4123 break;
4124 }
4125 case TIM_DMA_CC2:
4126 {
4127 /* Set the DMA Period elapsed callback */
4128 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4129
4130 /* Set the DMA error callback */
4131 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4132
4133 /* Enable the DMA channel */
4134 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4135 {
4136 return HAL_ERROR;
4137 }
4138 break;
4139 }
4140 case TIM_DMA_CC3:
4141 {
4142 /* Set the DMA Period elapsed callback */
4143 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4144
4145 /* Set the DMA error callback */
4146 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4147
4148 /* Enable the DMA channel */
4149 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4150 {
4151 return HAL_ERROR;
4152 }
4153 break;
4154 }
4155 case TIM_DMA_CC4:
4156 {
4157 /* Set the DMA Period elapsed callback */
4158 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4159
4160 /* Set the DMA error callback */
4161 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4162
4163 /* Enable the DMA channel */
4164 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4165 {
4166 return HAL_ERROR;
4167 }
4168 break;
4169 }
4170 case TIM_DMA_COM:
4171 {
4172 /* Set the DMA Period elapsed callback */
4173 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4174
4175 /* Set the DMA error callback */
4176 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4177
4178 /* Enable the DMA channel */
4179 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4180 {
4181 return HAL_ERROR;
4182 }
4183 break;
4184 }
4185 case TIM_DMA_TRIGGER:
4186 {
4187 /* Set the DMA Period elapsed callback */
4188 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4189
4190 /* Set the DMA error callback */
4191 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4192
4193 /* Enable the DMA channel */
4194 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4195 {
4196 return HAL_ERROR;
4197 }
4198 break;
4199 }
4200 default:
4201 break;
4202 }
4203
4204 /* configure the DMA Burst Mode */
4205 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4206
4207 /* Enable the TIM DMA Request */
4208 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4209
4210 htim->State = HAL_TIM_STATE_READY;
4211
4212 /* Return function status */
4213 return HAL_OK;
4214 }
4215
4216 /**
4217 * @brief Stop the DMA burst reading
4218 * @param htim TIM handle
4219 * @param BurstRequestSrc TIM DMA Request sources to disable.
4220 * @retval HAL status
4221 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4222 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4223 {
4224 HAL_StatusTypeDef status = HAL_OK;
4225 /* Check the parameters */
4226 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4227
4228 /* Abort the DMA transfer (at least disable the DMA channel) */
4229 switch (BurstRequestSrc)
4230 {
4231 case TIM_DMA_UPDATE:
4232 {
4233 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
4234 break;
4235 }
4236 case TIM_DMA_CC1:
4237 {
4238 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
4239 break;
4240 }
4241 case TIM_DMA_CC2:
4242 {
4243 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
4244 break;
4245 }
4246 case TIM_DMA_CC3:
4247 {
4248 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
4249 break;
4250 }
4251 case TIM_DMA_CC4:
4252 {
4253 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
4254 break;
4255 }
4256 case TIM_DMA_COM:
4257 {
4258 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4259 break;
4260 }
4261 case TIM_DMA_TRIGGER:
4262 {
4263 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
4264 break;
4265 }
4266 default:
4267 break;
4268 }
4269
4270 if (HAL_OK == status)
4271 {
4272 /* Disable the TIM Update DMA request */
4273 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4274 }
4275
4276 /* Return function status */
4277 return status;
4278 }
4279
4280 /**
4281 * @brief Generate a software event
4282 * @param htim TIM handle
4283 * @param EventSource specifies the event source.
4284 * This parameter can be one of the following values:
4285 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
4286 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
4287 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
4288 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
4289 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
4290 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
4291 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
4292 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
4293 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
4294 * @note Basic timers can only generate an update event.
4295 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
4296 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
4297 * only for timer instances supporting break input(s).
4298 * @retval HAL status
4299 */
4300
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)4301 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
4302 {
4303 /* Check the parameters */
4304 assert_param(IS_TIM_INSTANCE(htim->Instance));
4305 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
4306
4307 /* Process Locked */
4308 __HAL_LOCK(htim);
4309
4310 /* Change the TIM state */
4311 htim->State = HAL_TIM_STATE_BUSY;
4312
4313 /* Set the event sources */
4314 htim->Instance->EGR = EventSource;
4315
4316 /* Change the TIM state */
4317 htim->State = HAL_TIM_STATE_READY;
4318
4319 __HAL_UNLOCK(htim);
4320
4321 /* Return function status */
4322 return HAL_OK;
4323 }
4324
4325 /**
4326 * @brief Configures the OCRef clear feature
4327 * @param htim TIM handle
4328 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
4329 * contains the OCREF clear feature and parameters for the TIM peripheral.
4330 * @param Channel specifies the TIM Channel
4331 * This parameter can be one of the following values:
4332 * @arg TIM_CHANNEL_1: TIM Channel 1
4333 * @arg TIM_CHANNEL_2: TIM Channel 2
4334 * @arg TIM_CHANNEL_3: TIM Channel 3
4335 * @arg TIM_CHANNEL_4: TIM Channel 4
4336 * @arg TIM_CHANNEL_5: TIM Channel 5
4337 * @arg TIM_CHANNEL_6: TIM Channel 6
4338 * @retval HAL status
4339 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)4340 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
4341 TIM_ClearInputConfigTypeDef *sClearInputConfig,
4342 uint32_t Channel)
4343 {
4344 /* Check the parameters */
4345 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
4346 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
4347
4348 /* Process Locked */
4349 __HAL_LOCK(htim);
4350
4351 htim->State = HAL_TIM_STATE_BUSY;
4352
4353 switch (sClearInputConfig->ClearInputSource)
4354 {
4355 case TIM_CLEARINPUTSOURCE_NONE:
4356 {
4357 /* Clear the OCREF clear selection bit and the the ETR Bits */
4358 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
4359 break;
4360 }
4361 case TIM_CLEARINPUTSOURCE_OCREFCLR:
4362 {
4363 /* Clear the OCREF clear selection bit */
4364 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
4365 }
4366 break;
4367
4368 case TIM_CLEARINPUTSOURCE_ETR:
4369 {
4370 /* Check the parameters */
4371 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
4372 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
4373 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
4374
4375 TIM_ETR_SetConfig(htim->Instance,
4376 sClearInputConfig->ClearInputPrescaler,
4377 sClearInputConfig->ClearInputPolarity,
4378 sClearInputConfig->ClearInputFilter);
4379
4380 /* Set the OCREF clear selection bit */
4381 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
4382 break;
4383 }
4384
4385 default:
4386 break;
4387 }
4388
4389 switch (Channel)
4390 {
4391 case TIM_CHANNEL_1:
4392 {
4393 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4394 {
4395 /* Enable the OCREF clear feature for Channel 1 */
4396 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4397 }
4398 else
4399 {
4400 /* Disable the OCREF clear feature for Channel 1 */
4401 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4402 }
4403 break;
4404 }
4405 case TIM_CHANNEL_2:
4406 {
4407 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4408 {
4409 /* Enable the OCREF clear feature for Channel 2 */
4410 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4411 }
4412 else
4413 {
4414 /* Disable the OCREF clear feature for Channel 2 */
4415 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4416 }
4417 break;
4418 }
4419 case TIM_CHANNEL_3:
4420 {
4421 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4422 {
4423 /* Enable the OCREF clear feature for Channel 3 */
4424 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
4425 }
4426 else
4427 {
4428 /* Disable the OCREF clear feature for Channel 3 */
4429 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
4430 }
4431 break;
4432 }
4433 case TIM_CHANNEL_4:
4434 {
4435 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4436 {
4437 /* Enable the OCREF clear feature for Channel 4 */
4438 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
4439 }
4440 else
4441 {
4442 /* Disable the OCREF clear feature for Channel 4 */
4443 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
4444 }
4445 break;
4446 }
4447 case TIM_CHANNEL_5:
4448 {
4449 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4450 {
4451 /* Enable the OCREF clear feature for Channel 5 */
4452 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
4453 }
4454 else
4455 {
4456 /* Disable the OCREF clear feature for Channel 5 */
4457 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
4458 }
4459 break;
4460 }
4461 case TIM_CHANNEL_6:
4462 {
4463 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4464 {
4465 /* Enable the OCREF clear feature for Channel 6 */
4466 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
4467 }
4468 else
4469 {
4470 /* Disable the OCREF clear feature for Channel 6 */
4471 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
4472 }
4473 break;
4474 }
4475 default:
4476 break;
4477 }
4478
4479 htim->State = HAL_TIM_STATE_READY;
4480
4481 __HAL_UNLOCK(htim);
4482
4483 return HAL_OK;
4484 }
4485
4486 /**
4487 * @brief Configures the clock source to be used
4488 * @param htim TIM handle
4489 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
4490 * contains the clock source information for the TIM peripheral.
4491 * @retval HAL status
4492 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,TIM_ClockConfigTypeDef * sClockSourceConfig)4493 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
4494 {
4495 uint32_t tmpsmcr;
4496
4497 /* Process Locked */
4498 __HAL_LOCK(htim);
4499
4500 htim->State = HAL_TIM_STATE_BUSY;
4501
4502 /* Check the parameters */
4503 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
4504
4505 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
4506 tmpsmcr = htim->Instance->SMCR;
4507 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
4508 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
4509 htim->Instance->SMCR = tmpsmcr;
4510
4511 switch (sClockSourceConfig->ClockSource)
4512 {
4513 case TIM_CLOCKSOURCE_INTERNAL:
4514 {
4515 assert_param(IS_TIM_INSTANCE(htim->Instance));
4516 /* Disable slave mode to clock the prescaler directly with the internal clock */
4517 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4518 break;
4519 }
4520
4521 case TIM_CLOCKSOURCE_ETRMODE1:
4522 {
4523 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
4524 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
4525
4526 /* Check ETR input conditioning related parameters */
4527 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4528 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4529 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4530
4531 /* Configure the ETR Clock source */
4532 TIM_ETR_SetConfig(htim->Instance,
4533 sClockSourceConfig->ClockPrescaler,
4534 sClockSourceConfig->ClockPolarity,
4535 sClockSourceConfig->ClockFilter);
4536 /* Get the TIMx SMCR register value */
4537 tmpsmcr = htim->Instance->SMCR;
4538 /* Reset the SMS and TS Bits */
4539 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
4540 /* Select the External clock mode1 and the ETRF trigger */
4541 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
4542 /* Write to TIMx SMCR */
4543 htim->Instance->SMCR = tmpsmcr;
4544 break;
4545 }
4546
4547 case TIM_CLOCKSOURCE_ETRMODE2:
4548 {
4549 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
4550 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
4551
4552 /* Check ETR input conditioning related parameters */
4553 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4554 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4555 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4556
4557 /* Configure the ETR Clock source */
4558 TIM_ETR_SetConfig(htim->Instance,
4559 sClockSourceConfig->ClockPrescaler,
4560 sClockSourceConfig->ClockPolarity,
4561 sClockSourceConfig->ClockFilter);
4562 /* Enable the External clock mode2 */
4563 htim->Instance->SMCR |= TIM_SMCR_ECE;
4564 break;
4565 }
4566
4567 case TIM_CLOCKSOURCE_TI1:
4568 {
4569 /* Check whether or not the timer instance supports external clock mode 1 */
4570 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4571
4572 /* Check TI1 input conditioning related parameters */
4573 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4574 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4575
4576 TIM_TI1_ConfigInputStage(htim->Instance,
4577 sClockSourceConfig->ClockPolarity,
4578 sClockSourceConfig->ClockFilter);
4579 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
4580 break;
4581 }
4582
4583 case TIM_CLOCKSOURCE_TI2:
4584 {
4585 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
4586 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4587
4588 /* Check TI2 input conditioning related parameters */
4589 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4590 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4591
4592 TIM_TI2_ConfigInputStage(htim->Instance,
4593 sClockSourceConfig->ClockPolarity,
4594 sClockSourceConfig->ClockFilter);
4595 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
4596 break;
4597 }
4598
4599 case TIM_CLOCKSOURCE_TI1ED:
4600 {
4601 /* Check whether or not the timer instance supports external clock mode 1 */
4602 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4603
4604 /* Check TI1 input conditioning related parameters */
4605 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4606 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4607
4608 TIM_TI1_ConfigInputStage(htim->Instance,
4609 sClockSourceConfig->ClockPolarity,
4610 sClockSourceConfig->ClockFilter);
4611 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
4612 break;
4613 }
4614
4615 case TIM_CLOCKSOURCE_ITR0:
4616 case TIM_CLOCKSOURCE_ITR1:
4617 case TIM_CLOCKSOURCE_ITR2:
4618 case TIM_CLOCKSOURCE_ITR3:
4619 {
4620 /* Check whether or not the timer instance supports internal trigger input */
4621 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
4622
4623 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
4624 break;
4625 }
4626
4627 default:
4628 break;
4629 }
4630 htim->State = HAL_TIM_STATE_READY;
4631
4632 __HAL_UNLOCK(htim);
4633
4634 return HAL_OK;
4635 }
4636
4637 /**
4638 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
4639 * or a XOR combination between CH1_input, CH2_input & CH3_input
4640 * @param htim TIM handle.
4641 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
4642 * output of a XOR gate.
4643 * This parameter can be one of the following values:
4644 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
4645 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
4646 * pins are connected to the TI1 input (XOR combination)
4647 * @retval HAL status
4648 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)4649 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
4650 {
4651 uint32_t tmpcr2;
4652
4653 /* Check the parameters */
4654 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
4655 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
4656
4657 /* Get the TIMx CR2 register value */
4658 tmpcr2 = htim->Instance->CR2;
4659
4660 /* Reset the TI1 selection */
4661 tmpcr2 &= ~TIM_CR2_TI1S;
4662
4663 /* Set the TI1 selection */
4664 tmpcr2 |= TI1_Selection;
4665
4666 /* Write to TIMxCR2 */
4667 htim->Instance->CR2 = tmpcr2;
4668
4669 return HAL_OK;
4670 }
4671
4672 /**
4673 * @brief Configures the TIM in Slave mode
4674 * @param htim TIM handle.
4675 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
4676 * contains the selected trigger (internal trigger input, filtered
4677 * timer input or external trigger input) and the Slave mode
4678 * (Disable, Reset, Gated, Trigger, External clock mode 1).
4679 * @retval HAL status
4680 */
HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)4681 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
4682 {
4683 /* Check the parameters */
4684 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4685 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4686 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4687
4688 __HAL_LOCK(htim);
4689
4690 htim->State = HAL_TIM_STATE_BUSY;
4691
4692 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
4693
4694 /* Disable Trigger Interrupt */
4695 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
4696
4697 /* Disable Trigger DMA request */
4698 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4699
4700 htim->State = HAL_TIM_STATE_READY;
4701
4702 __HAL_UNLOCK(htim);
4703
4704 return HAL_OK;
4705 }
4706
4707 /**
4708 * @brief Configures the TIM in Slave mode in interrupt mode
4709 * @param htim TIM handle.
4710 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
4711 * contains the selected trigger (internal trigger input, filtered
4712 * timer input or external trigger input) and the Slave mode
4713 * (Disable, Reset, Gated, Trigger, External clock mode 1).
4714 * @retval HAL status
4715 */
HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)4716 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
4717 TIM_SlaveConfigTypeDef *sSlaveConfig)
4718 {
4719 /* Check the parameters */
4720 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4721 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4722 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4723
4724 __HAL_LOCK(htim);
4725
4726 htim->State = HAL_TIM_STATE_BUSY;
4727
4728 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
4729
4730 /* Enable Trigger Interrupt */
4731 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
4732
4733 /* Disable Trigger DMA request */
4734 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4735
4736 htim->State = HAL_TIM_STATE_READY;
4737
4738 __HAL_UNLOCK(htim);
4739
4740 return HAL_OK;
4741 }
4742
4743 /**
4744 * @brief Read the captured value from Capture Compare unit
4745 * @param htim TIM handle.
4746 * @param Channel TIM Channels to be enabled
4747 * This parameter can be one of the following values:
4748 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4749 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4750 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4751 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4752 * @retval Captured value
4753 */
HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef * htim,uint32_t Channel)4754 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
4755 {
4756 uint32_t tmpreg = 0U;
4757
4758 __HAL_LOCK(htim);
4759
4760 switch (Channel)
4761 {
4762 case TIM_CHANNEL_1:
4763 {
4764 /* Check the parameters */
4765 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4766
4767 /* Return the capture 1 value */
4768 tmpreg = htim->Instance->CCR1;
4769
4770 break;
4771 }
4772 case TIM_CHANNEL_2:
4773 {
4774 /* Check the parameters */
4775 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4776
4777 /* Return the capture 2 value */
4778 tmpreg = htim->Instance->CCR2;
4779
4780 break;
4781 }
4782
4783 case TIM_CHANNEL_3:
4784 {
4785 /* Check the parameters */
4786 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4787
4788 /* Return the capture 3 value */
4789 tmpreg = htim->Instance->CCR3;
4790
4791 break;
4792 }
4793
4794 case TIM_CHANNEL_4:
4795 {
4796 /* Check the parameters */
4797 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4798
4799 /* Return the capture 4 value */
4800 tmpreg = htim->Instance->CCR4;
4801
4802 break;
4803 }
4804
4805 default:
4806 break;
4807 }
4808
4809 __HAL_UNLOCK(htim);
4810 return tmpreg;
4811 }
4812
4813 /**
4814 * @}
4815 */
4816
4817 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
4818 * @brief TIM Callbacks functions
4819 *
4820 @verbatim
4821 ==============================================================================
4822 ##### TIM Callbacks functions #####
4823 ==============================================================================
4824 [..]
4825 This section provides TIM callback functions:
4826 (+) Timer Period elapsed callback
4827 (+) Timer Output Compare callback
4828 (+) Timer Input capture callback
4829 (+) Timer Trigger callback
4830 (+) Timer Error callback
4831
4832 @endverbatim
4833 * @{
4834 */
4835
4836 /**
4837 * @brief Period elapsed callback in non-blocking mode
4838 * @param htim TIM handle
4839 * @retval None
4840 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)4841 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4842 {
4843 /* Prevent unused argument(s) compilation warning */
4844 UNUSED(htim);
4845
4846 /* NOTE : This function should not be modified, when the callback is needed,
4847 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4848 */
4849
4850 }
4851 /**
4852 * @brief Output Compare callback in non-blocking mode
4853 * @param htim TIM OC handle
4854 * @retval None
4855 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)4856 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
4857 {
4858 /* Prevent unused argument(s) compilation warning */
4859 UNUSED(htim);
4860
4861 /* NOTE : This function should not be modified, when the callback is needed,
4862 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4863 */
4864 }
4865 /**
4866 * @brief Input Capture callback in non-blocking mode
4867 * @param htim TIM IC handle
4868 * @retval None
4869 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)4870 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
4871 {
4872 /* Prevent unused argument(s) compilation warning */
4873 UNUSED(htim);
4874
4875 /* NOTE : This function should not be modified, when the callback is needed,
4876 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
4877 */
4878 }
4879
4880 /**
4881 * @brief PWM Pulse finished callback in non-blocking mode
4882 * @param htim TIM handle
4883 * @retval None
4884 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)4885 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
4886 {
4887 /* Prevent unused argument(s) compilation warning */
4888 UNUSED(htim);
4889
4890 /* NOTE : This function should not be modified, when the callback is needed,
4891 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4892 */
4893 }
4894
4895 /**
4896 * @brief Hall Trigger detection callback in non-blocking mode
4897 * @param htim TIM handle
4898 * @retval None
4899 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)4900 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
4901 {
4902 /* Prevent unused argument(s) compilation warning */
4903 UNUSED(htim);
4904
4905 /* NOTE : This function should not be modified, when the callback is needed,
4906 the HAL_TIM_TriggerCallback could be implemented in the user file
4907 */
4908 }
4909
4910 /**
4911 * @brief Timer error callback in non-blocking mode
4912 * @param htim TIM handle
4913 * @retval None
4914 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)4915 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
4916 {
4917 /* Prevent unused argument(s) compilation warning */
4918 UNUSED(htim);
4919
4920 /* NOTE : This function should not be modified, when the callback is needed,
4921 the HAL_TIM_ErrorCallback could be implemented in the user file
4922 */
4923 }
4924
4925 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4926 /**
4927 * @brief Register a User TIM callback to be used instead of the weak predefined callback
4928 * @param htim tim handle
4929 * @param CallbackID ID of the callback to be registered
4930 * This parameter can be one of the following values:
4931 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
4932 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
4933 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
4934 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
4935 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
4936 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
4937 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
4938 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
4939 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
4940 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
4941 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
4942 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
4943 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
4944 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
4945 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
4946 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
4947 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
4948 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
4949 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
4950 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
4951 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
4952 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
4953 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
4954 * @param pCallback pointer to the callback function
4955 * @retval status
4956 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)4957 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
4958 {
4959 HAL_StatusTypeDef status = HAL_OK;
4960
4961 if (pCallback == NULL)
4962 {
4963 return HAL_ERROR;
4964 }
4965 /* Process locked */
4966 __HAL_LOCK(htim);
4967
4968 if (htim->State == HAL_TIM_STATE_READY)
4969 {
4970 switch (CallbackID)
4971 {
4972 case HAL_TIM_BASE_MSPINIT_CB_ID :
4973 htim->Base_MspInitCallback = pCallback;
4974 break;
4975
4976 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
4977 htim->Base_MspDeInitCallback = pCallback;
4978 break;
4979
4980 case HAL_TIM_IC_MSPINIT_CB_ID :
4981 htim->IC_MspInitCallback = pCallback;
4982 break;
4983
4984 case HAL_TIM_IC_MSPDEINIT_CB_ID :
4985 htim->IC_MspDeInitCallback = pCallback;
4986 break;
4987
4988 case HAL_TIM_OC_MSPINIT_CB_ID :
4989 htim->OC_MspInitCallback = pCallback;
4990 break;
4991
4992 case HAL_TIM_OC_MSPDEINIT_CB_ID :
4993 htim->OC_MspDeInitCallback = pCallback;
4994 break;
4995
4996 case HAL_TIM_PWM_MSPINIT_CB_ID :
4997 htim->PWM_MspInitCallback = pCallback;
4998 break;
4999
5000 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5001 htim->PWM_MspDeInitCallback = pCallback;
5002 break;
5003
5004 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5005 htim->OnePulse_MspInitCallback = pCallback;
5006 break;
5007
5008 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5009 htim->OnePulse_MspDeInitCallback = pCallback;
5010 break;
5011
5012 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5013 htim->Encoder_MspInitCallback = pCallback;
5014 break;
5015
5016 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5017 htim->Encoder_MspDeInitCallback = pCallback;
5018 break;
5019
5020 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5021 htim->HallSensor_MspInitCallback = pCallback;
5022 break;
5023
5024 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5025 htim->HallSensor_MspDeInitCallback = pCallback;
5026 break;
5027
5028 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5029 htim->PeriodElapsedCallback = pCallback;
5030 break;
5031
5032 case HAL_TIM_TRIGGER_CB_ID :
5033 htim->TriggerCallback = pCallback;
5034 break;
5035
5036 case HAL_TIM_IC_CAPTURE_CB_ID :
5037 htim->IC_CaptureCallback = pCallback;
5038 break;
5039
5040 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5041 htim->OC_DelayElapsedCallback = pCallback;
5042 break;
5043
5044 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5045 htim->PWM_PulseFinishedCallback = pCallback;
5046 break;
5047
5048 case HAL_TIM_ERROR_CB_ID :
5049 htim->ErrorCallback = pCallback;
5050 break;
5051
5052 case HAL_TIM_COMMUTATION_CB_ID :
5053 htim->CommutationCallback = pCallback;
5054 break;
5055
5056 case HAL_TIM_BREAK_CB_ID :
5057 htim->BreakCallback = pCallback;
5058 break;
5059
5060 case HAL_TIM_BREAK2_CB_ID :
5061 htim->Break2Callback = pCallback;
5062 break;
5063
5064 default :
5065 /* Return error status */
5066 status = HAL_ERROR;
5067 break;
5068 }
5069 }
5070 else if (htim->State == HAL_TIM_STATE_RESET)
5071 {
5072 switch (CallbackID)
5073 {
5074 case HAL_TIM_BASE_MSPINIT_CB_ID :
5075 htim->Base_MspInitCallback = pCallback;
5076 break;
5077
5078 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5079 htim->Base_MspDeInitCallback = pCallback;
5080 break;
5081
5082 case HAL_TIM_IC_MSPINIT_CB_ID :
5083 htim->IC_MspInitCallback = pCallback;
5084 break;
5085
5086 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5087 htim->IC_MspDeInitCallback = pCallback;
5088 break;
5089
5090 case HAL_TIM_OC_MSPINIT_CB_ID :
5091 htim->OC_MspInitCallback = pCallback;
5092 break;
5093
5094 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5095 htim->OC_MspDeInitCallback = pCallback;
5096 break;
5097
5098 case HAL_TIM_PWM_MSPINIT_CB_ID :
5099 htim->PWM_MspInitCallback = pCallback;
5100 break;
5101
5102 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5103 htim->PWM_MspDeInitCallback = pCallback;
5104 break;
5105
5106 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5107 htim->OnePulse_MspInitCallback = pCallback;
5108 break;
5109
5110 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5111 htim->OnePulse_MspDeInitCallback = pCallback;
5112 break;
5113
5114 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5115 htim->Encoder_MspInitCallback = pCallback;
5116 break;
5117
5118 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5119 htim->Encoder_MspDeInitCallback = pCallback;
5120 break;
5121
5122 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5123 htim->HallSensor_MspInitCallback = pCallback;
5124 break;
5125
5126 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5127 htim->HallSensor_MspDeInitCallback = pCallback;
5128 break;
5129
5130 default :
5131 /* Return error status */
5132 status = HAL_ERROR;
5133 break;
5134 }
5135 }
5136 else
5137 {
5138 /* Return error status */
5139 status = HAL_ERROR;
5140 }
5141
5142 /* Release Lock */
5143 __HAL_UNLOCK(htim);
5144
5145 return status;
5146 }
5147
5148 /**
5149 * @brief Unregister a TIM callback
5150 * TIM callback is redirected to the weak predefined callback
5151 * @param htim tim handle
5152 * @param CallbackID ID of the callback to be unregistered
5153 * This parameter can be one of the following values:
5154 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5155 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5156 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5157 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5158 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5159 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5160 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5161 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5162 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5163 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5164 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5165 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5166 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5167 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5168 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5169 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5170 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5171 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5172 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5173 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5174 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5175 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5176 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5177 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)5178 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
5179 {
5180 HAL_StatusTypeDef status = HAL_OK;
5181
5182 /* Process locked */
5183 __HAL_LOCK(htim);
5184
5185 if (htim->State == HAL_TIM_STATE_READY)
5186 {
5187 switch (CallbackID)
5188 {
5189 case HAL_TIM_BASE_MSPINIT_CB_ID :
5190 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
5191 break;
5192
5193 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5194 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
5195 break;
5196
5197 case HAL_TIM_IC_MSPINIT_CB_ID :
5198 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
5199 break;
5200
5201 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5202 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
5203 break;
5204
5205 case HAL_TIM_OC_MSPINIT_CB_ID :
5206 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
5207 break;
5208
5209 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5210 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
5211 break;
5212
5213 case HAL_TIM_PWM_MSPINIT_CB_ID :
5214 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
5215 break;
5216
5217 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5218 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
5219 break;
5220
5221 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5222 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
5223 break;
5224
5225 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5226 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
5227 break;
5228
5229 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5230 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
5231 break;
5232
5233 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5234 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
5235 break;
5236
5237 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5238 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
5239 break;
5240
5241 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5242 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
5243 break;
5244
5245 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5246 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
5247 break;
5248
5249 case HAL_TIM_TRIGGER_CB_ID :
5250 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
5251 break;
5252
5253 case HAL_TIM_IC_CAPTURE_CB_ID :
5254 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
5255 break;
5256
5257 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5258 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
5259 break;
5260
5261 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5262 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
5263 break;
5264
5265 case HAL_TIM_ERROR_CB_ID :
5266 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
5267 break;
5268
5269 case HAL_TIM_COMMUTATION_CB_ID :
5270 htim->CommutationCallback = HAL_TIMEx_CommutationCallback; /* Legacy weak Commutation Callback */
5271 break;
5272
5273 case HAL_TIM_BREAK_CB_ID :
5274 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
5275 break;
5276
5277 case HAL_TIM_BREAK2_CB_ID :
5278 htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */
5279 break;
5280
5281 default :
5282 /* Return error status */
5283 status = HAL_ERROR;
5284 break;
5285 }
5286 }
5287 else if (htim->State == HAL_TIM_STATE_RESET)
5288 {
5289 switch (CallbackID)
5290 {
5291 case HAL_TIM_BASE_MSPINIT_CB_ID :
5292 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
5293 break;
5294
5295 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5296 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
5297 break;
5298
5299 case HAL_TIM_IC_MSPINIT_CB_ID :
5300 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
5301 break;
5302
5303 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5304 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
5305 break;
5306
5307 case HAL_TIM_OC_MSPINIT_CB_ID :
5308 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
5309 break;
5310
5311 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5312 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
5313 break;
5314
5315 case HAL_TIM_PWM_MSPINIT_CB_ID :
5316 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
5317 break;
5318
5319 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5320 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
5321 break;
5322
5323 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5324 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
5325 break;
5326
5327 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5328 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
5329 break;
5330
5331 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5332 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
5333 break;
5334
5335 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5336 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
5337 break;
5338
5339 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5340 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
5341 break;
5342
5343 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5344 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
5345 break;
5346
5347 default :
5348 /* Return error status */
5349 status = HAL_ERROR;
5350 break;
5351 }
5352 }
5353 else
5354 {
5355 /* Return error status */
5356 status = HAL_ERROR;
5357 }
5358
5359 /* Release Lock */
5360 __HAL_UNLOCK(htim);
5361
5362 return status;
5363 }
5364 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5365
5366 /**
5367 * @}
5368 */
5369
5370 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
5371 * @brief Peripheral State functions
5372 *
5373 @verbatim
5374 ==============================================================================
5375 ##### Peripheral State functions #####
5376 ==============================================================================
5377 [..]
5378 This subsection permits to get in run-time the status of the peripheral
5379 and the data flow.
5380
5381 @endverbatim
5382 * @{
5383 */
5384
5385 /**
5386 * @brief Return the TIM Base handle state.
5387 * @param htim TIM Base handle
5388 * @retval HAL state
5389 */
HAL_TIM_Base_GetState(TIM_HandleTypeDef * htim)5390 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
5391 {
5392 return htim->State;
5393 }
5394
5395 /**
5396 * @brief Return the TIM OC handle state.
5397 * @param htim TIM Output Compare handle
5398 * @retval HAL state
5399 */
HAL_TIM_OC_GetState(TIM_HandleTypeDef * htim)5400 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
5401 {
5402 return htim->State;
5403 }
5404
5405 /**
5406 * @brief Return the TIM PWM handle state.
5407 * @param htim TIM handle
5408 * @retval HAL state
5409 */
HAL_TIM_PWM_GetState(TIM_HandleTypeDef * htim)5410 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
5411 {
5412 return htim->State;
5413 }
5414
5415 /**
5416 * @brief Return the TIM Input Capture handle state.
5417 * @param htim TIM IC handle
5418 * @retval HAL state
5419 */
HAL_TIM_IC_GetState(TIM_HandleTypeDef * htim)5420 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
5421 {
5422 return htim->State;
5423 }
5424
5425 /**
5426 * @brief Return the TIM One Pulse Mode handle state.
5427 * @param htim TIM OPM handle
5428 * @retval HAL state
5429 */
HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef * htim)5430 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
5431 {
5432 return htim->State;
5433 }
5434
5435 /**
5436 * @brief Return the TIM Encoder Mode handle state.
5437 * @param htim TIM Encoder Interface handle
5438 * @retval HAL state
5439 */
HAL_TIM_Encoder_GetState(TIM_HandleTypeDef * htim)5440 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
5441 {
5442 return htim->State;
5443 }
5444
5445 /**
5446 * @}
5447 */
5448
5449 /**
5450 * @}
5451 */
5452
5453 /** @defgroup TIM_Private_Functions TIM Private Functions
5454 * @{
5455 */
5456
5457 /**
5458 * @brief TIM DMA error callback
5459 * @param hdma pointer to DMA handle.
5460 * @retval None
5461 */
TIM_DMAError(DMA_HandleTypeDef * hdma)5462 void TIM_DMAError(DMA_HandleTypeDef *hdma)
5463 {
5464 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5465
5466 htim->State = HAL_TIM_STATE_READY;
5467
5468 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5469 htim->ErrorCallback(htim);
5470 #else
5471 HAL_TIM_ErrorCallback(htim);
5472 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5473 }
5474
5475 /**
5476 * @brief TIM DMA Delay Pulse complete callback.
5477 * @param hdma pointer to DMA handle.
5478 * @retval None
5479 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)5480 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
5481 {
5482 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5483
5484 htim->State = HAL_TIM_STATE_READY;
5485
5486 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5487 {
5488 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5489 }
5490 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5491 {
5492 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5493 }
5494 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5495 {
5496 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5497 }
5498 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5499 {
5500 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5501 }
5502 else
5503 {
5504 /* nothing to do */
5505 }
5506
5507 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5508 htim->PWM_PulseFinishedCallback(htim);
5509 #else
5510 HAL_TIM_PWM_PulseFinishedCallback(htim);
5511 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5512
5513 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5514 }
5515 /**
5516 * @brief TIM DMA Capture complete callback.
5517 * @param hdma pointer to DMA handle.
5518 * @retval None
5519 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)5520 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
5521 {
5522 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5523
5524 htim->State = HAL_TIM_STATE_READY;
5525
5526 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5527 {
5528 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5529 }
5530 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5531 {
5532 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5533 }
5534 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5535 {
5536 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5537 }
5538 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5539 {
5540 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5541 }
5542 else
5543 {
5544 /* nothing to do */
5545 }
5546
5547 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5548 htim->IC_CaptureCallback(htim);
5549 #else
5550 HAL_TIM_IC_CaptureCallback(htim);
5551 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5552
5553 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5554 }
5555
5556 /**
5557 * @brief TIM DMA Period Elapse complete callback.
5558 * @param hdma pointer to DMA handle.
5559 * @retval None
5560 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)5561 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
5562 {
5563 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5564
5565 htim->State = HAL_TIM_STATE_READY;
5566
5567 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5568 htim->PeriodElapsedCallback(htim);
5569 #else
5570 HAL_TIM_PeriodElapsedCallback(htim);
5571 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5572 }
5573
5574 /**
5575 * @brief TIM DMA Trigger callback.
5576 * @param hdma pointer to DMA handle.
5577 * @retval None
5578 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)5579 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
5580 {
5581 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5582
5583 htim->State = HAL_TIM_STATE_READY;
5584
5585 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5586 htim->TriggerCallback(htim);
5587 #else
5588 HAL_TIM_TriggerCallback(htim);
5589 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5590 }
5591
5592 /**
5593 * @brief Time Base configuration
5594 * @param TIMx TIM peripheral
5595 * @param Structure TIM Base configuration structure
5596 * @retval None
5597 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,TIM_Base_InitTypeDef * Structure)5598 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
5599 {
5600 uint32_t tmpcr1;
5601 tmpcr1 = TIMx->CR1;
5602
5603 /* Set TIM Time Base Unit parameters ---------------------------------------*/
5604 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
5605 {
5606 /* Select the Counter Mode */
5607 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
5608 tmpcr1 |= Structure->CounterMode;
5609 }
5610
5611 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
5612 {
5613 /* Set the clock division */
5614 tmpcr1 &= ~TIM_CR1_CKD;
5615 tmpcr1 |= (uint32_t)Structure->ClockDivision;
5616 }
5617
5618 /* Set the auto-reload preload */
5619 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
5620
5621 TIMx->CR1 = tmpcr1;
5622
5623 /* Set the Autoreload value */
5624 TIMx->ARR = (uint32_t)Structure->Period ;
5625
5626 /* Set the Prescaler value */
5627 TIMx->PSC = Structure->Prescaler;
5628
5629 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
5630 {
5631 /* Set the Repetition Counter value */
5632 TIMx->RCR = Structure->RepetitionCounter;
5633 }
5634
5635 /* Generate an update event to reload the Prescaler
5636 and the repetition counter (only for advanced timer) value immediately */
5637 TIMx->EGR = TIM_EGR_UG;
5638 }
5639
5640 /**
5641 * @brief Timer Output Compare 1 configuration
5642 * @param TIMx to select the TIM peripheral
5643 * @param OC_Config The ouput configuration structure
5644 * @retval None
5645 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)5646 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
5647 {
5648 uint32_t tmpccmrx;
5649 uint32_t tmpccer;
5650 uint32_t tmpcr2;
5651
5652 /* Disable the Channel 1: Reset the CC1E Bit */
5653 TIMx->CCER &= ~TIM_CCER_CC1E;
5654
5655 /* Get the TIMx CCER register value */
5656 tmpccer = TIMx->CCER;
5657 /* Get the TIMx CR2 register value */
5658 tmpcr2 = TIMx->CR2;
5659
5660 /* Get the TIMx CCMR1 register value */
5661 tmpccmrx = TIMx->CCMR1;
5662
5663 /* Reset the Output Compare Mode Bits */
5664 tmpccmrx &= ~TIM_CCMR1_OC1M;
5665 tmpccmrx &= ~TIM_CCMR1_CC1S;
5666 /* Select the Output Compare Mode */
5667 tmpccmrx |= OC_Config->OCMode;
5668
5669 /* Reset the Output Polarity level */
5670 tmpccer &= ~TIM_CCER_CC1P;
5671 /* Set the Output Compare Polarity */
5672 tmpccer |= OC_Config->OCPolarity;
5673
5674 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
5675 {
5676 /* Check parameters */
5677 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
5678
5679 /* Reset the Output N Polarity level */
5680 tmpccer &= ~TIM_CCER_CC1NP;
5681 /* Set the Output N Polarity */
5682 tmpccer |= OC_Config->OCNPolarity;
5683 /* Reset the Output N State */
5684 tmpccer &= ~TIM_CCER_CC1NE;
5685 }
5686
5687 if (IS_TIM_BREAK_INSTANCE(TIMx))
5688 {
5689 /* Check parameters */
5690 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
5691 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
5692
5693 /* Reset the Output Compare and Output Compare N IDLE State */
5694 tmpcr2 &= ~TIM_CR2_OIS1;
5695 tmpcr2 &= ~TIM_CR2_OIS1N;
5696 /* Set the Output Idle state */
5697 tmpcr2 |= OC_Config->OCIdleState;
5698 /* Set the Output N Idle state */
5699 tmpcr2 |= OC_Config->OCNIdleState;
5700 }
5701
5702 /* Write to TIMx CR2 */
5703 TIMx->CR2 = tmpcr2;
5704
5705 /* Write to TIMx CCMR1 */
5706 TIMx->CCMR1 = tmpccmrx;
5707
5708 /* Set the Capture Compare Register value */
5709 TIMx->CCR1 = OC_Config->Pulse;
5710
5711 /* Write to TIMx CCER */
5712 TIMx->CCER = tmpccer;
5713 }
5714
5715 /**
5716 * @brief Timer Output Compare 2 configuration
5717 * @param TIMx to select the TIM peripheral
5718 * @param OC_Config The ouput configuration structure
5719 * @retval None
5720 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)5721 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
5722 {
5723 uint32_t tmpccmrx;
5724 uint32_t tmpccer;
5725 uint32_t tmpcr2;
5726
5727 /* Disable the Channel 2: Reset the CC2E Bit */
5728 TIMx->CCER &= ~TIM_CCER_CC2E;
5729
5730 /* Get the TIMx CCER register value */
5731 tmpccer = TIMx->CCER;
5732 /* Get the TIMx CR2 register value */
5733 tmpcr2 = TIMx->CR2;
5734
5735 /* Get the TIMx CCMR1 register value */
5736 tmpccmrx = TIMx->CCMR1;
5737
5738 /* Reset the Output Compare mode and Capture/Compare selection Bits */
5739 tmpccmrx &= ~TIM_CCMR1_OC2M;
5740 tmpccmrx &= ~TIM_CCMR1_CC2S;
5741
5742 /* Select the Output Compare Mode */
5743 tmpccmrx |= (OC_Config->OCMode << 8U);
5744
5745 /* Reset the Output Polarity level */
5746 tmpccer &= ~TIM_CCER_CC2P;
5747 /* Set the Output Compare Polarity */
5748 tmpccer |= (OC_Config->OCPolarity << 4U);
5749
5750 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
5751 {
5752 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
5753
5754 /* Reset the Output N Polarity level */
5755 tmpccer &= ~TIM_CCER_CC2NP;
5756 /* Set the Output N Polarity */
5757 tmpccer |= (OC_Config->OCNPolarity << 4U);
5758 /* Reset the Output N State */
5759 tmpccer &= ~TIM_CCER_CC2NE;
5760
5761 }
5762
5763 if (IS_TIM_BREAK_INSTANCE(TIMx))
5764 {
5765 /* Check parameters */
5766 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
5767 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
5768
5769 /* Reset the Output Compare and Output Compare N IDLE State */
5770 tmpcr2 &= ~TIM_CR2_OIS2;
5771 tmpcr2 &= ~TIM_CR2_OIS2N;
5772 /* Set the Output Idle state */
5773 tmpcr2 |= (OC_Config->OCIdleState << 2U);
5774 /* Set the Output N Idle state */
5775 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
5776 }
5777
5778 /* Write to TIMx CR2 */
5779 TIMx->CR2 = tmpcr2;
5780
5781 /* Write to TIMx CCMR1 */
5782 TIMx->CCMR1 = tmpccmrx;
5783
5784 /* Set the Capture Compare Register value */
5785 TIMx->CCR2 = OC_Config->Pulse;
5786
5787 /* Write to TIMx CCER */
5788 TIMx->CCER = tmpccer;
5789 }
5790
5791 /**
5792 * @brief Timer Output Compare 3 configuration
5793 * @param TIMx to select the TIM peripheral
5794 * @param OC_Config The ouput configuration structure
5795 * @retval None
5796 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)5797 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
5798 {
5799 uint32_t tmpccmrx;
5800 uint32_t tmpccer;
5801 uint32_t tmpcr2;
5802
5803 /* Disable the Channel 3: Reset the CC2E Bit */
5804 TIMx->CCER &= ~TIM_CCER_CC3E;
5805
5806 /* Get the TIMx CCER register value */
5807 tmpccer = TIMx->CCER;
5808 /* Get the TIMx CR2 register value */
5809 tmpcr2 = TIMx->CR2;
5810
5811 /* Get the TIMx CCMR2 register value */
5812 tmpccmrx = TIMx->CCMR2;
5813
5814 /* Reset the Output Compare mode and Capture/Compare selection Bits */
5815 tmpccmrx &= ~TIM_CCMR2_OC3M;
5816 tmpccmrx &= ~TIM_CCMR2_CC3S;
5817 /* Select the Output Compare Mode */
5818 tmpccmrx |= OC_Config->OCMode;
5819
5820 /* Reset the Output Polarity level */
5821 tmpccer &= ~TIM_CCER_CC3P;
5822 /* Set the Output Compare Polarity */
5823 tmpccer |= (OC_Config->OCPolarity << 8U);
5824
5825 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
5826 {
5827 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
5828
5829 /* Reset the Output N Polarity level */
5830 tmpccer &= ~TIM_CCER_CC3NP;
5831 /* Set the Output N Polarity */
5832 tmpccer |= (OC_Config->OCNPolarity << 8U);
5833 /* Reset the Output N State */
5834 tmpccer &= ~TIM_CCER_CC3NE;
5835 }
5836
5837 if (IS_TIM_BREAK_INSTANCE(TIMx))
5838 {
5839 /* Check parameters */
5840 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
5841 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
5842
5843 /* Reset the Output Compare and Output Compare N IDLE State */
5844 tmpcr2 &= ~TIM_CR2_OIS3;
5845 tmpcr2 &= ~TIM_CR2_OIS3N;
5846 /* Set the Output Idle state */
5847 tmpcr2 |= (OC_Config->OCIdleState << 4U);
5848 /* Set the Output N Idle state */
5849 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
5850 }
5851
5852 /* Write to TIMx CR2 */
5853 TIMx->CR2 = tmpcr2;
5854
5855 /* Write to TIMx CCMR2 */
5856 TIMx->CCMR2 = tmpccmrx;
5857
5858 /* Set the Capture Compare Register value */
5859 TIMx->CCR3 = OC_Config->Pulse;
5860
5861 /* Write to TIMx CCER */
5862 TIMx->CCER = tmpccer;
5863 }
5864
5865 /**
5866 * @brief Timer Output Compare 4 configuration
5867 * @param TIMx to select the TIM peripheral
5868 * @param OC_Config The ouput configuration structure
5869 * @retval None
5870 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)5871 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
5872 {
5873 uint32_t tmpccmrx;
5874 uint32_t tmpccer;
5875 uint32_t tmpcr2;
5876
5877 /* Disable the Channel 4: Reset the CC4E Bit */
5878 TIMx->CCER &= ~TIM_CCER_CC4E;
5879
5880 /* Get the TIMx CCER register value */
5881 tmpccer = TIMx->CCER;
5882 /* Get the TIMx CR2 register value */
5883 tmpcr2 = TIMx->CR2;
5884
5885 /* Get the TIMx CCMR2 register value */
5886 tmpccmrx = TIMx->CCMR2;
5887
5888 /* Reset the Output Compare mode and Capture/Compare selection Bits */
5889 tmpccmrx &= ~TIM_CCMR2_OC4M;
5890 tmpccmrx &= ~TIM_CCMR2_CC4S;
5891
5892 /* Select the Output Compare Mode */
5893 tmpccmrx |= (OC_Config->OCMode << 8U);
5894
5895 /* Reset the Output Polarity level */
5896 tmpccer &= ~TIM_CCER_CC4P;
5897 /* Set the Output Compare Polarity */
5898 tmpccer |= (OC_Config->OCPolarity << 12U);
5899
5900 if (IS_TIM_BREAK_INSTANCE(TIMx))
5901 {
5902 /* Check parameters */
5903 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
5904
5905 /* Reset the Output Compare IDLE State */
5906 tmpcr2 &= ~TIM_CR2_OIS4;
5907
5908 /* Set the Output Idle state */
5909 tmpcr2 |= (OC_Config->OCIdleState << 6U);
5910 }
5911
5912 /* Write to TIMx CR2 */
5913 TIMx->CR2 = tmpcr2;
5914
5915 /* Write to TIMx CCMR2 */
5916 TIMx->CCMR2 = tmpccmrx;
5917
5918 /* Set the Capture Compare Register value */
5919 TIMx->CCR4 = OC_Config->Pulse;
5920
5921 /* Write to TIMx CCER */
5922 TIMx->CCER = tmpccer;
5923 }
5924
5925 /**
5926 * @brief Timer Output Compare 5 configuration
5927 * @param TIMx to select the TIM peripheral
5928 * @param OC_Config The ouput configuration structure
5929 * @retval None
5930 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)5931 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
5932 TIM_OC_InitTypeDef *OC_Config)
5933 {
5934 uint32_t tmpccmrx;
5935 uint32_t tmpccer;
5936 uint32_t tmpcr2;
5937
5938 /* Disable the output: Reset the CCxE Bit */
5939 TIMx->CCER &= ~TIM_CCER_CC5E;
5940
5941 /* Get the TIMx CCER register value */
5942 tmpccer = TIMx->CCER;
5943 /* Get the TIMx CR2 register value */
5944 tmpcr2 = TIMx->CR2;
5945 /* Get the TIMx CCMR1 register value */
5946 tmpccmrx = TIMx->CCMR3;
5947
5948 /* Reset the Output Compare Mode Bits */
5949 tmpccmrx &= ~(TIM_CCMR3_OC5M);
5950 /* Select the Output Compare Mode */
5951 tmpccmrx |= OC_Config->OCMode;
5952
5953 /* Reset the Output Polarity level */
5954 tmpccer &= ~TIM_CCER_CC5P;
5955 /* Set the Output Compare Polarity */
5956 tmpccer |= (OC_Config->OCPolarity << 16U);
5957
5958 if (IS_TIM_BREAK_INSTANCE(TIMx))
5959 {
5960 /* Reset the Output Compare IDLE State */
5961 tmpcr2 &= ~TIM_CR2_OIS5;
5962 /* Set the Output Idle state */
5963 tmpcr2 |= (OC_Config->OCIdleState << 8U);
5964 }
5965 /* Write to TIMx CR2 */
5966 TIMx->CR2 = tmpcr2;
5967
5968 /* Write to TIMx CCMR3 */
5969 TIMx->CCMR3 = tmpccmrx;
5970
5971 /* Set the Capture Compare Register value */
5972 TIMx->CCR5 = OC_Config->Pulse;
5973
5974 /* Write to TIMx CCER */
5975 TIMx->CCER = tmpccer;
5976 }
5977
5978 /**
5979 * @brief Timer Output Compare 6 configuration
5980 * @param TIMx to select the TIM peripheral
5981 * @param OC_Config The ouput configuration structure
5982 * @retval None
5983 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)5984 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
5985 TIM_OC_InitTypeDef *OC_Config)
5986 {
5987 uint32_t tmpccmrx;
5988 uint32_t tmpccer;
5989 uint32_t tmpcr2;
5990
5991 /* Disable the output: Reset the CCxE Bit */
5992 TIMx->CCER &= ~TIM_CCER_CC6E;
5993
5994 /* Get the TIMx CCER register value */
5995 tmpccer = TIMx->CCER;
5996 /* Get the TIMx CR2 register value */
5997 tmpcr2 = TIMx->CR2;
5998 /* Get the TIMx CCMR1 register value */
5999 tmpccmrx = TIMx->CCMR3;
6000
6001 /* Reset the Output Compare Mode Bits */
6002 tmpccmrx &= ~(TIM_CCMR3_OC6M);
6003 /* Select the Output Compare Mode */
6004 tmpccmrx |= (OC_Config->OCMode << 8U);
6005
6006 /* Reset the Output Polarity level */
6007 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
6008 /* Set the Output Compare Polarity */
6009 tmpccer |= (OC_Config->OCPolarity << 20U);
6010
6011 if (IS_TIM_BREAK_INSTANCE(TIMx))
6012 {
6013 /* Reset the Output Compare IDLE State */
6014 tmpcr2 &= ~TIM_CR2_OIS6;
6015 /* Set the Output Idle state */
6016 tmpcr2 |= (OC_Config->OCIdleState << 10U);
6017 }
6018
6019 /* Write to TIMx CR2 */
6020 TIMx->CR2 = tmpcr2;
6021
6022 /* Write to TIMx CCMR3 */
6023 TIMx->CCMR3 = tmpccmrx;
6024
6025 /* Set the Capture Compare Register value */
6026 TIMx->CCR6 = OC_Config->Pulse;
6027
6028 /* Write to TIMx CCER */
6029 TIMx->CCER = tmpccer;
6030 }
6031
6032 /**
6033 * @brief Slave Timer configuration function
6034 * @param htim TIM handle
6035 * @param sSlaveConfig Slave timer configuration
6036 * @retval None
6037 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)6038 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
6039 TIM_SlaveConfigTypeDef *sSlaveConfig)
6040 {
6041 uint32_t tmpsmcr;
6042 uint32_t tmpccmr1;
6043 uint32_t tmpccer;
6044
6045 /* Get the TIMx SMCR register value */
6046 tmpsmcr = htim->Instance->SMCR;
6047
6048 /* Reset the Trigger Selection Bits */
6049 tmpsmcr &= ~TIM_SMCR_TS;
6050 /* Set the Input Trigger source */
6051 tmpsmcr |= sSlaveConfig->InputTrigger;
6052
6053 /* Reset the slave mode Bits */
6054 tmpsmcr &= ~TIM_SMCR_SMS;
6055 /* Set the slave mode */
6056 tmpsmcr |= sSlaveConfig->SlaveMode;
6057
6058 /* Write to TIMx SMCR */
6059 htim->Instance->SMCR = tmpsmcr;
6060
6061 /* Configure the trigger prescaler, filter, and polarity */
6062 switch (sSlaveConfig->InputTrigger)
6063 {
6064 case TIM_TS_ETRF:
6065 {
6066 /* Check the parameters */
6067 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
6068 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
6069 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6070 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6071 /* Configure the ETR Trigger source */
6072 TIM_ETR_SetConfig(htim->Instance,
6073 sSlaveConfig->TriggerPrescaler,
6074 sSlaveConfig->TriggerPolarity,
6075 sSlaveConfig->TriggerFilter);
6076 break;
6077 }
6078
6079 case TIM_TS_TI1F_ED:
6080 {
6081 /* Check the parameters */
6082 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6083 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6084
6085 /* Disable the Channel 1: Reset the CC1E Bit */
6086 tmpccer = htim->Instance->CCER;
6087 htim->Instance->CCER &= ~TIM_CCER_CC1E;
6088 tmpccmr1 = htim->Instance->CCMR1;
6089
6090 /* Set the filter */
6091 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6092 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
6093
6094 /* Write to TIMx CCMR1 and CCER registers */
6095 htim->Instance->CCMR1 = tmpccmr1;
6096 htim->Instance->CCER = tmpccer;
6097 break;
6098 }
6099
6100 case TIM_TS_TI1FP1:
6101 {
6102 /* Check the parameters */
6103 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6104 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6105 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6106
6107 /* Configure TI1 Filter and Polarity */
6108 TIM_TI1_ConfigInputStage(htim->Instance,
6109 sSlaveConfig->TriggerPolarity,
6110 sSlaveConfig->TriggerFilter);
6111 break;
6112 }
6113
6114 case TIM_TS_TI2FP2:
6115 {
6116 /* Check the parameters */
6117 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6118 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6119 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6120
6121 /* Configure TI2 Filter and Polarity */
6122 TIM_TI2_ConfigInputStage(htim->Instance,
6123 sSlaveConfig->TriggerPolarity,
6124 sSlaveConfig->TriggerFilter);
6125 break;
6126 }
6127
6128 case TIM_TS_ITR0:
6129 case TIM_TS_ITR1:
6130 case TIM_TS_ITR2:
6131 case TIM_TS_ITR3:
6132 {
6133 /* Check the parameter */
6134 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6135 break;
6136 }
6137
6138 default:
6139 break;
6140 }
6141 }
6142
6143 /**
6144 * @brief Configure the TI1 as Input.
6145 * @param TIMx to select the TIM peripheral.
6146 * @param TIM_ICPolarity The Input Polarity.
6147 * This parameter can be one of the following values:
6148 * @arg TIM_ICPOLARITY_RISING
6149 * @arg TIM_ICPOLARITY_FALLING
6150 * @arg TIM_ICPOLARITY_BOTHEDGE
6151 * @param TIM_ICSelection specifies the input to be used.
6152 * This parameter can be one of the following values:
6153 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
6154 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
6155 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
6156 * @param TIM_ICFilter Specifies the Input Capture Filter.
6157 * This parameter must be a value between 0x00 and 0x0F.
6158 * @retval None
6159 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
6160 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
6161 * protected against un-initialized filter and polarity values.
6162 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6163 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6164 uint32_t TIM_ICFilter)
6165 {
6166 uint32_t tmpccmr1;
6167 uint32_t tmpccer;
6168
6169 /* Disable the Channel 1: Reset the CC1E Bit */
6170 TIMx->CCER &= ~TIM_CCER_CC1E;
6171 tmpccmr1 = TIMx->CCMR1;
6172 tmpccer = TIMx->CCER;
6173
6174 /* Select the Input */
6175 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
6176 {
6177 tmpccmr1 &= ~TIM_CCMR1_CC1S;
6178 tmpccmr1 |= TIM_ICSelection;
6179 }
6180 else
6181 {
6182 tmpccmr1 |= TIM_CCMR1_CC1S_0;
6183 }
6184
6185 /* Set the filter */
6186 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6187 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
6188
6189 /* Select the Polarity and set the CC1E Bit */
6190 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6191 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
6192
6193 /* Write to TIMx CCMR1 and CCER registers */
6194 TIMx->CCMR1 = tmpccmr1;
6195 TIMx->CCER = tmpccer;
6196 }
6197
6198 /**
6199 * @brief Configure the Polarity and Filter for TI1.
6200 * @param TIMx to select the TIM peripheral.
6201 * @param TIM_ICPolarity The Input Polarity.
6202 * This parameter can be one of the following values:
6203 * @arg TIM_ICPOLARITY_RISING
6204 * @arg TIM_ICPOLARITY_FALLING
6205 * @arg TIM_ICPOLARITY_BOTHEDGE
6206 * @param TIM_ICFilter Specifies the Input Capture Filter.
6207 * This parameter must be a value between 0x00 and 0x0F.
6208 * @retval None
6209 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6210 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6211 {
6212 uint32_t tmpccmr1;
6213 uint32_t tmpccer;
6214
6215 /* Disable the Channel 1: Reset the CC1E Bit */
6216 tmpccer = TIMx->CCER;
6217 TIMx->CCER &= ~TIM_CCER_CC1E;
6218 tmpccmr1 = TIMx->CCMR1;
6219
6220 /* Set the filter */
6221 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6222 tmpccmr1 |= (TIM_ICFilter << 4U);
6223
6224 /* Select the Polarity and set the CC1E Bit */
6225 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6226 tmpccer |= TIM_ICPolarity;
6227
6228 /* Write to TIMx CCMR1 and CCER registers */
6229 TIMx->CCMR1 = tmpccmr1;
6230 TIMx->CCER = tmpccer;
6231 }
6232
6233 /**
6234 * @brief Configure the TI2 as Input.
6235 * @param TIMx to select the TIM peripheral
6236 * @param TIM_ICPolarity The Input Polarity.
6237 * This parameter can be one of the following values:
6238 * @arg TIM_ICPOLARITY_RISING
6239 * @arg TIM_ICPOLARITY_FALLING
6240 * @arg TIM_ICPOLARITY_BOTHEDGE
6241 * @param TIM_ICSelection specifies the input to be used.
6242 * This parameter can be one of the following values:
6243 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
6244 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
6245 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
6246 * @param TIM_ICFilter Specifies the Input Capture Filter.
6247 * This parameter must be a value between 0x00 and 0x0F.
6248 * @retval None
6249 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
6250 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
6251 * protected against un-initialized filter and polarity values.
6252 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6253 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6254 uint32_t TIM_ICFilter)
6255 {
6256 uint32_t tmpccmr1;
6257 uint32_t tmpccer;
6258
6259 /* Disable the Channel 2: Reset the CC2E Bit */
6260 TIMx->CCER &= ~TIM_CCER_CC2E;
6261 tmpccmr1 = TIMx->CCMR1;
6262 tmpccer = TIMx->CCER;
6263
6264 /* Select the Input */
6265 tmpccmr1 &= ~TIM_CCMR1_CC2S;
6266 tmpccmr1 |= (TIM_ICSelection << 8U);
6267
6268 /* Set the filter */
6269 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6270 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
6271
6272 /* Select the Polarity and set the CC2E Bit */
6273 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6274 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
6275
6276 /* Write to TIMx CCMR1 and CCER registers */
6277 TIMx->CCMR1 = tmpccmr1 ;
6278 TIMx->CCER = tmpccer;
6279 }
6280
6281 /**
6282 * @brief Configure the Polarity and Filter for TI2.
6283 * @param TIMx to select the TIM peripheral.
6284 * @param TIM_ICPolarity The Input Polarity.
6285 * This parameter can be one of the following values:
6286 * @arg TIM_ICPOLARITY_RISING
6287 * @arg TIM_ICPOLARITY_FALLING
6288 * @arg TIM_ICPOLARITY_BOTHEDGE
6289 * @param TIM_ICFilter Specifies the Input Capture Filter.
6290 * This parameter must be a value between 0x00 and 0x0F.
6291 * @retval None
6292 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6293 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6294 {
6295 uint32_t tmpccmr1;
6296 uint32_t tmpccer;
6297
6298 /* Disable the Channel 2: Reset the CC2E Bit */
6299 TIMx->CCER &= ~TIM_CCER_CC2E;
6300 tmpccmr1 = TIMx->CCMR1;
6301 tmpccer = TIMx->CCER;
6302
6303 /* Set the filter */
6304 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6305 tmpccmr1 |= (TIM_ICFilter << 12U);
6306
6307 /* Select the Polarity and set the CC2E Bit */
6308 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6309 tmpccer |= (TIM_ICPolarity << 4U);
6310
6311 /* Write to TIMx CCMR1 and CCER registers */
6312 TIMx->CCMR1 = tmpccmr1 ;
6313 TIMx->CCER = tmpccer;
6314 }
6315
6316 /**
6317 * @brief Configure the TI3 as Input.
6318 * @param TIMx to select the TIM peripheral
6319 * @param TIM_ICPolarity The Input Polarity.
6320 * This parameter can be one of the following values:
6321 * @arg TIM_ICPOLARITY_RISING
6322 * @arg TIM_ICPOLARITY_FALLING
6323 * @arg TIM_ICPOLARITY_BOTHEDGE
6324 * @param TIM_ICSelection specifies the input to be used.
6325 * This parameter can be one of the following values:
6326 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
6327 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
6328 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
6329 * @param TIM_ICFilter Specifies the Input Capture Filter.
6330 * This parameter must be a value between 0x00 and 0x0F.
6331 * @retval None
6332 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
6333 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
6334 * protected against un-initialized filter and polarity values.
6335 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6336 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6337 uint32_t TIM_ICFilter)
6338 {
6339 uint32_t tmpccmr2;
6340 uint32_t tmpccer;
6341
6342 /* Disable the Channel 3: Reset the CC3E Bit */
6343 TIMx->CCER &= ~TIM_CCER_CC3E;
6344 tmpccmr2 = TIMx->CCMR2;
6345 tmpccer = TIMx->CCER;
6346
6347 /* Select the Input */
6348 tmpccmr2 &= ~TIM_CCMR2_CC3S;
6349 tmpccmr2 |= TIM_ICSelection;
6350
6351 /* Set the filter */
6352 tmpccmr2 &= ~TIM_CCMR2_IC3F;
6353 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
6354
6355 /* Select the Polarity and set the CC3E Bit */
6356 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
6357 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
6358
6359 /* Write to TIMx CCMR2 and CCER registers */
6360 TIMx->CCMR2 = tmpccmr2;
6361 TIMx->CCER = tmpccer;
6362 }
6363
6364 /**
6365 * @brief Configure the TI4 as Input.
6366 * @param TIMx to select the TIM peripheral
6367 * @param TIM_ICPolarity The Input Polarity.
6368 * This parameter can be one of the following values:
6369 * @arg TIM_ICPOLARITY_RISING
6370 * @arg TIM_ICPOLARITY_FALLING
6371 * @arg TIM_ICPOLARITY_BOTHEDGE
6372 * @param TIM_ICSelection specifies the input to be used.
6373 * This parameter can be one of the following values:
6374 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
6375 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
6376 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
6377 * @param TIM_ICFilter Specifies the Input Capture Filter.
6378 * This parameter must be a value between 0x00 and 0x0F.
6379 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
6380 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
6381 * protected against un-initialized filter and polarity values.
6382 * @retval None
6383 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6384 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6385 uint32_t TIM_ICFilter)
6386 {
6387 uint32_t tmpccmr2;
6388 uint32_t tmpccer;
6389
6390 /* Disable the Channel 4: Reset the CC4E Bit */
6391 TIMx->CCER &= ~TIM_CCER_CC4E;
6392 tmpccmr2 = TIMx->CCMR2;
6393 tmpccer = TIMx->CCER;
6394
6395 /* Select the Input */
6396 tmpccmr2 &= ~TIM_CCMR2_CC4S;
6397 tmpccmr2 |= (TIM_ICSelection << 8U);
6398
6399 /* Set the filter */
6400 tmpccmr2 &= ~TIM_CCMR2_IC4F;
6401 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
6402
6403 /* Select the Polarity and set the CC4E Bit */
6404 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
6405 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
6406
6407 /* Write to TIMx CCMR2 and CCER registers */
6408 TIMx->CCMR2 = tmpccmr2;
6409 TIMx->CCER = tmpccer ;
6410 }
6411
6412 /**
6413 * @brief Selects the Input Trigger source
6414 * @param TIMx to select the TIM peripheral
6415 * @param InputTriggerSource The Input Trigger source.
6416 * This parameter can be one of the following values:
6417 * @arg TIM_TS_ITR0: Internal Trigger 0
6418 * @arg TIM_TS_ITR1: Internal Trigger 1
6419 * @arg TIM_TS_ITR2: Internal Trigger 2
6420 * @arg TIM_TS_ITR3: Internal Trigger 3
6421 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
6422 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
6423 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
6424 * @arg TIM_TS_ETRF: External Trigger input
6425 * @retval None
6426 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)6427 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
6428 {
6429 uint32_t tmpsmcr;
6430
6431 /* Get the TIMx SMCR register value */
6432 tmpsmcr = TIMx->SMCR;
6433 /* Reset the TS Bits */
6434 tmpsmcr &= ~TIM_SMCR_TS;
6435 /* Set the Input Trigger source and the slave mode*/
6436 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
6437 /* Write to TIMx SMCR */
6438 TIMx->SMCR = tmpsmcr;
6439 }
6440 /**
6441 * @brief Configures the TIMx External Trigger (ETR).
6442 * @param TIMx to select the TIM peripheral
6443 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
6444 * This parameter can be one of the following values:
6445 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
6446 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
6447 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
6448 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
6449 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
6450 * This parameter can be one of the following values:
6451 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
6452 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
6453 * @param ExtTRGFilter External Trigger Filter.
6454 * This parameter must be a value between 0x00 and 0x0F
6455 * @retval None
6456 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)6457 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
6458 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
6459 {
6460 uint32_t tmpsmcr;
6461
6462 tmpsmcr = TIMx->SMCR;
6463
6464 /* Reset the ETR Bits */
6465 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
6466
6467 /* Set the Prescaler, the Filter value and the Polarity */
6468 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
6469
6470 /* Write to TIMx SMCR */
6471 TIMx->SMCR = tmpsmcr;
6472 }
6473
6474 /**
6475 * @brief Enables or disables the TIM Capture Compare Channel x.
6476 * @param TIMx to select the TIM peripheral
6477 * @param Channel specifies the TIM Channel
6478 * This parameter can be one of the following values:
6479 * @arg TIM_CHANNEL_1: TIM Channel 1
6480 * @arg TIM_CHANNEL_2: TIM Channel 2
6481 * @arg TIM_CHANNEL_3: TIM Channel 3
6482 * @arg TIM_CHANNEL_4: TIM Channel 4
6483 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
6484 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
6485 * @param ChannelState specifies the TIM Channel CCxE bit new state.
6486 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
6487 * @retval None
6488 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)6489 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
6490 {
6491 uint32_t tmp;
6492
6493 /* Check the parameters */
6494 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
6495 assert_param(IS_TIM_CHANNELS(Channel));
6496
6497 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
6498
6499 /* Reset the CCxE Bit */
6500 TIMx->CCER &= ~tmp;
6501
6502 /* Set or reset the CCxE Bit */
6503 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
6504 }
6505
6506 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6507 /**
6508 * @brief Reset interrupt callbacks to the legacy week callbacks.
6509 * @param htim pointer to a TIM_HandleTypeDef structure that contains
6510 * the configuration information for TIM module.
6511 * @retval None
6512 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)6513 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
6514 {
6515 /* Reset the TIM callback to the legacy weak callbacks */
6516 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
6517 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
6518 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
6519 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
6520 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
6521 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
6522 htim->CommutationCallback = HAL_TIMEx_CommutationCallback; /* Legacy weak CommutationCallback */
6523 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
6524 }
6525 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6526
6527 /**
6528 * @}
6529 */
6530
6531 #endif /* HAL_TIM_MODULE_ENABLED */
6532 /**
6533 * @}
6534 */
6535
6536 /**
6537 * @}
6538 */
6539 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
6540
