1 /**************************************************************************//** 2 * @file timer_reg.h 3 * @version V1.00 4 * @brief TIMER register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __TIMER_REG_H__ 10 #define __TIMER_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- Timer Controller -------------------------*/ 19 /** 20 @addtogroup TIMER Timer Controller(TIMER) 21 Memory Mapped Structure for TIMER Controller 22 @{ */ 23 24 typedef struct 25 { 26 27 28 /** 29 * @var TIMER_T::CTL 30 * Offset: 0x00 Timer Control Register 31 * --------------------------------------------------------------------------------------------------- 32 * |Bits |Field |Descriptions 33 * | :----: | :----: | :---- | 34 * |[7:0] |PSC |Prescale Counter 35 * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter 36 * | | |If this field is 0 (PSC = 0), then there is no scaling. 37 * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 38 * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Control 39 * | | |Setting this bit will enable the inter-timer trigger capture function. 40 * | | |The Timer0/2 will be in event counter mode and counting with external clock source or event 41 * | | |Also, Timer1/3 will be in trigger-counting mode of capture function. 42 * | | |0 = Inter-Timer Trigger Capture mode Disabled. 43 * | | |1 = Inter-Timer Trigger Capture mode Enabled. 44 * | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0. 45 * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit 46 * | | |0 = The behavior selection in periodic mode is Disabled. 47 * | | |When user updates CMPDAT while timer is running in periodic mode, 48 * | | |CNT will be reset to default value. 49 * | | |1 = The behavior selection in periodic mode is Enabled. 50 * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list, 51 * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. 52 * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. 53 * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. 54 * |[21] |TGLPINSEL |Toggle-output Pin Select 55 * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin). 56 * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). 57 * |[22] |CAPSRC |Capture Pin Source Selection 58 * | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin. 59 * | | |1 = Capture Function source is from internal ACMP output signal 60 * | | |User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source. 61 * |[23] |WKEN |Wake-up Function Enable Bit 62 * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 63 * | | |0 = Wake-up function Disabled if timer interrupt signal generated. 64 * | | |1 = Wake-up function Enabled if timer interrupt signal generated. 65 * |[24] |EXTCNTEN |Event Counter Mode Enable Bit 66 * | | |This bit is for external counting pin function enabled. 67 * | | |0 = Event counter mode Disabled. 68 * | | |1 = Event counter mode Enabled. 69 * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. 70 * |[25] |ACTSTS |Timer Active Status Bit (Read Only) 71 * | | |This bit indicates the 24-bit up counter status. 72 * | | |0 = 24-bit up counter is not active. 73 * | | |1 = 24-bit up counter is active. 74 * | | |Note: This bit may active when CNT 0 transition to CNT 1. 75 * |[28:27] |OPMODE |Timer Counting Mode Select 76 * | | |00 = The Timer controller is operated in One-shot mode. 77 * | | |01 = The Timer controller is operated in Periodic mode. 78 * | | |10 = The Timer controller is operated in Toggle-output mode. 79 * | | |11 = The Timer controller is operated in Continuous Counting mode. 80 * |[29] |INTEN |Timer Interrupt Enable Bit 81 * | | |0 = Timer time-out interrupt Disabled. 82 * | | |1 = Timer time-out interrupt Enabled. 83 * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 84 * |[30] |CNTEN |Timer Counting Enable Bit 85 * | | |0 = Stops/Suspends counting. 86 * | | |1 = Starts counting. 87 * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. 88 * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated. 89 * | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. 90 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) 91 * | | |0 = ICE debug mode acknowledgment effects TIMER counting. 92 * | | |TIMER counter will be held while CPU is held by ICE. 93 * | | |1 = ICE debug mode acknowledgment Disabled. 94 * | | |TIMER counter will keep going no matter CPU is held by ICE or not. 95 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 96 * @var TIMER_T::CMP 97 * Offset: 0x04 Timer Comparator Register 98 * --------------------------------------------------------------------------------------------------- 99 * |Bits |Field |Descriptions 100 * | :----: | :----: | :---- | 101 * |[23:0] |CMPDAT |Timer Comparator Value 102 * | | |CMPDAT is a 24-bit compared value register 103 * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. 104 * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). 105 * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. 106 * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field 107 * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 108 * @var TIMER_T::INTSTS 109 * Offset: 0x08 Timer Interrupt Status Register 110 * --------------------------------------------------------------------------------------------------- 111 * |Bits |Field |Descriptions 112 * | :----: | :----: | :---- | 113 * |[0] |TIF |Timer Interrupt Flag 114 * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. 115 * | | |0 = No effect. 116 * | | |1 = CNT value matches the CMPDAT value. 117 * | | |Note: This bit is cleared by writing 1 to it. 118 * |[1] |TWKF |Timer Wake-up Flag 119 * | | |This bit indicates the interrupt wake-up flag status of timer. 120 * | | |0 = Timer does not cause CPU wake-up. 121 * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. 122 * | | |Note: This bit is cleared by writing 1 to it. 123 * @var TIMER_T::CNT 124 * Offset: 0x0C Timer Data Register 125 * --------------------------------------------------------------------------------------------------- 126 * |Bits |Field |Descriptions 127 * | :----: | :----: | :---- | 128 * |[23:0] |CNT |Timer Data Register 129 * | | |Read operation. 130 * | | |Read this register to get CNT value. For example: 131 * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value. 132 * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value. 133 * | | |Write operation. 134 * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. 135 * |[31] |RSTACT |Timer Data Register Reset Active (Read Only) 136 * | | |This bit indicates if the counter reset operation active. 137 * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter 138 * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress 139 * | | |Once the counter reset operation done, timer clear this bit to 0 automatically. 140 * | | |0 = Reset operation is done. 141 * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress. 142 * | | |Note: This bit is read only. 143 * @var TIMER_T::CAP 144 * Offset: 0x10 Timer Capture Data Register 145 * --------------------------------------------------------------------------------------------------- 146 * |Bits |Field |Descriptions 147 * | :----: | :----: | :---- | 148 * |[23:0] |CAPDAT |Timer Capture Data Register 149 * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 150 * @var TIMER_T::EXTCTL 151 * Offset: 0x14 Timer External Control Register 152 * --------------------------------------------------------------------------------------------------- 153 * |Bits |Field |Descriptions 154 * | :----: | :----: | :---- | 155 * |[0] |CNTPHASE |Timer External Count Phase 156 * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3). 157 * | | |0 = A falling edge of external counting pin will be counted. 158 * | | |1 = A rising edge of external counting pin will be counted. 159 * |[3] |CAPEN |Timer External Capture Pin Enable Bit 160 * | | |This bit enables the TMx_EXT capture pin input function. 161 * | | |0 =TMx_EXT (x= 0~3) pin Disabled. 162 * | | |1 =TMx_EXT (x= 0~3) pin Enabled. 163 * |[4] |CAPFUNCS |Capture Function Selection 164 * | | |0 = External Capture Mode Enabled. 165 * | | |1 = External Reset Mode Enabled. 166 * | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field. 167 * | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately. 168 * |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit 169 * | | |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled. 170 * | | |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled. 171 * | | |Note: CAPIEN is used to enable timer external interrupt 172 * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. 173 * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. 174 * |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit 175 * | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled. 176 * | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled. 177 * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. 178 * |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit 179 * | | |0 = TMx (x= 0~3) pin de-bounce Disabled. 180 * | | |1 = TMx (x= 0~3) pin de-bounce Enabled. 181 * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 182 * |[8] |ACMPSSEL |ACMP Source Selection to Trigger Capture Function 183 * | | |0 = Capture Function source is from internal ACMP0 output signal. 184 * | | |1 = Capture Function source is from internal ACMP1 output signal. 185 * | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. 186 * |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect 187 * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. 188 * | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin. 189 * | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin. 190 * | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer. 191 * | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer.. 192 * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin. 193 * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin. 194 * | | |100, 101 = Reserved. 195 * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function 196 * | | |0 = Event Counter input source is from TMx (x= 0~3) pin. 197 * | | |1 = Event Counter input source is from USB internal SOF output signal. 198 * @var TIMER_T::EINTSTS 199 * Offset: 0x18 Timer External Interrupt Status Register 200 * --------------------------------------------------------------------------------------------------- 201 * |Bits |Field |Descriptions 202 * | :----: | :----: | :---- | 203 * |[0] |CAPIF |Timer External Capture Interrupt Flag 204 * | | |This bit indicates the timer external capture interrupt flag status. 205 * | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur. 206 * | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred. 207 * | | |Note1: This bit is cleared by writing 1 to it. 208 * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. 209 * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status 210 * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 211 * @var TIMER_T::TRGCTL 212 * Offset: 0x1C Timer Trigger Control Register 213 * --------------------------------------------------------------------------------------------------- 214 * |Bits |Field |Descriptions 215 * | :----: | :----: | :---- | 216 * |[0] |TRGSSEL |Trigger Source Select Bit 217 * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. 218 * | | |0 = Time-out interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC. 219 * | | |1 = Capture interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC. 220 * |[1] |TRGEPWM |Trigger PWM Enable Bit 221 * | | |If this bit is set to 1, each timer time-out event or capture event can be as PWM counter clock source. 222 * | | |0 = Timer interrupt trigger PWM Disabled. 223 * | | |1 = Timer interrupt trigger PWM Enabled. 224 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as PWM counter clock source. 225 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as PWM counter clock source. 226 * |[2] |TRGEADC |Trigger EADC Enable Bit 227 * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. 228 * | | |0 = Timer interrupt trigger EADC Disabled. 229 * | | |1 = Timer interrupt trigger EADC Enabled. 230 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion. 231 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger ADC conversion. 232 * |[3] |TRGDAC |Trigger DAC Enable Bit 233 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. 234 * | | |0 = Timer interrupt trigger DAC Disabled. 235 * | | |1 = Timer interrupt trigger DAC Enabled. 236 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC. 237 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC. 238 * |[4] |TRGPDMA |Trigger PDMA Enable Bit 239 * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. 240 * | | |0 = Timer interrupt trigger PDMA Disabled. 241 * | | |1 = Timer interrupt trigger PDMA Enabled. 242 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer. 243 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer. 244 * @var TIMER_T::ALTCTL 245 * Offset: 0x20 Timer Alternative Control Register 246 * --------------------------------------------------------------------------------------------------- 247 * |Bits |Field |Descriptions 248 * | :----: | :----: | :---- | 249 * |[0] |FUNCSEL |Function Selection 250 * | | |0 = Timer controller is used as timer function. 251 * | | |1 = Timer controller is used as PWM function. 252 * | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. 253 * @var TIMER_T::PWMCTL 254 * Offset: 0x40 Timer PWM Control Register 255 * --------------------------------------------------------------------------------------------------- 256 * |Bits |Field |Descriptions 257 * | :----: | :----: | :---- | 258 * |[0] |CNTEN |PWM Counter Enable Bit 259 * | | |0 = PWM counter and clock prescale Stop Running. 260 * | | |1 = PWM counter and clock prescale Start Running. 261 * |[2:1] |CNTTYPE |PWM Counter Behavior Type 262 * | | |00 = Up count type. 263 * | | |01 = Down count type. 264 * | | |10 = Up-down count type. 265 * | | |11 = Reserved. 266 * |[3] |CNTMODE |PWM Counter Mode 267 * | | |0 = Auto-reload mode. 268 * | | |1 = One-shot mode. 269 * |[8] |CTRLD |Center Re-load 270 * | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. 271 * |[9] |IMMLDEN |Immediately Load Enable Bit 272 * | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled 273 * | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period. 274 * | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP. 275 * | | |Note: If IMMLDEN is enabled, CTRLD will be invalid. 276 * |[16] |OUTMODE |PWM Output Mode 277 * | | |This bit controls the output mode of corresponding PWM channel. 278 * | | |0 = PWM independent mode. 279 * | | |1 = PWM complementary mode. 280 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) 281 * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. 282 * | | |0 = ICE debug mode counter halt disable. 283 * | | |1 = ICE debug mode counter halt enable. 284 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 285 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) 286 * | | |0 = ICE debug mode acknowledgment effects PWM output. 287 * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged. 288 * | | |1 = ICE debug mode acknowledgment disabled. 289 * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not. 290 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 291 * @var TIMER_T::PWMCLKSRC 292 * Offset: 0x44 Timer PWM Counter Clock Source Register 293 * --------------------------------------------------------------------------------------------------- 294 * |Bits |Field |Descriptions 295 * | :----: | :----: | :---- | 296 * |[2:0] |CLKSRC |PWM Counter Clock Source Select 297 * | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event. 298 * | | |000 = TMRx_CLK. 299 * | | |001 = Internal TIMER0 time-out or capture event. 300 * | | |010 = Internal TIMER1 time-out or capture event. 301 * | | |011 = Internal TIMER2 time-out or capture event. 302 * | | |100 = Internal TIMER3 time-out or capture event. 303 * | | |Others = Reserved. 304 * | | |Note: If Timer PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. 305 * @var TIMER_T::PWMCLKPSC 306 * Offset: 0x48 Timer PWM Counter Clock Pre-scale Register 307 * --------------------------------------------------------------------------------------------------- 308 * |Bits |Field |Descriptions 309 * | :----: | :----: | :---- | 310 * |[11:0] |CLKPSC |PWM Counter Clock Pre-scale 311 * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1) 312 * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source. 313 * @var TIMER_T::PWMCNTCLR 314 * Offset: 0x4C Timer PWM Clear Counter Register 315 * --------------------------------------------------------------------------------------------------- 316 * |Bits |Field |Descriptions 317 * | :----: | :----: | :---- | 318 * |[0] |CNTCLR |Clear PWM Counter Control Bit 319 * | | |It is automatically cleared by hardware. 320 * | | |0 = No effect. 321 * | | |1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type. 322 * @var TIMER_T::PWMPERIOD 323 * Offset: 0x50 Timer PWM Period Register 324 * --------------------------------------------------------------------------------------------------- 325 * |Bits |Field |Descriptions 326 * | :----: | :----: | :---- | 327 * |[15:0] |PERIOD |PWM Period Register 328 * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. 329 * | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD. 330 * | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. 331 * | | |In up and down count type: 332 * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK. 333 * | | |In up-down count type: 334 * | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK. 335 * | | |Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type. 336 * @var TIMER_T::PWMCMPDAT 337 * Offset: 0x54 Timer PWM Comparator Register 338 * --------------------------------------------------------------------------------------------------- 339 * |Bits |Field |Descriptions 340 * | :----: | :----: | :---- | 341 * |[15:0] |CMP |PWM Comparator Register 342 * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert. 343 * @var TIMER_T::PWMDTCTL 344 * Offset: 0x58 Timer PWM Dead-Time Control Register 345 * --------------------------------------------------------------------------------------------------- 346 * |Bits |Field |Descriptions 347 * | :----: | :----: | :---- | 348 * |[11:0] |DTCNT |Dead-time Counter (Write Protect) 349 * | | |The dead-time can be calculated from the following two formulas: 350 * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0. 351 * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1. 352 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 353 * |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect) 354 * | | |Dead-time insertion function is only active when PWM complementary mode is enabled 355 * | | |If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay. 356 * | | |0 = Dead-time insertion Disabled on the pin pair. 357 * | | |1 = Dead-time insertion Enabled on the pin pair. 358 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 359 * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) 360 * | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale. 361 * | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale. 362 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 363 * @var TIMER_T::PWMCNT 364 * Offset: 0x5C Timer PWM Counter Register 365 * --------------------------------------------------------------------------------------------------- 366 * |Bits |Field |Descriptions 367 * | :----: | :----: | :---- | 368 * |[15:0] |CNT |PWM Counter Value Register (Read Only) 369 * | | |User can monitor CNT to know the current counter value in 16-bit period counter. 370 * |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only) 371 * | | |0 = Counter is active in down count. 372 * | | |1 = Counter is active up count. 373 * @var TIMER_T::PWMMSKEN 374 * Offset: 0x60 Timer PWM Output Mask Enable Register 375 * --------------------------------------------------------------------------------------------------- 376 * |Bits |Field |Descriptions 377 * | :----: | :----: | :---- | 378 * |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit 379 * | | |The PWMx_CH0 output signal will be masked when this bit is enabled 380 * | | |The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data. 381 * | | |0 = PWMx_CH0 output signal is non-masked. 382 * | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data. 383 * |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit 384 * | | |The PWMx_CH1 output signal will be masked when this bit is enabled 385 * | | |The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data. 386 * | | |0 = PWMx_CH1 output signal is non-masked. 387 * | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data. 388 * @var TIMER_T::PWMMSK 389 * Offset: 0x64 Timer PWM Output Mask Data Control Register 390 * --------------------------------------------------------------------------------------------------- 391 * |Bits |Field |Descriptions 392 * | :----: | :----: | :---- | 393 * |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit 394 * | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1). 395 * | | |0 = Output logic Low to PWMx_CH0. 396 * | | |1 = Output logic High to PWMx_CH0. 397 * |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit 398 * | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1). 399 * | | |0 = Output logic Low to PWMx_CH1. 400 * | | |1 = Output logic High to PWMx_CH1. 401 * @var TIMER_T::PWMBNF 402 * Offset: 0x68 Timer PWM Brake Pin Noise Filter Register 403 * --------------------------------------------------------------------------------------------------- 404 * |Bits |Field |Descriptions 405 * | :----: | :----: | :---- | 406 * |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit 407 * | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled. 408 * | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled. 409 * |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection 410 * | | |000 = Noise filter clock is PCLKx. 411 * | | |001 = Noise filter clock is PCLKx/2. 412 * | | |010 = Noise filter clock is PCLKx/4. 413 * | | |011 = Noise filter clock is PCLKx/8. 414 * | | |100 = Noise filter clock is PCLKx/16. 415 * | | |101 = Noise filter clock is PCLKx/32. 416 * | | |110 = Noise filter clock is PCLKx/64. 417 * | | |111 = Noise filter clock is PCLKx/128. 418 * |[6:4] |BRKFCNT |Brake Pin Noise Filter Count 419 * | | |The fields is used to control the active noise filter sample time. 420 * | | |Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT. 421 * |[7] |BRKPINV |Brake Pin Detection Control Bit 422 * | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect. 423 * | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect . 424 * |[17:16] |BKPINSRC |Brake Pin Source Select 425 * | | |00 = Brake pin source comes from PWM0_BRAKE0 pin. 426 * | | |01 = Brake pin source comes from PWM0_BRAKE1 pin. 427 * | | |10 = Brake pin source comes from PWM1_BRAKE0 pin. 428 * | | |11 = Brake pin source comes from PWM1_BRAKE1 pin. 429 * @var TIMER_T::PWMFAILBRK 430 * Offset: 0x6C Timer PWM System Fail Brake Control Register 431 * --------------------------------------------------------------------------------------------------- 432 * |Bits |Field |Descriptions 433 * | :----: | :----: | :---- | 434 * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit 435 * | | |0 = Brake Function triggered by clock fail detection Disabled. 436 * | | |1 = Brake Function triggered by clock fail detection Enabled. 437 * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit 438 * | | |0 = Brake Function triggered by BOD event Disabled. 439 * | | |1 = Brake Function triggered by BOD event Enabled. 440 * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit 441 * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. 442 * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. 443 * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit 444 * | | |0 = Brake Function triggered by core lockup event Disabled. 445 * | | |1 = Brake Function triggered by core lockup event Enabled. 446 * @var TIMER_T::PWMBRKCTL 447 * Offset: 0x70 Timer PWM Brake Control Register 448 * --------------------------------------------------------------------------------------------------- 449 * |Bits |Field |Descriptions 450 * | :----: | :----: | :---- | 451 * |[0] |CPO0EBEN |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) 452 * | | |0 = Internal ACMP0_O signal as edge-detect brake source Disabled. 453 * | | |1 = Internal ACMP0_O signal as edge-detect brake source Enabled. 454 * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. 455 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 456 * |[1] |CPO1EBEN |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) 457 * | | |0 = Internal ACMP1_O signal as edge-detect brake source Disabled. 458 * | | |1 = Internal ACMP1_O signal as edge-detect brake source Enabled. 459 * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. 460 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 461 * |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect) 462 * | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled. 463 * | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled. 464 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 465 * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) 466 * | | |0 = System fail condition as edge-detect brake source Disabled. 467 * | | |1 = System fail condition as edge-detect brake source Enabled. 468 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 469 * |[8] |CPO0LBEN |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) 470 * | | |0 = Internal ACMP0_O signal as level-detect brake source Disabled. 471 * | | |1 = Internal ACMP0_O signal as level-detect brake source Enabled. 472 * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. 473 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 474 * |[9] |CPO1LBEN |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) 475 * | | |0 = Internal ACMP1_O signal as level-detect brake source Disabled. 476 * | | |1 = Internal ACMP1_O signal as level-detect brake source Enabled. 477 * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. 478 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 479 * |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect) 480 * | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled. 481 * | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled. 482 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 483 * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) 484 * | | |0 = System fail condition as level-detect brake source Disabled. 485 * | | |1 = System fail condition as level-detect brake source Enabled. 486 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 487 * |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect) 488 * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output. 489 * | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened. 490 * | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened. 491 * | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened. 492 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 493 * |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect) 494 * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output. 495 * | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened. 496 * | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened. 497 * | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened. 498 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 499 * @var TIMER_T::PWMPOLCTL 500 * Offset: 0x74 Timer PWM Pin Output Polar Control Register 501 * --------------------------------------------------------------------------------------------------- 502 * |Bits |Field |Descriptions 503 * | :----: | :----: | :---- | 504 * |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit 505 * | | |The bit is used to control polarity state of PWMx_CH0 output pin. 506 * | | |0 = PWMx_CH0 output pin polar inverse Disabled. 507 * | | |1 = PWMx_CH0 output pin polar inverse Enabled. 508 * |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit 509 * | | |The bit is used to control polarity state of PWMx_CH1 output pin. 510 * | | |0 = PWMx_CH1 output pin polar inverse Disabled. 511 * | | |1 = PWMx_CH1 output pin polar inverse Enabled. 512 * @var TIMER_T::PWMPOEN 513 * Offset: 0x78 Timer PWM Pin Output Enable Register 514 * --------------------------------------------------------------------------------------------------- 515 * |Bits |Field |Descriptions 516 * | :----: | :----: | :---- | 517 * |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit 518 * | | |0 = PWMx_CH0 pin at tri-state mode. 519 * | | |1 = PWMx_CH0 pin in output mode. 520 * |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit 521 * | | |0 = PWMx_CH1 pin at tri-state mode. 522 * | | |1 = PWMx_CH1 pin in output mode. 523 * @var TIMER_T::PWMSWBRK 524 * Offset: 0x7C Timer PWM Software Trigger Brake Control Register 525 * --------------------------------------------------------------------------------------------------- 526 * |Bits |Field |Descriptions 527 * | :----: | :----: | :---- | 528 * |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect) 529 * | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. 530 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 531 * |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect) 532 * | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. 533 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 534 * @var TIMER_T::PWMINTEN0 535 * Offset: 0x80 Timer PWM Interrupt Enable Register 0 536 * --------------------------------------------------------------------------------------------------- 537 * |Bits |Field |Descriptions 538 * | :----: | :----: | :---- | 539 * |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit 540 * | | |0 = Zero point interrupt Disabled. 541 * | | |1 = Zero point interrupt Enabled. 542 * |[1] |PIEN |PWM Period Point Interrupt Enable Bit 543 * | | |0 = Period point interrupt Disabled. 544 * | | |1 = Period point interrupt Enabled. 545 * | | |Note: When in up-down count type, period point means the center point of current PWM period. 546 * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit 547 * | | |0 = Compare up count interrupt Disabled. 548 * | | |1 = Compare up count interrupt Enabled. 549 * |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit 550 * | | |0 = Compare down count interrupt Disabled. 551 * | | |1 = Compare down count interrupt Enabled. 552 * @var TIMER_T::PWMINTEN1 553 * Offset: 0x84 Timer PWM Interrupt Enable Register 1 554 * --------------------------------------------------------------------------------------------------- 555 * |Bits |Field |Descriptions 556 * | :----: | :----: | :---- | 557 * |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable (Write Protect) 558 * | | |0 = PWM edge-detect brake interrupt Disabled. 559 * | | |1 = PWM edge-detect brake interrupt Enabled. 560 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 561 * |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable (Write Protect) 562 * | | |0 = PWM level-detect brake interrupt Disabled. 563 * | | |1 = PWM level-detect brake interrupt Enabled. 564 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 565 * @var TIMER_T::PWMINTSTS0 566 * Offset: 0x88 Timer PWM Interrupt Status Register 0 567 * --------------------------------------------------------------------------------------------------- 568 * |Bits |Field |Descriptions 569 * | :----: | :----: | :---- | 570 * |[0] |ZIF |PWM Zero Point Interrupt Flag 571 * | | |This bit is set by hardware when TIMERx_PWM counter reaches zero. 572 * | | |Note: This bit is cleared by writing 1 to it. 573 * |[1] |PIF |PWM Period Point Interrupt Flag 574 * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. 575 * | | |Note1: When in up-down count type, PIF flag means the center point flag of current PWM period. 576 * | | |Note2: This bit is cleared by writing 1 to it. 577 * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag 578 * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. 579 * | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type.. 580 * | | |Note2: This bit is cleared by writing 1 to it. 581 * |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag 582 * | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP. 583 * | | |Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type. 584 * | | |Note2: This bit is cleared by writing 1 to it. 585 * @var TIMER_T::PWMINTSTS1 586 * Offset: 0x8C Timer PWM Interrupt Status Register 1 587 * --------------------------------------------------------------------------------------------------- 588 * |Bits |Field |Descriptions 589 * | :----: | :----: | :---- | 590 * |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) 591 * | | |0 = PWMx_CH0 edge-detect brake event do not happened. 592 * | | |1 = PWMx_CH0 edge-detect brake event happened. 593 * | | |Note1: This bit is cleared by writing 1 to it. 594 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 595 * |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect) 596 * | | |0 = PWMx_CH1 edge-detect brake event do not happened. 597 * | | |1 = PWMx_CH1 edge-detect brake event happened. 598 * | | |Note1: This bit is cleared by writing 1 to it. 599 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 600 * |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) 601 * | | |0 = PWMx_CH0 level-detect brake event do not happened. 602 * | | |1 = PWMx_CH0 level-detect brake event happened. 603 * | | |Note1: This bit is cleared by writing 1 to it. 604 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 605 * |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect) 606 * | | |0 = PWMx_CH1 level-detect brake event do not happened. 607 * | | |1 = PWMx_CH1 level-detect brake event happened. 608 * | | |Note1: This bit is cleared by writing 1 to it. 609 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 610 * |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only) 611 * | | |0 = PWMx_CH0 edge-detect brake state is released. 612 * | | |1 = PWMx_CH0 at edge-detect brake state. 613 * | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. 614 * |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only) 615 * | | |0 = PWMx_CH1 edge-detect brake state is released. 616 * | | |1 = PWMx_CH1 at edge-detect brake state. 617 * | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. 618 * |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only) 619 * | | |0 = PWMx_CH0 level-detect brake state is released. 620 * | | |1 = PWMx_CH0 at level-detect brake state. 621 * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. 622 * |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only) 623 * | | |0 = PWMx_CH1 level-detect brake state is released. 624 * | | |1 = PWMx_CH1 at level-detect brake state. 625 * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. 626 * @var TIMER_T::PWMEADCTS 627 * Offset: 0x90 Timer PWM ADC Trigger Source Select Register 628 * --------------------------------------------------------------------------------------------------- 629 * |Bits |Field |Descriptions 630 * | :----: | :----: | :---- | 631 * |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger EADC Conversion 632 * | | |000 = Trigger EADC conversion at zero point (ZIF). 633 * | | |001 = Trigger EADC conversion at period point (PIF). 634 * | | |010 = Trigger EADC conversion at zero or period point (ZIF or PIF). 635 * | | |011 = Trigger EADC conversion at compare up count point (CMPUIF). 636 * | | |100 = Trigger EADC conversion at compare down count point (CMPDIF). 637 * | | |Others = Reserved. 638 * |[7] |TRGEN |PWM Counter Event Trigger EADC Conversion Enable Bit 639 * | | |0 = PWM counter event trigger EADC conversion Disabled. 640 * | | |1 = PWM counter event trigger EADC conversion Enabled. 641 * @var TIMER_T::PWMSCTL 642 * Offset: 0x94 Timer PWM Synchronous Control Register 643 * --------------------------------------------------------------------------------------------------- 644 * |Bits |Field |Descriptions 645 * | :----: | :----: | :---- | 646 * |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select 647 * | | |00 = PWM synchronous function Disabled. 648 * | | |01 = PWM synchronous counter start function Enabled. 649 * | | |10 = Reserved. 650 * | | |11 = PWM synchronous counter clear function Enabled. 651 * |[8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select 652 * | | |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN. 653 * | | |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN. 654 * | | |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0. 655 * | | |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1. 656 * @var TIMER_T::PWMSTRG 657 * Offset: 0x98 Timer PWM Synchronous Trigger Register 658 * --------------------------------------------------------------------------------------------------- 659 * |Bits |Field |Descriptions 660 * | :----: | :----: | :---- | 661 * |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only) 662 * | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting. 663 * | | |Note: This bit is only available in TIMER0 and TIMER2. 664 * @var TIMER_T::PWMSTATUS 665 * Offset: 0x9C Timer PWM Status Register 666 * --------------------------------------------------------------------------------------------------- 667 * |Bits |Field |Descriptions 668 * | :----: | :----: | :---- | 669 * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag 670 * | | |0 = Indicates the PWM counter value never reached its maximum value 0xFFFF. 671 * | | |1 = Indicates the PWM counter value has reached its maximum value. 672 * | | |Note: This bit is cleared by writing 1 to it. 673 * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag 674 * | | |0 = PWM counter event trigger EADC start conversion is not occurred. 675 * | | |1 = PWM counter event trigger EADC start conversion has occurred. 676 * | | |Note: This bit is cleared by writing 1 to it. 677 * @var TIMER_T::PWMPBUF 678 * Offset: 0xA0 Timer PWM Period Buffer Register 679 * --------------------------------------------------------------------------------------------------- 680 * |Bits |Field |Descriptions 681 * | :----: | :----: | :---- | 682 * |[15:0] |PBUF |PWM Period Buffer Register (Read Only) 683 * | | |Used as PERIOD active register. 684 * @var TIMER_T::PWMCMPBUF 685 * Offset: 0xA4 Timer PWM Comparator Buffer Register 686 * --------------------------------------------------------------------------------------------------- 687 * |Bits |Field |Descriptions 688 * | :----: | :----: | :---- | 689 * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only) 690 * | | |Used as CMP active register. 691 */ 692 __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */ 693 __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */ 694 __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */ 695 __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */ 696 __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */ 697 __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */ 698 __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */ 699 __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */ 700 __IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */ 701 __I uint32_t RESERVE0[7]; 702 __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */ 703 __IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */ 704 __IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */ 705 __IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */ 706 __IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */ 707 __IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */ 708 __IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-Time Control Register */ 709 __I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */ 710 __IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */ 711 __IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */ 712 __IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */ 713 __IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */ 714 __IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */ 715 __IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */ 716 __IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */ 717 __O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */ 718 __IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */ 719 __IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */ 720 __IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */ 721 __IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */ 722 __IO uint32_t PWMEADCTS; /*!< [0x0090] Timer PWM ADC Trigger Source Select Register */ 723 __IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */ 724 __O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */ 725 __IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */ 726 __I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */ 727 __I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */ 728 729 } TIMER_T; 730 731 /** 732 @addtogroup TIMER_CONST TIMER Bit Field Definition 733 Constant Definitions for TIMER Controller 734 @{ */ 735 736 #define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */ 737 #define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */ 738 739 #define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */ 740 #define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */ 741 742 #define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */ 743 #define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */ 744 745 #define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */ 746 #define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */ 747 748 #define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */ 749 #define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */ 750 751 #define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */ 752 #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */ 753 754 #define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */ 755 #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */ 756 757 #define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */ 758 #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */ 759 760 #define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */ 761 #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */ 762 763 #define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */ 764 #define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */ 765 766 #define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */ 767 #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */ 768 769 #define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */ 770 #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */ 771 772 #define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */ 773 #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */ 774 775 #define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */ 776 #define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */ 777 778 #define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */ 779 #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */ 780 781 #define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */ 782 #define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */ 783 784 #define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */ 785 #define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */ 786 787 #define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */ 788 #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */ 789 790 #define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */ 791 #define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */ 792 793 #define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */ 794 #define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */ 795 796 #define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */ 797 #define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */ 798 799 #define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */ 800 #define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */ 801 802 #define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */ 803 #define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */ 804 805 #define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */ 806 #define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */ 807 808 #define TIMER_EXTCTL_ACMPSSEL_Pos (8) /*!< TIMER_T::EXTCTL: ACMPSSEL Position */ 809 #define TIMER_EXTCTL_ACMPSSEL_Msk (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos) /*!< TIMER_T::EXTCTL: ACMPSSEL Mask */ 810 811 #define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */ 812 #define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */ 813 814 #define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */ 815 #define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */ 816 817 #define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */ 818 #define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */ 819 820 #define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */ 821 #define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */ 822 823 #define TIMER_TRGCTL_TRGEPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGEPWM Position */ 824 #define TIMER_TRGCTL_TRGEPWM_Msk (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos) /*!< TIMER_T::TRGCTL: TRGEPWM Mask */ 825 826 #define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */ 827 #define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */ 828 829 #define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */ 830 #define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */ 831 832 #define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */ 833 #define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */ 834 835 #define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */ 836 #define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */ 837 838 #define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */ 839 #define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */ 840 841 #define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */ 842 #define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */ 843 844 #define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */ 845 #define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */ 846 847 #define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */ 848 #define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */ 849 850 #define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */ 851 #define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */ 852 853 #define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */ 854 #define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */ 855 856 #define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */ 857 #define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */ 858 859 #define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */ 860 #define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */ 861 862 #define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */ 863 #define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */ 864 865 #define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */ 866 #define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */ 867 868 #define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */ 869 #define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */ 870 871 #define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */ 872 #define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */ 873 874 #define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */ 875 #define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */ 876 877 #define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */ 878 #define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */ 879 880 #define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */ 881 #define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */ 882 883 #define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */ 884 #define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */ 885 886 #define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */ 887 #define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */ 888 889 #define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */ 890 #define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */ 891 892 #define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */ 893 #define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */ 894 895 #define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */ 896 #define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */ 897 898 #define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */ 899 #define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */ 900 901 #define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */ 902 #define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */ 903 904 #define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */ 905 #define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */ 906 907 #define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */ 908 #define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */ 909 910 #define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */ 911 #define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */ 912 913 #define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */ 914 #define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */ 915 916 #define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */ 917 #define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */ 918 919 #define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */ 920 #define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */ 921 922 #define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */ 923 #define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask */ 924 925 #define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */ 926 #define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask */ 927 928 #define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */ 929 #define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */ 930 931 #define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position */ 932 #define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask */ 933 934 #define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position */ 935 #define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask */ 936 937 #define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */ 938 #define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */ 939 940 #define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */ 941 #define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */ 942 943 #define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position */ 944 #define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask */ 945 946 #define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position */ 947 #define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask */ 948 949 #define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */ 950 #define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */ 951 952 #define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */ 953 #define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */ 954 955 #define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */ 956 #define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */ 957 958 #define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */ 959 #define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */ 960 961 #define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */ 962 #define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */ 963 964 #define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */ 965 #define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */ 966 967 #define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */ 968 #define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */ 969 970 #define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */ 971 #define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */ 972 973 #define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */ 974 #define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */ 975 976 #define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */ 977 #define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */ 978 979 #define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */ 980 #define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */ 981 982 #define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */ 983 #define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */ 984 985 #define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */ 986 #define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */ 987 988 #define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */ 989 #define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */ 990 991 #define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */ 992 #define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */ 993 994 #define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */ 995 #define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */ 996 997 #define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */ 998 #define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */ 999 1000 #define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */ 1001 #define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */ 1002 1003 #define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */ 1004 #define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */ 1005 1006 #define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */ 1007 #define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */ 1008 1009 #define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */ 1010 #define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */ 1011 1012 #define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */ 1013 #define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */ 1014 1015 #define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */ 1016 #define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */ 1017 1018 #define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */ 1019 #define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */ 1020 1021 #define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */ 1022 #define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */ 1023 1024 #define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */ 1025 #define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */ 1026 1027 #define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */ 1028 #define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */ 1029 1030 #define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */ 1031 #define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */ 1032 1033 #define TIMER_PWMEADCTS_TRGSEL_Pos (0) /*!< TIMER_T::PWMEADCTS: TRGSEL Position */ 1034 #define TIMER_PWMEADCTS_TRGSEL_Msk (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< TIMER_T::PWMEADCTS: TRGSEL Mask */ 1035 1036 #define TIMER_PWMEADCTS_TRGEN_Pos (7) /*!< TIMER_T::PWMEADCTS: TRGEN Position */ 1037 #define TIMER_PWMEADCTS_TRGEN_Msk (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos) /*!< TIMER_T::PWMEADCTS: TRGEN Mask */ 1038 1039 #define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */ 1040 #define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */ 1041 1042 #define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */ 1043 #define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */ 1044 1045 #define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */ 1046 #define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */ 1047 1048 #define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */ 1049 #define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */ 1050 1051 #define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */ 1052 #define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */ 1053 1054 #define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */ 1055 #define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */ 1056 1057 #define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */ 1058 #define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */ 1059 1060 /**@}*/ /* TIMER_CONST */ 1061 /**@}*/ /* end of TIMER register group */ 1062 /**@}*/ /* end of REGISTER group */ 1063 1064 #endif /* __TIMER_REG_H__ */ 1065
