1 /**************************************************************************//** 2 * @file timer_reg.h 3 * @version V1.00 4 * @brief TIMER register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __TIMER_REG_H__ 10 #define __TIMER_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup TIMER Timer Controller (TIMER) 23 Memory Mapped Structure for TIMER Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var TIMER_T::CTL 32 * Offset: 0x00 Timer Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[7:0] |PSC |Prescale Counter 37 * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter 38 * | | |If this field is 0 (PSC = 0), then there is no scaling. 39 * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 40 * |[15] |FUNCSEL |Function Selection 41 * | | |0 = Timer controller is used as timer function. 42 * | | |1 = Timer controller is used as PWM function. 43 * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Bit 44 * | | |Setting this bit will enable the inter-timer trigger capture function. 45 * | | |The Timer0/2 will be in event counter mode and counting with external clock source or event 46 * | | |Also, Timer1/3 will be in trigger-counting mode of capture function. 47 * | | |0 = Inter-Timer Trigger Capture mode Disabled. 48 * | | |1 = Inter-Timer Trigger Capture mode Enabled. 49 * | | |Note: For Timer1/3, this bit is ineffective and the read back value is always 0. 50 * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit 51 * | | |0 = The behavior selection in periodic mode is Disabled. 52 * | | |When user updates CMPDAT while timer is running in periodic mode, 53 * | | |CNT will be reset to default value. 54 * | | |1 = The behavior selection in periodic mode is Enabled. 55 * | | |When user updates CMPDAT while timer is running in periodic mode, the limitations as bellows list, 56 * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. 57 * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. 58 * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. 59 * |[21] |TGLPINSEL |Toggle-output Pin Select 60 * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin). 61 * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). 62 * |[22] |CAPSRC |Capture Pin Source Selection 63 * | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin. 64 * | | |1 = Capture Function source is from internal ACMP output signal, internal clock (MIRC, LIRC, HIRC), or external clock (HXT, LXT). 65 * | | |Note: When CAPSRC = 1,User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or which clock is as timer capture source. 66 * |[23] |WKEN |Wake-up Function Enable Bit 67 * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 68 * | | |0 = Wake-up function Disabled if timer interrupt signal generated. 69 * | | |1 = Wake-up function Enabled if timer interrupt signal generated. 70 * |[24] |EXTCNTEN |Event Counter Mode Enable Bit 71 * | | |This bit is for external counting pin function enabled. 72 * | | |0 = Event counter mode Disabled. 73 * | | |1 = Event counter mode Enabled. 74 * | | |Note: When timer is used as an event counter, this bit should be set to 1. 75 * |[25] |ACTSTS |Timer Active Status Bit (Read Only) 76 * | | |This bit indicates the 24-bit up counter status. 77 * | | |0 = 24-bit up counter is not active. 78 * | | |1 = 24-bit up counter is active. 79 * | | |Note: This bit may active when CNT 0 transition to CNT 1. 80 * |[28:27] |OPMODE |Timer Counting Mode Select 81 * | | |00 = The timer controller is operated in One-shot mode. 82 * | | |01 = The timer controller is operated in Periodic mode. 83 * | | |10 = The timer controller is operated in Toggle-output mode. 84 * | | |11 = The timer controller is operated in Continuous Counting mode. 85 * |[29] |INTEN |Timer Interrupt Enable Bit 86 * | | |0 = Timer time-out interrupt Disabled. 87 * | | |1 = Timer time-out interrupt Enabled. 88 * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 89 * |[30] |CNTEN |Timer Counting Enable Bit 90 * | | |0 = Stops/Suspends counting. 91 * | | |1 = Starts counting. 92 * | | |Note 1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. 93 * | | |Note 2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated. 94 * | | |Note 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. 95 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect) 96 * | | |0 = ICE debug mode acknowledgement effects TIMER counting. 97 * | | |TIMER counter will be held while CPU is held by ICE. 98 * | | |1 = ICE debug mode acknowledgement Disabled. 99 * | | |TIMER counter will keep going no matter CPU is held by ICE or not. 100 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 101 * @var TIMER_T::CMP 102 * Offset: 0x04 Timer Comparator Register 103 * --------------------------------------------------------------------------------------------------- 104 * |Bits |Field |Descriptions 105 * | :----: | :----: | :---- | 106 * |[23:0] |CMPDAT |Timer Comparator Value 107 * | | |CMPDAT is a 24-bit compared value register 108 * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. 109 * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). 110 * | | |Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. 111 * | | |Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field 112 * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 113 * @var TIMER_T::INTSTS 114 * Offset: 0x08 Timer Interrupt Status Register 115 * --------------------------------------------------------------------------------------------------- 116 * |Bits |Field |Descriptions 117 * | :----: | :----: | :---- | 118 * |[0] |TIF |Timer Interrupt Flag 119 * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. 120 * | | |0 = No effect. 121 * | | |1 = CNT value matches the CMPDAT value. 122 * | | |Note: This bit is cleared by writing 1 to it. 123 * |[1] |TWKF |Timer Wake-up Flag 124 * | | |This bit indicates the interrupt wake-up flag status of timer. 125 * | | |0 = Timer does not cause CPU wake-up. 126 * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. 127 * | | |Note: This bit is cleared by writing 1 to it. 128 * @var TIMER_T::CNT 129 * Offset: 0x0C Timer Data Register 130 * --------------------------------------------------------------------------------------------------- 131 * |Bits |Field |Descriptions 132 * | :----: | :----: | :---- | 133 * |[23:0] |CNT |Timer Data Register 134 * | | |Read operation. 135 * | | |Read this register to get CNT value. For example: 136 * | | |If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value. 137 * | | |If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value. 138 * | | |Write operation. 139 * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. 140 * |[31] |RSTACT |Timer Data Register Reset Active (Read Only) 141 * | | |This bit indicates if the counter reset operation active. 142 * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter 143 * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress 144 * | | |Once the counter reset operation done, timer clear this bit to 0 automatically. 145 * | | |0 = Reset operation is done. 146 * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress. 147 * @var TIMER_T::CAP 148 * Offset: 0x10 Timer Capture Data Register 149 * --------------------------------------------------------------------------------------------------- 150 * |Bits |Field |Descriptions 151 * | :----: | :----: | :---- | 152 * |[23:0] |CAPDAT |Timer Capture Data Register 153 * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 154 * @var TIMER_T::EXTCTL 155 * Offset: 0x14 Timer External Control Register 156 * --------------------------------------------------------------------------------------------------- 157 * |Bits |Field |Descriptions 158 * | :----: | :----: | :---- | 159 * |[0] |CNTPHASE |Timer External Count Phase 160 * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3). 161 * | | |0 = A falling edge of external counting pin will be counted. 162 * | | |1 = A rising edge of external counting pin will be counted. 163 * |[3] |CAPEN |Timer Capture Enable Bit 164 * | | |This bit enables the capture input function. 165 * | | |0 =Capture source Disabled. 166 * | | |1 =Capture source Enabled. 167 * | | |Note: When CAPEN is 1, user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source. 168 * |[4] |CAPFUNCS |Capture Function Selection 169 * | | |0 = External Capture Mode Enabled. 170 * | | |1 = External Reset Mode Enabled. 171 * | | |Note 1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field. 172 * | | |Note 2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately. 173 * |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit 174 * | | |0 = TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Disabled. 175 * | | |1 = TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Enabled. 176 * | | |Note: CAPIEN is used to enable timer external interrupt 177 * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. 178 * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. 179 * |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit 180 * | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled. 181 * | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled. 182 * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. 183 * |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit 184 * | | |0 = TMx (x= 0~3) pin de-bounce Disabled. 185 * | | |1 = TMx (x= 0~3) pin de-bounce Enabled. 186 * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 187 * |[10:8] |INTERCAPSEL|Internal Capture Source Select 188 * | | |000 = Capture Function source is from internal ACMP0 output signal. 189 * | | |001 = Capture Function source is from internal ACMP1 output signal. 190 * | | |010 = Capture Function source is from HXT. 191 * | | |011 = Capture Function source is from LXT. 192 * | | |100 = Capture Function source is from HIRC. 193 * | | |101 = Capture Function source is from LIRC. 194 * | | |110 = Capture Function source is from MIRC. 195 * | | |111 = Capture Function source is from internal ACMP2 output signal.. 196 * | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. 197 * |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect 198 * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. 199 * | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin. 200 * | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin. 201 * | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer. 202 * | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer. 203 * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin. 204 * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin. 205 * | | |100, 101 = Reserved. 206 * | | |Note: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source. 207 * |[18:16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function 208 * | | |000 = Event Counter input source is from external TMx (x= 0~3) pin. 209 * | | |001 = Event Counter input source is from internal USB internal SOF output signal. 210 * | | |010 = Event Counter input source is from internal ACMP0 output signal. 211 * | | |011 = Event Counter input source is from internal ACMP1 output signal. 212 * | | |100 = Event Counter input source is from internal ACMP2 output signal. 213 * | | |101~111 = Reserved. 214 * |[31:28] |CAPDIVSCL |Timer Capture Source Divider Scale 215 * | | |This bits indicate the divide scale for capture source divider 216 * | | |0000 = Capture source/1. 217 * | | |0001 = Capture source/2. 218 * | | |0010 = Capture source/4. 219 * | | |0011 = Capture source/8. 220 * | | |0100 = Capture source/16. 221 * | | |0101 = Capture source/32. 222 * | | |0110 = Capture source/64. 223 * | | |0111 = Capture source/128. 224 * | | |1000 = Capture source/256. 225 * | | |1001~1111 = Reserved. 226 * | | |Note: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. 227 * @var TIMER_T::EINTSTS 228 * Offset: 0x18 Timer External Interrupt Status Register 229 * --------------------------------------------------------------------------------------------------- 230 * |Bits |Field |Descriptions 231 * | :----: | :----: | :---- | 232 * |[0] |CAPIF |Timer External Capture Interrupt Flag 233 * | | |This bit indicates the timer external capture interrupt flag status. 234 * | | |0 = TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt did not occur. 235 * | | |1 = TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt occurred. 236 * | | |Note 1: This bit is cleared by writing 1 to it. 237 * | | |Note 2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. 238 * | | |Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status 239 * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 240 * |[1] |CAPIFOV |Capture Latch Interrupt Flag Overrun Status (Read Only) 241 * | | |0 = Capture latch happened when the corresponding CAPIF is 0. 242 * | | |1 = Capture latch happened when the corresponding CAPIF is 1. 243 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPIF. 244 * @var TIMER_T::TRGCTL 245 * Offset: 0x1C Timer Trigger Control Register 246 * --------------------------------------------------------------------------------------------------- 247 * |Bits |Field |Descriptions 248 * | :----: | :----: | :---- | 249 * |[0] |TRGSSEL |Trigger Source Select Bit 250 * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. 251 * | | |0 = Time-out interrupt signal is used to internal trigger PWM, EPWM, PDMA, DAC, LPADC and EADC. 252 * | | |1 = Capture interrupt signal is used to internal trigger PWM, EPWM, PDMA, DAC, LPADC and EADC. 253 * |[1] |TRGPWM |Trigger PWM/EPWM Enable Bit 254 * | | |If this bit is set to 1, each timer time-out event or capture event can be as PWM/EPWM counter clock source. 255 * | | |0 = Timer interrupt trigger PWM/EPWM Disabled. 256 * | | |1 = Timer interrupt trigger PWM/EPWM Enabled. 257 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as PWM/EPWM counter clock source. 258 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as PWM/EPWM counter clock source. 259 * |[2] |TRGEADC |Trigger EADC Enable Bit 260 * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. 261 * | | |0 = Timer interrupt trigger EADC Disabled. 262 * | | |1 = Timer interrupt trigger EADC Enabled. 263 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion. 264 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion. 265 * |[3] |TRGDAC |Trigger DAC Enable Bit 266 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. 267 * | | |0 = Timer interrupt trigger DAC Disabled. 268 * | | |1 = Timer interrupt trigger DAC Enabled. 269 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC. 270 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC. 271 * |[4] |TRGPDMA |Trigger PDMA Enable Bit 272 * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. 273 * | | |0 = Timer interrupt trigger PDMA Disabled. 274 * | | |1 = Timer interrupt trigger PDMA Enabled. 275 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer. 276 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer. 277 * |[5] |TRGLPADC |Trigger LPADC Enable Bit 278 * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered LPADC transfer. 279 * | | |0 = Timer interrupt trigger LPADC Disabled. 280 * | | |1 = Timer interrupt trigger LPADC Enabled. 281 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger LPADC. 282 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger LPADC. 283 * |[8] |TRGTK |Trigger Touch-key Scan Enable Bit 284 * | | |If this bit is set to 1, timer time-out interrupt can trigger Touck-Key start scan. 285 * | | |0 = Timer time-out interrupt signal trigger Touch-Key scan Disabled. 286 * | | |1 = Timer time-out interrupt signal trigger Touch-Key scan Enabled. 287 * @var TIMER_T::CAPNF 288 * Offset: 0x24 Timer Capture Input Noise Filter Register 289 * --------------------------------------------------------------------------------------------------- 290 * |Bits |Field |Descriptions 291 * | :----: | :----: | :---- | 292 * |[0] |CAPNFEN |Capture Noise Filter Enable 293 * | | |0 = Capture Noise Filter function Disabled. 294 * | | |1 = Capture Noise Filter function Enabled. 295 * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection 296 * | | |000 = Noise filter clock is ECLKx. 297 * | | |001 = Noise filter clock is ECLKx/2. 298 * | | |010 = Noise filter clock is ECLKx/4. 299 * | | |011 = Noise filter clock is ECLKx/8. 300 * | | |100 = Noise filter clock is ECLKx/16. 301 * | | |101 = Noise filter clock is ECLKx/32. 302 * | | |110 = Noise filter clock is ECLKx/64. 303 * | | |111 = Noise filter clock is ECLKx/128. 304 * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count 305 * | | |These bits control the capture filter counter to count from 0 to CAPNFCNT. 306 * @var TIMER_T::PWMCTL 307 * Offset: 0x40 Timer PWM Control Register 308 * --------------------------------------------------------------------------------------------------- 309 * |Bits |Field |Descriptions 310 * | :----: | :----: | :---- | 311 * |[0] |CNTEN |PWM Counter Enable Bit 312 * | | |0 = PWM counter and clock prescale Stop Running. 313 * | | |1 = PWM counter and clock prescale Start Running. 314 * |[3] |CNTMODE |PWM Counter Mode 315 * | | |0 = Auto-reload mode. 316 * | | |1 = One-shot mode. 317 * |[12] |PWMINTWKEN|PWM Interrupt Wake-up Enable Bit 318 * | | |If PWM interrupt occurs when chip is in Power-down mode, PWMINTWKEN can determine whether chip wake-up occurs or not. 319 * | | |0 = PWM interrupt wake-up Disabled. 320 * | | |1 = PWM interrupt wake-up Enabled. 321 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) 322 * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. 323 * | | |0 = ICE debug mode counter halt Disabled. 324 * | | |1 = ICE debug mode counter halt Enabled. 325 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL control register. 326 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) 327 * | | |0 = ICE debug mode acknowledgement effects PWM output. 328 * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged. 329 * | | |1 = ICE debug mode acknowledgement disabled. 330 * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not. 331 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL control register. 332 * @var TIMER_T::PWMCLKPSC 333 * Offset: 0x44 Timer PWM Counter Clock Pre-scale Register 334 * --------------------------------------------------------------------------------------------------- 335 * |Bits |Field |Descriptions 336 * | :----: | :----: | :---- | 337 * |[7:0] |CLKPSC |PWM Counter Clock Pre-scale 338 * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1) 339 * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source. 340 * @var TIMER_T::PWMCNTCLR 341 * Offset: 0x48 Timer PWM Clear Counter Register 342 * --------------------------------------------------------------------------------------------------- 343 * |Bits |Field |Descriptions 344 * | :----: | :----: | :---- | 345 * |[0] |CNTCLR |Clear PWM Counter Control Bit 346 * | | |It is automatically cleared by hardware. 347 * | | |0 = No effect. 348 * | | |1 = Clear 16-bit PWM counter to 0x0000 in up count type. 349 * @var TIMER_T::PWMPERIOD 350 * Offset: 0x4C Timer PWM Period Register 351 * --------------------------------------------------------------------------------------------------- 352 * |Bits |Field |Descriptions 353 * | :----: | :----: | :---- | 354 * |[15:0] |PERIOD |PWM Period Register 355 * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. 356 * | | |In up count type: 357 * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK. 358 * @var TIMER_T::PWMCMPDAT 359 * Offset: 0x50 Timer PWM Comparator Register 360 * --------------------------------------------------------------------------------------------------- 361 * |Bits |Field |Descriptions 362 * | :----: | :----: | :---- | 363 * |[15:0] |CMP |PWM Comparator Register 364 * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC , LPADC, PDMA, and DAC start conversion. 365 * @var TIMER_T::PWMCNT 366 * Offset: 0x54 Timer PWM Counter Register 367 * --------------------------------------------------------------------------------------------------- 368 * |Bits |Field |Descriptions 369 * | :----: | :----: | :---- | 370 * |[15:0] |CNT |PWM Counter Value Register (Read Only) 371 * | | |User can monitor CNT to know the current counter value in 16-bit period counter. 372 * @var TIMER_T::PWMPOLCTL 373 * Offset: 0x58 Timer PWM Pin Output Polar Control Register 374 * --------------------------------------------------------------------------------------------------- 375 * |Bits |Field |Descriptions 376 * | :----: | :----: | :---- | 377 * |[0] |PINV |PWMx Output Pin Polar Control Bit 378 * | | |The bit is used to control polarity state of PWMx_OUT pin. 379 * | | |0 = PWMx_OUT pin polar inverse Disabled. 380 * | | |1 = PWMx_OUT polar inverse Enabled. 381 * | | |Note: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin. 382 * @var TIMER_T::PWMPOCTL 383 * Offset: 0x5C Timer PWM Pin Output Control Register 384 * --------------------------------------------------------------------------------------------------- 385 * |Bits |Field |Descriptions 386 * | :----: | :----: | :---- | 387 * |[0] |POEN |PWMx Output Pin Enable Bit 388 * | | |0 = PWMx_OUT pin at tri-state mode. 389 * | | |1 = PWMx_OUT pin in output mode. 390 * | | |Note: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin. 391 * |[8] |POSEL |PWM Output Pin Select 392 * | | |0 = PWMx_OUT pin is TMx. 393 * | | |1 = PWMx_OUT pin is TMx_EXT. 394 * @var TIMER_T::PWMINTEN0 395 * Offset: 0x60 Timer PWM Interrupt Enable Register 0 396 * --------------------------------------------------------------------------------------------------- 397 * |Bits |Field |Descriptions 398 * | :----: | :----: | :---- | 399 * |[1] |PIEN |PWM Period Point Interrupt Enable Bit 400 * | | |0 = Period point interrupt Disabled. 401 * | | |1 = Period point interrupt Enabled. 402 * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit 403 * | | |0 = Compare up count interrupt Disabled. 404 * | | |1 = Compare up count interrupt Enabled. 405 * @var TIMER_T::PWMINTSTS0 406 * Offset: 0x64 Timer PWM Interrupt Status Register 0 407 * --------------------------------------------------------------------------------------------------- 408 * |Bits |Field |Descriptions 409 * | :----: | :----: | :---- | 410 * |[1] |PIF |PWM Period Point Interrupt Flag 411 * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. 412 * | | |Note: This bit is cleared by writing 1 to it. 413 * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag 414 * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. 415 * | | |Note: If CMP equal to PERIOD, there is no CMPUIF flag in up count type 416 * | | |Note 2: This bit is cleared by writing 1 to it. 417 * @var TIMER_T::PWMTRGCTL 418 * Offset: 0x68 Timer PWM Trigger Control Register 419 * --------------------------------------------------------------------------------------------------- 420 * |Bits |Field |Descriptions 421 * | :----: | :----: | :---- | 422 * |[1:0] |TRGSEL |PWM Counter Event Source Select to Trigger Conversion 423 * | | |00 = Trigger conversion at period point (PIF). 424 * | | |01 = Trigger conversion at compare up count point (CMPUIF). 425 * | | |10 = Trigger conversion at period or compare up count point (PIF or CMPUIF). 426 * | | |11 = Reserved. 427 * |[7] |PWMTRGEADC|PWM Counter Event Trigger EADC Conversion Enable Bit 428 * | | |0 = PWM counter event trigger EADC conversion Disabled. 429 * | | |1 = PWM counter event trigger EADC conversion Enabled. 430 * | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. 431 * |[8] |PWMTRGDAC |PWM Counter Event Trigger DAC Conversion Enable Bit 432 * | | |If this bit is set to 1, PWM can trigger DAC conversion. 433 * | | |0 = PWM trigger DAC Disabled. 434 * | | |1 = PWM trigger DAC Enabled. 435 * | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. 436 * |[9] |PWMTRGPDMA|PWM Counter Event Trigger PDMA Conversion Enable Bit 437 * | | |If this bit is set to 1, PWM can trigger PDMA conversion. 438 * | | |0 = PWM trigger PDMA Disabled. 439 * | | |1 = PWM trigger PDMA Enabled. 440 * | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. 441 * |[10] |PWMTRGLPADC|PWM Counter Event Trigger LPADC Conversion Enable Bit 442 * | | |If this bit is set to 1, PWM can trigger LPADC conversion. 443 * | | |0 = PWM trigger LPADC Disabled. 444 * | | |1 = PWM trigger LPADC Enabled. 445 * | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. 446 * @var TIMER_T::PWMSTATUS 447 * Offset: 0x6C Timer PWM Status Register 448 * --------------------------------------------------------------------------------------------------- 449 * |Bits |Field |Descriptions 450 * | :----: | :----: | :---- | 451 * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag 452 * | | |0 = The PWM counter value never reached its maximum value 0xFFFF. 453 * | | |1 = The PWM counter value has reached its maximum value. 454 * | | |Note: This bit is cleared by writing 1 to it. 455 * |[8] |PWMINTWKF |PWM Interrupt Wake-up Flag 456 * | | |0 = PWM interrupt wake-up has not occurred. 457 * | | |1 = PWM interrupt wake-up has occurred. 458 * | | |Note: This bit is cleared by writing 1 to it. 459 * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag 460 * | | |0 = PWM counter event trigger EADC start conversion is not occurred. 461 * | | |1 = PWM counter event trigger EADC start conversion has occurred. 462 * | | |Note: This bit is cleared by writing 1 to it. 463 * |[17] |DACTRGF |Trigger DAC Start Conversion Flag 464 * | | |0 = PWM counter event trigger DAC start conversion has not occurred. 465 * | | |1 = PWM counter event trigger DAC start conversion has occurred. 466 * | | |Note: This bit is cleared by writing 1 to it. 467 * |[18] |PDMATRGF |Trigger PDMA Start Conversion Flag 468 * | | |0 = PWM counter event trigger PDMA start conversion has not occurred. 469 * | | |1 = PWM counter event trigger PDMA start conversion has occurred. 470 * | | |Note: This bit is cleared by writing 1 to it. 471 * |[19] |LPADCTRGF |Trigger LPADC Start Conversion Flag 472 * | | |0 = PWM counter event trigger LPADC start conversion has not occurred. 473 * | | |1 = PWM counter event trigger LPADC start conversion has occurred. 474 * | | |Note: This bit is cleared by writing 1 to it. 475 * @var TIMER_T::PWMPBUF 476 * Offset: 0x70 Timer PWM Period Buffer Register 477 * --------------------------------------------------------------------------------------------------- 478 * |Bits |Field |Descriptions 479 * | :----: | :----: | :---- | 480 * |[15:0] |PBUF |PWM Period Buffer Register (Read Only) 481 * | | |Used as PERIOD active register. 482 * @var TIMER_T::PWMCMPBUF 483 * Offset: 0x74 Timer PWM Comparator Buffer Register 484 * --------------------------------------------------------------------------------------------------- 485 * |Bits |Field |Descriptions 486 * | :----: | :----: | :---- | 487 * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only) 488 * | | |Used as CMP active register. 489 * @var TIMER_T::PWMIFA 490 * Offset: 0xA8 Timer PWM Interrupt Flag Accumulator Register 491 * --------------------------------------------------------------------------------------------------- 492 * |Bits |Field |Descriptions 493 * | :----: | :----: | :---- | 494 * |[15:0] |IFACNT |PWM Interrupt Flag Accumulator Counter 495 * | | |This field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. 496 * | | |PWM accumulator flag (IFAIF) will be set in every (IFACNT+1) times during the the PWM counter operation. 497 * |[24] |STPMOD |PWM Accumulator Stop Mode Enable Bit 498 * | | |0 = PWM interrupt accumulator event to stop counting Disabled. 499 * | | |1 = PWM interrupt accumulator event to stop counting Enabled. 500 * |[29:28] |IFASEL |PWM Interrupt Flag Accumulator Source Select 501 * | | |01 = Accumulate at each PWM period point. 502 * | | |10 = Accumulate at each PWM up-count compared point. 503 * |[31] |IFAEN |PWM Interrupt Flag Accumulator Enable Bit 504 * | | |0 = PWM interrupt flag accumulator function Disabled. 505 * | | |1 = PWM interrupt flag accumulator function Enabled. 506 * @var TIMER_T::PWMAINTSTS 507 * Offset: 0xAC Timer PWM Accumulator Interrupt Flag Register 508 * --------------------------------------------------------------------------------------------------- 509 * |Bits |Field |Descriptions 510 * | :----: | :----: | :---- | 511 * |[0] |IFAIF |PWM Interrupt Flag Accumulator Interrupt Flag 512 * | | |This bit is set by hardware when the accumulator value reaches (IFACNT+1) 513 * | | |Note 1: This bit is cleared by writing 1 to it. 514 * | | |Note 2: If APDMAEN (TIMERx_PWMAPDMACTL[0]) is set, this bit will be auto clear after PDMA transfer done. 515 * @var TIMER_T::PWMAINTEN 516 * Offset: 0xB0 Timer PWM Accumulator Interrupt Enable Register 517 * --------------------------------------------------------------------------------------------------- 518 * |Bits |Field |Descriptions 519 * | :----: | :----: | :---- | 520 * |[0] |IFAIEN |PWM Interrupt Flag Accumulator Interrupt Enable Bit 521 * | | |0 = Interrupt Flag Accumulator interrupt Disabled. 522 * | | |1 = Interrupt Flag Accumulator interrupt Enabled. 523 * @var TIMER_T::PWMAPDMACTL 524 * Offset: 0xB4 Timer PWM Accumulator PDMA Control Register 525 * --------------------------------------------------------------------------------------------------- 526 * |Bits |Field |Descriptions 527 * | :----: | :----: | :---- | 528 * |[0] |APDMAEN |PWM Accumulator PDMA Enable Bit 529 * | | |0 = PWM interrupt accumulator event to trigger PDMA transfer Disabled. 530 * | | |1 = PWM interrupt accumulator event to trigger PDMA transfer Enabled. 531 */ 532 __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */ 533 __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */ 534 __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */ 535 __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */ 536 __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */ 537 __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */ 538 __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */ 539 __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */ 540 __I uint32_t RESERVE0[1]; 541 __IO uint32_t CAPNF; /*!< [0x0024] Timer Capture Input Noise Filter Register */ 542 __I uint32_t RESERVE1[6]; 543 __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */ 544 __IO uint32_t PWMCLKPSC; /*!< [0x0044] Timer PWM Counter Clock Pre-scale Register */ 545 __IO uint32_t PWMCNTCLR; /*!< [0x0048] Timer PWM Clear Counter Register */ 546 __IO uint32_t PWMPERIOD; /*!< [0x004c] Timer PWM Period Register */ 547 __IO uint32_t PWMCMPDAT; /*!< [0x0050] Timer PWM Comparator Register */ 548 __I uint32_t PWMCNT; /*!< [0x0054] Timer PWM Counter Register */ 549 __IO uint32_t PWMPOLCTL; /*!< [0x0058] Timer PWM Pin Output Polar Control Register */ 550 __IO uint32_t PWMPOCTL; /*!< [0x005c] Timer PWM Pin Output Control Register */ 551 __IO uint32_t PWMINTEN0; /*!< [0x0060] Timer PWM Interrupt Enable Register 0 */ 552 __IO uint32_t PWMINTSTS0; /*!< [0x0064] Timer PWM Interrupt Status Register 0 */ 553 __IO uint32_t PWMTRGCTL; /*!< [0x0068] Timer PWM Trigger Control Register */ 554 __IO uint32_t PWMSTATUS; /*!< [0x006c] Timer PWM Status Register */ 555 __I uint32_t PWMPBUF; /*!< [0x0070] Timer PWM Period Buffer Register */ 556 __I uint32_t PWMCMPBUF; /*!< [0x0074] Timer PWM Comparator Buffer Register */ 557 __I uint32_t RESERVE2[12]; 558 __IO uint32_t PWMIFA; /*!< [0x00a8] Timer PWM Interrupt Flag Accumulator Register */ 559 __IO uint32_t PWMAINTSTS; /*!< [0x00ac] Timer PWM Accumulator Interrupt Flag Register */ 560 __IO uint32_t PWMAINTEN; /*!< [0x00b0] Timer PWM Accumulator Interrupt Enable Register */ 561 __IO uint32_t PWMAPDMACTL; /*!< [0x00b4] Timer PWM Accumulator PDMA Control Register */ 562 563 } TIMER_T; 564 565 /** 566 @addtogroup TIMER_CONST TIMER Bit Field Definition 567 Constant Definitions for TIMER Controller 568 @{ */ 569 570 #define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */ 571 #define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */ 572 573 #define TIMER_CTL_FUNCSEL_Pos (15) /*!< TIMER_T::CTL: FUNCSEL Position */ 574 #define TIMER_CTL_FUNCSEL_Msk (0x1ul << TIMER_CTL_FUNCSEL_Pos) /*!< TIMER_T::CTL: FUNCSEL Mask */ 575 576 #define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */ 577 #define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */ 578 579 #define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */ 580 #define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */ 581 582 #define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */ 583 #define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */ 584 585 #define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */ 586 #define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */ 587 588 #define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */ 589 #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */ 590 591 #define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */ 592 #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */ 593 594 #define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */ 595 #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */ 596 597 #define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */ 598 #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */ 599 600 #define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */ 601 #define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */ 602 603 #define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */ 604 #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */ 605 606 #define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */ 607 #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */ 608 609 #define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */ 610 #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */ 611 612 #define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */ 613 #define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */ 614 615 #define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */ 616 #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */ 617 618 #define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */ 619 #define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */ 620 621 #define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */ 622 #define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */ 623 624 #define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */ 625 #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */ 626 627 #define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */ 628 #define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */ 629 630 #define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */ 631 #define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */ 632 633 #define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */ 634 #define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */ 635 636 #define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */ 637 #define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */ 638 639 #define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */ 640 #define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */ 641 642 #define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */ 643 #define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */ 644 645 #define TIMER_EXTCTL_INTERCAPSEL_Pos (8) /*!< TIMER_T::EXTCTL: INTERCAPSEL Position */ 646 #define TIMER_EXTCTL_INTERCAPSEL_Msk (0x7ul << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< TIMER_T::EXTCTL: INTERCAPSEL Mask */ 647 648 #define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */ 649 #define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */ 650 651 #define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */ 652 #define TIMER_EXTCTL_ECNTSSEL_Msk (0x7ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */ 653 654 #define TIMER_EXTCTL_CAPDIVSCL_Pos (28) /*!< TIMER_T::EXTCTL: CAPDIVSCL Position */ 655 #define TIMER_EXTCTL_CAPDIVSCL_Msk (0xful << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< TIMER_T::EXTCTL: CAPDIVSCL Mask */ 656 657 #define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */ 658 #define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */ 659 660 #define TIMER_EINTSTS_CAPIFOV_Pos (1) /*!< TIMER_T::EINTSTS: CAPIFOV Position */ 661 #define TIMER_EINTSTS_CAPIFOV_Msk (0x1ul << TIMER_EINTSTS_CAPIFOV_Pos) /*!< TIMER_T::EINTSTS: CAPIFOV Mask */ 662 663 #define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */ 664 #define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */ 665 666 #define TIMER_TRGCTL_TRGPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGPWM Position */ 667 #define TIMER_TRGCTL_TRGPWM_Msk (0x1ul << TIMER_TRGCTL_TRGPWM_Pos) /*!< TIMER_T::TRGCTL: TRGPWM Mask */ 668 669 #define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */ 670 #define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */ 671 672 #define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */ 673 #define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */ 674 675 #define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */ 676 #define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */ 677 678 #define TIMER_TRGCTL_TRGLPADC_Pos (5) /*!< TIMER_T::TRGCTL: TRGLPADC Position */ 679 #define TIMER_TRGCTL_TRGLPADC_Msk (0x1ul << TIMER_TRGCTL_TRGLPADC_Pos) /*!< TIMER_T::TRGCTL: TRGLPADC Mask */ 680 681 #define TIMER_TRGCTL_TGTKEN_Pos (8) /*!< TIMER_T::TRGCTL: TGTKEN Position */ 682 #define TIMER_TRGCTL_TGTKEN_Msk (0x1ul << TIMER_TRGCTL_TGTKEN_Pos) /*!< TIMER_T::TRGCTL: TGTKEN Mask */ 683 684 #define TIMER_CAPNF_CAPNFEN_Pos (0) /*!< TIMER_T::CAPNF: CAPNFEN Position */ 685 #define TIMER_CAPNF_CAPNFEN_Msk (0x1ul << TIMER_CAPNF_CAPNFEN_Pos) /*!< TIMER_T::CAPNF: CAPNFEN Mask */ 686 687 #define TIMER_CAPNF_CAPNFSEL_Pos (4) /*!< TIMER_T::CAPNF: CAPNFSEL Position */ 688 #define TIMER_CAPNF_CAPNFSEL_Msk (0x7ul << TIMER_CAPNF_CAPNFSEL_Pos) /*!< TIMER_T::CAPNF: CAPNFSEL Mask */ 689 690 #define TIMER_CAPNF_CAPNFCNT_Pos (8) /*!< TIMER_T::CAPNF: CAPNFCNT Position */ 691 #define TIMER_CAPNF_CAPNFCNT_Msk (0x7ul << TIMER_CAPNF_CAPNFCNT_Pos) /*!< TIMER_T::CAPNF: CAPNFCNT Mask */ 692 693 #define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */ 694 #define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */ 695 696 #define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */ 697 #define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */ 698 699 #define TIMER_PWMCTL_PWMINTWKEN_Pos (12) /*!< TIMER_T::PWMCTL: PWMINTWKEN Position */ 700 #define TIMER_PWMCTL_PWMINTWKEN_Msk (0x1ul << TIMER_PWMCTL_PWMINTWKEN_Pos) /*!< TIMER_T::PWMCTL: PWMINTWKEN Mask */ 701 702 #define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */ 703 #define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */ 704 705 #define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */ 706 #define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */ 707 708 #define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */ 709 #define TIMER_PWMCLKPSC_CLKPSC_Msk (0xfful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */ 710 711 #define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */ 712 #define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */ 713 714 #define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */ 715 #define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */ 716 717 #define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */ 718 #define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */ 719 720 #define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */ 721 #define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */ 722 723 #define TIMER_PWMPOLCTL_PINV_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV Position */ 724 #define TIMER_PWMPOLCTL_PINV_Msk (0x1ul << TIMER_PWMPOLCTL_PINV_Pos) /*!< TIMER_T::PWMPOLCTL: PINV Mask */ 725 726 #define TIMER_PWMPOCTL_POEN_Pos (0) /*!< TIMER_T::PWMPOCTL: POEN Position */ 727 #define TIMER_PWMPOCTL_POEN_Msk (0x1ul << TIMER_PWMPOCTL_POEN_Pos) /*!< TIMER_T::PWMPOCTL: POEN Mask */ 728 729 #define TIMER_PWMPOCTL_POSEL_Pos (8) /*!< TIMER_T::PWMPOCTL: POSEL Position */ 730 #define TIMER_PWMPOCTL_POSEL_Msk (0x1ul << TIMER_PWMPOCTL_POSEL_Pos) /*!< TIMER_T::PWMPOCTL: POSEL Mask */ 731 732 #define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */ 733 #define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */ 734 735 #define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */ 736 #define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */ 737 738 #define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */ 739 #define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */ 740 741 #define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */ 742 #define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */ 743 744 #define TIMER_PWMTRGCTL_TRGSEL_Pos (0) /*!< TIMER_T::PWMTRGCTL: TRGSEL Position */ 745 #define TIMER_PWMTRGCTL_TRGSEL_Msk (0x3ul << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< TIMER_T::PWMTRGCTL: TRGSEL Mask */ 746 747 #define TIMER_PWMTRGCTL_PWMTRGEADC_Pos (7) /*!< TIMER_T::PWMTRGCTL: PWMTRGEADC Position*/ 748 #define TIMER_PWMTRGCTL_PWMTRGEADC_Msk (0x1ul << TIMER_PWMTRGCTL_PWMTRGEADC_Pos) /*!< TIMER_T::PWMTRGCTL: PWMTRGEADC Mask */ 749 750 #define TIMER_PWMTRGCTL_PWMTRGDAC_Pos (8) /*!< TIMER_T::PWMTRGCTL: PWMTRGDAC Position */ 751 #define TIMER_PWMTRGCTL_PWMTRGDAC_Msk (0x1ul << TIMER_PWMTRGCTL_PWMTRGDAC_Pos) /*!< TIMER_T::PWMTRGCTL: PWMTRGDAC Mask */ 752 753 #define TIMER_PWMTRGCTL_PWMTRGPDMA_Pos (9) /*!< TIMER_T::PWMTRGCTL: PWMTRGPDMA Position*/ 754 #define TIMER_PWMTRGCTL_PWMTRGPDMA_Msk (0x1ul << TIMER_PWMTRGCTL_PWMTRGPDMA_Pos) /*!< TIMER_T::PWMTRGCTL: PWMTRGPDMA Mask */ 755 756 #define TIMER_PWMTRGCTL_PWMTRGLPADC_Pos (10) /*!< TIMER_T::PWMTRGCTL: PWMTRGLPADC Position*/ 757 #define TIMER_PWMTRGCTL_PWMTRGLPADC_Msk (0x1ul << TIMER_PWMTRGCTL_PWMTRGLPADC_Pos) /*!< TIMER_T::PWMTRGCTL: PWMTRGLPADC Mask */ 758 759 #define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */ 760 #define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */ 761 762 #define TIMER_PWMSTATUS_PWMINTWKF_Pos (8) /*!< TIMER_T::PWMSTATUS: PWMINTWKF Position */ 763 #define TIMER_PWMSTATUS_PWMINTWKF_Msk (0x1ul << TIMER_PWMSTATUS_PWMINTWKF_Pos) /*!< TIMER_T::PWMSTATUS: PWMINTWKF Mask */ 764 765 #define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */ 766 #define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */ 767 768 #define TIMER_PWMSTATUS_DACTRGF_Pos (17) /*!< TIMER_T::PWMSTATUS: DACTRGF Position */ 769 #define TIMER_PWMSTATUS_DACTRGF_Msk (0x1ul << TIMER_PWMSTATUS_DACTRGF_Pos) /*!< TIMER_T::PWMSTATUS: DACTRGF Mask */ 770 771 #define TIMER_PWMSTATUS_PDMATRGF_Pos (18) /*!< TIMER_T::PWMSTATUS: PDMATRGF Position */ 772 #define TIMER_PWMSTATUS_PDMATRGF_Msk (0x1ul << TIMER_PWMSTATUS_PDMATRGF_Pos) /*!< TIMER_T::PWMSTATUS: PDMATRGF Mask */ 773 774 #define TIMER_PWMSTATUS_LPADCTRGF_Pos (19) /*!< TIMER_T::PWMSTATUS: LPADCTRGF Position */ 775 #define TIMER_PWMSTATUS_LPADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_LPADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: LPADCTRGF Mask */ 776 777 #define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */ 778 #define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */ 779 780 #define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */ 781 #define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */ 782 783 #define TIMER_PWMIFA_IFACNT_Pos (0) /*!< TIMER_T::PWMIFA: IFACNT Position */ 784 #define TIMER_PWMIFA_IFACNT_Msk (0xfffful << TIMER_PWMIFA_IFACNT_Pos) /*!< TIMER_T::PWMIFA: IFACNT Mask */ 785 786 #define TIMER_PWMIFA_STPMOD_Pos (24) /*!< TIMER_T::PWMIFA: STPMOD Position */ 787 #define TIMER_PWMIFA_STPMOD_Msk (0x1ul << TIMER_PWMIFA_STPMOD_Pos) /*!< TIMER_T::PWMIFA: STPMOD Mask */ 788 789 #define TIMER_PWMIFA_IFASEL_Pos (28) /*!< TIMER_T::PWMIFA: IFASEL Position */ 790 #define TIMER_PWMIFA_IFASEL_Msk (0x3ul << TIMER_PWMIFA_IFASEL_Pos) /*!< TIMER_T::PWMIFA: IFASEL Mask */ 791 792 #define TIMER_PWMIFA_IFAEN_Pos (31) /*!< TIMER_T::PWMIFA: IFAEN Position */ 793 #define TIMER_PWMIFA_IFAEN_Msk (0x1ul << TIMER_PWMIFA_IFAEN_Pos) /*!< TIMER_T::PWMIFA: IFAEN Mask */ 794 795 #define TIMER_PWMAINTSTS_IFAIF_Pos (0) /*!< TIMER_T::PWMAINTSTS: IFAIF Position */ 796 #define TIMER_PWMAINTSTS_IFAIF_Msk (0x1ul << TIMER_PWMAINTSTS_IFAIF_Pos) /*!< TIMER_T::PWMAINTSTS: IFAIF Mask */ 797 798 #define TIMER_PWMAINTEN_IFAIEN_Pos (0) /*!< TIMER_T::PWMAINTEN: IFAIEN Position */ 799 #define TIMER_PWMAINTEN_IFAIEN_Msk (0x1ul << TIMER_PWMAINTEN_IFAIEN_Pos) /*!< TIMER_T::PWMAINTEN: IFAIEN Mask */ 800 801 #define TIMER_PWMAPDMACTL_APDMAEN_Pos (0) /*!< TIMER_T::PWMAPDMACTL: APDMAEN Position */ 802 #define TIMER_PWMAPDMACTL_APDMAEN_Msk (0x1ul << TIMER_PWMAPDMACTL_APDMAEN_Pos) /*!< TIMER_T::PWMAPDMACTL: APDMAEN Mask */ 803 804 /**@}*/ /* TIMER_CONST */ 805 /**@}*/ /* end of TIMER register group */ 806 /**@}*/ /* end of REGISTER group */ 807 808 #if defined ( __CC_ARM ) 809 #pragma no_anon_unions 810 #endif 811 812 #endif /* __TIMER_REG_H__ */ 813
