1 /*! 2 \file gd32a50x_syscfg.h 3 \brief definitions for the SYSCFG 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50x 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32A50X_SYSCFG_H 36 #define GD32A50X_SYSCFG_H 37 38 #include "gd32a50x.h" 39 40 /* SYSCFG definitions */ 41 #define SYSCFG SYSCFG_BASE 42 43 /* registers definitions */ 44 #define SYSCFG_CFG0 REG32(SYSCFG + 0x00000000U) /*!< system configuration register 0 */ 45 #define SYSCFG_CFG1 REG32(SYSCFG + 0x00000004U) /*!< system configuration register 1 */ 46 #define SYSCFG_EXTISS0 REG32(SYSCFG + 0x00000008U) /*!< EXTI sources selection register 0 */ 47 #define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0000000CU) /*!< EXTI sources selection register 1 */ 48 #define SYSCFG_EXTISS2 REG32(SYSCFG + 0x00000010U) /*!< EXTI sources selection register 2 */ 49 #define SYSCFG_EXTISS3 REG32(SYSCFG + 0x00000014U) /*!< EXTI sources selection register 3 */ 50 #define SYSCFG_CFG2 REG32(SYSCFG + 0x00000018U) /*!< system configuration register 2 */ 51 #define SYSCFG_STAT REG32(SYSCFG + 0x0000001CU) /*!< system status register */ 52 #define SYSCFG_CFG3 REG32(SYSCFG + 0x00000028U) /*!< system configuration register 3 */ 53 #define SYSCFG_TIMERINSEL REG32(SYSCFG + 0x0000002CU) /*!< TIMER input source selection register */ 54 55 /* bits definitions */ 56 /* SYSCFG_CFG0 */ 57 #define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap configuration */ 58 #define SYSCFG_CFG0_PA9_PA12_RMP BIT(4) /*!< PA9 and PA12 remapping bit for small packages (32 pins) */ 59 #define SYSCFG_CFG0_BOOT0_PF0_RMP BIT(6) /*!< BOOT0 and PF0 remapping bit */ 60 61 /* SYSCFG_CFG1 */ 62 #define SYSCFG_CFG1_ADC1CH14RMP BIT(28) /*!< ADC1 channel 14 remapping bit */ 63 #define SYSCFG_CFG1_ADC1CH15RMP BIT(29) /*!< ADC1 channel 15 remapping bit */ 64 #define SYSCFG_CFG1_ADC0CH8RMP BIT(30) /*!< ADC0 channel 8 remapping bit */ 65 #define SYSCFG_CFG1_ADC0CH9RMP BIT(31) /*!< ADC0 channel 9 remapping bit */ 66 67 /* SYSCFG_EXTISS0 */ 68 #define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */ 69 #define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */ 70 #define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */ 71 #define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */ 72 73 /* SYSCFG_EXTISS1 */ 74 #define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */ 75 #define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */ 76 #define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */ 77 #define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */ 78 79 /* SYSCFG_EXTISS2 */ 80 #define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */ 81 #define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */ 82 #define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */ 83 #define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */ 84 85 /* SYSCFG_EXTISS3 */ 86 #define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */ 87 #define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */ 88 #define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */ 89 #define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */ 90 91 /* SSYSCFG_CFG2 */ 92 #define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< Cortex-M33 LOCKUP output lock bit */ 93 #define SYSCFG_CFG2_SRAM_ECC_ERROR_LOCK BIT(1) /*!< SRAM ECC check error lock bit */ 94 #define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< LVD lock bit */ 95 96 /* SYSCFG_STAT */ 97 #define SYSCFG_STAT_SRAMECCMEIF BIT(0) /*!< SRAM multi-bits non-correction event flag */ 98 #define SYSCFG_STAT_SRAMECCSEIF BIT(1) /*!< SRAM single bit correction event flag */ 99 #define SYSCFG_STAT_FLASHECCIF BIT(2) /*!< Flash ECC NMI interrupt flag */ 100 #define SYSCFG_STAT_CKMNMIIF BIT(3) /*!< HXTAL clock moniotor NMI interrupt flag */ 101 #define SYSCFG_STAT_NMIPINIF BIT(4) /*!< NMI interrupt flag from nmi pin */ 102 103 /* SSYSCFG_CFG3 */ 104 #define SYSCFG_CFG3_SRAMECCMEIE BIT(0) /*!< SRAM multi-bits non-correction NMI interrupt enable */ 105 #define SYSCFG_CFG3_SRAMECCSEIE BIT(1) /*!< SRAM single bit correction interrupt enable */ 106 #define SYSCFG_CFG3_FLASHECCIE BIT(2) /*!< Flash ECC NMI interrupt enable */ 107 #define SYSCFG_CFG3_CKMNMIIE BIT(3) /*!< HXTAL clock moniotor NMI interrupt enable */ 108 #define SYSCFG_CFG3_NMIPINIE BIT(4) /*!< NMI pin interrupt enable */ 109 #define SYSCFG_CFG3_SRAMECCSERRBITS BITS(12,17) /*!< which one bit has an SRAM ECC single-bit correctable error */ 110 #define SYSCFG_CFG3_SRAMECCEADDR BITS(18,31) /*!< record the faulting system address (Address[15:0] >> 2) where the last SRAM ECC event on SRAM occurred. */ 111 112 /* SYSCFG_TIMERINSEL */ 113 #define SYSCFG_TIMERINSEL_TIMER7_CH0N_SEL BIT(0) /*!< TIMER7 channel 0 complementary input selection */ 114 #define SYSCFG_TIMERINSEL_TIMER20_BKIN3_SEL BIT(2) /*!< TIMER20 break input 3 selection */ 115 #define SYSCFG_TIMERINSEL_TIMER20_BKIN2_SEL BIT(3) /*!< TIMER20 break input 2 selection */ 116 #define SYSCFG_TIMERINSEL_TIMER20_BKIN1_SEL BIT(4) /*!< TIMER20 break input 1 selection */ 117 #define SYSCFG_TIMERINSEL_TIMER20_BKIN0_SEL BIT(5) /*!< TIMER20 break input 0 selection */ 118 #define SYSCFG_TIMERINSEL_TIMER19_BKIN3_SEL BIT(6) /*!< TIMER19 break input 3 selection */ 119 #define SYSCFG_TIMERINSEL_TIMER19_BKIN2_SEL BIT(7) /*!< TIMER19 break input 2 selection */ 120 #define SYSCFG_TIMERINSEL_TIMER19_BKIN1_SEL BIT(8) /*!< TIMER19 break input 1 selection */ 121 #define SYSCFG_TIMERINSEL_TIMER19_BKIN0_SEL BIT(9) /*!< TIMER19 break input 0 selection */ 122 #define SYSCFG_TIMERINSEL_TIMER7_BKIN3_SEL BIT(14) /*!< TIMER7 break input 3 selection */ 123 #define SYSCFG_TIMERINSEL_TIMER7_BKIN2_SEL BIT(15) /*!< TIMER7 break input 2 selection */ 124 #define SYSCFG_TIMERINSEL_TIMER7_BKIN1_SEL BIT(16) /*!< TIMER7 break input 1 selection */ 125 #define SYSCFG_TIMERINSEL_TIMER7_BKIN0_SEL BIT(17) /*!< TIMER7 break input 0 selection */ 126 #define SYSCFG_TIMERINSEL_TIMER0_BKIN3_SEL BIT(18) /*!< TIMER0 break input 3 selection */ 127 #define SYSCFG_TIMERINSEL_TIMER0_BKIN2_SEL BIT(19) /*!< TIMER0 break input 2 selection */ 128 #define SYSCFG_TIMERINSEL_TIMER0_BKIN1_SEL BIT(20) /*!< TIMER0 break input 1 selection */ 129 #define SYSCFG_TIMERINSEL_TIMER0_BKIN0_SEL BIT(21) /*!< TIMER0 break input 0 selection */ 130 #define SYSCFG_TIMERINSEL_TIMER20_ETI_SEL BITS(22,23) /*!< TIMER20 external trigger selection */ 131 #define SYSCFG_TIMERINSEL_TIMER19_ETI_SEL BITS(24,25) /*!< TIMER19 external trigger selection */ 132 #define SYSCFG_TIMERINSEL_TIMER7_ETI_SEL BITS(28,29) /*!< TIMER7 external trigger selection */ 133 #define SYSCFG_TIMERINSEL_TIMER0_ETI_SEL BITS(30,31) /*!< TIMER0 external trigger selection */ 134 135 /* constants definitions */ 136 /* boot mode definitions */ 137 #define SYSCFG_BOOTMODE_FLASH ((uint8_t)0x00U) /*!< boot from main flash */ 138 #define SYSCFG_BOOTMODE_SYSTEM ((uint8_t)0x01U) /*!< boot from system flash memory */ 139 #define SYSCFG_BOOTMODE_SRAM ((uint8_t)0x03U) /*!< boot from embedded SRAM */ 140 141 /* PA9/PA12 remap definitions */ 142 #define SYSCFG_PA9_PA12_REMAP SYSCFG_CFG0_PA9_PA12_RMP /*!< PA9/PA12 pins are mapping on PA10/PA11 pins */ 143 144 /* PF0/BOOT0 remap definitions */ 145 #define SYSCFG_BOOT0_REMAP_PF0 SYSCFG_CFG0_BOOT0_PF0_RMP /*!< PF0 pin is mapping on the BOOT0 pin */ 146 147 /* EXTI source select definition */ 148 #define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */ 149 #define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */ 150 #define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */ 151 #define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */ 152 153 /* EXTI source select mask bits definition */ 154 #define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ 155 156 /* EXTI source select jumping step definition */ 157 #define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */ 158 159 /* EXTI source select moving step definition */ 160 #define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ 161 162 /* EXTI source port definitions */ 163 #define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ 164 #define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */ 165 #define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */ 166 #define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */ 167 #define EXTI_SOURCE_GPIOE ((uint8_t)0x04U) /*!< EXTI GPIOE configuration */ 168 #define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */ 169 170 /* EXTI source pin definitions */ 171 #define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */ 172 #define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */ 173 #define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */ 174 #define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */ 175 #define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */ 176 #define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */ 177 #define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */ 178 #define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */ 179 #define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */ 180 #define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */ 181 #define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */ 182 #define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */ 183 #define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */ 184 #define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */ 185 #define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */ 186 #define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ 187 188 /* lock definitions */ 189 #define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */ 190 #define SYSCFG_LOCK_SRAM_ECC_ERROR SYSCFG_CFG2_SRAM_ECC_ERROR_LOCK /*!< SRAM ECC error lock */ 191 #define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */ 192 193 /* TIMER external trigger definitions */ 194 #define TIMER_ETI_TRG0 ((uint8_t)0x00U) /*!< TIMER external trigger 0 */ 195 #define TIMER_ETI_TRG1 ((uint8_t)0x01U) /*!< TIMER external trigger 1 */ 196 #define TIMER_ETI_TRG2 ((uint8_t)0x02U) /*!< TIMER external trigger 2 */ 197 #define TIMER_ETI_TRG_NONE ((uint8_t)0x03U) /*!< do not seclet TIMER external trigger source */ 198 199 /* TIMERx break input y */ 200 #define TIMER20_BKIN3_TRIG SYSCFG_TIMERINSEL_TIMER20_BKIN3_SEL /*!< TIMER20 break input 3 selection */ 201 #define TIMER20_BKIN2_TRIG SYSCFG_TIMERINSEL_TIMER20_BKIN2_SEL /*!< TIMER20 break input 2 selection */ 202 #define TIMER20_BKIN1_TRIG SYSCFG_TIMERINSEL_TIMER20_BKIN1_SEL /*!< TIMER20 break input 1 selection */ 203 #define TIMER20_BKIN0_TRIG SYSCFG_TIMERINSEL_TIMER20_BKIN0_SEL /*!< TIMER20 break input 0 selection */ 204 #define TIMER19_BKIN3_TRIG SYSCFG_TIMERINSEL_TIMER19_BKIN3_SEL /*!< TIMER19 break input 3 selection */ 205 #define TIMER19_BKIN2_TRIG SYSCFG_TIMERINSEL_TIMER19_BKIN2_SEL /*!< TIMER19 break input 2 selection */ 206 #define TIMER19_BKIN1_TRIG SYSCFG_TIMERINSEL_TIMER19_BKIN1_SEL /*!< TIMER19 break input 1 selection */ 207 #define TIMER19_BKIN0_TRIG SYSCFG_TIMERINSEL_TIMER19_BKIN0_SEL /*!< TIMER19 break input 0 selection */ 208 #define TIMER7_BKIN3_TRIG SYSCFG_TIMERINSEL_TIMER7_BKIN3_SEL /*!< TIMER7 break input 3 selection */ 209 #define TIMER7_BKIN2_TRIG SYSCFG_TIMERINSEL_TIMER7_BKIN2_SEL /*!< TIMER7 break input 2 selection */ 210 #define TIMER7_BKIN1_TRIG SYSCFG_TIMERINSEL_TIMER7_BKIN1_SEL /*!< TIMER7 break input 1 selection */ 211 #define TIMER7_BKIN0_TRIG SYSCFG_TIMERINSEL_TIMER7_BKIN0_SEL /*!< TIMER7 break input 0 selection */ 212 #define TIMER0_BKIN3_TRIG SYSCFG_TIMERINSEL_TIMER0_BKIN3_SEL /*!< TIMER0 break input 3 selection */ 213 #define TIMER0_BKIN2_TRIG SYSCFG_TIMERINSEL_TIMER0_BKIN2_SEL /*!< TIMER0 break input 2 selection */ 214 #define TIMER0_BKIN1_TRIG SYSCFG_TIMERINSEL_TIMER0_BKIN1_SEL /*!< TIMER0 break input 1 selection */ 215 #define TIMER0_BKIN0_TRIG SYSCFG_TIMERINSEL_TIMER0_BKIN0_SEL /*!< TIMER0 break input 0 selection */ 216 217 /* TIMER7 channel0 complementary input source definitions */ 218 #define TIMER7CH0N_TIMER7CH0_TIMER0CH0_IN SYSCFG_TIMERINSEL_TIMER7_CH0N_SEL /*!< exclusive or of TIMER7_CH0_IN,TIMER7_CH0N_IN,and TIMER0_CH0_IN */ 219 #define TIMER7_CH0N_IN (~SYSCFG_TIMERINSEL_TIMER7_CH0N_SEL) /*!< TIMER7_CH0N_IN */ 220 221 /* SYSCFG flag definitions */ 222 #define SYSCFG_FLAG_SRAMECCMERR SYSCFG_STAT_SRAMECCMEIF /*!< SRAM multi-bits non-correction ECC error flag */ 223 #define SYSCFG_FLAG_SRAMECCSERR SYSCFG_STAT_SRAMECCSEIF /*!< SRAM single bit correction ECC error flag */ 224 #define SYSCFG_FLAG_FLASHECCERR SYSCFG_STAT_FLASHECCIF /*!< FLASH ECC NMI error flag */ 225 #define SYSCFG_FLAG_CKMNMIERR SYSCFG_STAT_CKMNMIIF /*!< HXTAL clock monitor NMI error flag */ 226 #define SYSCFG_FLAG_NMIPINERR SYSCFG_STAT_NMIPINIF /*!< NMI pin error flag */ 227 228 /* SYSCFG interrupt flag constants definitions */ 229 #define SYSCFG_INT_FLAG_SRAMECCMERR SYSCFG_STAT_SRAMECCMEIF /*!< SRAM multi-bits non-correction ECC error interrupt flag */ 230 #define SYSCFG_INT_FLAG_SRAMECCSERR SYSCFG_STAT_SRAMECCSEIF /*!< SRAM single bit correction ECC error interrupt flag */ 231 #define SYSCFG_INT_FLAG_FLASHECCERR SYSCFG_STAT_FLASHECCIF /*!< FLASH ECC NMI error interrupt flag */ 232 #define SYSCFG_INT_FLAG_CKMNMIERR SYSCFG_STAT_CKMNMIIF /*!< HXTAL clock monitor NMI error interrupt flag */ 233 #define SYSCFG_INT_FLAG_NMIPINERR SYSCFG_STAT_NMIPINIF /*!< NMI pin error interrupt flag */ 234 235 /* SYSCFG interrupt enable/disable constants definitions */ 236 #define SYSCFG_INT_SRAMECCME SYSCFG_CFG3_SRAMECCMEIE /*!< SRAM multi-bits non-correction ECC error */ 237 #define SYSCFG_INT_SRAMECCSE SYSCFG_CFG3_SRAMECCSEIE /*!< SRAM single bit correction ECC error */ 238 #define SYSCFG_INT_FLASHECCE SYSCFG_CFG3_FLASHECCIE /*!< FLASH ECC NMI error */ 239 #define SYSCFG_INT_CKMNMI SYSCFG_CFG3_CKMNMIIE /*!< receive buffer not empty interrupt */ 240 #define SYSCFG_INT_NMIPIN SYSCFG_CFG3_NMIPINIE /*!< HXTAL clock monitor NMI error */ 241 242 typedef enum { 243 ADC1_IN14_REMAP = 1, /*!< ADC1 channel 14 remapping */ 244 ADC1_IN15_REMAP, /*!< ADC1 channel 15 remapping */ 245 ADC0_IN8_REMAP, /*!< ADC0 channel 8 remapping */ 246 ADC0_IN9_REMAP /*!< ADC0 channel 9 remapping */ 247 } syscfg_adcx_chy_enum; 248 249 typedef enum { 250 TIMER0SEL = 1, /*!< select TIMER0 */ 251 TIMER7SEL, /*!< select TIMER7 */ 252 TIMER19SEL, /*!< select TIMER19 */ 253 TIMER20SEL, /*!< select TIMER20 */ 254 } syscfg_timersel_enum; 255 256 /* function declarations */ 257 /* initialization functions */ 258 /* reset the SYSCFG registers */ 259 void syscfg_deinit(void); 260 261 /* configure the GPIO pin as EXTI Line */ 262 void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); 263 264 /* enable remap pin function */ 265 void syscfg_pin_remap_enable(uint32_t remap_pin); 266 /* disable remap pin function */ 267 void syscfg_pin_remap_disable(uint32_t remap_pin); 268 /* configure ADC channel GPIO pin remap function */ 269 void syscfg_adc_ch_remap_config(syscfg_adcx_chy_enum adcx_iny_remap, ControlStatus newvalue); 270 271 /* select TIMER external trigger source */ 272 void syscfg_timer_eti_sel(syscfg_timersel_enum timer_num, uint32_t eti_num); 273 /* select TRIGSEL as TIMER break input source */ 274 void syscfg_timer_bkin_select_trigsel(uint32_t bkin_source); 275 /* select GPIO as TIMER break input source */ 276 void syscfg_timer_bkin_select_gpio(uint32_t bkin_source); 277 /* select TIMER7 channel0 complementary input source */ 278 void syscfg_timer7_ch0n_select(uint32_t timer7_ch0n_in); 279 280 /* configure TIMER0/7/19/20 break input to the selected parameter connection */ 281 void syscfg_lock_config(uint32_t syscfg_lock); 282 283 /* flag and interrupt functions */ 284 /* get SYSCFG flags */ 285 FlagStatus syscfg_flag_get(uint32_t syscfg_flag); 286 /* clear SYSCFG flags */ 287 void syscfg_flag_clear(uint32_t syscfg_flag); 288 /* enable SYSCFG interrupts */ 289 void syscfg_interrupt_enable(uint32_t interrupt); 290 /* disable SYSCFG interrupts */ 291 void syscfg_interrupt_disable(uint32_t interrupt); 292 /* get SYSCFG interrupt flag status */ 293 FlagStatus syscfg_interrupt_flag_get(uint32_t interrupt); 294 /* get the current boot mode */ 295 uint8_t syscfg_bootmode_get(void); 296 /* get the address where SRAM ECC error occur on */ 297 uint16_t syscfg_sram_ecc_address_get(void); 298 /* get the bit which has SRAM ECC signle error */ 299 uint8_t syscfg_sram_ecc_bit_get(void); 300 301 #endif /* GD32A50X_SYSCFG_H */ 302
