1 /**************************************************************************//** 2 * @file M480.h 3 * @version V1.00 4 * @brief M480 peripheral access layer header file. 5 * This file contains all the peripheral register's definitions, 6 * bits definitions and memory mapping for NuMicro M480 MCU. 7 * 8 * SPDX-License-Identifier: Apache-2.0 9 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 10 *****************************************************************************/ 11 /** 12 \mainpage NuMicro M480 Driver Reference Guide 13 * 14 * <b>Introduction</b> 15 * 16 * This user manual describes the usage of M480 Series MCU device driver 17 * 18 * <b>Disclaimer</b> 19 * 20 * The Software is furnished "AS IS", without warranty as to performance or results, and 21 * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all 22 * warranties, express, implied or otherwise, with regard to the Software, its use, or 23 * operation, including without limitation any and all warranties of merchantability, fitness 24 * for a particular purpose, and non-infringement of intellectual property rights. 25 * 26 * <b>Important Notice</b> 27 * 28 * Nuvoton Products are neither intended nor warranted for usage in systems or equipment, 29 * any malfunction or failure of which may cause loss of human life, bodily injury or severe 30 * property damage. Such applications are deemed, "Insecure Usage". 31 * 32 * Insecure usage includes, but is not limited to: equipment for surgical implementation, 33 * atomic energy control instruments, airplane or spaceship instruments, the control or 34 * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal 35 * instruments, all types of safety devices, and other applications intended to support or 36 * sustain life. 37 * 38 * All Insecure Usage shall be made at customer's risk, and in the event that third parties 39 * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify 40 * the damages and liabilities thus incurred by Nuvoton. 41 * 42 * Please note that all data and specifications are subject to change without notice. All the 43 * trademarks of products and companies mentioned in this datasheet belong to their respective 44 * owners. 45 * 46 * <b>Copyright Notice</b> 47 * 48 * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 49 */ 50 #ifndef __M480_H__ 51 #define __M480_H__ 52 53 #ifdef __cplusplus 54 extern "C" { 55 #endif 56 57 /******************************************************************************/ 58 /* Processor and Core Peripherals */ 59 /******************************************************************************/ 60 /** @addtogroup CMSIS_Device Device CMSIS Definitions 61 Configuration of the Cortex-M4 Processor and Core Peripherals 62 @{ 63 */ 64 65 /** 66 * @details Interrupt Number Definition. 67 */ 68 typedef enum IRQn 69 { 70 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ 71 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 72 MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ 73 BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ 74 UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ 75 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ 76 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ 77 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ 78 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ 79 80 /****** M480 Specific Interrupt Numbers ********************************************************/ 81 82 BOD_IRQn = 0, /*!< Brown Out detection Interrupt */ 83 IRC_IRQn = 1, /*!< Internal RC Interrupt */ 84 PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */ 85 RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */ 86 CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */ 87 RTC_IRQn = 6, /*!< Real Time Clock Interrupt */ 88 TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */ 89 WDT_IRQn = 8, /*!< Watchdog timer Interrupt */ 90 WWDT_IRQn = 9, /*!< Window Watchdog timer Interrupt */ 91 EINT0_IRQn = 10, /*!< External Input 0 Interrupt */ 92 EINT1_IRQn = 11, /*!< External Input 1 Interrupt */ 93 EINT2_IRQn = 12, /*!< External Input 2 Interrupt */ 94 EINT3_IRQn = 13, /*!< External Input 3 Interrupt */ 95 EINT4_IRQn = 14, /*!< External Input 4 Interrupt */ 96 EINT5_IRQn = 15, /*!< External Input 5 Interrupt */ 97 GPA_IRQn = 16, /*!< GPIO Port A Interrupt */ 98 GPB_IRQn = 17, /*!< GPIO Port B Interrupt */ 99 GPC_IRQn = 18, /*!< GPIO Port C Interrupt */ 100 GPD_IRQn = 19, /*!< GPIO Port D Interrupt */ 101 GPE_IRQn = 20, /*!< GPIO Port E Interrupt */ 102 GPF_IRQn = 21, /*!< GPIO Port F Interrupt */ 103 QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */ 104 SPI0_IRQn = 23, /*!< SPI0 Interrupt */ 105 BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */ 106 EPWM0P0_IRQn = 25, /*!< EPWM0P0 Interrupt */ 107 EPWM0P1_IRQn = 26, /*!< EPWM0P1 Interrupt */ 108 EPWM0P2_IRQn = 27, /*!< EPWM0P2 Interrupt */ 109 BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */ 110 EPWM1P0_IRQn = 29, /*!< EPWM1P0 Interrupt */ 111 EPWM1P1_IRQn = 30, /*!< EPWM1P1 Interrupt */ 112 EPWM1P2_IRQn = 31, /*!< EPWM1P2 Interrupt */ 113 TMR0_IRQn = 32, /*!< Timer 0 Interrupt */ 114 TMR1_IRQn = 33, /*!< Timer 1 Interrupt */ 115 TMR2_IRQn = 34, /*!< Timer 2 Interrupt */ 116 TMR3_IRQn = 35, /*!< Timer 3 Interrupt */ 117 UART0_IRQn = 36, /*!< UART 0 Interrupt */ 118 UART1_IRQn = 37, /*!< UART 1 Interrupt */ 119 I2C0_IRQn = 38, /*!< I2C 0 Interrupt */ 120 I2C1_IRQn = 39, /*!< I2C 1 Interrupt */ 121 PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */ 122 DAC_IRQn = 41, /*!< DAC Interrupt */ 123 EADC00_IRQn = 42, /*!< EADC00 Interrupt */ 124 EADC01_IRQn = 43, /*!< EADC01 Interrupt */ 125 ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */ 126 EADC02_IRQn = 46, /*!< EADC02 Interrupt */ 127 EADC03_IRQn = 47, /*!< EADC03 Interrupt */ 128 UART2_IRQn = 48, /*!< UART2 Interrupt */ 129 UART3_IRQn = 49, /*!< UART3 Interrupt */ 130 QSPI1_IRQn = 50, /*!< QSPI1 Interrupt */ 131 SPI1_IRQn = 51, /*!< SPI1 Interrupt */ 132 SPI2_IRQn = 52, /*!< SPI2 Interrupt */ 133 USBD_IRQn = 53, /*!< USB device Interrupt */ 134 USBH_IRQn = 54, /*!< USB host Interrupt */ 135 USBOTG_IRQn = 55, /*!< USB OTG Interrupt */ 136 CAN0_IRQn = 56, /*!< CAN0 Interrupt */ 137 CAN1_IRQn = 57, /*!< CAN1 Interrupt */ 138 SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */ 139 SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */ 140 SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */ 141 SPI3_IRQn = 62, /*!< SPI3 Interrupt */ 142 EMAC_TX_IRQn = 66, /*!< Ethernet MAC TX Interrupt */ 143 EMAC_RX_IRQn = 67, /*!< Ethernet MAC RX Interrupt */ 144 SDH0_IRQn = 64, /*!< Secure Digital Host Controller 0 Interrupt */ 145 USBD20_IRQn = 65, /*!< High Speed USB device Interrupt */ 146 I2S0_IRQn = 68, /*!< I2S0 Interrupt */ 147 OPA_IRQn = 70, /*!< OPA Interrupt */ 148 CRPT_IRQn = 71, /*!< CRPT Interrupt */ 149 GPG_IRQn = 72, /*!< GPIO Port G Interrupt */ 150 EINT6_IRQn = 73, /*!< External Input 6 Interrupt */ 151 UART4_IRQn = 74, /*!< UART4 Interrupt */ 152 UART5_IRQn = 75, /*!< UART5 Interrupt */ 153 USCI0_IRQn = 76, /*!< USCI0 Interrupt */ 154 USCI1_IRQn = 77, /*!< USCI1 Interrupt */ 155 BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */ 156 BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */ 157 SPIM_IRQn = 80, /*!< SPIM Interrupt */ 158 CCAP_IRQn = 81, /*!< CCAP Interrupt */ 159 I2C2_IRQn = 82, /*!< I2C2 Interrupt */ 160 QEI0_IRQn = 84, /*!< QEI0 Interrupt */ 161 QEI1_IRQn = 85, /*!< QEI1 Interrupt */ 162 ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */ 163 ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */ 164 GPH_IRQn = 88, /*!< GPIO Port H Interrupt */ 165 EINT7_IRQn = 89, /*!< External Input 7 Interrupt */ 166 SDH1_IRQn = 90, /*!< Secure Digital Host Controller 1 Interrupt */ 167 HSUSBH_IRQn = 92, /*!< High speed USB host Interrupt */ 168 USBOTG20_IRQn = 93, /*!< High speed USB OTG Interrupt */ 169 TRNG_IRQn = 101, /*!< TRNG Interrupt */ 170 UART6_IRQn = 102, /*!< UART6 Interrupt */ 171 UART7_IRQn = 103, /*!< UART7 Interrupt */ 172 EADC10_IRQn = 104, /*!< EADC10 Interrupt */ 173 EADC11_IRQn = 105, /*!< EADC11 Interrupt */ 174 EADC12_IRQn = 106, /*!< EADC12 Interrupt */ 175 EADC13_IRQn = 107, /*!< EADC13 Interrupt */ 176 CAN2_IRQn = 108, /*!< CAN2 Interrupt */ 177 } 178 IRQn_Type; 179 180 181 /* 182 * ========================================================================== 183 * ----------- Processor and Core Peripheral Section ------------------------ 184 * ========================================================================== 185 */ 186 187 /* Configuration of the Cortex-M4 Processor and Core Peripherals */ 188 #define __CM4_REV 0x0201UL /*!< Core Revision r2p1 */ 189 #define __NVIC_PRIO_BITS 4UL /*!< Number of Bits used for Priority Levels */ 190 #define __Vendor_SysTickConfig 0UL /*!< Set to 1 if different SysTick Config is used */ 191 #define __MPU_PRESENT 1UL /*!< MPU present or not */ 192 #ifdef __FPU_PRESENT 193 #undef __FPU_PRESENT 194 #define __FPU_PRESENT 1UL /*!< FPU present or not */ 195 #else 196 #define __FPU_PRESENT 1UL /*!< FPU present or not */ 197 #endif 198 199 /*@}*/ /* end of group CMSIS_Device */ 200 201 202 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 203 #include "system_M480.h" /* System include file */ 204 #include <stdint.h> 205 206 207 208 #if defined ( __CC_ARM ) 209 #pragma anon_unions 210 #endif 211 212 /******************************************************************************/ 213 /* Register definitions */ 214 /******************************************************************************/ 215 216 #include "sys_reg.h" 217 #include "clk_reg.h" 218 #include "fmc_reg.h" 219 #include "gpio_reg.h" 220 #include "pdma_reg.h" 221 #include "timer_reg.h" 222 #include "wdt_reg.h" 223 #include "wwdt_reg.h" 224 #include "rtc_reg.h" 225 #include "epwm_reg.h" 226 #include "bpwm_reg.h" 227 #include "qei_reg.h" 228 #include "ecap_reg.h" 229 #include "uart_reg.h" 230 #include "emac_reg.h" 231 #include "sc_reg.h" 232 #include "i2s_reg.h" 233 #include "spi_reg.h" 234 #include "qspi_reg.h" 235 #include "spim_reg.h" 236 #include "i2c_reg.h" 237 #include "uuart_reg.h" 238 #include "uspi_reg.h" 239 #include "ui2c_reg.h" 240 #include "can_reg.h" 241 #include "sdh_reg.h" 242 #include "ebi_reg.h" 243 #include "usbd_reg.h" 244 #include "hsusbd_reg.h" 245 #include "usbh_reg.h" 246 #include "hsusbh_reg.h" 247 #include "otg_reg.h" 248 #include "hsotg_reg.h" 249 #include "crc_reg.h" 250 #include "crypto_reg.h" 251 #include "trng_reg.h" 252 #include "eadc_reg.h" 253 #include "dac_reg.h" 254 #include "acmp_reg.h" 255 #include "opa_reg.h" 256 #include "ccap_reg.h" 257 258 259 /** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base 260 Memory Mapped Structure for Peripherals 261 @{ 262 */ 263 /* Peripheral and SRAM base address */ 264 #define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */ 265 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */ 266 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */ 267 #define AHBPERIPH_BASE PERIPH_BASE /*!< AHB Base Address */ 268 #define APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000) /*!< APB Base Address */ 269 270 /*!< AHB peripherals */ 271 #define SYS_BASE (AHBPERIPH_BASE + 0x00000UL) 272 #define CLK_BASE (AHBPERIPH_BASE + 0x00200UL) 273 #define NMI_BASE (AHBPERIPH_BASE + 0x00300UL) 274 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL) 275 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL) 276 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL) 277 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL) 278 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL) 279 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL) 280 #define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL) 281 #define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL) 282 #define GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL) 283 #define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL) 284 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL) 285 #define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL) 286 #define USBH_BASE (AHBPERIPH_BASE + 0x09000UL) 287 #define HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL) 288 #define EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL) 289 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL) 290 #define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL) 291 #define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL) 292 #define EBI_BASE (AHBPERIPH_BASE + 0x10000UL) 293 #define HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL) 294 #define CCAP_BASE (AHBPERIPH_BASE + 0x30000UL) 295 #define CRC_BASE (AHBPERIPH_BASE + 0x31000UL) 296 #define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL) 297 298 /*!< APB2 peripherals */ 299 #define WDT_BASE (APBPERIPH_BASE + 0x00000UL) 300 #define WWDT_BASE (APBPERIPH_BASE + 0x00100UL) 301 #define OPA_BASE (APBPERIPH_BASE + 0x06000UL) 302 #define I2S_BASE (APBPERIPH_BASE + 0x08000UL) 303 #define EADC1_BASE (APBPERIPH_BASE + 0x0B000UL) 304 #define TIMER0_BASE (APBPERIPH_BASE + 0x10000UL) 305 #define TIMER1_BASE (APBPERIPH_BASE + 0x10100UL) 306 #define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL) 307 #define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL) 308 #define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL) 309 #define SPI1_BASE (APBPERIPH_BASE + 0x22000UL) 310 #define SPI3_BASE (APBPERIPH_BASE + 0x24000UL) 311 #define UART0_BASE (APBPERIPH_BASE + 0x30000UL) 312 #define UART2_BASE (APBPERIPH_BASE + 0x32000UL) 313 #define UART4_BASE (APBPERIPH_BASE + 0x34000UL) 314 #define UART6_BASE (APBPERIPH_BASE + 0x36000UL) 315 #define I2C0_BASE (APBPERIPH_BASE + 0x40000UL) 316 #define I2C2_BASE (APBPERIPH_BASE + 0x42000UL) 317 #define CAN0_BASE (APBPERIPH_BASE + 0x60000UL) 318 #define CAN2_BASE (APBPERIPH_BASE + 0x62000UL) 319 #define QEI0_BASE (APBPERIPH_BASE + 0x70000UL) 320 #define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL) 321 #define USCI0_BASE (APBPERIPH_BASE + 0x90000UL) 322 323 324 /*!< APB1 peripherals */ 325 #define RTC_BASE (APBPERIPH_BASE + 0x01000UL) 326 #define EADC_BASE (APBPERIPH_BASE + 0x03000UL) 327 #define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL) 328 #define USBD_BASE (APBPERIPH_BASE + 0x80000UL) 329 #define OTG_BASE (APBPERIPH_BASE + 0x0D000UL) 330 #define HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL) 331 #define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL) 332 #define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL) 333 #define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL) 334 #define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL) 335 #define SPI0_BASE (APBPERIPH_BASE + 0x21000UL) 336 #define SPI2_BASE (APBPERIPH_BASE + 0x23000UL) 337 #define QSPI1_BASE (APBPERIPH_BASE + 0x29000UL) 338 #define UART1_BASE (APBPERIPH_BASE + 0x31000UL) 339 #define UART3_BASE (APBPERIPH_BASE + 0x33000UL) 340 #define UART5_BASE (APBPERIPH_BASE + 0x35000UL) 341 #define UART7_BASE (APBPERIPH_BASE + 0x37000UL) 342 #define I2C1_BASE (APBPERIPH_BASE + 0x41000UL) 343 #define CAN1_BASE (APBPERIPH_BASE + 0x61000UL) 344 #define QEI1_BASE (APBPERIPH_BASE + 0x71000UL) 345 #define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL) 346 #define TRNG_BASE (APBPERIPH_BASE + 0x79000UL) 347 #define USCI1_BASE (APBPERIPH_BASE + 0x91000UL) 348 #define CRPT_BASE (0x50080000UL) 349 #define SPIM_BASE (0x40007000UL) 350 351 #define SC0_BASE (APBPERIPH_BASE + 0x50000UL) 352 #define SC1_BASE (APBPERIPH_BASE + 0x51000UL) 353 #define SC2_BASE (APBPERIPH_BASE + 0x52000UL) 354 #define DAC0_BASE (APBPERIPH_BASE + 0x07000UL) 355 #define DAC1_BASE (APBPERIPH_BASE + 0x07040UL) 356 #define DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL) 357 #define OPA0_BASE (APBPERIPH_BASE + 0x06000UL) 358 359 /*@}*/ /* end of group PERIPHERAL_MEM_MAP */ 360 361 362 /** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer 363 The Declaration of Peripherals 364 @{ 365 */ 366 367 #define SYS ((SYS_T *) SYS_BASE) 368 #define CLK ((CLK_T *) CLK_BASE) 369 #define NMI ((NMI_T *) NMI_BASE) 370 #define PA ((GPIO_T *) GPIOA_BASE) 371 #define PB ((GPIO_T *) GPIOB_BASE) 372 #define PC ((GPIO_T *) GPIOC_BASE) 373 #define PD ((GPIO_T *) GPIOD_BASE) 374 #define PE ((GPIO_T *) GPIOE_BASE) 375 #define PF ((GPIO_T *) GPIOF_BASE) 376 #define PG ((GPIO_T *) GPIOG_BASE) 377 #define PH ((GPIO_T *) GPIOH_BASE) 378 #define GPA ((GPIO_T *) GPIOA_BASE) 379 #define GPB ((GPIO_T *) GPIOB_BASE) 380 #define GPC ((GPIO_T *) GPIOC_BASE) 381 #define GPD ((GPIO_T *) GPIOD_BASE) 382 #define GPE ((GPIO_T *) GPIOE_BASE) 383 #define GPF ((GPIO_T *) GPIOF_BASE) 384 #define GPG ((GPIO_T *) GPIOG_BASE) 385 #define GPH ((GPIO_T *) GPIOH_BASE) 386 #define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE) 387 #define PDMA ((PDMA_T *) PDMA_BASE) 388 #define USBH ((USBH_T *) USBH_BASE) 389 #define HSUSBH ((HSUSBH_T *) HSUSBH_BASE) 390 #define EMAC ((EMAC_T *) EMAC_BASE) 391 #define FMC ((FMC_T *) FMC_BASE) 392 #define SDH0 ((SDH_T *) SDH0_BASE) 393 #define SDH1 ((SDH_T *) SDH1_BASE) 394 #define EBI ((EBI_T *) EBI_BASE) 395 #define CRC ((CRC_T *) CRC_BASE) 396 #define TAMPER ((TAMPER_T *) TAMPER_BASE) 397 398 #define WDT ((WDT_T *) WDT_BASE) 399 #define WWDT ((WWDT_T *) WWDT_BASE) 400 #define RTC ((RTC_T *) RTC_BASE) 401 #define EADC ((EADC_T *) EADC_BASE) 402 #define EADC0 ((EADC_T *) EADC_BASE) 403 #define EADC1 ((EADC_T *) EADC1_BASE) 404 #define ACMP01 ((ACMP_T *) ACMP01_BASE) 405 406 #define I2S0 ((I2S_T *) I2S_BASE) 407 #define USBD ((USBD_T *) USBD_BASE) 408 #define OTG ((OTG_T *) OTG_BASE) 409 #define HSUSBD ((HSUSBD_T *)HSUSBD_BASE) 410 #define HSOTG ((HSOTG_T *) HSOTG_BASE) 411 #define TIMER0 ((TIMER_T *) TIMER0_BASE) 412 #define TIMER1 ((TIMER_T *) TIMER1_BASE) 413 #define TIMER2 ((TIMER_T *) TIMER2_BASE) 414 #define TIMER3 ((TIMER_T *) TIMER3_BASE) 415 #define EPWM0 ((EPWM_T *) EPWM0_BASE) 416 #define EPWM1 ((EPWM_T *) EPWM1_BASE) 417 #define BPWM0 ((BPWM_T *) BPWM0_BASE) 418 #define BPWM1 ((BPWM_T *) BPWM1_BASE) 419 #define ECAP0 ((ECAP_T *) ECAP0_BASE) 420 #define ECAP1 ((ECAP_T *) ECAP1_BASE) 421 #define QEI0 ((QEI_T *) QEI0_BASE) 422 #define QEI1 ((QEI_T *) QEI1_BASE) 423 #define QSPI0 ((QSPI_T *) QSPI0_BASE) 424 #define QSPI1 ((QSPI_T *) QSPI1_BASE) 425 #define SPI0 ((SPI_T *) SPI0_BASE) 426 #define SPI1 ((SPI_T *) SPI1_BASE) 427 #define SPI2 ((SPI_T *) SPI2_BASE) 428 #define SPI3 ((SPI_T *) SPI3_BASE) 429 #define UART0 ((UART_T *) UART0_BASE) 430 #define UART1 ((UART_T *) UART1_BASE) 431 #define UART2 ((UART_T *) UART2_BASE) 432 #define UART3 ((UART_T *) UART3_BASE) 433 #define UART4 ((UART_T *) UART4_BASE) 434 #define UART5 ((UART_T *) UART5_BASE) 435 #define UART6 ((UART_T *) UART6_BASE) 436 #define UART7 ((UART_T *) UART7_BASE) 437 #define I2C0 ((I2C_T *) I2C0_BASE) 438 #define I2C1 ((I2C_T *) I2C1_BASE) 439 #define I2C2 ((I2C_T *) I2C2_BASE) 440 #define SC0 ((SC_T *) SC0_BASE) 441 #define SC1 ((SC_T *) SC1_BASE) 442 #define SC2 ((SC_T *) SC2_BASE) 443 #define CAN0 ((CAN_T *) CAN0_BASE) 444 #define CAN1 ((CAN_T *) CAN1_BASE) 445 #define CAN2 ((CAN_T *) CAN2_BASE) 446 #define CRPT ((CRPT_T *) CRPT_BASE) 447 #define TRNG ((TRNG_T *) TRNG_BASE) 448 #define SPIM ((volatile SPIM_T *) SPIM_BASE) 449 #define DAC0 ((DAC_T *) DAC0_BASE) 450 #define DAC1 ((DAC_T *) DAC1_BASE) 451 #define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Configuration Struct */ 452 #define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Configuration Struct */ 453 #define OPA ((OPA_T *) OPA_BASE) 454 #define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Configuration Struct */ 455 #define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Configuration Struct */ 456 #define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Configuration Struct */ 457 #define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Configuration Struct */ 458 #define CCAP ((CCAP_T *) CCAP_BASE) 459 460 /*@}*/ /* end of group ERIPHERAL_DECLARATION */ 461 462 /** @addtogroup IO_ROUTINE I/O Routines 463 The Declaration of I/O Routines 464 @{ 465 */ 466 467 typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type 468 typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type 469 typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type 470 471 /** 472 * @brief Get a 8-bit unsigned value from specified address 473 * @param[in] addr Address to get 8-bit data from 474 * @return 8-bit unsigned value stored in specified address 475 */ 476 #define M8(addr) (*((vu8 *) (addr))) 477 478 /** 479 * @brief Get a 16-bit unsigned value from specified address 480 * @param[in] addr Address to get 16-bit data from 481 * @return 16-bit unsigned value stored in specified address 482 * @note The input address must be 16-bit aligned 483 */ 484 #define M16(addr) (*((vu16 *) (addr))) 485 486 /** 487 * @brief Get a 32-bit unsigned value from specified address 488 * @param[in] addr Address to get 32-bit data from 489 * @return 32-bit unsigned value stored in specified address 490 * @note The input address must be 32-bit aligned 491 */ 492 #define M32(addr) (*((vu32 *) (addr))) 493 494 /** 495 * @brief Set a 32-bit unsigned value to specified I/O port 496 * @param[in] port Port address to set 32-bit data 497 * @param[in] value Value to write to I/O port 498 * @return None 499 * @note The output port must be 32-bit aligned 500 */ 501 #define outpw(port,value) *((volatile unsigned int *)(port)) = (value) 502 503 /** 504 * @brief Get a 32-bit unsigned value from specified I/O port 505 * @param[in] port Port address to get 32-bit data from 506 * @return 32-bit unsigned value stored in specified I/O port 507 * @note The input port must be 32-bit aligned 508 */ 509 #define inpw(port) (*((volatile unsigned int *)(port))) 510 511 /** 512 * @brief Set a 16-bit unsigned value to specified I/O port 513 * @param[in] port Port address to set 16-bit data 514 * @param[in] value Value to write to I/O port 515 * @return None 516 * @note The output port must be 16-bit aligned 517 */ 518 #define outps(port,value) *((volatile unsigned short *)(port)) = (value) 519 520 /** 521 * @brief Get a 16-bit unsigned value from specified I/O port 522 * @param[in] port Port address to get 16-bit data from 523 * @return 16-bit unsigned value stored in specified I/O port 524 * @note The input port must be 16-bit aligned 525 */ 526 #define inps(port) (*((volatile unsigned short *)(port))) 527 528 /** 529 * @brief Set a 8-bit unsigned value to specified I/O port 530 * @param[in] port Port address to set 8-bit data 531 * @param[in] value Value to write to I/O port 532 * @return None 533 */ 534 #define outpb(port,value) *((volatile unsigned char *)(port)) = (value) 535 536 /** 537 * @brief Get a 8-bit unsigned value from specified I/O port 538 * @param[in] port Port address to get 8-bit data from 539 * @return 8-bit unsigned value stored in specified I/O port 540 */ 541 #define inpb(port) (*((volatile unsigned char *)(port))) 542 543 /** 544 * @brief Set a 32-bit unsigned value to specified I/O port 545 * @param[in] port Port address to set 32-bit data 546 * @param[in] value Value to write to I/O port 547 * @return None 548 * @note The output port must be 32-bit aligned 549 */ 550 #define outp32(port,value) *((volatile unsigned int *)(port)) = (value) 551 552 /** 553 * @brief Get a 32-bit unsigned value from specified I/O port 554 * @param[in] port Port address to get 32-bit data from 555 * @return 32-bit unsigned value stored in specified I/O port 556 * @note The input port must be 32-bit aligned 557 */ 558 #define inp32(port) (*((volatile unsigned int *)(port))) 559 560 /** 561 * @brief Set a 16-bit unsigned value to specified I/O port 562 * @param[in] port Port address to set 16-bit data 563 * @param[in] value Value to write to I/O port 564 * @return None 565 * @note The output port must be 16-bit aligned 566 */ 567 #define outp16(port,value) *((volatile unsigned short *)(port)) = (value) 568 569 /** 570 * @brief Get a 16-bit unsigned value from specified I/O port 571 * @param[in] port Port address to get 16-bit data from 572 * @return 16-bit unsigned value stored in specified I/O port 573 * @note The input port must be 16-bit aligned 574 */ 575 #define inp16(port) (*((volatile unsigned short *)(port))) 576 577 /** 578 * @brief Set a 8-bit unsigned value to specified I/O port 579 * @param[in] port Port address to set 8-bit data 580 * @param[in] value Value to write to I/O port 581 * @return None 582 */ 583 #define outp8(port,value) *((volatile unsigned char *)(port)) = (value) 584 585 /** 586 * @brief Get a 8-bit unsigned value from specified I/O port 587 * @param[in] port Port address to get 8-bit data from 588 * @return 8-bit unsigned value stored in specified I/O port 589 */ 590 #define inp8(port) (*((volatile unsigned char *)(port))) 591 592 593 /*@}*/ /* end of group IO_ROUTINE */ 594 595 /******************************************************************************/ 596 /* Legacy Constants */ 597 /******************************************************************************/ 598 /** @addtogroup Legacy_Constants Legacy Constants 599 Legacy Constants 600 @{ 601 */ 602 603 #if 0 604 #ifndef NULL 605 #define NULL (0) ///< NULL pointer 606 #endif 607 608 #define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value 609 #define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value 610 611 #define ENABLE (1UL) ///< Enable, define to use in API parameters 612 #define DISABLE (0UL) ///< Disable, define to use in API parameters 613 614 /* Define one bit mask */ 615 #define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer 616 #define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer 617 #define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer 618 #define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer 619 #define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer 620 #define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer 621 #define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer 622 #define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer 623 #define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer 624 #define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer 625 #define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer 626 #define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer 627 #define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer 628 #define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer 629 #define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer 630 #define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer 631 #define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer 632 #define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer 633 #define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer 634 #define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer 635 #define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer 636 #define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer 637 #define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer 638 #define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer 639 #define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer 640 #define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer 641 #define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer 642 #define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer 643 #define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer 644 #define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer 645 #define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer 646 #define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer 647 #endif 648 649 /* Byte Mask Definitions */ 650 #define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer 651 #define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer 652 #define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer 653 #define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer 654 655 #define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ 656 #define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ 657 #define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ 658 #define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ 659 660 /*@}*/ /* end of group Legacy_Constants */ 661 662 663 /******************************************************************************/ 664 /* Peripheral header files */ 665 /******************************************************************************/ 666 #include "sys.h" 667 #include "clk.h" 668 669 #include "acmp.h" 670 #include "dac.h" 671 #include "emac.h" 672 #include "uart.h" 673 #include "usci_spi.h" 674 #include "gpio.h" 675 #include "ccap.h" 676 #include "ecap.h" 677 #include "qei.h" 678 #include "timer.h" 679 #include "timer_pwm.h" 680 #include "pdma.h" 681 #include "crypto.h" 682 #include "trng.h" 683 #include "fmc.h" 684 #include "spim.h" 685 #include "i2c.h" 686 #include "i2s.h" 687 #include "epwm.h" 688 #include "eadc.h" 689 #include "bpwm.h" 690 #include "wdt.h" 691 #include "wwdt.h" 692 #include "opa.h" 693 #include "crc.h" 694 #include "ebi.h" 695 #include "usci_i2c.h" 696 #include "scuart.h" 697 #include "sc.h" 698 #include "spi.h" 699 #include "qspi.h" 700 /* #include "can.h" */ 701 #include "rtc.h" 702 #include "usci_uart.h" 703 #include "sdh.h" 704 #include "usbd.h" 705 #include "hsusbd.h" 706 #include "otg.h" 707 #include "hsotg.h" 708 709 710 #ifdef __cplusplus 711 } 712 #endif 713 714 #endif /* __M480_H__ */ 715 716
