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Searched defs:TIER (Results 1 – 25 of 29) sorted by relevance

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/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_TMU.h82 __IO uint32_t TIER; /**< Interrupt Enable, offset: 0x20 */ member
DS32Z2_LFAST.h89 …__IO uint32_t TIER; /**< LFAST Tx Interrupt Enable Register, offset: … member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h50073 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h50071 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h50073 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_ca53.h50085 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
DMIMX8MN6_cm7.h50071 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h50073 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h50071 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h55300 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 … member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h53127 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 … member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h55300 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 … member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h55300 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 … member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h55300 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 … member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM2/
DMIMX8MM2_cm4.h68889 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h68889 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h68889 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM4/
DMIMX8MM4_cm4.h68889 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h68889 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_cm4.h68889 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
DMIMX8MM6_ca53.h68354 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h97105 __IO uint32_t TIER; /**< Interrupt Enable, offset: 0x20 */ member
DMIMX9352_ca55.h84788 __IO uint32_t TIER; /**< Interrupt Enable, offset: 0x20 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_ca53.h96013 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
DMIMX8ML8_dsp.h91964 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member

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