1 /* 2 * Copyright (c) 2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef __SVC_NUM_H__ 9 #define __SVC_NUM_H__ 10 11 /* 12 * SVC numbers for FF-M compliant implementations. 13 * 0x0 ~ 0x7F can be only called from Thread Mode, the rest from ISR only. 14 */ 15 16 /********************* SVC for Thread Mode ************************************/ 17 /* PSA Client APIs */ 18 #define TFM_SVC_PSA_FRAMEWORK_VERSION (0x0) 19 #define TFM_SVC_PSA_VERSION (0x1) 20 #define TFM_SVC_PSA_CONNECT (0x2) 21 #define TFM_SVC_PSA_CALL (0x3) 22 #define TFM_SVC_PSA_CLOSE (0x4) 23 /* PSA Secure Partition APIs */ 24 #define TFM_SVC_PSA_WAIT (0x5) 25 #define TFM_SVC_PSA_GET (0x6) 26 #define TFM_SVC_PSA_SET_RHANDLE (0x7) 27 #define TFM_SVC_PSA_READ (0x8) 28 #define TFM_SVC_PSA_SKIP (0x9) 29 #define TFM_SVC_PSA_WRITE (0xA) 30 #define TFM_SVC_PSA_REPLY (0xB) 31 #define TFM_SVC_PSA_NOTIFY (0xC) 32 #define TFM_SVC_PSA_CLEAR (0xD) 33 #define TFM_SVC_PSA_EOI (0xE) 34 #define TFM_SVC_PSA_PANIC (0xF) 35 #define TFM_SVC_PSA_LIFECYCLE (0x10) 36 #define TFM_SVC_PSA_IRQ_ENABLE (0x11) 37 #define TFM_SVC_PSA_IRQ_DISABLE (0x12) 38 #define TFM_SVC_PSA_RESET_SIGNAL (0x13) 39 /* TF-M specific, starts from 0x40 */ 40 #define TFM_SVC_GET_BOOT_DATA (0x40) 41 #define TFM_SVC_SPM_INIT (0x41) 42 #define TFM_SVC_FLIH_FUNC_RETURN (0x42) 43 #define TFM_SVC_THREAD_NUMBER_END (0x7F) 44 #if TFM_SP_LOG_RAW_ENABLED 45 #define TFM_SVC_OUTPUT_UNPRIV_STRING (TFM_SVC_THREAD_NUMBER_END) 46 #endif 47 48 #define TFM_SVC_HANDLER_NUMBER_START (0x80) 49 50 /********************* SVC for interrupt handling *****************************/ 51 #define TFM_SVC_PREPARE_DEPRIV_FLIH (0x80) 52 53 #endif /* __SVC_NUM_H__ */ 54
