1 
2 #ifndef TFM_PERIPHERAL_REGULATORS_SECURE
3 #define TFM_PERIPHERAL_REGULATORS_SECURE 0
4 #endif
5 
6 #ifndef TFM_PERIPHERAL_CLOCK_SECURE
7 #define TFM_PERIPHERAL_CLOCK_SECURE 0
8 #endif
9 
10 #ifndef TFM_PERIPHERAL_POWER_SECURE
11 #define TFM_PERIPHERAL_POWER_SECURE 0
12 #endif
13 
14 #ifndef TFM_PERIPHERAL_SPIM0_SECURE
15 #define TFM_PERIPHERAL_SPIM0_SECURE 0
16 #endif
17 
18 #ifndef TFM_PERIPHERAL_SPIS0_SECURE
19 #define TFM_PERIPHERAL_SPIS0_SECURE 0
20 #endif
21 
22 #ifndef TFM_PERIPHERAL_TWIM0_SECURE
23 #define TFM_PERIPHERAL_TWIM0_SECURE 0
24 #endif
25 
26 #ifndef TFM_PERIPHERAL_TWIS0_SECURE
27 #define TFM_PERIPHERAL_TWIS0_SECURE 0
28 #endif
29 
30 #ifndef TFM_PERIPHERAL_UARTE0_SECURE
31 #define TFM_PERIPHERAL_UARTE0_SECURE 0
32 #endif
33 
34 #ifndef TFM_PERIPHERAL_SPIM1_SECURE
35 #define TFM_PERIPHERAL_SPIM1_SECURE 0
36 #endif
37 
38 #ifndef TFM_PERIPHERAL_SPIS1_SECURE
39 #define TFM_PERIPHERAL_SPIS1_SECURE 0
40 #endif
41 
42 #ifndef TFM_PERIPHERAL_TWIM1_SECURE
43 #define TFM_PERIPHERAL_TWIM1_SECURE 0
44 #endif
45 
46 #ifndef TFM_PERIPHERAL_TWIS1_SECURE
47 #define TFM_PERIPHERAL_TWIS1_SECURE 0
48 #endif
49 
50 #ifndef TFM_PERIPHERAL_UARTE1_SECURE
51 #define TFM_PERIPHERAL_UARTE1_SECURE 0
52 #endif
53 
54 #ifndef TFM_PERIPHERAL_SPIM2_SECURE
55 #define TFM_PERIPHERAL_SPIM2_SECURE 0
56 #endif
57 
58 #ifndef TFM_PERIPHERAL_SPIS2_SECURE
59 #define TFM_PERIPHERAL_SPIS2_SECURE 0
60 #endif
61 
62 #ifndef TFM_PERIPHERAL_TWIM2_SECURE
63 #define TFM_PERIPHERAL_TWIM2_SECURE 0
64 #endif
65 
66 #ifndef TFM_PERIPHERAL_TWIS2_SECURE
67 #define TFM_PERIPHERAL_TWIS2_SECURE 0
68 #endif
69 
70 #ifndef TFM_PERIPHERAL_UARTE2_SECURE
71 #define TFM_PERIPHERAL_UARTE2_SECURE 0
72 #endif
73 
74 #ifndef TFM_PERIPHERAL_SPIM3_SECURE
75 #define TFM_PERIPHERAL_SPIM3_SECURE 0
76 #endif
77 
78 #ifndef TFM_PERIPHERAL_SPIS3_SECURE
79 #define TFM_PERIPHERAL_SPIS3_SECURE 0
80 #endif
81 
82 #ifndef TFM_PERIPHERAL_TWIM3_SECURE
83 #define TFM_PERIPHERAL_TWIM3_SECURE 0
84 #endif
85 
86 #ifndef TFM_PERIPHERAL_TWIS3_SECURE
87 #define TFM_PERIPHERAL_TWIS3_SECURE 0
88 #endif
89 
90 #ifndef TFM_PERIPHERAL_UARTE3_SECURE
91 #define TFM_PERIPHERAL_UARTE3_SECURE 0
92 #endif
93 
94 #ifndef TFM_PERIPHERAL_SAADC_SECURE
95 #define TFM_PERIPHERAL_SAADC_SECURE 0
96 #endif
97 
98 #ifndef TFM_PERIPHERAL_TIMER0_SECURE
99 #define TFM_PERIPHERAL_TIMER0_SECURE 0
100 #endif
101 
102 #ifndef TFM_PERIPHERAL_TIMER1_SECURE
103 #define TFM_PERIPHERAL_TIMER1_SECURE 0
104 #endif
105 
106 #ifndef TFM_PERIPHERAL_TIMER2_SECURE
107 #define TFM_PERIPHERAL_TIMER2_SECURE 0
108 #endif
109 
110 #ifndef TFM_PERIPHERAL_RTC0_SECURE
111 #define TFM_PERIPHERAL_RTC0_SECURE 0
112 #endif
113 
114 #ifndef TFM_PERIPHERAL_RTC1_SECURE
115 #define TFM_PERIPHERAL_RTC1_SECURE 0
116 #endif
117 
118 #ifndef TFM_PERIPHERAL_DPPI_SECURE
119 #define TFM_PERIPHERAL_DPPI_SECURE 0
120 #endif
121 
122 #ifndef TFM_PERIPHERAL_WDT_SECURE
123 #define TFM_PERIPHERAL_WDT_SECURE 0
124 #endif
125 
126 #ifndef TFM_PERIPHERAL_EGU0_SECURE
127 #define TFM_PERIPHERAL_EGU0_SECURE 0
128 #endif
129 
130 #ifndef TFM_PERIPHERAL_EGU1_SECURE
131 #define TFM_PERIPHERAL_EGU1_SECURE 0
132 #endif
133 
134 #ifndef TFM_PERIPHERAL_EGU2_SECURE
135 #define TFM_PERIPHERAL_EGU2_SECURE 0
136 #endif
137 
138 #ifndef TFM_PERIPHERAL_EGU3_SECURE
139 #define TFM_PERIPHERAL_EGU3_SECURE 0
140 #endif
141 
142 #ifndef TFM_PERIPHERAL_EGU4_SECURE
143 #define TFM_PERIPHERAL_EGU4_SECURE 0
144 #endif
145 
146 #ifndef TFM_PERIPHERAL_EGU5_SECURE
147 #define TFM_PERIPHERAL_EGU5_SECURE 0
148 #endif
149 
150 #ifndef TFM_PERIPHERAL_PWM0_SECURE
151 #define TFM_PERIPHERAL_PWM0_SECURE 0
152 #endif
153 
154 #ifndef TFM_PERIPHERAL_PWM1_SECURE
155 #define TFM_PERIPHERAL_PWM1_SECURE 0
156 #endif
157 
158 #ifndef TFM_PERIPHERAL_PWM2_SECURE
159 #define TFM_PERIPHERAL_PWM2_SECURE 0
160 #endif
161 
162 #ifndef TFM_PERIPHERAL_PWM3_SECURE
163 #define TFM_PERIPHERAL_PWM3_SECURE 0
164 #endif
165 
166 #ifndef TFM_PERIPHERAL_PDM_SECURE
167 #define TFM_PERIPHERAL_PDM_SECURE 0
168 #endif
169 
170 #ifndef TFM_PERIPHERAL_I2S_SECURE
171 #define TFM_PERIPHERAL_I2S_SECURE 0
172 #endif
173 
174 #ifndef TFM_PERIPHERAL_IPC_SECURE
175 #define TFM_PERIPHERAL_IPC_SECURE 0
176 #endif
177 
178 #ifndef TFM_PERIPHERAL_FPU_SECURE
179 #define TFM_PERIPHERAL_FPU_SECURE 0
180 #endif
181 
182 #ifndef TFM_PERIPHERAL_NVMC_SECURE
183 #define TFM_PERIPHERAL_NVMC_SECURE 0
184 #endif
185 
186 #ifndef TFM_PERIPHERAL_VMC_SECURE
187 #define TFM_PERIPHERAL_VMC_SECURE 0
188 #endif
189 
190 #ifndef TFM_PERIPHERAL_GPIO0_SECURE
191 #define TFM_PERIPHERAL_GPIO0_SECURE 0
192 #endif
193 
194 #ifndef TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE
195 #define TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE 0
196 #endif
197 
198 #ifndef TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE
199 #define TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE 0
200 #endif
201