1 /* 2 * Copyright (c) 2019-2022 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __PLATFORM_IRQ_H__ 18 #define __PLATFORM_IRQ_H__ 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 /* ======================================================================= */ 25 /* ================== Interrupt Number Definition ===================== */ 26 /* ======================================================================= */ 27 28 29 typedef enum IRQn 30 { 31 /* =============== Core Specific Interrupt Numbers ====================== */ 32 NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt */ 33 HardFault_IRQn = -13, /* -13 HardFault Interrupt */ 34 MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt */ 35 BusFault_IRQn = -11, /* -11 Bus Fault Interrupt */ 36 UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt */ 37 SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt */ 38 SVCall_IRQn = -5, /* -5 SV Call Interrupt */ 39 DebugMonitor_IRQn = -4, /* -4 Debug Monitor Interrupt */ 40 PendSV_IRQn = -2, /* -2 Pend SV Interrupt */ 41 SysTick_IRQn = -1, /* -1 System Tick Interrupt */ 42 43 /* ============= Musca Specific SSE-200 Interrupt Numbers =============== */ 44 NS_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset Request 45 * Interrupt */ 46 NS_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */ 47 S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */ 48 TIMER0_IRQn = 3, /* CMSDK Timer 0 Interrupt */ 49 TIMER1_IRQn = 4, /* CMSDK Timer 1 Interrupt */ 50 DUALTIMER_IRQn = 5, /* CMSDK Dual Timer Interrupt */ 51 MHU0_IRQn = 6, /* Message Handling Unit 0 Interrupt */ 52 MHU1_IRQn = 7, /* Message Handling Unit 1 Interrupt */ 53 CRYPTOCELL_IRQn = 8, /* CryptoCell-312 Interrupt */ 54 S_MPC_COMBINED_IRQn = 9, /* Secure Combined MPC Interrupt */ 55 S_PPC_COMBINED_IRQn = 10, /* Secure Combined PPC Interrupt */ 56 S_MSC_COMBINED_IRQn = 11, /* Secure Combined MSC Interrupt */ 57 S_BRIDGE_ERR_IRQn = 12, /* Secure Bridge Error Combined 58 * Interrupt */ 59 I_CACHE_INV_ERR_IRQn = 13, /* Instruction Cache Invalidation 60 * Interrupt */ 61 /* Reserved = 14, Reserved */ 62 SYS_PPU_IRQn = 15, /* System PPU Interrupt */ 63 CPU0_PPU_IRQn = 16, /* CPU0 PPU Interrupt */ 64 CPU1_PPU_IRQn = 17, /* CPU1 PPU Interrupt */ 65 CPU0_DGB_PPU_IRQn = 18, /* CPU0 Debug PPU Interrupt */ 66 CPU1_DGB_PPU_IRQn = 19, /* CPU1 Debug PPU Interrupt */ 67 CRYPTOCELL_PPU_IRQn = 20, /* CryptoCell PPU Interrupt */ 68 /* Reserved = 21, Reserved */ 69 RAM0_PPU_IRQn = 22, /* RAM 0 PPU Interrupt */ 70 RAM1_PPU_IRQn = 23, /* RAM 1 PPU Interrupt */ 71 RAM2_PPU_IRQn = 24, /* RAM 2 PPU Interrupt */ 72 RAM3_PPU_IRQn = 25, /* RAM 3 PPU Interrupt */ 73 DEBUG_PPU_IRQn = 26, /* Debug PPU Interrupt */ 74 /* Reserved = 27, Reserved */ 75 CPU0_CTI_IRQn = 28, /* CPU0 CTI Interrupt */ 76 CPU1_CTI_IRQn = 29, /* CPU1 CTI Interrupt */ 77 /* Reserved = 30, Reserved */ 78 /* Reserved = 31, Reserved */ 79 /* ============ Musca Specific Expansion Interrupt Numbers ============== */ 80 /* None = 32, Not used. Tied to 0 */ 81 GpTimer_IRQn = 33, /* General Purpose Timer Interrupt */ 82 I2C0_IRQn = 34, /* I2C0 Interrupt */ 83 I2C1_IRQn = 35, /* I2C1 Interrupt */ 84 I2S_IRQn = 36, /* I2S Interrupt */ 85 SPI_IRQn = 37, /* SPI Interrupt */ 86 QSPI_IRQn = 38, /* QSPI Interrupt */ 87 UART0_Rx_IRQn = 39, /* UART0 receive FIFO interrupt */ 88 UART0_Tx_IRQn = 40, /* UART0 transmit FIFO interrupt */ 89 UART0_RxTimeout_IRQn = 41, /* UART0 receive timeout interrupt */ 90 UART0_ModemStatus_IRQn = 42, /* UART0 modem status interrupt */ 91 UART0_Error_IRQn = 43, /* UART0 error interrupt */ 92 UART0_IRQn = 44, /* UART0 interrupt */ 93 UART1_Rx_IRQn = 45, /* UART1 receive FIFO interrupt */ 94 UART1_Tx_IRQn = 46, /* UART1 transmit FIFO interrupt */ 95 UART1_RxTimeout_IRQn = 47, /* UART1 receive timeout interrupt */ 96 UART1_ModemStatus_IRQn = 48, /* UART1 modem status interrupt */ 97 UART1_Error_IRQn = 49, /* UART1 error interrupt */ 98 UART1_IRQn = 50, /* UART1 interrupt */ 99 GPIO_0_IRQn = 51, /* GPIO 0 interrupt */ 100 GPIO_1_IRQn = 52, /* GPIO 1 interrupt */ 101 GPIO_2_IRQn = 53, /* GPIO 2 interrupt */ 102 GPIO_3_IRQn = 54, /* GPIO 3 interrupt */ 103 GPIO_4_IRQn = 55, /* GPIO 4 interrupt */ 104 GPIO_5_IRQn = 56, /* GPIO 5 interrupt */ 105 GPIO_6_IRQn = 57, /* GPIO 6 interrupt */ 106 GPIO_7_IRQn = 58, /* GPIO 7 interrupt */ 107 GPIO_8_IRQn = 59, /* GPIO 8 interrupt */ 108 GPIO_9_IRQn = 60, /* GPIO 9 interrupt */ 109 GPIO_10_IRQn = 61, /* GPIO 10 interrupt */ 110 GPIO_11_IRQn = 62, /* GPIO 11 interrupt */ 111 GPIO_12_IRQn = 63, /* GPIO 12 interrupt */ 112 GPIO_13_IRQn = 64, /* GPIO 13 interrupt */ 113 GPIO_14_IRQn = 65, /* GPIO 14 interrupt */ 114 GPIO_15_IRQn = 66, /* GPIO 15 interrupt */ 115 Combined_IRQn = 67, /* Combined interrupt */ 116 PVT_IRQn = 68, /* PVT sensor interrupt */ 117 /* Reserved = 69, Reserved */ 118 PWM_0_IRQn = 70, /* PWM0 interrupt */ 119 RTC_IRQn = 71, /* RTC interrupt */ 120 GpTimer1_IRQn = 72, /* General Purpose Timer Alarm1 121 * Interrupt */ 122 GpTimer0_IRQn = 73, /* General Purpose Timer Alarm0 123 * Interrupt */ 124 PWM_1_IRQn = 74, /* PWM1 interrupt */ 125 PWM_2_IRQn = 75, /* PWM2 interrupt */ 126 IOMUX_IRQn = 76, /* IOMUX interrupt */ 127 TFM_FPU_S_TEST_IRQn = 77, /* TFM FPU Secure Test Interrupt */ 128 TFM_FPU_NS_TEST_IRQn = 78, /* TFM FPU Non-Secure Test Interrupt */ 129 } IRQn_Type; 130 131 #ifdef __cplusplus 132 } 133 #endif 134 135 #endif /* __PLATFORM_IRQ_H__ */ 136
