1 /***************************************************************************//** 2 * \file xmc7200_config.h 3 * 4 * \brief 5 * XMC7200 device configuration header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _XMC7200_CONFIG_H_ 28 #define _XMC7200_CONFIG_H_ 29 30 /* Clock Connections */ 31 typedef enum 32 { 33 PCLK_CPUSS_CLOCK_TRACE_IN = 0x0000u, /* cpuss.clock_trace_in */ 34 PCLK_SMARTIO12_CLOCK = 0x0001u, /* smartio[12].clock */ 35 PCLK_SMARTIO13_CLOCK = 0x0002u, /* smartio[13].clock */ 36 PCLK_SMARTIO14_CLOCK = 0x0003u, /* smartio[14].clock */ 37 PCLK_SMARTIO15_CLOCK = 0x0004u, /* smartio[15].clock */ 38 PCLK_SMARTIO17_CLOCK = 0x0005u, /* smartio[17].clock */ 39 PCLK_TCPWM0_CLOCKS0 = 0x0006u, /* tcpwm[0].clocks[0] */ 40 PCLK_TCPWM0_CLOCKS1 = 0x0007u, /* tcpwm[0].clocks[1] */ 41 PCLK_TCPWM0_CLOCKS2 = 0x0008u, /* tcpwm[0].clocks[2] */ 42 PCLK_TCPWM0_CLOCKS256 = 0x0009u, /* tcpwm[0].clocks[256] */ 43 PCLK_TCPWM0_CLOCKS257 = 0x000Au, /* tcpwm[0].clocks[257] */ 44 PCLK_TCPWM0_CLOCKS258 = 0x000Bu, /* tcpwm[0].clocks[258] */ 45 PCLK_TCPWM0_CLOCKS512 = 0x000Cu, /* tcpwm[0].clocks[512] */ 46 PCLK_TCPWM0_CLOCKS513 = 0x000Du, /* tcpwm[0].clocks[513] */ 47 PCLK_TCPWM0_CLOCKS514 = 0x000Eu, /* tcpwm[0].clocks[514] */ 48 PCLK_CANFD0_CLOCK_CAN0 = 0x0100u, /* canfd[0].clock_can[0] */ 49 PCLK_CANFD0_CLOCK_CAN1 = 0x0101u, /* canfd[0].clock_can[1] */ 50 PCLK_CANFD0_CLOCK_CAN2 = 0x0102u, /* canfd[0].clock_can[2] */ 51 PCLK_CANFD0_CLOCK_CAN3 = 0x0103u, /* canfd[0].clock_can[3] */ 52 PCLK_CANFD0_CLOCK_CAN4 = 0x0104u, /* canfd[0].clock_can[4] */ 53 PCLK_CANFD1_CLOCK_CAN0 = 0x0105u, /* canfd[1].clock_can[0] */ 54 PCLK_CANFD1_CLOCK_CAN1 = 0x0106u, /* canfd[1].clock_can[1] */ 55 PCLK_CANFD1_CLOCK_CAN2 = 0x0107u, /* canfd[1].clock_can[2] */ 56 PCLK_CANFD1_CLOCK_CAN3 = 0x0108u, /* canfd[1].clock_can[3] */ 57 PCLK_CANFD1_CLOCK_CAN4 = 0x0109u, /* canfd[1].clock_can[4] */ 58 PCLK_LIN0_CLOCK_CH_EN0 = 0x010Au, /* lin[0].clock_ch_en[0] */ 59 PCLK_LIN0_CLOCK_CH_EN1 = 0x010Bu, /* lin[0].clock_ch_en[1] */ 60 PCLK_LIN0_CLOCK_CH_EN2 = 0x010Cu, /* lin[0].clock_ch_en[2] */ 61 PCLK_LIN0_CLOCK_CH_EN3 = 0x010Du, /* lin[0].clock_ch_en[3] */ 62 PCLK_LIN0_CLOCK_CH_EN4 = 0x010Eu, /* lin[0].clock_ch_en[4] */ 63 PCLK_LIN0_CLOCK_CH_EN5 = 0x010Fu, /* lin[0].clock_ch_en[5] */ 64 PCLK_LIN0_CLOCK_CH_EN6 = 0x0110u, /* lin[0].clock_ch_en[6] */ 65 PCLK_LIN0_CLOCK_CH_EN7 = 0x0111u, /* lin[0].clock_ch_en[7] */ 66 PCLK_LIN0_CLOCK_CH_EN8 = 0x0112u, /* lin[0].clock_ch_en[8] */ 67 PCLK_LIN0_CLOCK_CH_EN9 = 0x0113u, /* lin[0].clock_ch_en[9] */ 68 PCLK_LIN0_CLOCK_CH_EN10 = 0x0114u, /* lin[0].clock_ch_en[10] */ 69 PCLK_LIN0_CLOCK_CH_EN11 = 0x0115u, /* lin[0].clock_ch_en[11] */ 70 PCLK_LIN0_CLOCK_CH_EN12 = 0x0116u, /* lin[0].clock_ch_en[12] */ 71 PCLK_LIN0_CLOCK_CH_EN13 = 0x0117u, /* lin[0].clock_ch_en[13] */ 72 PCLK_LIN0_CLOCK_CH_EN14 = 0x0118u, /* lin[0].clock_ch_en[14] */ 73 PCLK_LIN0_CLOCK_CH_EN15 = 0x0119u, /* lin[0].clock_ch_en[15] */ 74 PCLK_LIN0_CLOCK_CH_EN16 = 0x011Au, /* lin[0].clock_ch_en[16] */ 75 PCLK_LIN0_CLOCK_CH_EN17 = 0x011Bu, /* lin[0].clock_ch_en[17] */ 76 PCLK_LIN0_CLOCK_CH_EN18 = 0x011Cu, /* lin[0].clock_ch_en[18] */ 77 PCLK_LIN0_CLOCK_CH_EN19 = 0x011Du, /* lin[0].clock_ch_en[19] */ 78 PCLK_SCB0_CLOCK = 0x011Eu, /* scb[0].clock */ 79 PCLK_SCB1_CLOCK = 0x011Fu, /* scb[1].clock */ 80 PCLK_SCB2_CLOCK = 0x0120u, /* scb[2].clock */ 81 PCLK_SCB3_CLOCK = 0x0121u, /* scb[3].clock */ 82 PCLK_SCB4_CLOCK = 0x0122u, /* scb[4].clock */ 83 PCLK_SCB5_CLOCK = 0x0123u, /* scb[5].clock */ 84 PCLK_SCB6_CLOCK = 0x0124u, /* scb[6].clock */ 85 PCLK_SCB7_CLOCK = 0x0125u, /* scb[7].clock */ 86 PCLK_SCB8_CLOCK = 0x0126u, /* scb[8].clock */ 87 PCLK_SCB9_CLOCK = 0x0127u, /* scb[9].clock */ 88 PCLK_SCB10_CLOCK = 0x0128u, /* scb[10].clock */ 89 PCLK_FLEXRAY0_CLK_FLEXRAY = 0x0129u, /* flexray[0].clk_flexray */ 90 PCLK_PASS0_CLOCK_SAR0 = 0x012Au, /* pass[0].clock_sar[0] */ 91 PCLK_PASS0_CLOCK_SAR1 = 0x012Bu, /* pass[0].clock_sar[1] */ 92 PCLK_PASS0_CLOCK_SAR2 = 0x012Cu, /* pass[0].clock_sar[2] */ 93 PCLK_TCPWM1_CLOCKS0 = 0x012Du, /* tcpwm[1].clocks[0] */ 94 PCLK_TCPWM1_CLOCKS1 = 0x012Eu, /* tcpwm[1].clocks[1] */ 95 PCLK_TCPWM1_CLOCKS2 = 0x012Fu, /* tcpwm[1].clocks[2] */ 96 PCLK_TCPWM1_CLOCKS3 = 0x0130u, /* tcpwm[1].clocks[3] */ 97 PCLK_TCPWM1_CLOCKS4 = 0x0131u, /* tcpwm[1].clocks[4] */ 98 PCLK_TCPWM1_CLOCKS5 = 0x0132u, /* tcpwm[1].clocks[5] */ 99 PCLK_TCPWM1_CLOCKS6 = 0x0133u, /* tcpwm[1].clocks[6] */ 100 PCLK_TCPWM1_CLOCKS7 = 0x0134u, /* tcpwm[1].clocks[7] */ 101 PCLK_TCPWM1_CLOCKS8 = 0x0135u, /* tcpwm[1].clocks[8] */ 102 PCLK_TCPWM1_CLOCKS9 = 0x0136u, /* tcpwm[1].clocks[9] */ 103 PCLK_TCPWM1_CLOCKS10 = 0x0137u, /* tcpwm[1].clocks[10] */ 104 PCLK_TCPWM1_CLOCKS11 = 0x0138u, /* tcpwm[1].clocks[11] */ 105 PCLK_TCPWM1_CLOCKS12 = 0x0139u, /* tcpwm[1].clocks[12] */ 106 PCLK_TCPWM1_CLOCKS13 = 0x013Au, /* tcpwm[1].clocks[13] */ 107 PCLK_TCPWM1_CLOCKS14 = 0x013Bu, /* tcpwm[1].clocks[14] */ 108 PCLK_TCPWM1_CLOCKS15 = 0x013Cu, /* tcpwm[1].clocks[15] */ 109 PCLK_TCPWM1_CLOCKS16 = 0x013Du, /* tcpwm[1].clocks[16] */ 110 PCLK_TCPWM1_CLOCKS17 = 0x013Eu, /* tcpwm[1].clocks[17] */ 111 PCLK_TCPWM1_CLOCKS18 = 0x013Fu, /* tcpwm[1].clocks[18] */ 112 PCLK_TCPWM1_CLOCKS19 = 0x0140u, /* tcpwm[1].clocks[19] */ 113 PCLK_TCPWM1_CLOCKS20 = 0x0141u, /* tcpwm[1].clocks[20] */ 114 PCLK_TCPWM1_CLOCKS21 = 0x0142u, /* tcpwm[1].clocks[21] */ 115 PCLK_TCPWM1_CLOCKS22 = 0x0143u, /* tcpwm[1].clocks[22] */ 116 PCLK_TCPWM1_CLOCKS23 = 0x0144u, /* tcpwm[1].clocks[23] */ 117 PCLK_TCPWM1_CLOCKS24 = 0x0145u, /* tcpwm[1].clocks[24] */ 118 PCLK_TCPWM1_CLOCKS25 = 0x0146u, /* tcpwm[1].clocks[25] */ 119 PCLK_TCPWM1_CLOCKS26 = 0x0147u, /* tcpwm[1].clocks[26] */ 120 PCLK_TCPWM1_CLOCKS27 = 0x0148u, /* tcpwm[1].clocks[27] */ 121 PCLK_TCPWM1_CLOCKS28 = 0x0149u, /* tcpwm[1].clocks[28] */ 122 PCLK_TCPWM1_CLOCKS29 = 0x014Au, /* tcpwm[1].clocks[29] */ 123 PCLK_TCPWM1_CLOCKS30 = 0x014Bu, /* tcpwm[1].clocks[30] */ 124 PCLK_TCPWM1_CLOCKS31 = 0x014Cu, /* tcpwm[1].clocks[31] */ 125 PCLK_TCPWM1_CLOCKS32 = 0x014Du, /* tcpwm[1].clocks[32] */ 126 PCLK_TCPWM1_CLOCKS33 = 0x014Eu, /* tcpwm[1].clocks[33] */ 127 PCLK_TCPWM1_CLOCKS34 = 0x014Fu, /* tcpwm[1].clocks[34] */ 128 PCLK_TCPWM1_CLOCKS35 = 0x0150u, /* tcpwm[1].clocks[35] */ 129 PCLK_TCPWM1_CLOCKS36 = 0x0151u, /* tcpwm[1].clocks[36] */ 130 PCLK_TCPWM1_CLOCKS37 = 0x0152u, /* tcpwm[1].clocks[37] */ 131 PCLK_TCPWM1_CLOCKS38 = 0x0153u, /* tcpwm[1].clocks[38] */ 132 PCLK_TCPWM1_CLOCKS39 = 0x0154u, /* tcpwm[1].clocks[39] */ 133 PCLK_TCPWM1_CLOCKS40 = 0x0155u, /* tcpwm[1].clocks[40] */ 134 PCLK_TCPWM1_CLOCKS41 = 0x0156u, /* tcpwm[1].clocks[41] */ 135 PCLK_TCPWM1_CLOCKS42 = 0x0157u, /* tcpwm[1].clocks[42] */ 136 PCLK_TCPWM1_CLOCKS43 = 0x0158u, /* tcpwm[1].clocks[43] */ 137 PCLK_TCPWM1_CLOCKS44 = 0x0159u, /* tcpwm[1].clocks[44] */ 138 PCLK_TCPWM1_CLOCKS45 = 0x015Au, /* tcpwm[1].clocks[45] */ 139 PCLK_TCPWM1_CLOCKS46 = 0x015Bu, /* tcpwm[1].clocks[46] */ 140 PCLK_TCPWM1_CLOCKS47 = 0x015Cu, /* tcpwm[1].clocks[47] */ 141 PCLK_TCPWM1_CLOCKS48 = 0x015Du, /* tcpwm[1].clocks[48] */ 142 PCLK_TCPWM1_CLOCKS49 = 0x015Eu, /* tcpwm[1].clocks[49] */ 143 PCLK_TCPWM1_CLOCKS50 = 0x015Fu, /* tcpwm[1].clocks[50] */ 144 PCLK_TCPWM1_CLOCKS51 = 0x0160u, /* tcpwm[1].clocks[51] */ 145 PCLK_TCPWM1_CLOCKS52 = 0x0161u, /* tcpwm[1].clocks[52] */ 146 PCLK_TCPWM1_CLOCKS53 = 0x0162u, /* tcpwm[1].clocks[53] */ 147 PCLK_TCPWM1_CLOCKS54 = 0x0163u, /* tcpwm[1].clocks[54] */ 148 PCLK_TCPWM1_CLOCKS55 = 0x0164u, /* tcpwm[1].clocks[55] */ 149 PCLK_TCPWM1_CLOCKS56 = 0x0165u, /* tcpwm[1].clocks[56] */ 150 PCLK_TCPWM1_CLOCKS57 = 0x0166u, /* tcpwm[1].clocks[57] */ 151 PCLK_TCPWM1_CLOCKS58 = 0x0167u, /* tcpwm[1].clocks[58] */ 152 PCLK_TCPWM1_CLOCKS59 = 0x0168u, /* tcpwm[1].clocks[59] */ 153 PCLK_TCPWM1_CLOCKS60 = 0x0169u, /* tcpwm[1].clocks[60] */ 154 PCLK_TCPWM1_CLOCKS61 = 0x016Au, /* tcpwm[1].clocks[61] */ 155 PCLK_TCPWM1_CLOCKS62 = 0x016Bu, /* tcpwm[1].clocks[62] */ 156 PCLK_TCPWM1_CLOCKS63 = 0x016Cu, /* tcpwm[1].clocks[63] */ 157 PCLK_TCPWM1_CLOCKS64 = 0x016Du, /* tcpwm[1].clocks[64] */ 158 PCLK_TCPWM1_CLOCKS65 = 0x016Eu, /* tcpwm[1].clocks[65] */ 159 PCLK_TCPWM1_CLOCKS66 = 0x016Fu, /* tcpwm[1].clocks[66] */ 160 PCLK_TCPWM1_CLOCKS67 = 0x0170u, /* tcpwm[1].clocks[67] */ 161 PCLK_TCPWM1_CLOCKS68 = 0x0171u, /* tcpwm[1].clocks[68] */ 162 PCLK_TCPWM1_CLOCKS69 = 0x0172u, /* tcpwm[1].clocks[69] */ 163 PCLK_TCPWM1_CLOCKS70 = 0x0173u, /* tcpwm[1].clocks[70] */ 164 PCLK_TCPWM1_CLOCKS71 = 0x0174u, /* tcpwm[1].clocks[71] */ 165 PCLK_TCPWM1_CLOCKS72 = 0x0175u, /* tcpwm[1].clocks[72] */ 166 PCLK_TCPWM1_CLOCKS73 = 0x0176u, /* tcpwm[1].clocks[73] */ 167 PCLK_TCPWM1_CLOCKS74 = 0x0177u, /* tcpwm[1].clocks[74] */ 168 PCLK_TCPWM1_CLOCKS75 = 0x0178u, /* tcpwm[1].clocks[75] */ 169 PCLK_TCPWM1_CLOCKS76 = 0x0179u, /* tcpwm[1].clocks[76] */ 170 PCLK_TCPWM1_CLOCKS77 = 0x017Au, /* tcpwm[1].clocks[77] */ 171 PCLK_TCPWM1_CLOCKS78 = 0x017Bu, /* tcpwm[1].clocks[78] */ 172 PCLK_TCPWM1_CLOCKS79 = 0x017Cu, /* tcpwm[1].clocks[79] */ 173 PCLK_TCPWM1_CLOCKS80 = 0x017Du, /* tcpwm[1].clocks[80] */ 174 PCLK_TCPWM1_CLOCKS81 = 0x017Eu, /* tcpwm[1].clocks[81] */ 175 PCLK_TCPWM1_CLOCKS82 = 0x017Fu, /* tcpwm[1].clocks[82] */ 176 PCLK_TCPWM1_CLOCKS83 = 0x0180u, /* tcpwm[1].clocks[83] */ 177 PCLK_TCPWM1_CLOCKS256 = 0x0181u, /* tcpwm[1].clocks[256] */ 178 PCLK_TCPWM1_CLOCKS257 = 0x0182u, /* tcpwm[1].clocks[257] */ 179 PCLK_TCPWM1_CLOCKS258 = 0x0183u, /* tcpwm[1].clocks[258] */ 180 PCLK_TCPWM1_CLOCKS259 = 0x0184u, /* tcpwm[1].clocks[259] */ 181 PCLK_TCPWM1_CLOCKS260 = 0x0185u, /* tcpwm[1].clocks[260] */ 182 PCLK_TCPWM1_CLOCKS261 = 0x0186u, /* tcpwm[1].clocks[261] */ 183 PCLK_TCPWM1_CLOCKS262 = 0x0187u, /* tcpwm[1].clocks[262] */ 184 PCLK_TCPWM1_CLOCKS263 = 0x0188u, /* tcpwm[1].clocks[263] */ 185 PCLK_TCPWM1_CLOCKS264 = 0x0189u, /* tcpwm[1].clocks[264] */ 186 PCLK_TCPWM1_CLOCKS265 = 0x018Au, /* tcpwm[1].clocks[265] */ 187 PCLK_TCPWM1_CLOCKS266 = 0x018Bu, /* tcpwm[1].clocks[266] */ 188 PCLK_TCPWM1_CLOCKS267 = 0x018Cu, /* tcpwm[1].clocks[267] */ 189 PCLK_TCPWM1_CLOCKS512 = 0x018Du, /* tcpwm[1].clocks[512] */ 190 PCLK_TCPWM1_CLOCKS513 = 0x018Eu, /* tcpwm[1].clocks[513] */ 191 PCLK_TCPWM1_CLOCKS514 = 0x018Fu, /* tcpwm[1].clocks[514] */ 192 PCLK_TCPWM1_CLOCKS515 = 0x0190u, /* tcpwm[1].clocks[515] */ 193 PCLK_TCPWM1_CLOCKS516 = 0x0191u, /* tcpwm[1].clocks[516] */ 194 PCLK_TCPWM1_CLOCKS517 = 0x0192u, /* tcpwm[1].clocks[517] */ 195 PCLK_TCPWM1_CLOCKS518 = 0x0193u, /* tcpwm[1].clocks[518] */ 196 PCLK_TCPWM1_CLOCKS519 = 0x0194u, /* tcpwm[1].clocks[519] */ 197 PCLK_TCPWM1_CLOCKS520 = 0x0195u, /* tcpwm[1].clocks[520] */ 198 PCLK_TCPWM1_CLOCKS521 = 0x0196u, /* tcpwm[1].clocks[521] */ 199 PCLK_TCPWM1_CLOCKS522 = 0x0197u, /* tcpwm[1].clocks[522] */ 200 PCLK_TCPWM1_CLOCKS523 = 0x0198u, /* tcpwm[1].clocks[523] */ 201 PCLK_TCPWM1_CLOCKS524 = 0x0199u /* tcpwm[1].clocks[524] */ 202 } en_clk_dst_t; 203 204 /* Trigger Group */ 205 /* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. 206 * Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. 207 */ 208 /* Trigger Group Inputs */ 209 /* Trigger Input Group 0 - P-DMA0[0:15] Request Assignments */ 210 typedef enum 211 { 212 TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ 213 TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ 214 TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ 215 TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ 216 TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ 217 TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ 218 TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ 219 TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ 220 TRIG_IN_MUX_0_PDMA0_TR_OUT8 = 0x00000009u, /* cpuss.dw0_tr_out[8] */ 221 TRIG_IN_MUX_0_PDMA0_TR_OUT9 = 0x0000000Au, /* cpuss.dw0_tr_out[9] */ 222 TRIG_IN_MUX_0_PDMA0_TR_OUT10 = 0x0000000Bu, /* cpuss.dw0_tr_out[10] */ 223 TRIG_IN_MUX_0_PDMA0_TR_OUT11 = 0x0000000Cu, /* cpuss.dw0_tr_out[11] */ 224 TRIG_IN_MUX_0_PDMA0_TR_OUT12 = 0x0000000Du, /* cpuss.dw0_tr_out[12] */ 225 TRIG_IN_MUX_0_PDMA0_TR_OUT13 = 0x0000000Eu, /* cpuss.dw0_tr_out[13] */ 226 TRIG_IN_MUX_0_PDMA0_TR_OUT14 = 0x0000000Fu, /* cpuss.dw0_tr_out[14] */ 227 TRIG_IN_MUX_0_PDMA0_TR_OUT15 = 0x00000010u, /* cpuss.dw0_tr_out[15] */ 228 TRIG_IN_MUX_0_PDMA0_TR_OUT16 = 0x00000011u, /* cpuss.dw0_tr_out[16] */ 229 TRIG_IN_MUX_0_PDMA0_TR_OUT17 = 0x00000012u, /* cpuss.dw0_tr_out[17] */ 230 TRIG_IN_MUX_0_PDMA0_TR_OUT18 = 0x00000013u, /* cpuss.dw0_tr_out[18] */ 231 TRIG_IN_MUX_0_PDMA0_TR_OUT19 = 0x00000014u, /* cpuss.dw0_tr_out[19] */ 232 TRIG_IN_MUX_0_PDMA0_TR_OUT20 = 0x00000015u, /* cpuss.dw0_tr_out[20] */ 233 TRIG_IN_MUX_0_PDMA0_TR_OUT21 = 0x00000016u, /* cpuss.dw0_tr_out[21] */ 234 TRIG_IN_MUX_0_PDMA0_TR_OUT22 = 0x00000017u, /* cpuss.dw0_tr_out[22] */ 235 TRIG_IN_MUX_0_PDMA0_TR_OUT23 = 0x00000018u, /* cpuss.dw0_tr_out[23] */ 236 TRIG_IN_MUX_0_PDMA0_TR_OUT24 = 0x00000019u, /* cpuss.dw0_tr_out[24] */ 237 TRIG_IN_MUX_0_PDMA0_TR_OUT25 = 0x0000001Au, /* cpuss.dw0_tr_out[25] */ 238 TRIG_IN_MUX_0_PDMA0_TR_OUT26 = 0x0000001Bu, /* cpuss.dw0_tr_out[26] */ 239 TRIG_IN_MUX_0_PDMA0_TR_OUT27 = 0x0000001Cu, /* cpuss.dw0_tr_out[27] */ 240 TRIG_IN_MUX_0_PDMA0_TR_OUT28 = 0x0000001Du, /* cpuss.dw0_tr_out[28] */ 241 TRIG_IN_MUX_0_PDMA0_TR_OUT29 = 0x0000001Eu, /* cpuss.dw0_tr_out[29] */ 242 TRIG_IN_MUX_0_PDMA0_TR_OUT30 = 0x0000001Fu, /* cpuss.dw0_tr_out[30] */ 243 TRIG_IN_MUX_0_PDMA0_TR_OUT31 = 0x00000020u, /* cpuss.dw0_tr_out[31] */ 244 TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000021u, /* cpuss.dw1_tr_out[0] */ 245 TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x00000022u, /* cpuss.dw1_tr_out[1] */ 246 TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x00000023u, /* cpuss.dw1_tr_out[2] */ 247 TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x00000024u, /* cpuss.dw1_tr_out[3] */ 248 TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x00000025u, /* cpuss.dw1_tr_out[4] */ 249 TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x00000026u, /* cpuss.dw1_tr_out[5] */ 250 TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x00000027u, /* cpuss.dw1_tr_out[6] */ 251 TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000028u, /* cpuss.dw1_tr_out[7] */ 252 TRIG_IN_MUX_0_PDMA1_TR_OUT8 = 0x00000029u, /* cpuss.dw1_tr_out[8] */ 253 TRIG_IN_MUX_0_PDMA1_TR_OUT9 = 0x0000002Au, /* cpuss.dw1_tr_out[9] */ 254 TRIG_IN_MUX_0_PDMA1_TR_OUT10 = 0x0000002Bu, /* cpuss.dw1_tr_out[10] */ 255 TRIG_IN_MUX_0_PDMA1_TR_OUT11 = 0x0000002Cu, /* cpuss.dw1_tr_out[11] */ 256 TRIG_IN_MUX_0_PDMA1_TR_OUT12 = 0x0000002Du, /* cpuss.dw1_tr_out[12] */ 257 TRIG_IN_MUX_0_PDMA1_TR_OUT13 = 0x0000002Eu, /* cpuss.dw1_tr_out[13] */ 258 TRIG_IN_MUX_0_PDMA1_TR_OUT14 = 0x0000002Fu, /* cpuss.dw1_tr_out[14] */ 259 TRIG_IN_MUX_0_PDMA1_TR_OUT15 = 0x00000030u, /* cpuss.dw1_tr_out[15] */ 260 TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000031u, /* cpuss.dmac_tr_out[0] */ 261 TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x00000032u, /* cpuss.dmac_tr_out[1] */ 262 TRIG_IN_MUX_0_MDMA_TR_OUT2 = 0x00000033u, /* cpuss.dmac_tr_out[2] */ 263 TRIG_IN_MUX_0_MDMA_TR_OUT3 = 0x00000034u, /* cpuss.dmac_tr_out[3] */ 264 TRIG_IN_MUX_0_MDMA_TR_OUT4 = 0x00000035u, /* cpuss.dmac_tr_out[4] */ 265 TRIG_IN_MUX_0_MDMA_TR_OUT5 = 0x00000036u, /* cpuss.dmac_tr_out[5] */ 266 TRIG_IN_MUX_0_MDMA_TR_OUT6 = 0x00000037u, /* cpuss.dmac_tr_out[6] */ 267 TRIG_IN_MUX_0_MDMA_TR_OUT7 = 0x00000038u, /* cpuss.dmac_tr_out[7] */ 268 TRIG_IN_MUX_0_CAN0_TT_TR_OUT0 = 0x00000039u, /* canfd[0].tr_tmp_rtp_out[0] */ 269 TRIG_IN_MUX_0_CAN0_TT_TR_OUT1 = 0x0000003Au, /* canfd[0].tr_tmp_rtp_out[1] */ 270 TRIG_IN_MUX_0_CAN0_TT_TR_OUT2 = 0x0000003Bu, /* canfd[0].tr_tmp_rtp_out[2] */ 271 TRIG_IN_MUX_0_CAN0_TT_TR_OUT3 = 0x0000003Cu, /* canfd[0].tr_tmp_rtp_out[3] */ 272 TRIG_IN_MUX_0_CAN0_TT_TR_OUT4 = 0x0000003Du, /* canfd[0].tr_tmp_rtp_out[4] */ 273 TRIG_IN_MUX_0_CAN1_TT_TR_OUT0 = 0x0000003Eu, /* canfd[1].tr_tmp_rtp_out[0] */ 274 TRIG_IN_MUX_0_CAN1_TT_TR_OUT1 = 0x0000003Fu, /* canfd[1].tr_tmp_rtp_out[1] */ 275 TRIG_IN_MUX_0_CAN1_TT_TR_OUT2 = 0x00000040u, /* canfd[1].tr_tmp_rtp_out[2] */ 276 TRIG_IN_MUX_0_CAN1_TT_TR_OUT3 = 0x00000041u, /* canfd[1].tr_tmp_rtp_out[3] */ 277 TRIG_IN_MUX_0_CAN1_TT_TR_OUT4 = 0x00000042u, /* canfd[1].tr_tmp_rtp_out[4] */ 278 TRIG_IN_MUX_0_FLEXRAY_TT_TR_OUT = 0x00000043u, /* flexray[0].tr_tint0_out */ 279 TRIG_IN_MUX_0_HSIOM_IO_INPUT0 = 0x00000044u, /* peri.tr_io_input[0] */ 280 TRIG_IN_MUX_0_HSIOM_IO_INPUT1 = 0x00000045u, /* peri.tr_io_input[1] */ 281 TRIG_IN_MUX_0_HSIOM_IO_INPUT2 = 0x00000046u, /* peri.tr_io_input[2] */ 282 TRIG_IN_MUX_0_HSIOM_IO_INPUT3 = 0x00000047u, /* peri.tr_io_input[3] */ 283 TRIG_IN_MUX_0_HSIOM_IO_INPUT4 = 0x00000048u, /* peri.tr_io_input[4] */ 284 TRIG_IN_MUX_0_HSIOM_IO_INPUT5 = 0x00000049u, /* peri.tr_io_input[5] */ 285 TRIG_IN_MUX_0_HSIOM_IO_INPUT6 = 0x0000004Au, /* peri.tr_io_input[6] */ 286 TRIG_IN_MUX_0_HSIOM_IO_INPUT7 = 0x0000004Bu, /* peri.tr_io_input[7] */ 287 TRIG_IN_MUX_0_HSIOM_IO_INPUT8 = 0x0000004Cu, /* peri.tr_io_input[8] */ 288 TRIG_IN_MUX_0_HSIOM_IO_INPUT9 = 0x0000004Du, /* peri.tr_io_input[9] */ 289 TRIG_IN_MUX_0_HSIOM_IO_INPUT10 = 0x0000004Eu, /* peri.tr_io_input[10] */ 290 TRIG_IN_MUX_0_HSIOM_IO_INPUT11 = 0x0000004Fu, /* peri.tr_io_input[11] */ 291 TRIG_IN_MUX_0_HSIOM_IO_INPUT12 = 0x00000050u, /* peri.tr_io_input[12] */ 292 TRIG_IN_MUX_0_HSIOM_IO_INPUT13 = 0x00000051u, /* peri.tr_io_input[13] */ 293 TRIG_IN_MUX_0_HSIOM_IO_INPUT14 = 0x00000052u, /* peri.tr_io_input[14] */ 294 TRIG_IN_MUX_0_HSIOM_IO_INPUT15 = 0x00000053u, /* peri.tr_io_input[15] */ 295 TRIG_IN_MUX_0_HSIOM_IO_INPUT16 = 0x00000054u, /* peri.tr_io_input[16] */ 296 TRIG_IN_MUX_0_HSIOM_IO_INPUT17 = 0x00000055u, /* peri.tr_io_input[17] */ 297 TRIG_IN_MUX_0_HSIOM_IO_INPUT18 = 0x00000056u, /* peri.tr_io_input[18] */ 298 TRIG_IN_MUX_0_HSIOM_IO_INPUT19 = 0x00000057u, /* peri.tr_io_input[19] */ 299 TRIG_IN_MUX_0_HSIOM_IO_INPUT20 = 0x00000058u, /* peri.tr_io_input[20] */ 300 TRIG_IN_MUX_0_HSIOM_IO_INPUT21 = 0x00000059u, /* peri.tr_io_input[21] */ 301 TRIG_IN_MUX_0_HSIOM_IO_INPUT22 = 0x0000005Au, /* peri.tr_io_input[22] */ 302 TRIG_IN_MUX_0_HSIOM_IO_INPUT23 = 0x0000005Bu, /* peri.tr_io_input[23] */ 303 TRIG_IN_MUX_0_FAULT_TR_OUT0 = 0x0000005Cu, /* cpuss.tr_fault[0] */ 304 TRIG_IN_MUX_0_FAULT_TR_OUT1 = 0x0000005Du, /* cpuss.tr_fault[1] */ 305 TRIG_IN_MUX_0_FAULT_TR_OUT2 = 0x0000005Eu, /* cpuss.tr_fault[2] */ 306 TRIG_IN_MUX_0_FAULT_TR_OUT3 = 0x0000005Fu /* cpuss.tr_fault[3] */ 307 } en_trig_input_pdma0_tr_0_t; 308 309 /* Trigger Input Group 1 - P-DMA0[16:31] Request Assignments */ 310 typedef enum 311 { 312 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT00 = 0x00000101u, /* tcpwm[0].tr_out0[0] */ 313 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT01 = 0x00000102u, /* tcpwm[0].tr_out0[1] */ 314 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT02 = 0x00000103u, /* tcpwm[0].tr_out0[2] */ 315 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT00 = 0x00000104u, /* tcpwm[0].tr_out0[256] */ 316 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT01 = 0x00000105u, /* tcpwm[0].tr_out0[257] */ 317 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT02 = 0x00000106u, /* tcpwm[0].tr_out0[258] */ 318 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT00 = 0x00000107u, /* tcpwm[0].tr_out0[512] */ 319 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT01 = 0x00000108u, /* tcpwm[0].tr_out0[513] */ 320 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT02 = 0x00000109u, /* tcpwm[0].tr_out0[514] */ 321 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT00 = 0x0000010Au, /* tcpwm[1].tr_out0[0] */ 322 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT01 = 0x0000010Bu, /* tcpwm[1].tr_out0[1] */ 323 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT02 = 0x0000010Cu, /* tcpwm[1].tr_out0[2] */ 324 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT03 = 0x0000010Du, /* tcpwm[1].tr_out0[3] */ 325 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT04 = 0x0000010Eu, /* tcpwm[1].tr_out0[4] */ 326 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT05 = 0x0000010Fu, /* tcpwm[1].tr_out0[5] */ 327 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT06 = 0x00000110u, /* tcpwm[1].tr_out0[6] */ 328 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT07 = 0x00000111u, /* tcpwm[1].tr_out0[7] */ 329 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT08 = 0x00000112u, /* tcpwm[1].tr_out0[8] */ 330 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT09 = 0x00000113u, /* tcpwm[1].tr_out0[9] */ 331 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT010 = 0x00000114u, /* tcpwm[1].tr_out0[10] */ 332 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT011 = 0x00000115u, /* tcpwm[1].tr_out0[11] */ 333 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT012 = 0x00000116u, /* tcpwm[1].tr_out0[12] */ 334 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT013 = 0x00000117u, /* tcpwm[1].tr_out0[13] */ 335 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT014 = 0x00000118u, /* tcpwm[1].tr_out0[14] */ 336 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT015 = 0x00000119u, /* tcpwm[1].tr_out0[15] */ 337 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT016 = 0x0000011Au, /* tcpwm[1].tr_out0[16] */ 338 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT017 = 0x0000011Bu, /* tcpwm[1].tr_out0[17] */ 339 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT018 = 0x0000011Cu, /* tcpwm[1].tr_out0[18] */ 340 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT019 = 0x0000011Du, /* tcpwm[1].tr_out0[19] */ 341 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT020 = 0x0000011Eu, /* tcpwm[1].tr_out0[20] */ 342 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT021 = 0x0000011Fu, /* tcpwm[1].tr_out0[21] */ 343 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT022 = 0x00000120u, /* tcpwm[1].tr_out0[22] */ 344 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT023 = 0x00000121u, /* tcpwm[1].tr_out0[23] */ 345 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT024 = 0x00000122u, /* tcpwm[1].tr_out0[24] */ 346 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT025 = 0x00000123u, /* tcpwm[1].tr_out0[25] */ 347 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT026 = 0x00000124u, /* tcpwm[1].tr_out0[26] */ 348 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT027 = 0x00000125u, /* tcpwm[1].tr_out0[27] */ 349 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT028 = 0x00000126u, /* tcpwm[1].tr_out0[28] */ 350 TRIG_IN_MUX_1_TCPWM1_16_TR_OUT029 = 0x00000127u, /* tcpwm[1].tr_out0[29] */ 351 TRIG_IN_MUX_1_TCPWM1_16M_TR_OUT00 = 0x00000128u, /* tcpwm[1].tr_out0[256] */ 352 TRIG_IN_MUX_1_TCPWM1_16M_TR_OUT01 = 0x00000129u, /* tcpwm[1].tr_out0[257] */ 353 TRIG_IN_MUX_1_TCPWM1_16M_TR_OUT02 = 0x0000012Au, /* tcpwm[1].tr_out0[258] */ 354 TRIG_IN_MUX_1_TCPWM1_16M_TR_OUT03 = 0x0000012Bu, /* tcpwm[1].tr_out0[259] */ 355 TRIG_IN_MUX_1_TCPWM1_16M_TR_OUT04 = 0x0000012Cu, /* tcpwm[1].tr_out0[260] */ 356 TRIG_IN_MUX_1_TCPWM1_16M_TR_OUT05 = 0x0000012Du, /* tcpwm[1].tr_out0[261] */ 357 TRIG_IN_MUX_1_TCPWM1_16M_TR_OUT06 = 0x0000012Eu, /* tcpwm[1].tr_out0[262] */ 358 TRIG_IN_MUX_1_TCPWM1_16M_TR_OUT07 = 0x0000012Fu, /* tcpwm[1].tr_out0[263] */ 359 TRIG_IN_MUX_1_TCPWM1_16M_TR_OUT08 = 0x00000130u, /* tcpwm[1].tr_out0[264] */ 360 TRIG_IN_MUX_1_TCPWM1_16M_TR_OUT09 = 0x00000131u, /* tcpwm[1].tr_out0[265] */ 361 TRIG_IN_MUX_1_TCPWM1_16M_TR_OUT010 = 0x00000132u, /* tcpwm[1].tr_out0[266] */ 362 TRIG_IN_MUX_1_TCPWM1_16M_TR_OUT011 = 0x00000133u, /* tcpwm[1].tr_out0[267] */ 363 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT00 = 0x00000134u, /* tcpwm[1].tr_out0[512] */ 364 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT01 = 0x00000135u, /* tcpwm[1].tr_out0[513] */ 365 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT02 = 0x00000136u, /* tcpwm[1].tr_out0[514] */ 366 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT03 = 0x00000137u, /* tcpwm[1].tr_out0[515] */ 367 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT04 = 0x00000138u, /* tcpwm[1].tr_out0[516] */ 368 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT05 = 0x00000139u, /* tcpwm[1].tr_out0[517] */ 369 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT06 = 0x0000013Au, /* tcpwm[1].tr_out0[518] */ 370 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT07 = 0x0000013Bu, /* tcpwm[1].tr_out0[519] */ 371 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT08 = 0x0000013Cu, /* tcpwm[1].tr_out0[520] */ 372 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT09 = 0x0000013Du, /* tcpwm[1].tr_out0[521] */ 373 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT010 = 0x0000013Eu, /* tcpwm[1].tr_out0[522] */ 374 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT011 = 0x0000013Fu, /* tcpwm[1].tr_out0[523] */ 375 TRIG_IN_MUX_1_TCPWM1_32_TR_OUT012 = 0x00000140u, /* tcpwm[1].tr_out0[524] */ 376 TRIG_IN_MUX_1_PASS_GEN_TR_OUT0 = 0x00000141u, /* pass[0].tr_sar_gen_out[0] */ 377 TRIG_IN_MUX_1_PASS_GEN_TR_OUT1 = 0x00000142u, /* pass[0].tr_sar_gen_out[1] */ 378 TRIG_IN_MUX_1_PASS_GEN_TR_OUT2 = 0x00000143u, /* pass[0].tr_sar_gen_out[2] */ 379 TRIG_IN_MUX_1_PASS_GEN_TR_OUT3 = 0x00000144u, /* pass[0].tr_sar_gen_out[3] */ 380 TRIG_IN_MUX_1_PASS_GEN_TR_OUT4 = 0x00000145u, /* pass[0].tr_sar_gen_out[4] */ 381 TRIG_IN_MUX_1_PASS_GEN_TR_OUT5 = 0x00000146u, /* pass[0].tr_sar_gen_out[5] */ 382 TRIG_IN_MUX_1_CTI_TR_OUT0 = 0x00000147u, /* cpuss.cti_tr_out[0] */ 383 TRIG_IN_MUX_1_CTI_TR_OUT1 = 0x00000148u, /* cpuss.cti_tr_out[1] */ 384 TRIG_IN_MUX_1_EVTGEN_TR_OUT0 = 0x00000149u, /* evtgen[0].tr_out[0] */ 385 TRIG_IN_MUX_1_EVTGEN_TR_OUT1 = 0x0000014Au, /* evtgen[0].tr_out[1] */ 386 TRIG_IN_MUX_1_EVTGEN_TR_OUT2 = 0x0000014Bu, /* evtgen[0].tr_out[2] */ 387 TRIG_IN_MUX_1_EVTGEN_TR_OUT3 = 0x0000014Cu /* evtgen[0].tr_out[3] */ 388 } en_trig_input_pdma0_tr_1_t; 389 390 /* Trigger Input Group 2 - P-DMA1[0:15] Request Assignments */ 391 typedef enum 392 { 393 TRIG_IN_MUX_2_PDMA1_TR_OUT0 = 0x00000201u, /* cpuss.dw1_tr_out[0] */ 394 TRIG_IN_MUX_2_PDMA1_TR_OUT1 = 0x00000202u, /* cpuss.dw1_tr_out[1] */ 395 TRIG_IN_MUX_2_PDMA1_TR_OUT2 = 0x00000203u, /* cpuss.dw1_tr_out[2] */ 396 TRIG_IN_MUX_2_PDMA1_TR_OUT3 = 0x00000204u, /* cpuss.dw1_tr_out[3] */ 397 TRIG_IN_MUX_2_PDMA1_TR_OUT4 = 0x00000205u, /* cpuss.dw1_tr_out[4] */ 398 TRIG_IN_MUX_2_PDMA1_TR_OUT5 = 0x00000206u, /* cpuss.dw1_tr_out[5] */ 399 TRIG_IN_MUX_2_PDMA1_TR_OUT6 = 0x00000207u, /* cpuss.dw1_tr_out[6] */ 400 TRIG_IN_MUX_2_PDMA1_TR_OUT7 = 0x00000208u, /* cpuss.dw1_tr_out[7] */ 401 TRIG_IN_MUX_2_PDMA1_TR_OUT8 = 0x00000209u, /* cpuss.dw1_tr_out[8] */ 402 TRIG_IN_MUX_2_PDMA1_TR_OUT9 = 0x0000020Au, /* cpuss.dw1_tr_out[9] */ 403 TRIG_IN_MUX_2_PDMA1_TR_OUT10 = 0x0000020Bu, /* cpuss.dw1_tr_out[10] */ 404 TRIG_IN_MUX_2_PDMA1_TR_OUT11 = 0x0000020Cu, /* cpuss.dw1_tr_out[11] */ 405 TRIG_IN_MUX_2_PDMA1_TR_OUT12 = 0x0000020Du, /* cpuss.dw1_tr_out[12] */ 406 TRIG_IN_MUX_2_PDMA1_TR_OUT13 = 0x0000020Eu, /* cpuss.dw1_tr_out[13] */ 407 TRIG_IN_MUX_2_PDMA1_TR_OUT14 = 0x0000020Fu, /* cpuss.dw1_tr_out[14] */ 408 TRIG_IN_MUX_2_PDMA1_TR_OUT15 = 0x00000210u, /* cpuss.dw1_tr_out[15] */ 409 TRIG_IN_MUX_2_PDMA0_TR_OUT0 = 0x00000211u, /* cpuss.dw0_tr_out[0] */ 410 TRIG_IN_MUX_2_PDMA0_TR_OUT1 = 0x00000212u, /* cpuss.dw0_tr_out[1] */ 411 TRIG_IN_MUX_2_PDMA0_TR_OUT2 = 0x00000213u, /* cpuss.dw0_tr_out[2] */ 412 TRIG_IN_MUX_2_PDMA0_TR_OUT3 = 0x00000214u, /* cpuss.dw0_tr_out[3] */ 413 TRIG_IN_MUX_2_PDMA0_TR_OUT4 = 0x00000215u, /* cpuss.dw0_tr_out[4] */ 414 TRIG_IN_MUX_2_PDMA0_TR_OUT5 = 0x00000216u, /* cpuss.dw0_tr_out[5] */ 415 TRIG_IN_MUX_2_PDMA0_TR_OUT6 = 0x00000217u, /* cpuss.dw0_tr_out[6] */ 416 TRIG_IN_MUX_2_PDMA0_TR_OUT7 = 0x00000218u, /* cpuss.dw0_tr_out[7] */ 417 TRIG_IN_MUX_2_PDMA0_TR_OUT8 = 0x00000219u, /* cpuss.dw0_tr_out[8] */ 418 TRIG_IN_MUX_2_PDMA0_TR_OUT9 = 0x0000021Au, /* cpuss.dw0_tr_out[9] */ 419 TRIG_IN_MUX_2_PDMA0_TR_OUT10 = 0x0000021Bu, /* cpuss.dw0_tr_out[10] */ 420 TRIG_IN_MUX_2_PDMA0_TR_OUT11 = 0x0000021Cu, /* cpuss.dw0_tr_out[11] */ 421 TRIG_IN_MUX_2_PDMA0_TR_OUT12 = 0x0000021Du, /* cpuss.dw0_tr_out[12] */ 422 TRIG_IN_MUX_2_PDMA0_TR_OUT13 = 0x0000021Eu, /* cpuss.dw0_tr_out[13] */ 423 TRIG_IN_MUX_2_PDMA0_TR_OUT14 = 0x0000021Fu, /* cpuss.dw0_tr_out[14] */ 424 TRIG_IN_MUX_2_PDMA0_TR_OUT15 = 0x00000220u, /* cpuss.dw0_tr_out[15] */ 425 TRIG_IN_MUX_2_PDMA0_TR_OUT16 = 0x00000221u, /* cpuss.dw0_tr_out[16] */ 426 TRIG_IN_MUX_2_PDMA0_TR_OUT17 = 0x00000222u, /* cpuss.dw0_tr_out[17] */ 427 TRIG_IN_MUX_2_PDMA0_TR_OUT18 = 0x00000223u, /* cpuss.dw0_tr_out[18] */ 428 TRIG_IN_MUX_2_PDMA0_TR_OUT19 = 0x00000224u, /* cpuss.dw0_tr_out[19] */ 429 TRIG_IN_MUX_2_PDMA0_TR_OUT20 = 0x00000225u, /* cpuss.dw0_tr_out[20] */ 430 TRIG_IN_MUX_2_PDMA0_TR_OUT21 = 0x00000226u, /* cpuss.dw0_tr_out[21] */ 431 TRIG_IN_MUX_2_PDMA0_TR_OUT22 = 0x00000227u, /* cpuss.dw0_tr_out[22] */ 432 TRIG_IN_MUX_2_PDMA0_TR_OUT23 = 0x00000228u, /* cpuss.dw0_tr_out[23] */ 433 TRIG_IN_MUX_2_PDMA0_TR_OUT24 = 0x00000229u, /* cpuss.dw0_tr_out[24] */ 434 TRIG_IN_MUX_2_PDMA0_TR_OUT25 = 0x0000022Au, /* cpuss.dw0_tr_out[25] */ 435 TRIG_IN_MUX_2_PDMA0_TR_OUT26 = 0x0000022Bu, /* cpuss.dw0_tr_out[26] */ 436 TRIG_IN_MUX_2_PDMA0_TR_OUT27 = 0x0000022Cu, /* cpuss.dw0_tr_out[27] */ 437 TRIG_IN_MUX_2_PDMA0_TR_OUT28 = 0x0000022Du, /* cpuss.dw0_tr_out[28] */ 438 TRIG_IN_MUX_2_PDMA0_TR_OUT29 = 0x0000022Eu, /* cpuss.dw0_tr_out[29] */ 439 TRIG_IN_MUX_2_PDMA0_TR_OUT30 = 0x0000022Fu, /* cpuss.dw0_tr_out[30] */ 440 TRIG_IN_MUX_2_PDMA0_TR_OUT31 = 0x00000230u, /* cpuss.dw0_tr_out[31] */ 441 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT030 = 0x00000231u, /* tcpwm[1].tr_out0[30] */ 442 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT031 = 0x00000232u, /* tcpwm[1].tr_out0[31] */ 443 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT032 = 0x00000233u, /* tcpwm[1].tr_out0[32] */ 444 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT033 = 0x00000234u, /* tcpwm[1].tr_out0[33] */ 445 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT034 = 0x00000235u, /* tcpwm[1].tr_out0[34] */ 446 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT035 = 0x00000236u, /* tcpwm[1].tr_out0[35] */ 447 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT036 = 0x00000237u, /* tcpwm[1].tr_out0[36] */ 448 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT037 = 0x00000238u, /* tcpwm[1].tr_out0[37] */ 449 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT038 = 0x00000239u, /* tcpwm[1].tr_out0[38] */ 450 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT039 = 0x0000023Au, /* tcpwm[1].tr_out0[39] */ 451 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT040 = 0x0000023Bu, /* tcpwm[1].tr_out0[40] */ 452 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT041 = 0x0000023Cu, /* tcpwm[1].tr_out0[41] */ 453 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT042 = 0x0000023Du, /* tcpwm[1].tr_out0[42] */ 454 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT043 = 0x0000023Eu, /* tcpwm[1].tr_out0[43] */ 455 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT044 = 0x0000023Fu, /* tcpwm[1].tr_out0[44] */ 456 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT045 = 0x00000240u, /* tcpwm[1].tr_out0[45] */ 457 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT046 = 0x00000241u, /* tcpwm[1].tr_out0[46] */ 458 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT047 = 0x00000242u, /* tcpwm[1].tr_out0[47] */ 459 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT048 = 0x00000243u, /* tcpwm[1].tr_out0[48] */ 460 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT049 = 0x00000244u, /* tcpwm[1].tr_out0[49] */ 461 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT050 = 0x00000245u, /* tcpwm[1].tr_out0[50] */ 462 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT051 = 0x00000246u, /* tcpwm[1].tr_out0[51] */ 463 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT052 = 0x00000247u, /* tcpwm[1].tr_out0[52] */ 464 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT053 = 0x00000248u, /* tcpwm[1].tr_out0[53] */ 465 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT054 = 0x00000249u, /* tcpwm[1].tr_out0[54] */ 466 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT055 = 0x0000024Au, /* tcpwm[1].tr_out0[55] */ 467 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT056 = 0x0000024Bu, /* tcpwm[1].tr_out0[56] */ 468 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT057 = 0x0000024Cu, /* tcpwm[1].tr_out0[57] */ 469 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT058 = 0x0000024Du, /* tcpwm[1].tr_out0[58] */ 470 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT059 = 0x0000024Eu, /* tcpwm[1].tr_out0[59] */ 471 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT060 = 0x0000024Fu, /* tcpwm[1].tr_out0[60] */ 472 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT061 = 0x00000250u, /* tcpwm[1].tr_out0[61] */ 473 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT062 = 0x00000251u, /* tcpwm[1].tr_out0[62] */ 474 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT063 = 0x00000252u, /* tcpwm[1].tr_out0[63] */ 475 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT064 = 0x00000253u, /* tcpwm[1].tr_out0[64] */ 476 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT065 = 0x00000254u, /* tcpwm[1].tr_out0[65] */ 477 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT066 = 0x00000255u, /* tcpwm[1].tr_out0[66] */ 478 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT067 = 0x00000256u, /* tcpwm[1].tr_out0[67] */ 479 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT068 = 0x00000257u, /* tcpwm[1].tr_out0[68] */ 480 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT069 = 0x00000258u, /* tcpwm[1].tr_out0[69] */ 481 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT070 = 0x00000259u, /* tcpwm[1].tr_out0[70] */ 482 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT071 = 0x0000025Au, /* tcpwm[1].tr_out0[71] */ 483 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT072 = 0x0000025Bu, /* tcpwm[1].tr_out0[72] */ 484 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT073 = 0x0000025Cu, /* tcpwm[1].tr_out0[73] */ 485 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT074 = 0x0000025Du, /* tcpwm[1].tr_out0[74] */ 486 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT075 = 0x0000025Eu, /* tcpwm[1].tr_out0[75] */ 487 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT076 = 0x0000025Fu, /* tcpwm[1].tr_out0[76] */ 488 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT077 = 0x00000260u, /* tcpwm[1].tr_out0[77] */ 489 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT078 = 0x00000261u, /* tcpwm[1].tr_out0[78] */ 490 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT079 = 0x00000262u, /* tcpwm[1].tr_out0[79] */ 491 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT080 = 0x00000263u, /* tcpwm[1].tr_out0[80] */ 492 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT081 = 0x00000264u, /* tcpwm[1].tr_out0[81] */ 493 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT082 = 0x00000265u, /* tcpwm[1].tr_out0[82] */ 494 TRIG_IN_MUX_2_TCPWM1_16_TR_OUT083 = 0x00000266u, /* tcpwm[1].tr_out0[83] */ 495 TRIG_IN_MUX_2_HSIOM_IO_INPUT24 = 0x00000267u, /* peri.tr_io_input[24] */ 496 TRIG_IN_MUX_2_HSIOM_IO_INPUT25 = 0x00000268u, /* peri.tr_io_input[25] */ 497 TRIG_IN_MUX_2_HSIOM_IO_INPUT26 = 0x00000269u, /* peri.tr_io_input[26] */ 498 TRIG_IN_MUX_2_HSIOM_IO_INPUT27 = 0x0000026Au, /* peri.tr_io_input[27] */ 499 TRIG_IN_MUX_2_HSIOM_IO_INPUT28 = 0x0000026Bu, /* peri.tr_io_input[28] */ 500 TRIG_IN_MUX_2_HSIOM_IO_INPUT29 = 0x0000026Cu, /* peri.tr_io_input[29] */ 501 TRIG_IN_MUX_2_HSIOM_IO_INPUT30 = 0x0000026Du, /* peri.tr_io_input[30] */ 502 TRIG_IN_MUX_2_HSIOM_IO_INPUT31 = 0x0000026Eu, /* peri.tr_io_input[31] */ 503 TRIG_IN_MUX_2_HSIOM_IO_INPUT32 = 0x0000026Fu, /* peri.tr_io_input[32] */ 504 TRIG_IN_MUX_2_HSIOM_IO_INPUT33 = 0x00000270u, /* peri.tr_io_input[33] */ 505 TRIG_IN_MUX_2_HSIOM_IO_INPUT34 = 0x00000271u, /* peri.tr_io_input[34] */ 506 TRIG_IN_MUX_2_HSIOM_IO_INPUT35 = 0x00000272u, /* peri.tr_io_input[35] */ 507 TRIG_IN_MUX_2_HSIOM_IO_INPUT36 = 0x00000273u, /* peri.tr_io_input[36] */ 508 TRIG_IN_MUX_2_HSIOM_IO_INPUT37 = 0x00000274u, /* peri.tr_io_input[37] */ 509 TRIG_IN_MUX_2_HSIOM_IO_INPUT38 = 0x00000275u, /* peri.tr_io_input[38] */ 510 TRIG_IN_MUX_2_HSIOM_IO_INPUT39 = 0x00000276u, /* peri.tr_io_input[39] */ 511 TRIG_IN_MUX_2_HSIOM_IO_INPUT40 = 0x00000277u, /* peri.tr_io_input[40] */ 512 TRIG_IN_MUX_2_HSIOM_IO_INPUT41 = 0x00000278u, /* peri.tr_io_input[41] */ 513 TRIG_IN_MUX_2_HSIOM_IO_INPUT42 = 0x00000279u, /* peri.tr_io_input[42] */ 514 TRIG_IN_MUX_2_HSIOM_IO_INPUT43 = 0x0000027Au, /* peri.tr_io_input[43] */ 515 TRIG_IN_MUX_2_HSIOM_IO_INPUT44 = 0x0000027Bu, /* peri.tr_io_input[44] */ 516 TRIG_IN_MUX_2_HSIOM_IO_INPUT45 = 0x0000027Cu, /* peri.tr_io_input[45] */ 517 TRIG_IN_MUX_2_HSIOM_IO_INPUT46 = 0x0000027Du, /* peri.tr_io_input[46] */ 518 TRIG_IN_MUX_2_HSIOM_IO_INPUT47 = 0x0000027Eu /* peri.tr_io_input[47] */ 519 } en_trig_input_pdma1_tr_t; 520 521 /* Trigger Input Group 3 - M-DMA Request Assignments */ 522 typedef enum 523 { 524 TRIG_IN_MUX_3_TCPWM0_16_TR_OUT00 = 0x00000301u, /* tcpwm[0].tr_out0[0] */ 525 TRIG_IN_MUX_3_TCPWM0_16_TR_OUT01 = 0x00000302u, /* tcpwm[0].tr_out0[1] */ 526 TRIG_IN_MUX_3_TCPWM0_16_TR_OUT02 = 0x00000303u, /* tcpwm[0].tr_out0[2] */ 527 TRIG_IN_MUX_3_TCPWM0_16M_TR_OUT00 = 0x00000304u, /* tcpwm[0].tr_out0[256] */ 528 TRIG_IN_MUX_3_TCPWM0_16M_TR_OUT01 = 0x00000305u, /* tcpwm[0].tr_out0[257] */ 529 TRIG_IN_MUX_3_TCPWM0_16M_TR_OUT02 = 0x00000306u /* tcpwm[0].tr_out0[258] */ 530 } en_trig_input_mdma_t; 531 532 /* Trigger Input Group 4 - */ 533 typedef enum 534 { 535 TRIG_IN_MUX_4_PDMA0_TR_OUT0 = 0x00000401u, /* cpuss.dw0_tr_out[0] */ 536 TRIG_IN_MUX_4_PDMA0_TR_OUT1 = 0x00000402u, /* cpuss.dw0_tr_out[1] */ 537 TRIG_IN_MUX_4_PDMA0_TR_OUT2 = 0x00000403u, /* cpuss.dw0_tr_out[2] */ 538 TRIG_IN_MUX_4_PDMA0_TR_OUT3 = 0x00000404u, /* cpuss.dw0_tr_out[3] */ 539 TRIG_IN_MUX_4_PDMA0_TR_OUT4 = 0x00000405u, /* cpuss.dw0_tr_out[4] */ 540 TRIG_IN_MUX_4_PDMA0_TR_OUT5 = 0x00000406u, /* cpuss.dw0_tr_out[5] */ 541 TRIG_IN_MUX_4_PDMA0_TR_OUT6 = 0x00000407u, /* cpuss.dw0_tr_out[6] */ 542 TRIG_IN_MUX_4_PDMA0_TR_OUT7 = 0x00000408u, /* cpuss.dw0_tr_out[7] */ 543 TRIG_IN_MUX_4_PDMA0_TR_OUT8 = 0x00000409u, /* cpuss.dw0_tr_out[8] */ 544 TRIG_IN_MUX_4_PDMA0_TR_OUT9 = 0x0000040Au, /* cpuss.dw0_tr_out[9] */ 545 TRIG_IN_MUX_4_PDMA0_TR_OUT10 = 0x0000040Bu, /* cpuss.dw0_tr_out[10] */ 546 TRIG_IN_MUX_4_PDMA0_TR_OUT11 = 0x0000040Cu, /* cpuss.dw0_tr_out[11] */ 547 TRIG_IN_MUX_4_PDMA0_TR_OUT12 = 0x0000040Du, /* cpuss.dw0_tr_out[12] */ 548 TRIG_IN_MUX_4_PDMA0_TR_OUT13 = 0x0000040Eu, /* cpuss.dw0_tr_out[13] */ 549 TRIG_IN_MUX_4_PDMA0_TR_OUT14 = 0x0000040Fu, /* cpuss.dw0_tr_out[14] */ 550 TRIG_IN_MUX_4_PDMA0_TR_OUT15 = 0x00000410u, /* cpuss.dw0_tr_out[15] */ 551 TRIG_IN_MUX_4_PDMA0_TR_OUT16 = 0x00000411u, /* cpuss.dw0_tr_out[16] */ 552 TRIG_IN_MUX_4_PDMA0_TR_OUT17 = 0x00000412u, /* cpuss.dw0_tr_out[17] */ 553 TRIG_IN_MUX_4_PDMA0_TR_OUT18 = 0x00000413u, /* cpuss.dw0_tr_out[18] */ 554 TRIG_IN_MUX_4_PDMA0_TR_OUT19 = 0x00000414u, /* cpuss.dw0_tr_out[19] */ 555 TRIG_IN_MUX_4_PDMA0_TR_OUT20 = 0x00000415u, /* cpuss.dw0_tr_out[20] */ 556 TRIG_IN_MUX_4_PDMA0_TR_OUT21 = 0x00000416u, /* cpuss.dw0_tr_out[21] */ 557 TRIG_IN_MUX_4_PDMA0_TR_OUT22 = 0x00000417u, /* cpuss.dw0_tr_out[22] */ 558 TRIG_IN_MUX_4_PDMA0_TR_OUT23 = 0x00000418u, /* cpuss.dw0_tr_out[23] */ 559 TRIG_IN_MUX_4_PDMA0_TR_OUT24 = 0x00000419u, /* cpuss.dw0_tr_out[24] */ 560 TRIG_IN_MUX_4_PDMA0_TR_OUT25 = 0x0000041Au, /* cpuss.dw0_tr_out[25] */ 561 TRIG_IN_MUX_4_PDMA0_TR_OUT26 = 0x0000041Bu, /* cpuss.dw0_tr_out[26] */ 562 TRIG_IN_MUX_4_PDMA0_TR_OUT27 = 0x0000041Cu, /* cpuss.dw0_tr_out[27] */ 563 TRIG_IN_MUX_4_PDMA0_TR_OUT28 = 0x0000041Du, /* cpuss.dw0_tr_out[28] */ 564 TRIG_IN_MUX_4_PDMA0_TR_OUT29 = 0x0000041Eu, /* cpuss.dw0_tr_out[29] */ 565 TRIG_IN_MUX_4_PDMA0_TR_OUT30 = 0x0000041Fu, /* cpuss.dw0_tr_out[30] */ 566 TRIG_IN_MUX_4_PDMA0_TR_OUT31 = 0x00000420u, /* cpuss.dw0_tr_out[31] */ 567 TRIG_IN_MUX_4_PDMA1_TR_OUT0 = 0x00000421u, /* cpuss.dw1_tr_out[0] */ 568 TRIG_IN_MUX_4_PDMA1_TR_OUT1 = 0x00000422u, /* cpuss.dw1_tr_out[1] */ 569 TRIG_IN_MUX_4_PDMA1_TR_OUT2 = 0x00000423u, /* cpuss.dw1_tr_out[2] */ 570 TRIG_IN_MUX_4_PDMA1_TR_OUT3 = 0x00000424u, /* cpuss.dw1_tr_out[3] */ 571 TRIG_IN_MUX_4_PDMA1_TR_OUT4 = 0x00000425u, /* cpuss.dw1_tr_out[4] */ 572 TRIG_IN_MUX_4_PDMA1_TR_OUT5 = 0x00000426u, /* cpuss.dw1_tr_out[5] */ 573 TRIG_IN_MUX_4_PDMA1_TR_OUT6 = 0x00000427u, /* cpuss.dw1_tr_out[6] */ 574 TRIG_IN_MUX_4_PDMA1_TR_OUT7 = 0x00000428u, /* cpuss.dw1_tr_out[7] */ 575 TRIG_IN_MUX_4_PDMA1_TR_OUT8 = 0x00000429u, /* cpuss.dw1_tr_out[8] */ 576 TRIG_IN_MUX_4_PDMA1_TR_OUT9 = 0x0000042Au, /* cpuss.dw1_tr_out[9] */ 577 TRIG_IN_MUX_4_PDMA1_TR_OUT10 = 0x0000042Bu, /* cpuss.dw1_tr_out[10] */ 578 TRIG_IN_MUX_4_PDMA1_TR_OUT11 = 0x0000042Cu, /* cpuss.dw1_tr_out[11] */ 579 TRIG_IN_MUX_4_PDMA1_TR_OUT12 = 0x0000042Du, /* cpuss.dw1_tr_out[12] */ 580 TRIG_IN_MUX_4_PDMA1_TR_OUT13 = 0x0000042Eu, /* cpuss.dw1_tr_out[13] */ 581 TRIG_IN_MUX_4_PDMA1_TR_OUT14 = 0x0000042Fu, /* cpuss.dw1_tr_out[14] */ 582 TRIG_IN_MUX_4_PDMA1_TR_OUT15 = 0x00000430u, /* cpuss.dw1_tr_out[15] */ 583 TRIG_IN_MUX_4_MDMA_TR_OUT0 = 0x00000431u, /* cpuss.dmac_tr_out[0] */ 584 TRIG_IN_MUX_4_MDMA_TR_OUT1 = 0x00000432u, /* cpuss.dmac_tr_out[1] */ 585 TRIG_IN_MUX_4_MDMA_TR_OUT2 = 0x00000433u, /* cpuss.dmac_tr_out[2] */ 586 TRIG_IN_MUX_4_MDMA_TR_OUT3 = 0x00000434u, /* cpuss.dmac_tr_out[3] */ 587 TRIG_IN_MUX_4_MDMA_TR_OUT4 = 0x00000435u, /* cpuss.dmac_tr_out[4] */ 588 TRIG_IN_MUX_4_MDMA_TR_OUT5 = 0x00000436u, /* cpuss.dmac_tr_out[5] */ 589 TRIG_IN_MUX_4_MDMA_TR_OUT6 = 0x00000437u, /* cpuss.dmac_tr_out[6] */ 590 TRIG_IN_MUX_4_MDMA_TR_OUT7 = 0x00000438u, /* cpuss.dmac_tr_out[7] */ 591 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT00 = 0x00000439u, /* tcpwm[0].tr_out0[0] */ 592 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT01 = 0x0000043Au, /* tcpwm[0].tr_out0[1] */ 593 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT02 = 0x0000043Bu, /* tcpwm[0].tr_out0[2] */ 594 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT00 = 0x0000043Cu, /* tcpwm[0].tr_out0[256] */ 595 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT01 = 0x0000043Du, /* tcpwm[0].tr_out0[257] */ 596 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT02 = 0x0000043Eu, /* tcpwm[0].tr_out0[258] */ 597 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT00 = 0x0000043Fu, /* tcpwm[0].tr_out0[512] */ 598 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT01 = 0x00000440u, /* tcpwm[0].tr_out0[513] */ 599 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT02 = 0x00000441u, /* tcpwm[0].tr_out0[514] */ 600 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT00 = 0x00000442u, /* tcpwm[1].tr_out0[0] */ 601 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT01 = 0x00000443u, /* tcpwm[1].tr_out0[1] */ 602 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT02 = 0x00000444u, /* tcpwm[1].tr_out0[2] */ 603 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT03 = 0x00000445u, /* tcpwm[1].tr_out0[3] */ 604 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT04 = 0x00000446u, /* tcpwm[1].tr_out0[4] */ 605 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT05 = 0x00000447u, /* tcpwm[1].tr_out0[5] */ 606 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT06 = 0x00000448u, /* tcpwm[1].tr_out0[6] */ 607 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT07 = 0x00000449u, /* tcpwm[1].tr_out0[7] */ 608 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT08 = 0x0000044Au, /* tcpwm[1].tr_out0[8] */ 609 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT09 = 0x0000044Bu, /* tcpwm[1].tr_out0[9] */ 610 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT010 = 0x0000044Cu, /* tcpwm[1].tr_out0[10] */ 611 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT011 = 0x0000044Du, /* tcpwm[1].tr_out0[11] */ 612 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT012 = 0x0000044Eu, /* tcpwm[1].tr_out0[12] */ 613 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT013 = 0x0000044Fu, /* tcpwm[1].tr_out0[13] */ 614 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT014 = 0x00000450u, /* tcpwm[1].tr_out0[14] */ 615 TRIG_IN_MUX_4_TCPWM1_16_TR_OUT015 = 0x00000451u, /* tcpwm[1].tr_out0[15] */ 616 TRIG_IN_MUX_4_TCPWM1_16M_TR_OUT00 = 0x00000452u, /* tcpwm[1].tr_out0[256] */ 617 TRIG_IN_MUX_4_TCPWM1_16M_TR_OUT01 = 0x00000453u, /* tcpwm[1].tr_out0[257] */ 618 TRIG_IN_MUX_4_TCPWM1_16M_TR_OUT02 = 0x00000454u, /* tcpwm[1].tr_out0[258] */ 619 TRIG_IN_MUX_4_TCPWM1_16M_TR_OUT03 = 0x00000455u, /* tcpwm[1].tr_out0[259] */ 620 TRIG_IN_MUX_4_TCPWM1_16M_TR_OUT04 = 0x00000456u, /* tcpwm[1].tr_out0[260] */ 621 TRIG_IN_MUX_4_TCPWM1_16M_TR_OUT05 = 0x00000457u, /* tcpwm[1].tr_out0[261] */ 622 TRIG_IN_MUX_4_TCPWM1_32_TR_OUT00 = 0x00000458u, /* tcpwm[1].tr_out0[512] */ 623 TRIG_IN_MUX_4_TCPWM1_32_TR_OUT01 = 0x00000459u, /* tcpwm[1].tr_out0[513] */ 624 TRIG_IN_MUX_4_TCPWM1_32_TR_OUT02 = 0x0000045Au, /* tcpwm[1].tr_out0[514] */ 625 TRIG_IN_MUX_4_TCPWM1_32_TR_OUT03 = 0x0000045Bu, /* tcpwm[1].tr_out0[515] */ 626 TRIG_IN_MUX_4_TCPWM1_32_TR_OUT04 = 0x0000045Cu, /* tcpwm[1].tr_out0[516] */ 627 TRIG_IN_MUX_4_TCPWM1_32_TR_OUT05 = 0x0000045Du, /* tcpwm[1].tr_out0[517] */ 628 TRIG_IN_MUX_4_TCPWM1_32_TR_OUT06 = 0x0000045Eu, /* tcpwm[1].tr_out0[518] */ 629 TRIG_IN_MUX_4_SMIF_TX_TR_OUT = 0x0000045Fu, /* smif[0].tr_tx_req */ 630 TRIG_IN_MUX_4_SMIF_RX_TR_OUT = 0x00000460u, /* smif[0].tr_rx_req */ 631 TRIG_IN_MUX_4_I2S0_TX_TR_OUT = 0x00000461u, /* audioss[0].tr_i2s_tx_req */ 632 TRIG_IN_MUX_4_I2S0_RX_TR_OUT = 0x00000462u, /* audioss[0].tr_i2s_rx_req */ 633 TRIG_IN_MUX_4_I2S1_TX_TR_OUT = 0x00000463u, /* audioss[1].tr_i2s_tx_req */ 634 TRIG_IN_MUX_4_I2S1_RX_TR_OUT = 0x00000464u, /* audioss[1].tr_i2s_rx_req */ 635 TRIG_IN_MUX_4_I2S2_TX_TR_OUT = 0x00000465u, /* audioss[2].tr_i2s_tx_req */ 636 TRIG_IN_MUX_4_I2S2_RX_TR_OUT = 0x00000466u /* audioss[2].tr_i2s_rx_req */ 637 } en_trig_input_tcpwm0_out_t; 638 639 /* Trigger Input Group 5 - */ 640 typedef enum 641 { 642 TRIG_IN_MUX_5_TCPWM0_16_TR_OUT00 = 0x00000501u, /* tcpwm[0].tr_out0[0] */ 643 TRIG_IN_MUX_5_TCPWM0_16_TR_OUT01 = 0x00000502u, /* tcpwm[0].tr_out0[1] */ 644 TRIG_IN_MUX_5_TCPWM0_16_TR_OUT02 = 0x00000503u, /* tcpwm[0].tr_out0[2] */ 645 TRIG_IN_MUX_5_TCPWM0_16M_TR_OUT00 = 0x00000504u, /* tcpwm[0].tr_out0[256] */ 646 TRIG_IN_MUX_5_TCPWM0_16M_TR_OUT01 = 0x00000505u, /* tcpwm[0].tr_out0[257] */ 647 TRIG_IN_MUX_5_TCPWM0_16M_TR_OUT02 = 0x00000506u, /* tcpwm[0].tr_out0[258] */ 648 TRIG_IN_MUX_5_TCPWM0_32_TR_OUT00 = 0x00000507u, /* tcpwm[0].tr_out0[512] */ 649 TRIG_IN_MUX_5_TCPWM0_32_TR_OUT01 = 0x00000508u, /* tcpwm[0].tr_out0[513] */ 650 TRIG_IN_MUX_5_TCPWM0_32_TR_OUT02 = 0x00000509u, /* tcpwm[0].tr_out0[514] */ 651 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT00 = 0x0000050Au, /* tcpwm[1].tr_out0[0] */ 652 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT01 = 0x0000050Bu, /* tcpwm[1].tr_out0[1] */ 653 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT02 = 0x0000050Cu, /* tcpwm[1].tr_out0[2] */ 654 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT03 = 0x0000050Du, /* tcpwm[1].tr_out0[3] */ 655 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT04 = 0x0000050Eu, /* tcpwm[1].tr_out0[4] */ 656 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT05 = 0x0000050Fu, /* tcpwm[1].tr_out0[5] */ 657 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT06 = 0x00000510u, /* tcpwm[1].tr_out0[6] */ 658 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT07 = 0x00000511u, /* tcpwm[1].tr_out0[7] */ 659 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT08 = 0x00000512u, /* tcpwm[1].tr_out0[8] */ 660 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT09 = 0x00000513u, /* tcpwm[1].tr_out0[9] */ 661 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT010 = 0x00000514u, /* tcpwm[1].tr_out0[10] */ 662 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT011 = 0x00000515u, /* tcpwm[1].tr_out0[11] */ 663 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT012 = 0x00000516u, /* tcpwm[1].tr_out0[12] */ 664 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT013 = 0x00000517u, /* tcpwm[1].tr_out0[13] */ 665 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT014 = 0x00000518u, /* tcpwm[1].tr_out0[14] */ 666 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT015 = 0x00000519u, /* tcpwm[1].tr_out0[15] */ 667 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT016 = 0x0000051Au, /* tcpwm[1].tr_out0[16] */ 668 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT017 = 0x0000051Bu, /* tcpwm[1].tr_out0[17] */ 669 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT018 = 0x0000051Cu, /* tcpwm[1].tr_out0[18] */ 670 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT019 = 0x0000051Du, /* tcpwm[1].tr_out0[19] */ 671 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT020 = 0x0000051Eu, /* tcpwm[1].tr_out0[20] */ 672 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT021 = 0x0000051Fu, /* tcpwm[1].tr_out0[21] */ 673 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT022 = 0x00000520u, /* tcpwm[1].tr_out0[22] */ 674 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT023 = 0x00000521u, /* tcpwm[1].tr_out0[23] */ 675 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT024 = 0x00000522u, /* tcpwm[1].tr_out0[24] */ 676 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT025 = 0x00000523u, /* tcpwm[1].tr_out0[25] */ 677 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT026 = 0x00000524u, /* tcpwm[1].tr_out0[26] */ 678 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT027 = 0x00000525u, /* tcpwm[1].tr_out0[27] */ 679 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT028 = 0x00000526u, /* tcpwm[1].tr_out0[28] */ 680 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT029 = 0x00000527u, /* tcpwm[1].tr_out0[29] */ 681 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT030 = 0x00000528u, /* tcpwm[1].tr_out0[30] */ 682 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT031 = 0x00000529u, /* tcpwm[1].tr_out0[31] */ 683 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT032 = 0x0000052Au, /* tcpwm[1].tr_out0[32] */ 684 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT033 = 0x0000052Bu, /* tcpwm[1].tr_out0[33] */ 685 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT034 = 0x0000052Cu, /* tcpwm[1].tr_out0[34] */ 686 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT035 = 0x0000052Du, /* tcpwm[1].tr_out0[35] */ 687 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT036 = 0x0000052Eu, /* tcpwm[1].tr_out0[36] */ 688 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT037 = 0x0000052Fu, /* tcpwm[1].tr_out0[37] */ 689 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT038 = 0x00000530u, /* tcpwm[1].tr_out0[38] */ 690 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT039 = 0x00000531u, /* tcpwm[1].tr_out0[39] */ 691 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT040 = 0x00000532u, /* tcpwm[1].tr_out0[40] */ 692 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT041 = 0x00000533u, /* tcpwm[1].tr_out0[41] */ 693 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT042 = 0x00000534u, /* tcpwm[1].tr_out0[42] */ 694 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT043 = 0x00000535u, /* tcpwm[1].tr_out0[43] */ 695 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT044 = 0x00000536u, /* tcpwm[1].tr_out0[44] */ 696 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT045 = 0x00000537u, /* tcpwm[1].tr_out0[45] */ 697 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT046 = 0x00000538u, /* tcpwm[1].tr_out0[46] */ 698 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT047 = 0x00000539u, /* tcpwm[1].tr_out0[47] */ 699 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT048 = 0x0000053Au, /* tcpwm[1].tr_out0[48] */ 700 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT049 = 0x0000053Bu, /* tcpwm[1].tr_out0[49] */ 701 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT050 = 0x0000053Cu, /* tcpwm[1].tr_out0[50] */ 702 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT051 = 0x0000053Du, /* tcpwm[1].tr_out0[51] */ 703 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT052 = 0x0000053Eu, /* tcpwm[1].tr_out0[52] */ 704 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT053 = 0x0000053Fu, /* tcpwm[1].tr_out0[53] */ 705 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT054 = 0x00000540u, /* tcpwm[1].tr_out0[54] */ 706 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT055 = 0x00000541u, /* tcpwm[1].tr_out0[55] */ 707 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT056 = 0x00000542u, /* tcpwm[1].tr_out0[56] */ 708 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT057 = 0x00000543u, /* tcpwm[1].tr_out0[57] */ 709 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT058 = 0x00000544u, /* tcpwm[1].tr_out0[58] */ 710 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT059 = 0x00000545u, /* tcpwm[1].tr_out0[59] */ 711 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT060 = 0x00000546u, /* tcpwm[1].tr_out0[60] */ 712 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT061 = 0x00000547u, /* tcpwm[1].tr_out0[61] */ 713 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT062 = 0x00000548u, /* tcpwm[1].tr_out0[62] */ 714 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT063 = 0x00000549u, /* tcpwm[1].tr_out0[63] */ 715 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT064 = 0x0000054Au, /* tcpwm[1].tr_out0[64] */ 716 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT065 = 0x0000054Bu, /* tcpwm[1].tr_out0[65] */ 717 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT066 = 0x0000054Cu, /* tcpwm[1].tr_out0[66] */ 718 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT067 = 0x0000054Du, /* tcpwm[1].tr_out0[67] */ 719 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT068 = 0x0000054Eu, /* tcpwm[1].tr_out0[68] */ 720 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT069 = 0x0000054Fu, /* tcpwm[1].tr_out0[69] */ 721 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT070 = 0x00000550u, /* tcpwm[1].tr_out0[70] */ 722 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT071 = 0x00000551u, /* tcpwm[1].tr_out0[71] */ 723 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT072 = 0x00000552u, /* tcpwm[1].tr_out0[72] */ 724 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT073 = 0x00000553u, /* tcpwm[1].tr_out0[73] */ 725 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT074 = 0x00000554u, /* tcpwm[1].tr_out0[74] */ 726 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT075 = 0x00000555u, /* tcpwm[1].tr_out0[75] */ 727 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT076 = 0x00000556u, /* tcpwm[1].tr_out0[76] */ 728 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT077 = 0x00000557u, /* tcpwm[1].tr_out0[77] */ 729 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT078 = 0x00000558u, /* tcpwm[1].tr_out0[78] */ 730 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT079 = 0x00000559u, /* tcpwm[1].tr_out0[79] */ 731 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT080 = 0x0000055Au, /* tcpwm[1].tr_out0[80] */ 732 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT081 = 0x0000055Bu, /* tcpwm[1].tr_out0[81] */ 733 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT082 = 0x0000055Cu, /* tcpwm[1].tr_out0[82] */ 734 TRIG_IN_MUX_5_TCPWM1_16_TR_OUT083 = 0x0000055Du, /* tcpwm[1].tr_out0[83] */ 735 TRIG_IN_MUX_5_TCPWM1_16M_TR_OUT00 = 0x0000055Eu, /* tcpwm[1].tr_out0[256] */ 736 TRIG_IN_MUX_5_TCPWM1_16M_TR_OUT01 = 0x0000055Fu, /* tcpwm[1].tr_out0[257] */ 737 TRIG_IN_MUX_5_TCPWM1_16M_TR_OUT02 = 0x00000560u, /* tcpwm[1].tr_out0[258] */ 738 TRIG_IN_MUX_5_TCPWM1_16M_TR_OUT03 = 0x00000561u, /* tcpwm[1].tr_out0[259] */ 739 TRIG_IN_MUX_5_TCPWM1_16M_TR_OUT04 = 0x00000562u, /* tcpwm[1].tr_out0[260] */ 740 TRIG_IN_MUX_5_TCPWM1_16M_TR_OUT05 = 0x00000563u, /* tcpwm[1].tr_out0[261] */ 741 TRIG_IN_MUX_5_TCPWM1_16M_TR_OUT06 = 0x00000564u, /* tcpwm[1].tr_out0[262] */ 742 TRIG_IN_MUX_5_TCPWM1_16M_TR_OUT07 = 0x00000565u, /* tcpwm[1].tr_out0[263] */ 743 TRIG_IN_MUX_5_TCPWM1_16M_TR_OUT08 = 0x00000566u, /* tcpwm[1].tr_out0[264] */ 744 TRIG_IN_MUX_5_TCPWM1_16M_TR_OUT09 = 0x00000567u, /* tcpwm[1].tr_out0[265] */ 745 TRIG_IN_MUX_5_TCPWM1_16M_TR_OUT010 = 0x00000568u, /* tcpwm[1].tr_out0[266] */ 746 TRIG_IN_MUX_5_TCPWM1_16M_TR_OUT011 = 0x00000569u, /* tcpwm[1].tr_out0[267] */ 747 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT00 = 0x0000056Au, /* tcpwm[1].tr_out0[512] */ 748 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT01 = 0x0000056Bu, /* tcpwm[1].tr_out0[513] */ 749 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT02 = 0x0000056Cu, /* tcpwm[1].tr_out0[514] */ 750 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT03 = 0x0000056Du, /* tcpwm[1].tr_out0[515] */ 751 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT04 = 0x0000056Eu, /* tcpwm[1].tr_out0[516] */ 752 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT05 = 0x0000056Fu, /* tcpwm[1].tr_out0[517] */ 753 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT06 = 0x00000570u, /* tcpwm[1].tr_out0[518] */ 754 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT07 = 0x00000571u, /* tcpwm[1].tr_out0[519] */ 755 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT08 = 0x00000572u, /* tcpwm[1].tr_out0[520] */ 756 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT09 = 0x00000573u, /* tcpwm[1].tr_out0[521] */ 757 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT010 = 0x00000574u, /* tcpwm[1].tr_out0[522] */ 758 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT011 = 0x00000575u, /* tcpwm[1].tr_out0[523] */ 759 TRIG_IN_MUX_5_TCPWM1_32_TR_OUT012 = 0x00000576u, /* tcpwm[1].tr_out0[524] */ 760 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT0 = 0x00000577u, /* canfd[0].tr_dbg_dma_req[0] */ 761 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT1 = 0x00000578u, /* canfd[0].tr_dbg_dma_req[1] */ 762 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT2 = 0x00000579u, /* canfd[0].tr_dbg_dma_req[2] */ 763 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT3 = 0x0000057Au, /* canfd[0].tr_dbg_dma_req[3] */ 764 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT4 = 0x0000057Bu, /* canfd[0].tr_dbg_dma_req[4] */ 765 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT0 = 0x0000057Cu, /* canfd[0].tr_fifo0[0] */ 766 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT1 = 0x0000057Du, /* canfd[0].tr_fifo0[1] */ 767 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT2 = 0x0000057Eu, /* canfd[0].tr_fifo0[2] */ 768 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT3 = 0x0000057Fu, /* canfd[0].tr_fifo0[3] */ 769 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT4 = 0x00000580u, /* canfd[0].tr_fifo0[4] */ 770 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT0 = 0x00000581u, /* canfd[0].tr_fifo1[0] */ 771 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT1 = 0x00000582u, /* canfd[0].tr_fifo1[1] */ 772 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT2 = 0x00000583u, /* canfd[0].tr_fifo1[2] */ 773 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT3 = 0x00000584u, /* canfd[0].tr_fifo1[3] */ 774 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT4 = 0x00000585u, /* canfd[0].tr_fifo1[4] */ 775 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT0 = 0x00000586u, /* canfd[1].tr_dbg_dma_req[0] */ 776 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT1 = 0x00000587u, /* canfd[1].tr_dbg_dma_req[1] */ 777 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT2 = 0x00000588u, /* canfd[1].tr_dbg_dma_req[2] */ 778 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT3 = 0x00000589u, /* canfd[1].tr_dbg_dma_req[3] */ 779 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT4 = 0x0000058Au, /* canfd[1].tr_dbg_dma_req[4] */ 780 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT0 = 0x0000058Bu, /* canfd[1].tr_fifo0[0] */ 781 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT1 = 0x0000058Cu, /* canfd[1].tr_fifo0[1] */ 782 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT2 = 0x0000058Du, /* canfd[1].tr_fifo0[2] */ 783 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT3 = 0x0000058Eu, /* canfd[1].tr_fifo0[3] */ 784 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT4 = 0x0000058Fu, /* canfd[1].tr_fifo0[4] */ 785 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT0 = 0x00000590u, /* canfd[1].tr_fifo1[0] */ 786 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT1 = 0x00000591u, /* canfd[1].tr_fifo1[1] */ 787 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT2 = 0x00000592u, /* canfd[1].tr_fifo1[2] */ 788 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT3 = 0x00000593u, /* canfd[1].tr_fifo1[3] */ 789 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT4 = 0x00000594u, /* canfd[1].tr_fifo1[4] */ 790 TRIG_IN_MUX_5_CAN0_TT_TR_OUT0 = 0x00000595u, /* canfd[0].tr_tmp_rtp_out[0] */ 791 TRIG_IN_MUX_5_CAN0_TT_TR_OUT1 = 0x00000596u, /* canfd[0].tr_tmp_rtp_out[1] */ 792 TRIG_IN_MUX_5_CAN0_TT_TR_OUT2 = 0x00000597u, /* canfd[0].tr_tmp_rtp_out[2] */ 793 TRIG_IN_MUX_5_CAN0_TT_TR_OUT3 = 0x00000598u, /* canfd[0].tr_tmp_rtp_out[3] */ 794 TRIG_IN_MUX_5_CAN0_TT_TR_OUT4 = 0x00000599u, /* canfd[0].tr_tmp_rtp_out[4] */ 795 TRIG_IN_MUX_5_CAN1_TT_TR_OUT0 = 0x0000059Au, /* canfd[1].tr_tmp_rtp_out[0] */ 796 TRIG_IN_MUX_5_CAN1_TT_TR_OUT1 = 0x0000059Bu, /* canfd[1].tr_tmp_rtp_out[1] */ 797 TRIG_IN_MUX_5_CAN1_TT_TR_OUT2 = 0x0000059Cu, /* canfd[1].tr_tmp_rtp_out[2] */ 798 TRIG_IN_MUX_5_CAN1_TT_TR_OUT3 = 0x0000059Du, /* canfd[1].tr_tmp_rtp_out[3] */ 799 TRIG_IN_MUX_5_CAN1_TT_TR_OUT4 = 0x0000059Eu, /* canfd[1].tr_tmp_rtp_out[4] */ 800 TRIG_IN_MUX_5_FLEXRAY_TT_TR_OUT = 0x0000059Fu, /* flexray[0].tr_tint0_out */ 801 TRIG_IN_MUX_5_EVTGEN_TR_OUT4 = 0x000005A0u, /* evtgen[0].tr_out[4] */ 802 TRIG_IN_MUX_5_EVTGEN_TR_OUT5 = 0x000005A1u, /* evtgen[0].tr_out[5] */ 803 TRIG_IN_MUX_5_EVTGEN_TR_OUT6 = 0x000005A2u, /* evtgen[0].tr_out[6] */ 804 TRIG_IN_MUX_5_EVTGEN_TR_OUT7 = 0x000005A3u, /* evtgen[0].tr_out[7] */ 805 TRIG_IN_MUX_5_EVTGEN_TR_OUT8 = 0x000005A4u, /* evtgen[0].tr_out[8] */ 806 TRIG_IN_MUX_5_EVTGEN_TR_OUT9 = 0x000005A5u, /* evtgen[0].tr_out[9] */ 807 TRIG_IN_MUX_5_EVTGEN_TR_OUT10 = 0x000005A6u, /* evtgen[0].tr_out[10] */ 808 TRIG_IN_MUX_5_EVTGEN_TR_OUT11 = 0x000005A7u /* evtgen[0].tr_out[11] */ 809 } en_trig_input_tcpwm1_out_t; 810 811 /* Trigger Input Group 6 - TCPWM trigger inputs */ 812 typedef enum 813 { 814 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT10 = 0x00000601u, /* tcpwm[1].tr_out1[0] */ 815 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT11 = 0x00000602u, /* tcpwm[1].tr_out1[1] */ 816 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT12 = 0x00000603u, /* tcpwm[1].tr_out1[2] */ 817 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT13 = 0x00000604u, /* tcpwm[1].tr_out1[3] */ 818 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT14 = 0x00000605u, /* tcpwm[1].tr_out1[4] */ 819 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT15 = 0x00000606u, /* tcpwm[1].tr_out1[5] */ 820 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT16 = 0x00000607u, /* tcpwm[1].tr_out1[6] */ 821 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT17 = 0x00000608u, /* tcpwm[1].tr_out1[7] */ 822 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT18 = 0x00000609u, /* tcpwm[1].tr_out1[8] */ 823 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT19 = 0x0000060Au, /* tcpwm[1].tr_out1[9] */ 824 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT110 = 0x0000060Bu, /* tcpwm[1].tr_out1[10] */ 825 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT111 = 0x0000060Cu, /* tcpwm[1].tr_out1[11] */ 826 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT112 = 0x0000060Du, /* tcpwm[1].tr_out1[12] */ 827 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT113 = 0x0000060Eu, /* tcpwm[1].tr_out1[13] */ 828 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT114 = 0x0000060Fu, /* tcpwm[1].tr_out1[14] */ 829 TRIG_IN_MUX_6_TCPWM1_16_TR_OUT115 = 0x00000610u, /* tcpwm[1].tr_out1[15] */ 830 TRIG_IN_MUX_6_SCB_TX_TR_OUT0 = 0x00000611u, /* scb[0].tr_tx_req */ 831 TRIG_IN_MUX_6_SCB_RX_TR_OUT0 = 0x00000612u, /* scb[0].tr_rx_req */ 832 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT0 = 0x00000613u, /* scb[0].tr_i2c_scl_filtered */ 833 TRIG_IN_MUX_6_SCB_TX_TR_OUT1 = 0x00000614u, /* scb[1].tr_tx_req */ 834 TRIG_IN_MUX_6_SCB_RX_TR_OUT1 = 0x00000615u, /* scb[1].tr_rx_req */ 835 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT1 = 0x00000616u, /* scb[1].tr_i2c_scl_filtered */ 836 TRIG_IN_MUX_6_SCB_TX_TR_OUT2 = 0x00000617u, /* scb[2].tr_tx_req */ 837 TRIG_IN_MUX_6_SCB_RX_TR_OUT2 = 0x00000618u, /* scb[2].tr_rx_req */ 838 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT2 = 0x00000619u, /* scb[2].tr_i2c_scl_filtered */ 839 TRIG_IN_MUX_6_SCB_TX_TR_OUT3 = 0x0000061Au, /* scb[3].tr_tx_req */ 840 TRIG_IN_MUX_6_SCB_RX_TR_OUT3 = 0x0000061Bu, /* scb[3].tr_rx_req */ 841 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT3 = 0x0000061Cu, /* scb[3].tr_i2c_scl_filtered */ 842 TRIG_IN_MUX_6_SCB_TX_TR_OUT4 = 0x0000061Du, /* scb[4].tr_tx_req */ 843 TRIG_IN_MUX_6_SCB_RX_TR_OUT4 = 0x0000061Eu, /* scb[4].tr_rx_req */ 844 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT4 = 0x0000061Fu, /* scb[4].tr_i2c_scl_filtered */ 845 TRIG_IN_MUX_6_SCB_TX_TR_OUT5 = 0x00000620u, /* scb[5].tr_tx_req */ 846 TRIG_IN_MUX_6_SCB_RX_TR_OUT5 = 0x00000621u, /* scb[5].tr_rx_req */ 847 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT5 = 0x00000622u, /* scb[5].tr_i2c_scl_filtered */ 848 TRIG_IN_MUX_6_SCB_TX_TR_OUT6 = 0x00000623u, /* scb[6].tr_tx_req */ 849 TRIG_IN_MUX_6_SCB_RX_TR_OUT6 = 0x00000624u, /* scb[6].tr_rx_req */ 850 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT6 = 0x00000625u, /* scb[6].tr_i2c_scl_filtered */ 851 TRIG_IN_MUX_6_SCB_TX_TR_OUT7 = 0x00000626u, /* scb[7].tr_tx_req */ 852 TRIG_IN_MUX_6_SCB_RX_TR_OUT7 = 0x00000627u, /* scb[7].tr_rx_req */ 853 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT7 = 0x00000628u, /* scb[7].tr_i2c_scl_filtered */ 854 TRIG_IN_MUX_6_SCB_TX_TR_OUT8 = 0x00000629u, /* scb[8].tr_tx_req */ 855 TRIG_IN_MUX_6_SCB_RX_TR_OUT8 = 0x0000062Au, /* scb[8].tr_rx_req */ 856 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT8 = 0x0000062Bu, /* scb[8].tr_i2c_scl_filtered */ 857 TRIG_IN_MUX_6_SCB_TX_TR_OUT9 = 0x0000062Cu, /* scb[9].tr_tx_req */ 858 TRIG_IN_MUX_6_CB_RX_TR_OUT9 = 0x0000062Du, /* scb[9].tr_rx_req */ 859 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT9 = 0x0000062Eu, /* scb[9].tr_i2c_scl_filtered */ 860 TRIG_IN_MUX_6_SCB_TX_TR_OUT10 = 0x0000062Fu, /* scb[10].tr_tx_req */ 861 TRIG_IN_MUX_6_SCB_RX_TR_OUT10 = 0x00000630u, /* scb[10].tr_rx_req */ 862 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT10 = 0x00000631u, /* scb[10].tr_i2c_scl_filtered */ 863 TRIG_IN_MUX_6_FLEXRAY_IBUF_TR_OUT = 0x00000632u, /* flexray[0].tr_ibf_out */ 864 TRIG_IN_MUX_6_FLEXRAY_OBUF_TR_OUT = 0x00000633u, /* flexray[0].tr_obf_out */ 865 TRIG_IN_MUX_6_PASS_GEN_TR_OUT0 = 0x00000634u, /* pass[0].tr_sar_gen_out[0] */ 866 TRIG_IN_MUX_6_PASS_GEN_TR_OUT1 = 0x00000635u, /* pass[0].tr_sar_gen_out[1] */ 867 TRIG_IN_MUX_6_PASS_GEN_TR_OUT2 = 0x00000636u, /* pass[0].tr_sar_gen_out[2] */ 868 TRIG_IN_MUX_6_PASS_GEN_TR_OUT3 = 0x00000637u, /* pass[0].tr_sar_gen_out[3] */ 869 TRIG_IN_MUX_6_PASS_GEN_TR_OUT4 = 0x00000638u, /* pass[0].tr_sar_gen_out[4] */ 870 TRIG_IN_MUX_6_PASS_GEN_TR_OUT5 = 0x00000639u, /* pass[0].tr_sar_gen_out[5] */ 871 TRIG_IN_MUX_6_HSIOM_IO_INPUT0 = 0x0000063Au, /* peri.tr_io_input[0] */ 872 TRIG_IN_MUX_6_HSIOM_IO_INPUT1 = 0x0000063Bu, /* peri.tr_io_input[1] */ 873 TRIG_IN_MUX_6_HSIOM_IO_INPUT2 = 0x0000063Cu, /* peri.tr_io_input[2] */ 874 TRIG_IN_MUX_6_HSIOM_IO_INPUT3 = 0x0000063Du, /* peri.tr_io_input[3] */ 875 TRIG_IN_MUX_6_HSIOM_IO_INPUT4 = 0x0000063Eu, /* peri.tr_io_input[4] */ 876 TRIG_IN_MUX_6_HSIOM_IO_INPUT5 = 0x0000063Fu, /* peri.tr_io_input[5] */ 877 TRIG_IN_MUX_6_HSIOM_IO_INPUT6 = 0x00000640u, /* peri.tr_io_input[6] */ 878 TRIG_IN_MUX_6_HSIOM_IO_INPUT7 = 0x00000641u, /* peri.tr_io_input[7] */ 879 TRIG_IN_MUX_6_HSIOM_IO_INPUT8 = 0x00000642u, /* peri.tr_io_input[8] */ 880 TRIG_IN_MUX_6_HSIOM_IO_INPUT9 = 0x00000643u, /* peri.tr_io_input[9] */ 881 TRIG_IN_MUX_6_HSIOM_IO_INPUT10 = 0x00000644u, /* peri.tr_io_input[10] */ 882 TRIG_IN_MUX_6_HSIOM_IO_INPUT11 = 0x00000645u, /* peri.tr_io_input[11] */ 883 TRIG_IN_MUX_6_HSIOM_IO_INPUT12 = 0x00000646u, /* peri.tr_io_input[12] */ 884 TRIG_IN_MUX_6_HSIOM_IO_INPUT13 = 0x00000647u, /* peri.tr_io_input[13] */ 885 TRIG_IN_MUX_6_HSIOM_IO_INPUT14 = 0x00000648u, /* peri.tr_io_input[14] */ 886 TRIG_IN_MUX_6_HSIOM_IO_INPUT15 = 0x00000649u, /* peri.tr_io_input[15] */ 887 TRIG_IN_MUX_6_HSIOM_IO_INPUT16 = 0x0000064Au, /* peri.tr_io_input[16] */ 888 TRIG_IN_MUX_6_HSIOM_IO_INPUT17 = 0x0000064Bu, /* peri.tr_io_input[17] */ 889 TRIG_IN_MUX_6_HSIOM_IO_INPUT18 = 0x0000064Cu, /* peri.tr_io_input[18] */ 890 TRIG_IN_MUX_6_HSIOM_IO_INPUT19 = 0x0000064Du, /* peri.tr_io_input[19] */ 891 TRIG_IN_MUX_6_HSIOM_IO_INPUT20 = 0x0000064Eu, /* peri.tr_io_input[20] */ 892 TRIG_IN_MUX_6_HSIOM_IO_INPUT21 = 0x0000064Fu, /* peri.tr_io_input[21] */ 893 TRIG_IN_MUX_6_HSIOM_IO_INPUT22 = 0x00000650u, /* peri.tr_io_input[22] */ 894 TRIG_IN_MUX_6_HSIOM_IO_INPUT23 = 0x00000651u, /* peri.tr_io_input[23] */ 895 TRIG_IN_MUX_6_HSIOM_IO_INPUT24 = 0x00000652u, /* peri.tr_io_input[24] */ 896 TRIG_IN_MUX_6_HSIOM_IO_INPUT25 = 0x00000653u, /* peri.tr_io_input[25] */ 897 TRIG_IN_MUX_6_HSIOM_IO_INPUT26 = 0x00000654u, /* peri.tr_io_input[26] */ 898 TRIG_IN_MUX_6_HSIOM_IO_INPUT27 = 0x00000655u, /* peri.tr_io_input[27] */ 899 TRIG_IN_MUX_6_HSIOM_IO_INPUT28 = 0x00000656u, /* peri.tr_io_input[28] */ 900 TRIG_IN_MUX_6_HSIOM_IO_INPUT29 = 0x00000657u, /* peri.tr_io_input[29] */ 901 TRIG_IN_MUX_6_HSIOM_IO_INPUT30 = 0x00000658u, /* peri.tr_io_input[30] */ 902 TRIG_IN_MUX_6_HSIOM_IO_INPUT31 = 0x00000659u, /* peri.tr_io_input[31] */ 903 TRIG_IN_MUX_6_HSIOM_IO_INPUT32 = 0x0000065Au, /* peri.tr_io_input[32] */ 904 TRIG_IN_MUX_6_HSIOM_IO_INPUT33 = 0x0000065Bu, /* peri.tr_io_input[33] */ 905 TRIG_IN_MUX_6_HSIOM_IO_INPUT34 = 0x0000065Cu, /* peri.tr_io_input[34] */ 906 TRIG_IN_MUX_6_HSIOM_IO_INPUT35 = 0x0000065Du, /* peri.tr_io_input[35] */ 907 TRIG_IN_MUX_6_HSIOM_IO_INPUT36 = 0x0000065Eu, /* peri.tr_io_input[36] */ 908 TRIG_IN_MUX_6_HSIOM_IO_INPUT37 = 0x0000065Fu, /* peri.tr_io_input[37] */ 909 TRIG_IN_MUX_6_HSIOM_IO_INPUT38 = 0x00000660u, /* peri.tr_io_input[38] */ 910 TRIG_IN_MUX_6_HSIOM_IO_INPUT39 = 0x00000661u, /* peri.tr_io_input[39] */ 911 TRIG_IN_MUX_6_HSIOM_IO_INPUT40 = 0x00000662u, /* peri.tr_io_input[40] */ 912 TRIG_IN_MUX_6_HSIOM_IO_INPUT41 = 0x00000663u, /* peri.tr_io_input[41] */ 913 TRIG_IN_MUX_6_HSIOM_IO_INPUT42 = 0x00000664u, /* peri.tr_io_input[42] */ 914 TRIG_IN_MUX_6_HSIOM_IO_INPUT43 = 0x00000665u, /* peri.tr_io_input[43] */ 915 TRIG_IN_MUX_6_HSIOM_IO_INPUT44 = 0x00000666u, /* peri.tr_io_input[44] */ 916 TRIG_IN_MUX_6_HSIOM_IO_INPUT45 = 0x00000667u, /* peri.tr_io_input[45] */ 917 TRIG_IN_MUX_6_HSIOM_IO_INPUT46 = 0x00000668u, /* peri.tr_io_input[46] */ 918 TRIG_IN_MUX_6_HSIOM_IO_INPUT47 = 0x00000669u, /* peri.tr_io_input[47] */ 919 TRIG_IN_MUX_6_CTI_TR_IN0 = 0x0000066Au, /* cpuss.cti_tr_out[0] */ 920 TRIG_IN_MUX_6_CTI_TR_IN1 = 0x0000066Bu, /* cpuss.cti_tr_out[1] */ 921 TRIG_IN_MUX_6_FAULT_TR_OUT0 = 0x0000066Cu, /* cpuss.tr_fault[0] */ 922 TRIG_IN_MUX_6_FAULT_TR_OUT1 = 0x0000066Du, /* cpuss.tr_fault[1] */ 923 TRIG_IN_MUX_6_FAULT_TR_OUT2 = 0x0000066Eu, /* cpuss.tr_fault[2] */ 924 TRIG_IN_MUX_6_FAULT_TR_OUT3 = 0x0000066Fu /* cpuss.tr_fault[3] */ 925 } en_trig_input_tcpwm1_in_t; 926 927 /* Trigger Input Group 7 - PASS trigger multiplexer */ 928 typedef enum 929 { 930 TRIG_IN_MUX_7_PDMA0_TR_OUT0 = 0x00000701u, /* cpuss.dw0_tr_out[0] */ 931 TRIG_IN_MUX_7_PDMA0_TR_OUT1 = 0x00000702u, /* cpuss.dw0_tr_out[1] */ 932 TRIG_IN_MUX_7_PDMA0_TR_OUT2 = 0x00000703u, /* cpuss.dw0_tr_out[2] */ 933 TRIG_IN_MUX_7_PDMA0_TR_OUT3 = 0x00000704u, /* cpuss.dw0_tr_out[3] */ 934 TRIG_IN_MUX_7_PDMA0_TR_OUT4 = 0x00000705u, /* cpuss.dw0_tr_out[4] */ 935 TRIG_IN_MUX_7_PDMA0_TR_OUT5 = 0x00000706u, /* cpuss.dw0_tr_out[5] */ 936 TRIG_IN_MUX_7_PDMA0_TR_OUT6 = 0x00000707u, /* cpuss.dw0_tr_out[6] */ 937 TRIG_IN_MUX_7_PDMA0_TR_OUT7 = 0x00000708u, /* cpuss.dw0_tr_out[7] */ 938 TRIG_IN_MUX_7_PDMA0_TR_OUT8 = 0x00000709u, /* cpuss.dw0_tr_out[8] */ 939 TRIG_IN_MUX_7_PDMA0_TR_OUT9 = 0x0000070Au, /* cpuss.dw0_tr_out[9] */ 940 TRIG_IN_MUX_7_PDMA0_TR_OUT10 = 0x0000070Bu, /* cpuss.dw0_tr_out[10] */ 941 TRIG_IN_MUX_7_PDMA0_TR_OUT11 = 0x0000070Cu, /* cpuss.dw0_tr_out[11] */ 942 TRIG_IN_MUX_7_PDMA0_TR_OUT12 = 0x0000070Du, /* cpuss.dw0_tr_out[12] */ 943 TRIG_IN_MUX_7_PDMA0_TR_OUT13 = 0x0000070Eu, /* cpuss.dw0_tr_out[13] */ 944 TRIG_IN_MUX_7_PDMA0_TR_OUT14 = 0x0000070Fu, /* cpuss.dw0_tr_out[14] */ 945 TRIG_IN_MUX_7_PDMA0_TR_OUT15 = 0x00000710u, /* cpuss.dw0_tr_out[15] */ 946 TRIG_IN_MUX_7_PDMA0_TR_OUT16 = 0x00000711u, /* cpuss.dw0_tr_out[16] */ 947 TRIG_IN_MUX_7_PDMA0_TR_OUT17 = 0x00000712u, /* cpuss.dw0_tr_out[17] */ 948 TRIG_IN_MUX_7_PDMA0_TR_OUT18 = 0x00000713u, /* cpuss.dw0_tr_out[18] */ 949 TRIG_IN_MUX_7_PDMA0_TR_OUT19 = 0x00000714u, /* cpuss.dw0_tr_out[19] */ 950 TRIG_IN_MUX_7_PDMA0_TR_OUT20 = 0x00000715u, /* cpuss.dw0_tr_out[20] */ 951 TRIG_IN_MUX_7_PDMA0_TR_OUT21 = 0x00000716u, /* cpuss.dw0_tr_out[21] */ 952 TRIG_IN_MUX_7_PDMA0_TR_OUT22 = 0x00000717u, /* cpuss.dw0_tr_out[22] */ 953 TRIG_IN_MUX_7_PDMA0_TR_OUT23 = 0x00000718u, /* cpuss.dw0_tr_out[23] */ 954 TRIG_IN_MUX_7_PDMA0_TR_OUT24 = 0x00000719u, /* cpuss.dw0_tr_out[24] */ 955 TRIG_IN_MUX_7_PDMA0_TR_OUT25 = 0x0000071Au, /* cpuss.dw0_tr_out[25] */ 956 TRIG_IN_MUX_7_PDMA0_TR_OUT26 = 0x0000071Bu, /* cpuss.dw0_tr_out[26] */ 957 TRIG_IN_MUX_7_PDMA0_TR_OUT27 = 0x0000071Cu, /* cpuss.dw0_tr_out[27] */ 958 TRIG_IN_MUX_7_PDMA0_TR_OUT28 = 0x0000071Du, /* cpuss.dw0_tr_out[28] */ 959 TRIG_IN_MUX_7_PDMA0_TR_OUT29 = 0x0000071Eu, /* cpuss.dw0_tr_out[29] */ 960 TRIG_IN_MUX_7_PDMA0_TR_OUT30 = 0x0000071Fu, /* cpuss.dw0_tr_out[30] */ 961 TRIG_IN_MUX_7_PDMA0_TR_OUT31 = 0x00000720u, /* cpuss.dw0_tr_out[31] */ 962 TRIG_IN_MUX_7_TCPWM1_16M_TR_OUT00 = 0x00000721u, /* tcpwm[1].tr_out0[256] */ 963 TRIG_IN_MUX_7_TCPWM1_16M_TR_OUT01 = 0x00000722u, /* tcpwm[1].tr_out0[257] */ 964 TRIG_IN_MUX_7_TCPWM1_16M_TR_OUT02 = 0x00000723u, /* tcpwm[1].tr_out0[258] */ 965 TRIG_IN_MUX_7_TCPWM1_16M_TR_OUT03 = 0x00000724u, /* tcpwm[1].tr_out0[259] */ 966 TRIG_IN_MUX_7_TCPWM1_16M_TR_OUT04 = 0x00000725u, /* tcpwm[1].tr_out0[260] */ 967 TRIG_IN_MUX_7_TCPWM1_16M_TR_OUT05 = 0x00000726u, /* tcpwm[1].tr_out0[261] */ 968 TRIG_IN_MUX_7_TCPWM1_16M_TR_OUT06 = 0x00000727u, /* tcpwm[1].tr_out0[262] */ 969 TRIG_IN_MUX_7_TCPWM1_16M_TR_OUT07 = 0x00000728u, /* tcpwm[1].tr_out0[263] */ 970 TRIG_IN_MUX_7_TCPWM1_16M_TR_OUT08 = 0x00000729u, /* tcpwm[1].tr_out0[264] */ 971 TRIG_IN_MUX_7_TCPWM1_16M_TR_OUT09 = 0x0000072Au, /* tcpwm[1].tr_out0[265] */ 972 TRIG_IN_MUX_7_TCPWM1_16M_TR_OUT010 = 0x0000072Bu, /* tcpwm[1].tr_out0[266] */ 973 TRIG_IN_MUX_7_TCPWM1_16M_TR_OUT011 = 0x0000072Cu, /* tcpwm[1].tr_out0[267] */ 974 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT00 = 0x0000072Du, /* tcpwm[1].tr_out0[512] */ 975 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT01 = 0x0000072Eu, /* tcpwm[1].tr_out0[513] */ 976 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT02 = 0x0000072Fu, /* tcpwm[1].tr_out0[514] */ 977 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT03 = 0x00000730u, /* tcpwm[1].tr_out0[515] */ 978 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT04 = 0x00000731u, /* tcpwm[1].tr_out0[516] */ 979 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT05 = 0x00000732u, /* tcpwm[1].tr_out0[517] */ 980 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT06 = 0x00000733u, /* tcpwm[1].tr_out0[518] */ 981 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT07 = 0x00000734u, /* tcpwm[1].tr_out0[519] */ 982 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT08 = 0x00000735u, /* tcpwm[1].tr_out0[520] */ 983 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT09 = 0x00000736u, /* tcpwm[1].tr_out0[521] */ 984 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT010 = 0x00000737u, /* tcpwm[1].tr_out0[522] */ 985 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT011 = 0x00000738u, /* tcpwm[1].tr_out0[523] */ 986 TRIG_IN_MUX_7_TCPWM1_32_TR_OUT012 = 0x00000739u, /* tcpwm[1].tr_out0[524] */ 987 TRIG_IN_MUX_7_HSIOM_IO_INPUT0 = 0x0000073Au, /* peri.tr_io_input[0] */ 988 TRIG_IN_MUX_7_HSIOM_IO_INPUT1 = 0x0000073Bu, /* peri.tr_io_input[1] */ 989 TRIG_IN_MUX_7_HSIOM_IO_INPUT2 = 0x0000073Cu, /* peri.tr_io_input[2] */ 990 TRIG_IN_MUX_7_HSIOM_IO_INPUT3 = 0x0000073Du, /* peri.tr_io_input[3] */ 991 TRIG_IN_MUX_7_HSIOM_IO_INPUT4 = 0x0000073Eu, /* peri.tr_io_input[4] */ 992 TRIG_IN_MUX_7_HSIOM_IO_INPUT5 = 0x0000073Fu, /* peri.tr_io_input[5] */ 993 TRIG_IN_MUX_7_HSIOM_IO_INPUT6 = 0x00000740u, /* peri.tr_io_input[6] */ 994 TRIG_IN_MUX_7_HSIOM_IO_INPUT7 = 0x00000741u, /* peri.tr_io_input[7] */ 995 TRIG_IN_MUX_7_EVTGEN_TR_OUT12 = 0x00000742u, /* evtgen[0].tr_out[12] */ 996 TRIG_IN_MUX_7_EVTGEN_TR_OUT13 = 0x00000743u, /* evtgen[0].tr_out[13] */ 997 TRIG_IN_MUX_7_EVTGEN_TR_OUT14 = 0x00000744u /* evtgen[0].tr_out[14] */ 998 } en_trig_input_pass_t; 999 1000 /* Trigger Input Group 8 - CAN TT Synchronization triggers */ 1001 typedef enum 1002 { 1003 TRIG_IN_MUX_8_CAN0_TT_TR_OUT0 = 0x00000801u, /* canfd[0].tr_tmp_rtp_out[0] */ 1004 TRIG_IN_MUX_8_CAN0_TT_TR_OUT1 = 0x00000802u, /* canfd[0].tr_tmp_rtp_out[1] */ 1005 TRIG_IN_MUX_8_CAN0_TT_TR_OUT2 = 0x00000803u, /* canfd[0].tr_tmp_rtp_out[2] */ 1006 TRIG_IN_MUX_8_CAN0_TT_TR_OUT3 = 0x00000804u, /* canfd[0].tr_tmp_rtp_out[3] */ 1007 TRIG_IN_MUX_8_CAN0_TT_TR_OUT4 = 0x00000805u, /* canfd[0].tr_tmp_rtp_out[4] */ 1008 TRIG_IN_MUX_8_CAN1_TT_TR_OUT0 = 0x00000806u, /* canfd[1].tr_tmp_rtp_out[0] */ 1009 TRIG_IN_MUX_8_CAN1_TT_TR_OUT1 = 0x00000807u, /* canfd[1].tr_tmp_rtp_out[1] */ 1010 TRIG_IN_MUX_8_CAN1_TT_TR_OUT2 = 0x00000808u, /* canfd[1].tr_tmp_rtp_out[2] */ 1011 TRIG_IN_MUX_8_CAN1_TT_TR_OUT3 = 0x00000809u, /* canfd[1].tr_tmp_rtp_out[3] */ 1012 TRIG_IN_MUX_8_CAN1_TT_TR_OUT4 = 0x0000080Au, /* canfd[1].tr_tmp_rtp_out[4] */ 1013 TRIG_IN_MUX_8_FLEXRAY_TT_TR_OUT = 0x0000080Bu /* flexray[0].tr_tint0_out */ 1014 } en_trig_input_cantt_t; 1015 1016 /* Trigger Input Group 9 - 2nd level MUX using input from MUX_11/12/13 */ 1017 typedef enum 1018 { 1019 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT0 = 0x00000901u, /* tr_group[10].output[0] */ 1020 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT1 = 0x00000902u, /* tr_group[10].output[1] */ 1021 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT2 = 0x00000903u, /* tr_group[10].output[2] */ 1022 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT3 = 0x00000904u, /* tr_group[10].output[3] */ 1023 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT4 = 0x00000905u, /* tr_group[10].output[4] */ 1024 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT0 = 0x00000906u, /* tr_group[11].output[0] */ 1025 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT1 = 0x00000907u, /* tr_group[11].output[1] */ 1026 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT2 = 0x00000908u, /* tr_group[11].output[2] */ 1027 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT3 = 0x00000909u, /* tr_group[11].output[3] */ 1028 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT4 = 0x0000090Au, /* tr_group[11].output[4] */ 1029 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT0 = 0x0000090Bu, /* tr_group[12].output[0] */ 1030 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT1 = 0x0000090Cu, /* tr_group[12].output[1] */ 1031 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT2 = 0x0000090Du, /* tr_group[12].output[2] */ 1032 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT3 = 0x0000090Eu, /* tr_group[12].output[3] */ 1033 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT4 = 0x0000090Fu /* tr_group[12].output[4] */ 1034 } en_trig_input_debugmain_t; 1035 1036 /* Trigger Input Group 10 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1037 typedef enum 1038 { 1039 TRIG_IN_MUX_10_PDMA0_TR_OUT0 = 0x00000A01u, /* cpuss.dw0_tr_out[0] */ 1040 TRIG_IN_MUX_10_PDMA0_TR_OUT1 = 0x00000A02u, /* cpuss.dw0_tr_out[1] */ 1041 TRIG_IN_MUX_10_PDMA0_TR_OUT2 = 0x00000A03u, /* cpuss.dw0_tr_out[2] */ 1042 TRIG_IN_MUX_10_PDMA0_TR_OUT3 = 0x00000A04u, /* cpuss.dw0_tr_out[3] */ 1043 TRIG_IN_MUX_10_PDMA0_TR_OUT4 = 0x00000A05u, /* cpuss.dw0_tr_out[4] */ 1044 TRIG_IN_MUX_10_PDMA0_TR_OUT5 = 0x00000A06u, /* cpuss.dw0_tr_out[5] */ 1045 TRIG_IN_MUX_10_PDMA0_TR_OUT6 = 0x00000A07u, /* cpuss.dw0_tr_out[6] */ 1046 TRIG_IN_MUX_10_PDMA0_TR_OUT7 = 0x00000A08u, /* cpuss.dw0_tr_out[7] */ 1047 TRIG_IN_MUX_10_PDMA0_TR_OUT8 = 0x00000A09u, /* cpuss.dw0_tr_out[8] */ 1048 TRIG_IN_MUX_10_PDMA0_TR_OUT9 = 0x00000A0Au, /* cpuss.dw0_tr_out[9] */ 1049 TRIG_IN_MUX_10_PDMA0_TR_OUT10 = 0x00000A0Bu, /* cpuss.dw0_tr_out[10] */ 1050 TRIG_IN_MUX_10_PDMA0_TR_OUT11 = 0x00000A0Cu, /* cpuss.dw0_tr_out[11] */ 1051 TRIG_IN_MUX_10_PDMA0_TR_OUT12 = 0x00000A0Du, /* cpuss.dw0_tr_out[12] */ 1052 TRIG_IN_MUX_10_PDMA0_TR_OUT13 = 0x00000A0Eu, /* cpuss.dw0_tr_out[13] */ 1053 TRIG_IN_MUX_10_PDMA0_TR_OUT14 = 0x00000A0Fu, /* cpuss.dw0_tr_out[14] */ 1054 TRIG_IN_MUX_10_PDMA0_TR_OUT15 = 0x00000A10u, /* cpuss.dw0_tr_out[15] */ 1055 TRIG_IN_MUX_10_PDMA0_TR_OUT16 = 0x00000A11u, /* cpuss.dw0_tr_out[16] */ 1056 TRIG_IN_MUX_10_PDMA0_TR_OUT17 = 0x00000A12u, /* cpuss.dw0_tr_out[17] */ 1057 TRIG_IN_MUX_10_PDMA0_TR_OUT18 = 0x00000A13u, /* cpuss.dw0_tr_out[18] */ 1058 TRIG_IN_MUX_10_PDMA0_TR_OUT19 = 0x00000A14u, /* cpuss.dw0_tr_out[19] */ 1059 TRIG_IN_MUX_10_PDMA0_TR_OUT20 = 0x00000A15u, /* cpuss.dw0_tr_out[20] */ 1060 TRIG_IN_MUX_10_PDMA0_TR_OUT21 = 0x00000A16u, /* cpuss.dw0_tr_out[21] */ 1061 TRIG_IN_MUX_10_PDMA0_TR_OUT22 = 0x00000A17u, /* cpuss.dw0_tr_out[22] */ 1062 TRIG_IN_MUX_10_PDMA0_TR_OUT23 = 0x00000A18u, /* cpuss.dw0_tr_out[23] */ 1063 TRIG_IN_MUX_10_PDMA0_TR_OUT24 = 0x00000A19u, /* cpuss.dw0_tr_out[24] */ 1064 TRIG_IN_MUX_10_PDMA0_TR_OUT25 = 0x00000A1Au, /* cpuss.dw0_tr_out[25] */ 1065 TRIG_IN_MUX_10_PDMA0_TR_OUT26 = 0x00000A1Bu, /* cpuss.dw0_tr_out[26] */ 1066 TRIG_IN_MUX_10_PDMA0_TR_OUT27 = 0x00000A1Cu, /* cpuss.dw0_tr_out[27] */ 1067 TRIG_IN_MUX_10_PDMA0_TR_OUT28 = 0x00000A1Du, /* cpuss.dw0_tr_out[28] */ 1068 TRIG_IN_MUX_10_PDMA0_TR_OUT29 = 0x00000A1Eu, /* cpuss.dw0_tr_out[29] */ 1069 TRIG_IN_MUX_10_PDMA0_TR_OUT30 = 0x00000A1Fu, /* cpuss.dw0_tr_out[30] */ 1070 TRIG_IN_MUX_10_PDMA0_TR_OUT31 = 0x00000A20u, /* cpuss.dw0_tr_out[31] */ 1071 TRIG_IN_MUX_10_PDMA0_TR_OUT32 = 0x00000A21u, /* cpuss.dw0_tr_out[32] */ 1072 TRIG_IN_MUX_10_PDMA0_TR_OUT33 = 0x00000A22u, /* cpuss.dw0_tr_out[33] */ 1073 TRIG_IN_MUX_10_PDMA0_TR_OUT34 = 0x00000A23u, /* cpuss.dw0_tr_out[34] */ 1074 TRIG_IN_MUX_10_PDMA0_TR_OUT35 = 0x00000A24u, /* cpuss.dw0_tr_out[35] */ 1075 TRIG_IN_MUX_10_PDMA0_TR_OUT36 = 0x00000A25u, /* cpuss.dw0_tr_out[36] */ 1076 TRIG_IN_MUX_10_PDMA0_TR_OUT37 = 0x00000A26u, /* cpuss.dw0_tr_out[37] */ 1077 TRIG_IN_MUX_10_PDMA0_TR_OUT38 = 0x00000A27u, /* cpuss.dw0_tr_out[38] */ 1078 TRIG_IN_MUX_10_PDMA0_TR_OUT39 = 0x00000A28u, /* cpuss.dw0_tr_out[39] */ 1079 TRIG_IN_MUX_10_PDMA0_TR_OUT40 = 0x00000A29u, /* cpuss.dw0_tr_out[40] */ 1080 TRIG_IN_MUX_10_PDMA0_TR_OUT41 = 0x00000A2Au, /* cpuss.dw0_tr_out[41] */ 1081 TRIG_IN_MUX_10_PDMA0_TR_OUT42 = 0x00000A2Bu, /* cpuss.dw0_tr_out[42] */ 1082 TRIG_IN_MUX_10_PDMA0_TR_OUT43 = 0x00000A2Cu, /* cpuss.dw0_tr_out[43] */ 1083 TRIG_IN_MUX_10_PDMA0_TR_OUT44 = 0x00000A2Du, /* cpuss.dw0_tr_out[44] */ 1084 TRIG_IN_MUX_10_PDMA0_TR_OUT45 = 0x00000A2Eu, /* cpuss.dw0_tr_out[45] */ 1085 TRIG_IN_MUX_10_PDMA0_TR_OUT46 = 0x00000A2Fu, /* cpuss.dw0_tr_out[46] */ 1086 TRIG_IN_MUX_10_PDMA0_TR_OUT47 = 0x00000A30u, /* cpuss.dw0_tr_out[47] */ 1087 TRIG_IN_MUX_10_PDMA0_TR_OUT48 = 0x00000A31u, /* cpuss.dw0_tr_out[48] */ 1088 TRIG_IN_MUX_10_PDMA0_TR_OUT49 = 0x00000A32u, /* cpuss.dw0_tr_out[49] */ 1089 TRIG_IN_MUX_10_PDMA0_TR_OUT50 = 0x00000A33u, /* cpuss.dw0_tr_out[50] */ 1090 TRIG_IN_MUX_10_PDMA0_TR_OUT51 = 0x00000A34u, /* cpuss.dw0_tr_out[51] */ 1091 TRIG_IN_MUX_10_PDMA0_TR_OUT52 = 0x00000A35u, /* cpuss.dw0_tr_out[52] */ 1092 TRIG_IN_MUX_10_PDMA0_TR_OUT53 = 0x00000A36u, /* cpuss.dw0_tr_out[53] */ 1093 TRIG_IN_MUX_10_PDMA0_TR_OUT54 = 0x00000A37u, /* cpuss.dw0_tr_out[54] */ 1094 TRIG_IN_MUX_10_PDMA0_TR_OUT55 = 0x00000A38u, /* cpuss.dw0_tr_out[55] */ 1095 TRIG_IN_MUX_10_PDMA0_TR_OUT56 = 0x00000A39u, /* cpuss.dw0_tr_out[56] */ 1096 TRIG_IN_MUX_10_PDMA0_TR_OUT57 = 0x00000A3Au, /* cpuss.dw0_tr_out[57] */ 1097 TRIG_IN_MUX_10_PDMA0_TR_OUT58 = 0x00000A3Bu, /* cpuss.dw0_tr_out[58] */ 1098 TRIG_IN_MUX_10_PDMA0_TR_OUT59 = 0x00000A3Cu, /* cpuss.dw0_tr_out[59] */ 1099 TRIG_IN_MUX_10_PDMA0_TR_OUT60 = 0x00000A3Du, /* cpuss.dw0_tr_out[60] */ 1100 TRIG_IN_MUX_10_PDMA0_TR_OUT61 = 0x00000A3Eu, /* cpuss.dw0_tr_out[61] */ 1101 TRIG_IN_MUX_10_PDMA0_TR_OUT62 = 0x00000A3Fu, /* cpuss.dw0_tr_out[62] */ 1102 TRIG_IN_MUX_10_PDMA0_TR_OUT63 = 0x00000A40u, /* cpuss.dw0_tr_out[63] */ 1103 TRIG_IN_MUX_10_PDMA0_TR_OUT64 = 0x00000A41u, /* cpuss.dw0_tr_out[64] */ 1104 TRIG_IN_MUX_10_PDMA0_TR_OUT65 = 0x00000A42u, /* cpuss.dw0_tr_out[65] */ 1105 TRIG_IN_MUX_10_PDMA0_TR_OUT66 = 0x00000A43u, /* cpuss.dw0_tr_out[66] */ 1106 TRIG_IN_MUX_10_PDMA0_TR_OUT67 = 0x00000A44u, /* cpuss.dw0_tr_out[67] */ 1107 TRIG_IN_MUX_10_PDMA0_TR_OUT68 = 0x00000A45u, /* cpuss.dw0_tr_out[68] */ 1108 TRIG_IN_MUX_10_PDMA0_TR_OUT69 = 0x00000A46u, /* cpuss.dw0_tr_out[69] */ 1109 TRIG_IN_MUX_10_PDMA0_TR_OUT70 = 0x00000A47u, /* cpuss.dw0_tr_out[70] */ 1110 TRIG_IN_MUX_10_PDMA0_TR_OUT71 = 0x00000A48u, /* cpuss.dw0_tr_out[71] */ 1111 TRIG_IN_MUX_10_PDMA0_TR_OUT72 = 0x00000A49u, /* cpuss.dw0_tr_out[72] */ 1112 TRIG_IN_MUX_10_PDMA0_TR_OUT73 = 0x00000A4Au, /* cpuss.dw0_tr_out[73] */ 1113 TRIG_IN_MUX_10_PDMA0_TR_OUT74 = 0x00000A4Bu, /* cpuss.dw0_tr_out[74] */ 1114 TRIG_IN_MUX_10_PDMA0_TR_OUT75 = 0x00000A4Cu, /* cpuss.dw0_tr_out[75] */ 1115 TRIG_IN_MUX_10_PDMA0_TR_OUT76 = 0x00000A4Du, /* cpuss.dw0_tr_out[76] */ 1116 TRIG_IN_MUX_10_PDMA0_TR_OUT77 = 0x00000A4Eu, /* cpuss.dw0_tr_out[77] */ 1117 TRIG_IN_MUX_10_PDMA0_TR_OUT78 = 0x00000A4Fu, /* cpuss.dw0_tr_out[78] */ 1118 TRIG_IN_MUX_10_PDMA0_TR_OUT79 = 0x00000A50u, /* cpuss.dw0_tr_out[79] */ 1119 TRIG_IN_MUX_10_PDMA0_TR_OUT80 = 0x00000A51u, /* cpuss.dw0_tr_out[80] */ 1120 TRIG_IN_MUX_10_PDMA0_TR_OUT81 = 0x00000A52u, /* cpuss.dw0_tr_out[81] */ 1121 TRIG_IN_MUX_10_PDMA0_TR_OUT82 = 0x00000A53u, /* cpuss.dw0_tr_out[82] */ 1122 TRIG_IN_MUX_10_PDMA0_TR_OUT83 = 0x00000A54u, /* cpuss.dw0_tr_out[83] */ 1123 TRIG_IN_MUX_10_PDMA0_TR_OUT84 = 0x00000A55u, /* cpuss.dw0_tr_out[84] */ 1124 TRIG_IN_MUX_10_PDMA0_TR_OUT85 = 0x00000A56u, /* cpuss.dw0_tr_out[85] */ 1125 TRIG_IN_MUX_10_PDMA0_TR_OUT86 = 0x00000A57u, /* cpuss.dw0_tr_out[86] */ 1126 TRIG_IN_MUX_10_PDMA0_TR_OUT87 = 0x00000A58u, /* cpuss.dw0_tr_out[87] */ 1127 TRIG_IN_MUX_10_PDMA0_TR_OUT88 = 0x00000A59u, /* cpuss.dw0_tr_out[88] */ 1128 TRIG_IN_MUX_10_PDMA0_TR_OUT89 = 0x00000A5Au, /* cpuss.dw0_tr_out[89] */ 1129 TRIG_IN_MUX_10_PDMA0_TR_OUT90 = 0x00000A5Bu, /* cpuss.dw0_tr_out[90] */ 1130 TRIG_IN_MUX_10_PDMA0_TR_OUT91 = 0x00000A5Cu, /* cpuss.dw0_tr_out[91] */ 1131 TRIG_IN_MUX_10_PDMA0_TR_OUT92 = 0x00000A5Du, /* cpuss.dw0_tr_out[92] */ 1132 TRIG_IN_MUX_10_PDMA0_TR_OUT93 = 0x00000A5Eu, /* cpuss.dw0_tr_out[93] */ 1133 TRIG_IN_MUX_10_PDMA0_TR_OUT94 = 0x00000A5Fu, /* cpuss.dw0_tr_out[94] */ 1134 TRIG_IN_MUX_10_PDMA0_TR_OUT95 = 0x00000A60u, /* cpuss.dw0_tr_out[95] */ 1135 TRIG_IN_MUX_10_PDMA0_TR_OUT96 = 0x00000A61u, /* cpuss.dw0_tr_out[96] */ 1136 TRIG_IN_MUX_10_PDMA0_TR_OUT97 = 0x00000A62u, /* cpuss.dw0_tr_out[97] */ 1137 TRIG_IN_MUX_10_PDMA0_TR_OUT98 = 0x00000A63u, /* cpuss.dw0_tr_out[98] */ 1138 TRIG_IN_MUX_10_PDMA0_TR_OUT99 = 0x00000A64u, /* cpuss.dw0_tr_out[99] */ 1139 TRIG_IN_MUX_10_PDMA0_TR_OUT100 = 0x00000A65u, /* cpuss.dw0_tr_out[100] */ 1140 TRIG_IN_MUX_10_PDMA0_TR_OUT101 = 0x00000A66u, /* cpuss.dw0_tr_out[101] */ 1141 TRIG_IN_MUX_10_PDMA0_TR_OUT102 = 0x00000A67u, /* cpuss.dw0_tr_out[102] */ 1142 TRIG_IN_MUX_10_PDMA0_TR_OUT103 = 0x00000A68u, /* cpuss.dw0_tr_out[103] */ 1143 TRIG_IN_MUX_10_PDMA0_TR_OUT104 = 0x00000A69u, /* cpuss.dw0_tr_out[104] */ 1144 TRIG_IN_MUX_10_PDMA0_TR_OUT105 = 0x00000A6Au, /* cpuss.dw0_tr_out[105] */ 1145 TRIG_IN_MUX_10_PDMA0_TR_OUT106 = 0x00000A6Bu, /* cpuss.dw0_tr_out[106] */ 1146 TRIG_IN_MUX_10_PDMA0_TR_OUT107 = 0x00000A6Cu, /* cpuss.dw0_tr_out[107] */ 1147 TRIG_IN_MUX_10_PDMA0_TR_OUT108 = 0x00000A6Du, /* cpuss.dw0_tr_out[108] */ 1148 TRIG_IN_MUX_10_PDMA0_TR_OUT109 = 0x00000A6Eu, /* cpuss.dw0_tr_out[109] */ 1149 TRIG_IN_MUX_10_PDMA0_TR_OUT110 = 0x00000A6Fu, /* cpuss.dw0_tr_out[110] */ 1150 TRIG_IN_MUX_10_PDMA0_TR_OUT111 = 0x00000A70u, /* cpuss.dw0_tr_out[111] */ 1151 TRIG_IN_MUX_10_PDMA0_TR_OUT112 = 0x00000A71u, /* cpuss.dw0_tr_out[112] */ 1152 TRIG_IN_MUX_10_PDMA0_TR_OUT113 = 0x00000A72u, /* cpuss.dw0_tr_out[113] */ 1153 TRIG_IN_MUX_10_PDMA0_TR_OUT114 = 0x00000A73u, /* cpuss.dw0_tr_out[114] */ 1154 TRIG_IN_MUX_10_PDMA0_TR_OUT115 = 0x00000A74u, /* cpuss.dw0_tr_out[115] */ 1155 TRIG_IN_MUX_10_PDMA0_TR_OUT116 = 0x00000A75u, /* cpuss.dw0_tr_out[116] */ 1156 TRIG_IN_MUX_10_PDMA0_TR_OUT117 = 0x00000A76u, /* cpuss.dw0_tr_out[117] */ 1157 TRIG_IN_MUX_10_PDMA0_TR_OUT118 = 0x00000A77u, /* cpuss.dw0_tr_out[118] */ 1158 TRIG_IN_MUX_10_PDMA0_TR_OUT119 = 0x00000A78u, /* cpuss.dw0_tr_out[119] */ 1159 TRIG_IN_MUX_10_PDMA0_TR_OUT120 = 0x00000A79u, /* cpuss.dw0_tr_out[120] */ 1160 TRIG_IN_MUX_10_PDMA0_TR_OUT121 = 0x00000A7Au, /* cpuss.dw0_tr_out[121] */ 1161 TRIG_IN_MUX_10_PDMA0_TR_OUT122 = 0x00000A7Bu, /* cpuss.dw0_tr_out[122] */ 1162 TRIG_IN_MUX_10_PDMA0_TR_OUT123 = 0x00000A7Cu, /* cpuss.dw0_tr_out[123] */ 1163 TRIG_IN_MUX_10_PDMA0_TR_OUT124 = 0x00000A7Du, /* cpuss.dw0_tr_out[124] */ 1164 TRIG_IN_MUX_10_PDMA0_TR_OUT125 = 0x00000A7Eu, /* cpuss.dw0_tr_out[125] */ 1165 TRIG_IN_MUX_10_PDMA0_TR_OUT126 = 0x00000A7Fu, /* cpuss.dw0_tr_out[126] */ 1166 TRIG_IN_MUX_10_PDMA0_TR_OUT127 = 0x00000A80u, /* cpuss.dw0_tr_out[127] */ 1167 TRIG_IN_MUX_10_PDMA0_TR_OUT128 = 0x00000A81u, /* cpuss.dw0_tr_out[128] */ 1168 TRIG_IN_MUX_10_PDMA0_TR_OUT129 = 0x00000A82u, /* cpuss.dw0_tr_out[129] */ 1169 TRIG_IN_MUX_10_PDMA0_TR_OUT130 = 0x00000A83u, /* cpuss.dw0_tr_out[130] */ 1170 TRIG_IN_MUX_10_PDMA0_TR_OUT131 = 0x00000A84u, /* cpuss.dw0_tr_out[131] */ 1171 TRIG_IN_MUX_10_PDMA0_TR_OUT132 = 0x00000A85u, /* cpuss.dw0_tr_out[132] */ 1172 TRIG_IN_MUX_10_PDMA0_TR_OUT133 = 0x00000A86u, /* cpuss.dw0_tr_out[133] */ 1173 TRIG_IN_MUX_10_PDMA0_TR_OUT134 = 0x00000A87u, /* cpuss.dw0_tr_out[134] */ 1174 TRIG_IN_MUX_10_PDMA0_TR_OUT135 = 0x00000A88u, /* cpuss.dw0_tr_out[135] */ 1175 TRIG_IN_MUX_10_PDMA0_TR_OUT136 = 0x00000A89u, /* cpuss.dw0_tr_out[136] */ 1176 TRIG_IN_MUX_10_PDMA0_TR_OUT137 = 0x00000A8Au, /* cpuss.dw0_tr_out[137] */ 1177 TRIG_IN_MUX_10_PDMA0_TR_OUT138 = 0x00000A8Bu, /* cpuss.dw0_tr_out[138] */ 1178 TRIG_IN_MUX_10_PDMA0_TR_OUT139 = 0x00000A8Cu, /* cpuss.dw0_tr_out[139] */ 1179 TRIG_IN_MUX_10_PDMA0_TR_OUT140 = 0x00000A8Du, /* cpuss.dw0_tr_out[140] */ 1180 TRIG_IN_MUX_10_PDMA0_TR_OUT141 = 0x00000A8Eu, /* cpuss.dw0_tr_out[141] */ 1181 TRIG_IN_MUX_10_PDMA0_TR_OUT142 = 0x00000A8Fu, /* cpuss.dw0_tr_out[142] */ 1182 TRIG_IN_MUX_10_SCB_TX_TR_OUT0 = 0x00000A90u, /* scb[0].tr_tx_req */ 1183 TRIG_IN_MUX_10_SCB_TX_TR_OUT1 = 0x00000A91u, /* scb[1].tr_tx_req */ 1184 TRIG_IN_MUX_10_SCB_TX_TR_OUT2 = 0x00000A92u, /* scb[2].tr_tx_req */ 1185 TRIG_IN_MUX_10_SCB_TX_TR_OUT3 = 0x00000A93u, /* scb[3].tr_tx_req */ 1186 TRIG_IN_MUX_10_SCB_TX_TR_OUT4 = 0x00000A94u, /* scb[4].tr_tx_req */ 1187 TRIG_IN_MUX_10_SCB_TX_TR_OUT5 = 0x00000A95u, /* scb[5].tr_tx_req */ 1188 TRIG_IN_MUX_10_SCB_TX_TR_OUT6 = 0x00000A96u, /* scb[6].tr_tx_req */ 1189 TRIG_IN_MUX_10_SCB_TX_TR_OUT7 = 0x00000A97u, /* scb[7].tr_tx_req */ 1190 TRIG_IN_MUX_10_SCB_TX_TR_OUT8 = 0x00000A98u, /* scb[8].tr_tx_req */ 1191 TRIG_IN_MUX_10_SCB_TX_TR_OUT9 = 0x00000A99u, /* scb[9].tr_tx_req */ 1192 TRIG_IN_MUX_10_SCB_TX_TR_OUT10 = 0x00000A9Au, /* scb[10].tr_tx_req */ 1193 TRIG_IN_MUX_10_SCB_RX_TR_OUT0 = 0x00000A9Bu, /* scb[0].tr_rx_req */ 1194 TRIG_IN_MUX_10_SCB_RX_TR_OUT1 = 0x00000A9Cu, /* scb[1].tr_rx_req */ 1195 TRIG_IN_MUX_10_SCB_RX_TR_OUT2 = 0x00000A9Du, /* scb[2].tr_rx_req */ 1196 TRIG_IN_MUX_10_SCB_RX_TR_OUT3 = 0x00000A9Eu, /* scb[3].tr_rx_req */ 1197 TRIG_IN_MUX_10_SCB_RX_TR_OUT4 = 0x00000A9Fu, /* scb[4].tr_rx_req */ 1198 TRIG_IN_MUX_10_SCB_RX_TR_OUT5 = 0x00000AA0u, /* scb[5].tr_rx_req */ 1199 TRIG_IN_MUX_10_SCB_RX_TR_OUT6 = 0x00000AA1u, /* scb[6].tr_rx_req */ 1200 TRIG_IN_MUX_10_SCB_RX_TR_OUT7 = 0x00000AA2u, /* scb[7].tr_rx_req */ 1201 TRIG_IN_MUX_10_SCB_RX_TR_OUT8 = 0x00000AA3u, /* scb[8].tr_rx_req */ 1202 TRIG_IN_MUX_10_SCB_RX_TR_OUT9 = 0x00000AA4u, /* scb[9].tr_rx_req */ 1203 TRIG_IN_MUX_10_SCB_RX_TR_OUT10 = 0x00000AA5u, /* scb[10].tr_rx_req */ 1204 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT0 = 0x00000AA6u, /* scb[0].tr_i2c_scl_filtered */ 1205 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT1 = 0x00000AA7u, /* scb[1].tr_i2c_scl_filtered */ 1206 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT2 = 0x00000AA8u, /* scb[2].tr_i2c_scl_filtered */ 1207 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT3 = 0x00000AA9u, /* scb[3].tr_i2c_scl_filtered */ 1208 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT4 = 0x00000AAAu, /* scb[4].tr_i2c_scl_filtered */ 1209 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT5 = 0x00000AABu, /* scb[5].tr_i2c_scl_filtered */ 1210 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT6 = 0x00000AACu, /* scb[6].tr_i2c_scl_filtered */ 1211 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT7 = 0x00000AADu, /* scb[7].tr_i2c_scl_filtered */ 1212 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT8 = 0x00000AAEu, /* scb[8].tr_i2c_scl_filtered */ 1213 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT9 = 0x00000AAFu, /* scb[9].tr_i2c_scl_filtered */ 1214 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT10 = 0x00000AB0u, /* scb[10].tr_i2c_scl_filtered */ 1215 TRIG_IN_MUX_10_CAN0_DBG_TR_OUT0 = 0x00000AB1u, /* canfd[0].tr_dbg_dma_req[0] */ 1216 TRIG_IN_MUX_10_CAN0_DBG_TR_OUT1 = 0x00000AB2u, /* canfd[0].tr_dbg_dma_req[1] */ 1217 TRIG_IN_MUX_10_CAN0_DBG_TR_OUT2 = 0x00000AB3u, /* canfd[0].tr_dbg_dma_req[2] */ 1218 TRIG_IN_MUX_10_CAN0_DBG_TR_OUT3 = 0x00000AB4u, /* canfd[0].tr_dbg_dma_req[3] */ 1219 TRIG_IN_MUX_10_CAN0_DBG_TR_OUT4 = 0x00000AB5u, /* canfd[0].tr_dbg_dma_req[4] */ 1220 TRIG_IN_MUX_10_CAN0_FIFO0_TR_OUT0 = 0x00000AB6u, /* canfd[0].tr_fifo0[0] */ 1221 TRIG_IN_MUX_10_CAN0_FIFO0_TR_OUT1 = 0x00000AB7u, /* canfd[0].tr_fifo0[1] */ 1222 TRIG_IN_MUX_10_CAN0_FIFO0_TR_OUT2 = 0x00000AB8u, /* canfd[0].tr_fifo0[2] */ 1223 TRIG_IN_MUX_10_CAN0_FIFO0_TR_OUT3 = 0x00000AB9u, /* canfd[0].tr_fifo0[3] */ 1224 TRIG_IN_MUX_10_CAN0_FIFO0_TR_OUT4 = 0x00000ABAu, /* canfd[0].tr_fifo0[4] */ 1225 TRIG_IN_MUX_10_CAN0_FIFO1_TR_OUT0 = 0x00000ABBu, /* canfd[0].tr_fifo1[0] */ 1226 TRIG_IN_MUX_10_CAN0_FIFO1_TR_OUT1 = 0x00000ABCu, /* canfd[0].tr_fifo1[1] */ 1227 TRIG_IN_MUX_10_CAN0_FIFO1_TR_OUT2 = 0x00000ABDu, /* canfd[0].tr_fifo1[2] */ 1228 TRIG_IN_MUX_10_CAN0_FIFO1_TR_OUT3 = 0x00000ABEu, /* canfd[0].tr_fifo1[3] */ 1229 TRIG_IN_MUX_10_CAN0_FIFO1_TR_OUT4 = 0x00000ABFu, /* canfd[0].tr_fifo1[4] */ 1230 TRIG_IN_MUX_10_CAN0_TT_TR_OUT0 = 0x00000AC0u, /* canfd[0].tr_tmp_rtp_out[0] */ 1231 TRIG_IN_MUX_10_CAN0_TT_TR_OUT1 = 0x00000AC1u, /* canfd[0].tr_tmp_rtp_out[1] */ 1232 TRIG_IN_MUX_10_CAN0_TT_TR_OUT2 = 0x00000AC2u, /* canfd[0].tr_tmp_rtp_out[2] */ 1233 TRIG_IN_MUX_10_CAN0_TT_TR_OUT3 = 0x00000AC3u, /* canfd[0].tr_tmp_rtp_out[3] */ 1234 TRIG_IN_MUX_10_CAN0_TT_TR_OUT4 = 0x00000AC4u, /* canfd[0].tr_tmp_rtp_out[4] */ 1235 TRIG_IN_MUX_10_CAN1_DBG_TR_OUT0 = 0x00000AC5u, /* canfd[1].tr_dbg_dma_req[0] */ 1236 TRIG_IN_MUX_10_CAN1_DBG_TR_OUT1 = 0x00000AC6u, /* canfd[1].tr_dbg_dma_req[1] */ 1237 TRIG_IN_MUX_10_CAN1_DBG_TR_OUT2 = 0x00000AC7u, /* canfd[1].tr_dbg_dma_req[2] */ 1238 TRIG_IN_MUX_10_CAN1_DBG_TR_OUT3 = 0x00000AC8u, /* canfd[1].tr_dbg_dma_req[3] */ 1239 TRIG_IN_MUX_10_CAN1_DBG_TR_OUT4 = 0x00000AC9u, /* canfd[1].tr_dbg_dma_req[4] */ 1240 TRIG_IN_MUX_10_CAN1_FIFO0_TR_OUT0 = 0x00000ACAu, /* canfd[1].tr_fifo0[0] */ 1241 TRIG_IN_MUX_10_CAN1_FIFO0_TR_OUT1 = 0x00000ACBu, /* canfd[1].tr_fifo0[1] */ 1242 TRIG_IN_MUX_10_CAN1_FIFO0_TR_OUT2 = 0x00000ACCu, /* canfd[1].tr_fifo0[2] */ 1243 TRIG_IN_MUX_10_CAN1_FIFO0_TR_OUT3 = 0x00000ACDu, /* canfd[1].tr_fifo0[3] */ 1244 TRIG_IN_MUX_10_CAN1_FIFO0_TR_OUT4 = 0x00000ACEu, /* canfd[1].tr_fifo0[4] */ 1245 TRIG_IN_MUX_10_CAN1_FIFO1_TR_OUT0 = 0x00000ACFu, /* canfd[1].tr_fifo1[0] */ 1246 TRIG_IN_MUX_10_CAN1_FIFO1_TR_OUT1 = 0x00000AD0u, /* canfd[1].tr_fifo1[1] */ 1247 TRIG_IN_MUX_10_CAN1_FIFO1_TR_OUT2 = 0x00000AD1u, /* canfd[1].tr_fifo1[2] */ 1248 TRIG_IN_MUX_10_CAN1_FIFO1_TR_OUT3 = 0x00000AD2u, /* canfd[1].tr_fifo1[3] */ 1249 TRIG_IN_MUX_10_CAN1_FIFO1_TR_OUT4 = 0x00000AD3u, /* canfd[1].tr_fifo1[4] */ 1250 TRIG_IN_MUX_10_CAN1_TT_TR_OUT0 = 0x00000AD4u, /* canfd[1].tr_tmp_rtp_out[0] */ 1251 TRIG_IN_MUX_10_CAN1_TT_TR_OUT1 = 0x00000AD5u, /* canfd[1].tr_tmp_rtp_out[1] */ 1252 TRIG_IN_MUX_10_CAN1_TT_TR_OUT2 = 0x00000AD6u, /* canfd[1].tr_tmp_rtp_out[2] */ 1253 TRIG_IN_MUX_10_CAN1_TT_TR_OUT3 = 0x00000AD7u, /* canfd[1].tr_tmp_rtp_out[3] */ 1254 TRIG_IN_MUX_10_CAN1_TT_TR_OUT4 = 0x00000AD8u, /* canfd[1].tr_tmp_rtp_out[4] */ 1255 TRIG_IN_MUX_10_CTI_TR_OUT0 = 0x00000AD9u, /* cpuss.cti_tr_out[0] */ 1256 TRIG_IN_MUX_10_CTI_TR_OUT1 = 0x00000ADAu, /* cpuss.cti_tr_out[1] */ 1257 TRIG_IN_MUX_10_FAULT_TR_OU0 = 0x00000ADBu, /* cpuss.tr_fault[0] */ 1258 TRIG_IN_MUX_10_FAULT_TR_OU1 = 0x00000ADCu, /* cpuss.tr_fault[1] */ 1259 TRIG_IN_MUX_10_FAULT_TR_OU2 = 0x00000ADDu, /* cpuss.tr_fault[2] */ 1260 TRIG_IN_MUX_10_FAULT_TR_OU3 = 0x00000ADEu, /* cpuss.tr_fault[3] */ 1261 TRIG_IN_MUX_10_EVTGEN_TR_OUT0 = 0x00000ADFu, /* evtgen[0].tr_out[0] */ 1262 TRIG_IN_MUX_10_EVTGEN_TR_OUT1 = 0x00000AE0u, /* evtgen[0].tr_out[1] */ 1263 TRIG_IN_MUX_10_EVTGEN_TR_OUT2 = 0x00000AE1u, /* evtgen[0].tr_out[2] */ 1264 TRIG_IN_MUX_10_EVTGEN_TR_OUT3 = 0x00000AE2u, /* evtgen[0].tr_out[3] */ 1265 TRIG_IN_MUX_10_EVTGEN_TR_OUT4 = 0x00000AE3u, /* evtgen[0].tr_out[4] */ 1266 TRIG_IN_MUX_10_EVTGEN_TR_OUT5 = 0x00000AE4u, /* evtgen[0].tr_out[5] */ 1267 TRIG_IN_MUX_10_EVTGEN_TR_OUT6 = 0x00000AE5u, /* evtgen[0].tr_out[6] */ 1268 TRIG_IN_MUX_10_EVTGEN_TR_OUT7 = 0x00000AE6u, /* evtgen[0].tr_out[7] */ 1269 TRIG_IN_MUX_10_EVTGEN_TR_OUT8 = 0x00000AE7u, /* evtgen[0].tr_out[8] */ 1270 TRIG_IN_MUX_10_EVTGEN_TR_OUT9 = 0x00000AE8u, /* evtgen[0].tr_out[9] */ 1271 TRIG_IN_MUX_10_EVTGEN_TR_OUT10 = 0x00000AE9u, /* evtgen[0].tr_out[10] */ 1272 TRIG_IN_MUX_10_EVTGEN_TR_OUT11 = 0x00000AEAu, /* evtgen[0].tr_out[11] */ 1273 TRIG_IN_MUX_10_EVTGEN_TR_OUT12 = 0x00000AEBu, /* evtgen[0].tr_out[12] */ 1274 TRIG_IN_MUX_10_EVTGEN_TR_OUT13 = 0x00000AECu, /* evtgen[0].tr_out[13] */ 1275 TRIG_IN_MUX_10_EVTGEN_TR_OUT14 = 0x00000AEDu, /* evtgen[0].tr_out[14] */ 1276 TRIG_IN_MUX_10_EVTGEN_TR_OUT15 = 0x00000AEEu /* evtgen[0].tr_out[15] */ 1277 } en_trig_input_debugreduction1_t; 1278 1279 /* Trigger Input Group 11 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1280 typedef enum 1281 { 1282 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT00 = 0x00000B01u, /* tcpwm[1].tr_out0[512] */ 1283 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT01 = 0x00000B02u, /* tcpwm[1].tr_out0[513] */ 1284 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT02 = 0x00000B03u, /* tcpwm[1].tr_out0[514] */ 1285 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT03 = 0x00000B04u, /* tcpwm[1].tr_out0[515] */ 1286 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT04 = 0x00000B05u, /* tcpwm[1].tr_out0[516] */ 1287 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT05 = 0x00000B06u, /* tcpwm[1].tr_out0[517] */ 1288 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT06 = 0x00000B07u, /* tcpwm[1].tr_out0[518] */ 1289 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT07 = 0x00000B08u, /* tcpwm[1].tr_out0[519] */ 1290 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT08 = 0x00000B09u, /* tcpwm[1].tr_out0[520] */ 1291 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT09 = 0x00000B0Au, /* tcpwm[1].tr_out0[521] */ 1292 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT010 = 0x00000B0Bu, /* tcpwm[1].tr_out0[522] */ 1293 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT011 = 0x00000B0Cu, /* tcpwm[1].tr_out0[523] */ 1294 TRIG_IN_MUX_11_TCPWM1_32_TR_OUT012 = 0x00000B0Du, /* tcpwm[1].tr_out0[524] */ 1295 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT00 = 0x00000B0Eu, /* tcpwm[0].tr_out0[512] */ 1296 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT01 = 0x00000B0Fu, /* tcpwm[0].tr_out0[513] */ 1297 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT02 = 0x00000B10u, /* tcpwm[0].tr_out0[514] */ 1298 TRIG_IN_MUX_11_TCPWM1_16M_TR_OUT00 = 0x00000B11u, /* tcpwm[1].tr_out0[256] */ 1299 TRIG_IN_MUX_11_TCPWM1_16M_TR_OUT01 = 0x00000B12u, /* tcpwm[1].tr_out0[257] */ 1300 TRIG_IN_MUX_11_TCPWM1_16M_TR_OUT02 = 0x00000B13u, /* tcpwm[1].tr_out0[258] */ 1301 TRIG_IN_MUX_11_TCPWM1_16M_TR_OUT03 = 0x00000B14u, /* tcpwm[1].tr_out0[259] */ 1302 TRIG_IN_MUX_11_TCPWM1_16M_TR_OUT04 = 0x00000B15u, /* tcpwm[1].tr_out0[260] */ 1303 TRIG_IN_MUX_11_TCPWM1_16M_TR_OUT05 = 0x00000B16u, /* tcpwm[1].tr_out0[261] */ 1304 TRIG_IN_MUX_11_TCPWM1_16M_TR_OUT06 = 0x00000B17u, /* tcpwm[1].tr_out0[262] */ 1305 TRIG_IN_MUX_11_TCPWM1_16M_TR_OUT07 = 0x00000B18u, /* tcpwm[1].tr_out0[263] */ 1306 TRIG_IN_MUX_11_TCPWM1_16M_TR_OUT08 = 0x00000B19u, /* tcpwm[1].tr_out0[264] */ 1307 TRIG_IN_MUX_11_TCPWM1_16M_TR_OUT09 = 0x00000B1Au, /* tcpwm[1].tr_out0[265] */ 1308 TRIG_IN_MUX_11_TCPWM1_16M_TR_OUT010 = 0x00000B1Bu, /* tcpwm[1].tr_out0[266] */ 1309 TRIG_IN_MUX_11_TCPWM1_16M_TR_OUT011 = 0x00000B1Cu, /* tcpwm[1].tr_out0[267] */ 1310 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT00 = 0x00000B1Du, /* tcpwm[0].tr_out0[256] */ 1311 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT01 = 0x00000B1Eu, /* tcpwm[0].tr_out0[257] */ 1312 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT02 = 0x00000B1Fu, /* tcpwm[0].tr_out0[258] */ 1313 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT00 = 0x00000B20u, /* tcpwm[1].tr_out0[0] */ 1314 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT01 = 0x00000B21u, /* tcpwm[1].tr_out0[1] */ 1315 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT02 = 0x00000B22u, /* tcpwm[1].tr_out0[2] */ 1316 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT03 = 0x00000B23u, /* tcpwm[1].tr_out0[3] */ 1317 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT04 = 0x00000B24u, /* tcpwm[1].tr_out0[4] */ 1318 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT05 = 0x00000B25u, /* tcpwm[1].tr_out0[5] */ 1319 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT06 = 0x00000B26u, /* tcpwm[1].tr_out0[6] */ 1320 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT07 = 0x00000B27u, /* tcpwm[1].tr_out0[7] */ 1321 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT08 = 0x00000B28u, /* tcpwm[1].tr_out0[8] */ 1322 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT09 = 0x00000B29u, /* tcpwm[1].tr_out0[9] */ 1323 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT010 = 0x00000B2Au, /* tcpwm[1].tr_out0[10] */ 1324 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT011 = 0x00000B2Bu, /* tcpwm[1].tr_out0[11] */ 1325 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT012 = 0x00000B2Cu, /* tcpwm[1].tr_out0[12] */ 1326 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT013 = 0x00000B2Du, /* tcpwm[1].tr_out0[13] */ 1327 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT014 = 0x00000B2Eu, /* tcpwm[1].tr_out0[14] */ 1328 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT015 = 0x00000B2Fu, /* tcpwm[1].tr_out0[15] */ 1329 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT016 = 0x00000B30u, /* tcpwm[1].tr_out0[16] */ 1330 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT017 = 0x00000B31u, /* tcpwm[1].tr_out0[17] */ 1331 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT018 = 0x00000B32u, /* tcpwm[1].tr_out0[18] */ 1332 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT019 = 0x00000B33u, /* tcpwm[1].tr_out0[19] */ 1333 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT020 = 0x00000B34u, /* tcpwm[1].tr_out0[20] */ 1334 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT021 = 0x00000B35u, /* tcpwm[1].tr_out0[21] */ 1335 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT022 = 0x00000B36u, /* tcpwm[1].tr_out0[22] */ 1336 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT023 = 0x00000B37u, /* tcpwm[1].tr_out0[23] */ 1337 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT024 = 0x00000B38u, /* tcpwm[1].tr_out0[24] */ 1338 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT025 = 0x00000B39u, /* tcpwm[1].tr_out0[25] */ 1339 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT026 = 0x00000B3Au, /* tcpwm[1].tr_out0[26] */ 1340 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT027 = 0x00000B3Bu, /* tcpwm[1].tr_out0[27] */ 1341 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT028 = 0x00000B3Cu, /* tcpwm[1].tr_out0[28] */ 1342 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT029 = 0x00000B3Du, /* tcpwm[1].tr_out0[29] */ 1343 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT030 = 0x00000B3Eu, /* tcpwm[1].tr_out0[30] */ 1344 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT031 = 0x00000B3Fu, /* tcpwm[1].tr_out0[31] */ 1345 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT032 = 0x00000B40u, /* tcpwm[1].tr_out0[32] */ 1346 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT033 = 0x00000B41u, /* tcpwm[1].tr_out0[33] */ 1347 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT034 = 0x00000B42u, /* tcpwm[1].tr_out0[34] */ 1348 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT035 = 0x00000B43u, /* tcpwm[1].tr_out0[35] */ 1349 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT036 = 0x00000B44u, /* tcpwm[1].tr_out0[36] */ 1350 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT037 = 0x00000B45u, /* tcpwm[1].tr_out0[37] */ 1351 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT038 = 0x00000B46u, /* tcpwm[1].tr_out0[38] */ 1352 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT039 = 0x00000B47u, /* tcpwm[1].tr_out0[39] */ 1353 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT040 = 0x00000B48u, /* tcpwm[1].tr_out0[40] */ 1354 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT041 = 0x00000B49u, /* tcpwm[1].tr_out0[41] */ 1355 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT042 = 0x00000B4Au, /* tcpwm[1].tr_out0[42] */ 1356 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT043 = 0x00000B4Bu, /* tcpwm[1].tr_out0[43] */ 1357 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT044 = 0x00000B4Cu, /* tcpwm[1].tr_out0[44] */ 1358 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT045 = 0x00000B4Du, /* tcpwm[1].tr_out0[45] */ 1359 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT046 = 0x00000B4Eu, /* tcpwm[1].tr_out0[46] */ 1360 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT047 = 0x00000B4Fu, /* tcpwm[1].tr_out0[47] */ 1361 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT048 = 0x00000B50u, /* tcpwm[1].tr_out0[48] */ 1362 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT049 = 0x00000B51u, /* tcpwm[1].tr_out0[49] */ 1363 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT050 = 0x00000B52u, /* tcpwm[1].tr_out0[50] */ 1364 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT051 = 0x00000B53u, /* tcpwm[1].tr_out0[51] */ 1365 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT052 = 0x00000B54u, /* tcpwm[1].tr_out0[52] */ 1366 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT053 = 0x00000B55u, /* tcpwm[1].tr_out0[53] */ 1367 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT054 = 0x00000B56u, /* tcpwm[1].tr_out0[54] */ 1368 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT055 = 0x00000B57u, /* tcpwm[1].tr_out0[55] */ 1369 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT056 = 0x00000B58u, /* tcpwm[1].tr_out0[56] */ 1370 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT057 = 0x00000B59u, /* tcpwm[1].tr_out0[57] */ 1371 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT058 = 0x00000B5Au, /* tcpwm[1].tr_out0[58] */ 1372 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT059 = 0x00000B5Bu, /* tcpwm[1].tr_out0[59] */ 1373 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT060 = 0x00000B5Cu, /* tcpwm[1].tr_out0[60] */ 1374 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT061 = 0x00000B5Du, /* tcpwm[1].tr_out0[61] */ 1375 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT062 = 0x00000B5Eu, /* tcpwm[1].tr_out0[62] */ 1376 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT063 = 0x00000B5Fu, /* tcpwm[1].tr_out0[63] */ 1377 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT064 = 0x00000B60u, /* tcpwm[1].tr_out0[64] */ 1378 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT065 = 0x00000B61u, /* tcpwm[1].tr_out0[65] */ 1379 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT066 = 0x00000B62u, /* tcpwm[1].tr_out0[66] */ 1380 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT067 = 0x00000B63u, /* tcpwm[1].tr_out0[67] */ 1381 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT068 = 0x00000B64u, /* tcpwm[1].tr_out0[68] */ 1382 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT069 = 0x00000B65u, /* tcpwm[1].tr_out0[69] */ 1383 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT070 = 0x00000B66u, /* tcpwm[1].tr_out0[70] */ 1384 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT071 = 0x00000B67u, /* tcpwm[1].tr_out0[71] */ 1385 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT072 = 0x00000B68u, /* tcpwm[1].tr_out0[72] */ 1386 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT073 = 0x00000B69u, /* tcpwm[1].tr_out0[73] */ 1387 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT074 = 0x00000B6Au, /* tcpwm[1].tr_out0[74] */ 1388 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT075 = 0x00000B6Bu, /* tcpwm[1].tr_out0[75] */ 1389 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT076 = 0x00000B6Cu, /* tcpwm[1].tr_out0[76] */ 1390 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT077 = 0x00000B6Du, /* tcpwm[1].tr_out0[77] */ 1391 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT078 = 0x00000B6Eu, /* tcpwm[1].tr_out0[78] */ 1392 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT079 = 0x00000B6Fu, /* tcpwm[1].tr_out0[79] */ 1393 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT080 = 0x00000B70u, /* tcpwm[1].tr_out0[80] */ 1394 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT081 = 0x00000B71u, /* tcpwm[1].tr_out0[81] */ 1395 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT082 = 0x00000B72u, /* tcpwm[1].tr_out0[82] */ 1396 TRIG_IN_MUX_11_TCPWM1_16_TR_OUT083 = 0x00000B73u, /* tcpwm[1].tr_out0[83] */ 1397 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT00 = 0x00000B74u, /* tcpwm[0].tr_out0[0] */ 1398 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT01 = 0x00000B75u, /* tcpwm[0].tr_out0[1] */ 1399 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT02 = 0x00000B76u, /* tcpwm[0].tr_out0[2] */ 1400 TRIG_IN_MUX_11_SMIF_TX_TR_OUT = 0x00000B77u, /* smif[0].tr_tx_req */ 1401 TRIG_IN_MUX_11_SMIF_RX_TR_OUT = 0x00000B78u, /* smif[0].tr_rx_req */ 1402 TRIG_IN_MUX_11_FLEXRAY_TT_TR_OUT = 0x00000B79u, /* flexray[0].tr_tint0_out */ 1403 TRIG_IN_MUX_11_FLEXRAY_IBUF_TR_OUT = 0x00000B7Au, /* flexray[0].tr_ibf_out */ 1404 TRIG_IN_MUX_11_FLEXRAY_OBUF_TR_OUT = 0x00000B7Bu, /* flexray[0].tr_obf_out */ 1405 TRIG_IN_MUX_11_I2S0_TX_TR_OUT = 0x00000B7Cu, /* audioss[0].tr_i2s_tx_req */ 1406 TRIG_IN_MUX_11_I2S0_RX_TR_OUT = 0x00000B7Du, /* audioss[0].tr_i2s_rx_req */ 1407 TRIG_IN_MUX_11_I2S1_TX_TR_OUT = 0x00000B7Eu, /* audioss[1].tr_i2s_tx_req */ 1408 TRIG_IN_MUX_11_I2S1_RX_TR_OUT = 0x00000B7Fu, /* audioss[1].tr_i2s_rx_req */ 1409 TRIG_IN_MUX_11_I2S2_TX_TR_OUT = 0x00000B80u, /* audioss[2].tr_i2s_tx_req */ 1410 TRIG_IN_MUX_11_I2S2_RX_TR_OUT = 0x00000B81u, /* audioss[2].tr_i2s_rx_req */ 1411 TRIG_IN_MUX_11_HSIOM_IO_INPUT0 = 0x00000B82u, /* peri.tr_io_input[0] */ 1412 TRIG_IN_MUX_11_HSIOM_IO_INPUT1 = 0x00000B83u, /* peri.tr_io_input[1] */ 1413 TRIG_IN_MUX_11_HSIOM_IO_INPUT2 = 0x00000B84u, /* peri.tr_io_input[2] */ 1414 TRIG_IN_MUX_11_HSIOM_IO_INPUT3 = 0x00000B85u, /* peri.tr_io_input[3] */ 1415 TRIG_IN_MUX_11_HSIOM_IO_INPUT4 = 0x00000B86u, /* peri.tr_io_input[4] */ 1416 TRIG_IN_MUX_11_HSIOM_IO_INPUT5 = 0x00000B87u, /* peri.tr_io_input[5] */ 1417 TRIG_IN_MUX_11_HSIOM_IO_INPUT6 = 0x00000B88u, /* peri.tr_io_input[6] */ 1418 TRIG_IN_MUX_11_HSIOM_IO_INPUT7 = 0x00000B89u, /* peri.tr_io_input[7] */ 1419 TRIG_IN_MUX_11_HSIOM_IO_INPUT8 = 0x00000B8Au, /* peri.tr_io_input[8] */ 1420 TRIG_IN_MUX_11_HSIOM_IO_INPUT9 = 0x00000B8Bu, /* peri.tr_io_input[9] */ 1421 TRIG_IN_MUX_11_HSIOM_IO_INPUT10 = 0x00000B8Cu, /* peri.tr_io_input[10] */ 1422 TRIG_IN_MUX_11_HSIOM_IO_INPUT11 = 0x00000B8Du, /* peri.tr_io_input[11] */ 1423 TRIG_IN_MUX_11_HSIOM_IO_INPUT12 = 0x00000B8Eu, /* peri.tr_io_input[12] */ 1424 TRIG_IN_MUX_11_HSIOM_IO_INPUT13 = 0x00000B8Fu, /* peri.tr_io_input[13] */ 1425 TRIG_IN_MUX_11_HSIOM_IO_INPUT14 = 0x00000B90u, /* peri.tr_io_input[14] */ 1426 TRIG_IN_MUX_11_HSIOM_IO_INPUT15 = 0x00000B91u, /* peri.tr_io_input[15] */ 1427 TRIG_IN_MUX_11_HSIOM_IO_INPUT16 = 0x00000B92u, /* peri.tr_io_input[16] */ 1428 TRIG_IN_MUX_11_HSIOM_IO_INPUT17 = 0x00000B93u, /* peri.tr_io_input[17] */ 1429 TRIG_IN_MUX_11_HSIOM_IO_INPUT18 = 0x00000B94u, /* peri.tr_io_input[18] */ 1430 TRIG_IN_MUX_11_HSIOM_IO_INPUT19 = 0x00000B95u, /* peri.tr_io_input[19] */ 1431 TRIG_IN_MUX_11_HSIOM_IO_INPUT20 = 0x00000B96u, /* peri.tr_io_input[20] */ 1432 TRIG_IN_MUX_11_HSIOM_IO_INPUT21 = 0x00000B97u, /* peri.tr_io_input[21] */ 1433 TRIG_IN_MUX_11_HSIOM_IO_INPUT22 = 0x00000B98u, /* peri.tr_io_input[22] */ 1434 TRIG_IN_MUX_11_HSIOM_IO_INPUT23 = 0x00000B99u, /* peri.tr_io_input[23] */ 1435 TRIG_IN_MUX_11_HSIOM_IO_INPUT24 = 0x00000B9Au, /* peri.tr_io_input[24] */ 1436 TRIG_IN_MUX_11_HSIOM_IO_INPUT25 = 0x00000B9Bu, /* peri.tr_io_input[25] */ 1437 TRIG_IN_MUX_11_HSIOM_IO_INPUT26 = 0x00000B9Cu, /* peri.tr_io_input[26] */ 1438 TRIG_IN_MUX_11_HSIOM_IO_INPUT27 = 0x00000B9Du, /* peri.tr_io_input[27] */ 1439 TRIG_IN_MUX_11_HSIOM_IO_INPUT28 = 0x00000B9Eu, /* peri.tr_io_input[28] */ 1440 TRIG_IN_MUX_11_HSIOM_IO_INPUT29 = 0x00000B9Fu, /* peri.tr_io_input[29] */ 1441 TRIG_IN_MUX_11_HSIOM_IO_INPUT30 = 0x00000BA0u, /* peri.tr_io_input[30] */ 1442 TRIG_IN_MUX_11_HSIOM_IO_INPUT31 = 0x00000BA1u, /* peri.tr_io_input[31] */ 1443 TRIG_IN_MUX_11_HSIOM_IO_INPUT32 = 0x00000BA2u, /* peri.tr_io_input[32] */ 1444 TRIG_IN_MUX_11_HSIOM_IO_INPUT33 = 0x00000BA3u, /* peri.tr_io_input[33] */ 1445 TRIG_IN_MUX_11_HSIOM_IO_INPUT34 = 0x00000BA4u, /* peri.tr_io_input[34] */ 1446 TRIG_IN_MUX_11_HSIOM_IO_INPUT35 = 0x00000BA5u, /* peri.tr_io_input[35] */ 1447 TRIG_IN_MUX_11_HSIOM_IO_INPUT36 = 0x00000BA6u, /* peri.tr_io_input[36] */ 1448 TRIG_IN_MUX_11_HSIOM_IO_INPUT37 = 0x00000BA7u, /* peri.tr_io_input[37] */ 1449 TRIG_IN_MUX_11_HSIOM_IO_INPUT38 = 0x00000BA8u, /* peri.tr_io_input[38] */ 1450 TRIG_IN_MUX_11_HSIOM_IO_INPUT39 = 0x00000BA9u, /* peri.tr_io_input[39] */ 1451 TRIG_IN_MUX_11_HSIOM_IO_INPUT40 = 0x00000BAAu, /* peri.tr_io_input[40] */ 1452 TRIG_IN_MUX_11_HSIOM_IO_INPUT41 = 0x00000BABu, /* peri.tr_io_input[41] */ 1453 TRIG_IN_MUX_11_HSIOM_IO_INPUT42 = 0x00000BACu, /* peri.tr_io_input[42] */ 1454 TRIG_IN_MUX_11_HSIOM_IO_INPUT43 = 0x00000BADu, /* peri.tr_io_input[43] */ 1455 TRIG_IN_MUX_11_HSIOM_IO_INPUT44 = 0x00000BAEu, /* peri.tr_io_input[44] */ 1456 TRIG_IN_MUX_11_HSIOM_IO_INPUT45 = 0x00000BAFu, /* peri.tr_io_input[45] */ 1457 TRIG_IN_MUX_11_HSIOM_IO_INPUT46 = 0x00000BB0u, /* peri.tr_io_input[46] */ 1458 TRIG_IN_MUX_11_HSIOM_IO_INPUT47 = 0x00000BB1u /* peri.tr_io_input[47] */ 1459 } en_trig_input_debugreduction2_t; 1460 1461 /* Trigger Input Group 12 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1462 typedef enum 1463 { 1464 TRIG_IN_MUX_12_PDMA1_TR_OUT0 = 0x00000C01u, /* cpuss.dw1_tr_out[0] */ 1465 TRIG_IN_MUX_12_PDMA1_TR_OUT1 = 0x00000C02u, /* cpuss.dw1_tr_out[1] */ 1466 TRIG_IN_MUX_12_PDMA1_TR_OUT2 = 0x00000C03u, /* cpuss.dw1_tr_out[2] */ 1467 TRIG_IN_MUX_12_PDMA1_TR_OUT3 = 0x00000C04u, /* cpuss.dw1_tr_out[3] */ 1468 TRIG_IN_MUX_12_PDMA1_TR_OUT4 = 0x00000C05u, /* cpuss.dw1_tr_out[4] */ 1469 TRIG_IN_MUX_12_PDMA1_TR_OUT5 = 0x00000C06u, /* cpuss.dw1_tr_out[5] */ 1470 TRIG_IN_MUX_12_PDMA1_TR_OUT6 = 0x00000C07u, /* cpuss.dw1_tr_out[6] */ 1471 TRIG_IN_MUX_12_PDMA1_TR_OUT7 = 0x00000C08u, /* cpuss.dw1_tr_out[7] */ 1472 TRIG_IN_MUX_12_PDMA1_TR_OUT8 = 0x00000C09u, /* cpuss.dw1_tr_out[8] */ 1473 TRIG_IN_MUX_12_PDMA1_TR_OUT9 = 0x00000C0Au, /* cpuss.dw1_tr_out[9] */ 1474 TRIG_IN_MUX_12_PDMA1_TR_OUT10 = 0x00000C0Bu, /* cpuss.dw1_tr_out[10] */ 1475 TRIG_IN_MUX_12_PDMA1_TR_OUT11 = 0x00000C0Cu, /* cpuss.dw1_tr_out[11] */ 1476 TRIG_IN_MUX_12_PDMA1_TR_OUT12 = 0x00000C0Du, /* cpuss.dw1_tr_out[12] */ 1477 TRIG_IN_MUX_12_PDMA1_TR_OUT13 = 0x00000C0Eu, /* cpuss.dw1_tr_out[13] */ 1478 TRIG_IN_MUX_12_PDMA1_TR_OUT14 = 0x00000C0Fu, /* cpuss.dw1_tr_out[14] */ 1479 TRIG_IN_MUX_12_PDMA1_TR_OUT15 = 0x00000C10u, /* cpuss.dw1_tr_out[15] */ 1480 TRIG_IN_MUX_12_PDMA1_TR_OUT16 = 0x00000C11u, /* cpuss.dw1_tr_out[16] */ 1481 TRIG_IN_MUX_12_PDMA1_TR_OUT17 = 0x00000C12u, /* cpuss.dw1_tr_out[17] */ 1482 TRIG_IN_MUX_12_PDMA1_TR_OUT18 = 0x00000C13u, /* cpuss.dw1_tr_out[18] */ 1483 TRIG_IN_MUX_12_PDMA1_TR_OUT19 = 0x00000C14u, /* cpuss.dw1_tr_out[19] */ 1484 TRIG_IN_MUX_12_PDMA1_TR_OUT20 = 0x00000C15u, /* cpuss.dw1_tr_out[20] */ 1485 TRIG_IN_MUX_12_PDMA1_TR_OUT21 = 0x00000C16u, /* cpuss.dw1_tr_out[21] */ 1486 TRIG_IN_MUX_12_PDMA1_TR_OUT22 = 0x00000C17u, /* cpuss.dw1_tr_out[22] */ 1487 TRIG_IN_MUX_12_PDMA1_TR_OUT23 = 0x00000C18u, /* cpuss.dw1_tr_out[23] */ 1488 TRIG_IN_MUX_12_PDMA1_TR_OUT24 = 0x00000C19u, /* cpuss.dw1_tr_out[24] */ 1489 TRIG_IN_MUX_12_PDMA1_TR_OUT25 = 0x00000C1Au, /* cpuss.dw1_tr_out[25] */ 1490 TRIG_IN_MUX_12_PDMA1_TR_OUT26 = 0x00000C1Bu, /* cpuss.dw1_tr_out[26] */ 1491 TRIG_IN_MUX_12_PDMA1_TR_OUT27 = 0x00000C1Cu, /* cpuss.dw1_tr_out[27] */ 1492 TRIG_IN_MUX_12_PDMA1_TR_OUT28 = 0x00000C1Du, /* cpuss.dw1_tr_out[28] */ 1493 TRIG_IN_MUX_12_PDMA1_TR_OUT29 = 0x00000C1Eu, /* cpuss.dw1_tr_out[29] */ 1494 TRIG_IN_MUX_12_PDMA1_TR_OUT30 = 0x00000C1Fu, /* cpuss.dw1_tr_out[30] */ 1495 TRIG_IN_MUX_12_PDMA1_TR_OUT31 = 0x00000C20u, /* cpuss.dw1_tr_out[31] */ 1496 TRIG_IN_MUX_12_PDMA1_TR_OUT32 = 0x00000C21u, /* cpuss.dw1_tr_out[32] */ 1497 TRIG_IN_MUX_12_PDMA1_TR_OUT33 = 0x00000C22u, /* cpuss.dw1_tr_out[33] */ 1498 TRIG_IN_MUX_12_PDMA1_TR_OUT34 = 0x00000C23u, /* cpuss.dw1_tr_out[34] */ 1499 TRIG_IN_MUX_12_PDMA1_TR_OUT35 = 0x00000C24u, /* cpuss.dw1_tr_out[35] */ 1500 TRIG_IN_MUX_12_PDMA1_TR_OUT36 = 0x00000C25u, /* cpuss.dw1_tr_out[36] */ 1501 TRIG_IN_MUX_12_PDMA1_TR_OUT37 = 0x00000C26u, /* cpuss.dw1_tr_out[37] */ 1502 TRIG_IN_MUX_12_PDMA1_TR_OUT38 = 0x00000C27u, /* cpuss.dw1_tr_out[38] */ 1503 TRIG_IN_MUX_12_PDMA1_TR_OUT39 = 0x00000C28u, /* cpuss.dw1_tr_out[39] */ 1504 TRIG_IN_MUX_12_PDMA1_TR_OUT40 = 0x00000C29u, /* cpuss.dw1_tr_out[40] */ 1505 TRIG_IN_MUX_12_PDMA1_TR_OUT41 = 0x00000C2Au, /* cpuss.dw1_tr_out[41] */ 1506 TRIG_IN_MUX_12_PDMA1_TR_OUT42 = 0x00000C2Bu, /* cpuss.dw1_tr_out[42] */ 1507 TRIG_IN_MUX_12_PDMA1_TR_OUT43 = 0x00000C2Cu, /* cpuss.dw1_tr_out[43] */ 1508 TRIG_IN_MUX_12_PDMA1_TR_OUT44 = 0x00000C2Du, /* cpuss.dw1_tr_out[44] */ 1509 TRIG_IN_MUX_12_PDMA1_TR_OUT45 = 0x00000C2Eu, /* cpuss.dw1_tr_out[45] */ 1510 TRIG_IN_MUX_12_PDMA1_TR_OUT46 = 0x00000C2Fu, /* cpuss.dw1_tr_out[46] */ 1511 TRIG_IN_MUX_12_PDMA1_TR_OUT47 = 0x00000C30u, /* cpuss.dw1_tr_out[47] */ 1512 TRIG_IN_MUX_12_PDMA1_TR_OUT48 = 0x00000C31u, /* cpuss.dw1_tr_out[48] */ 1513 TRIG_IN_MUX_12_PDMA1_TR_OUT49 = 0x00000C32u, /* cpuss.dw1_tr_out[49] */ 1514 TRIG_IN_MUX_12_PDMA1_TR_OUT50 = 0x00000C33u, /* cpuss.dw1_tr_out[50] */ 1515 TRIG_IN_MUX_12_PDMA1_TR_OUT51 = 0x00000C34u, /* cpuss.dw1_tr_out[51] */ 1516 TRIG_IN_MUX_12_PDMA1_TR_OUT52 = 0x00000C35u, /* cpuss.dw1_tr_out[52] */ 1517 TRIG_IN_MUX_12_PDMA1_TR_OUT53 = 0x00000C36u, /* cpuss.dw1_tr_out[53] */ 1518 TRIG_IN_MUX_12_PDMA1_TR_OUT54 = 0x00000C37u, /* cpuss.dw1_tr_out[54] */ 1519 TRIG_IN_MUX_12_PDMA1_TR_OUT55 = 0x00000C38u, /* cpuss.dw1_tr_out[55] */ 1520 TRIG_IN_MUX_12_PDMA1_TR_OUT56 = 0x00000C39u, /* cpuss.dw1_tr_out[56] */ 1521 TRIG_IN_MUX_12_PDMA1_TR_OUT57 = 0x00000C3Au, /* cpuss.dw1_tr_out[57] */ 1522 TRIG_IN_MUX_12_PDMA1_TR_OUT58 = 0x00000C3Bu, /* cpuss.dw1_tr_out[58] */ 1523 TRIG_IN_MUX_12_PDMA1_TR_OUT59 = 0x00000C3Cu, /* cpuss.dw1_tr_out[59] */ 1524 TRIG_IN_MUX_12_PDMA1_TR_OUT60 = 0x00000C3Du, /* cpuss.dw1_tr_out[60] */ 1525 TRIG_IN_MUX_12_PDMA1_TR_OUT61 = 0x00000C3Eu, /* cpuss.dw1_tr_out[61] */ 1526 TRIG_IN_MUX_12_PDMA1_TR_OUT62 = 0x00000C3Fu, /* cpuss.dw1_tr_out[62] */ 1527 TRIG_IN_MUX_12_PDMA1_TR_OUT63 = 0x00000C40u, /* cpuss.dw1_tr_out[63] */ 1528 TRIG_IN_MUX_12_PDMA1_TR_OUT64 = 0x00000C41u, /* cpuss.dw1_tr_out[64] */ 1529 TRIG_IN_MUX_12_MDMA_TR_OUT0 = 0x00000C42u, /* cpuss.dmac_tr_out[0] */ 1530 TRIG_IN_MUX_12_MDMA_TR_OUT1 = 0x00000C43u, /* cpuss.dmac_tr_out[1] */ 1531 TRIG_IN_MUX_12_MDMA_TR_OUT2 = 0x00000C44u, /* cpuss.dmac_tr_out[2] */ 1532 TRIG_IN_MUX_12_MDMA_TR_OUT3 = 0x00000C45u, /* cpuss.dmac_tr_out[3] */ 1533 TRIG_IN_MUX_12_MDMA_TR_OUT4 = 0x00000C46u, /* cpuss.dmac_tr_out[4] */ 1534 TRIG_IN_MUX_12_MDMA_TR_OUT5 = 0x00000C47u, /* cpuss.dmac_tr_out[5] */ 1535 TRIG_IN_MUX_12_MDMA_TR_OUT6 = 0x00000C48u, /* cpuss.dmac_tr_out[6] */ 1536 TRIG_IN_MUX_12_MDMA_TR_OUT7 = 0x00000C49u, /* cpuss.dmac_tr_out[7] */ 1537 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT10 = 0x00000C4Au, /* tcpwm[0].tr_out1[0] */ 1538 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT11 = 0x00000C4Bu, /* tcpwm[0].tr_out1[1] */ 1539 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT12 = 0x00000C4Cu, /* tcpwm[0].tr_out1[2] */ 1540 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT10 = 0x00000C4Du, /* tcpwm[0].tr_out1[256] */ 1541 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT11 = 0x00000C4Eu, /* tcpwm[0].tr_out1[257] */ 1542 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT12 = 0x00000C4Fu, /* tcpwm[0].tr_out1[258] */ 1543 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT10 = 0x00000C50u, /* tcpwm[0].tr_out1[512] */ 1544 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT11 = 0x00000C51u, /* tcpwm[0].tr_out1[513] */ 1545 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT12 = 0x00000C52u, /* tcpwm[0].tr_out1[514] */ 1546 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT10 = 0x00000C53u, /* tcpwm[1].tr_out1[0] */ 1547 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT11 = 0x00000C54u, /* tcpwm[1].tr_out1[1] */ 1548 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT12 = 0x00000C55u, /* tcpwm[1].tr_out1[2] */ 1549 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT13 = 0x00000C56u, /* tcpwm[1].tr_out1[3] */ 1550 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT14 = 0x00000C57u, /* tcpwm[1].tr_out1[4] */ 1551 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT15 = 0x00000C58u, /* tcpwm[1].tr_out1[5] */ 1552 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT16 = 0x00000C59u, /* tcpwm[1].tr_out1[6] */ 1553 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT17 = 0x00000C5Au, /* tcpwm[1].tr_out1[7] */ 1554 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT18 = 0x00000C5Bu, /* tcpwm[1].tr_out1[8] */ 1555 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT19 = 0x00000C5Cu, /* tcpwm[1].tr_out1[9] */ 1556 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT110 = 0x00000C5Du, /* tcpwm[1].tr_out1[10] */ 1557 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT111 = 0x00000C5Eu, /* tcpwm[1].tr_out1[11] */ 1558 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT112 = 0x00000C5Fu, /* tcpwm[1].tr_out1[12] */ 1559 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT113 = 0x00000C60u, /* tcpwm[1].tr_out1[13] */ 1560 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT114 = 0x00000C61u, /* tcpwm[1].tr_out1[14] */ 1561 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT115 = 0x00000C62u, /* tcpwm[1].tr_out1[15] */ 1562 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT116 = 0x00000C63u, /* tcpwm[1].tr_out1[16] */ 1563 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT117 = 0x00000C64u, /* tcpwm[1].tr_out1[17] */ 1564 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT118 = 0x00000C65u, /* tcpwm[1].tr_out1[18] */ 1565 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT119 = 0x00000C66u, /* tcpwm[1].tr_out1[19] */ 1566 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT120 = 0x00000C67u, /* tcpwm[1].tr_out1[20] */ 1567 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT121 = 0x00000C68u, /* tcpwm[1].tr_out1[21] */ 1568 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT122 = 0x00000C69u, /* tcpwm[1].tr_out1[22] */ 1569 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT123 = 0x00000C6Au, /* tcpwm[1].tr_out1[23] */ 1570 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT124 = 0x00000C6Bu, /* tcpwm[1].tr_out1[24] */ 1571 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT125 = 0x00000C6Cu, /* tcpwm[1].tr_out1[25] */ 1572 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT126 = 0x00000C6Du, /* tcpwm[1].tr_out1[26] */ 1573 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT127 = 0x00000C6Eu, /* tcpwm[1].tr_out1[27] */ 1574 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT128 = 0x00000C6Fu, /* tcpwm[1].tr_out1[28] */ 1575 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT129 = 0x00000C70u, /* tcpwm[1].tr_out1[29] */ 1576 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT130 = 0x00000C71u, /* tcpwm[1].tr_out1[30] */ 1577 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT131 = 0x00000C72u, /* tcpwm[1].tr_out1[31] */ 1578 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT132 = 0x00000C73u, /* tcpwm[1].tr_out1[32] */ 1579 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT133 = 0x00000C74u, /* tcpwm[1].tr_out1[33] */ 1580 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT134 = 0x00000C75u, /* tcpwm[1].tr_out1[34] */ 1581 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT135 = 0x00000C76u, /* tcpwm[1].tr_out1[35] */ 1582 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT136 = 0x00000C77u, /* tcpwm[1].tr_out1[36] */ 1583 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT137 = 0x00000C78u, /* tcpwm[1].tr_out1[37] */ 1584 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT138 = 0x00000C79u, /* tcpwm[1].tr_out1[38] */ 1585 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT139 = 0x00000C7Au, /* tcpwm[1].tr_out1[39] */ 1586 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT140 = 0x00000C7Bu, /* tcpwm[1].tr_out1[40] */ 1587 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT141 = 0x00000C7Cu, /* tcpwm[1].tr_out1[41] */ 1588 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT142 = 0x00000C7Du, /* tcpwm[1].tr_out1[42] */ 1589 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT143 = 0x00000C7Eu, /* tcpwm[1].tr_out1[43] */ 1590 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT144 = 0x00000C7Fu, /* tcpwm[1].tr_out1[44] */ 1591 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT145 = 0x00000C80u, /* tcpwm[1].tr_out1[45] */ 1592 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT146 = 0x00000C81u, /* tcpwm[1].tr_out1[46] */ 1593 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT147 = 0x00000C82u, /* tcpwm[1].tr_out1[47] */ 1594 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT148 = 0x00000C83u, /* tcpwm[1].tr_out1[48] */ 1595 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT149 = 0x00000C84u, /* tcpwm[1].tr_out1[49] */ 1596 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT150 = 0x00000C85u, /* tcpwm[1].tr_out1[50] */ 1597 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT151 = 0x00000C86u, /* tcpwm[1].tr_out1[51] */ 1598 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT152 = 0x00000C87u, /* tcpwm[1].tr_out1[52] */ 1599 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT153 = 0x00000C88u, /* tcpwm[1].tr_out1[53] */ 1600 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT154 = 0x00000C89u, /* tcpwm[1].tr_out1[54] */ 1601 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT155 = 0x00000C8Au, /* tcpwm[1].tr_out1[55] */ 1602 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT156 = 0x00000C8Bu, /* tcpwm[1].tr_out1[56] */ 1603 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT157 = 0x00000C8Cu, /* tcpwm[1].tr_out1[57] */ 1604 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT158 = 0x00000C8Du, /* tcpwm[1].tr_out1[58] */ 1605 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT159 = 0x00000C8Eu, /* tcpwm[1].tr_out1[59] */ 1606 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT160 = 0x00000C8Fu, /* tcpwm[1].tr_out1[60] */ 1607 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT161 = 0x00000C90u, /* tcpwm[1].tr_out1[61] */ 1608 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT162 = 0x00000C91u, /* tcpwm[1].tr_out1[62] */ 1609 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT163 = 0x00000C92u, /* tcpwm[1].tr_out1[63] */ 1610 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT164 = 0x00000C93u, /* tcpwm[1].tr_out1[64] */ 1611 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT165 = 0x00000C94u, /* tcpwm[1].tr_out1[65] */ 1612 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT166 = 0x00000C95u, /* tcpwm[1].tr_out1[66] */ 1613 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT167 = 0x00000C96u, /* tcpwm[1].tr_out1[67] */ 1614 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT168 = 0x00000C97u, /* tcpwm[1].tr_out1[68] */ 1615 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT169 = 0x00000C98u, /* tcpwm[1].tr_out1[69] */ 1616 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT170 = 0x00000C99u, /* tcpwm[1].tr_out1[70] */ 1617 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT171 = 0x00000C9Au, /* tcpwm[1].tr_out1[71] */ 1618 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT172 = 0x00000C9Bu, /* tcpwm[1].tr_out1[72] */ 1619 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT173 = 0x00000C9Cu, /* tcpwm[1].tr_out1[73] */ 1620 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT174 = 0x00000C9Du, /* tcpwm[1].tr_out1[74] */ 1621 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT175 = 0x00000C9Eu, /* tcpwm[1].tr_out1[75] */ 1622 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT176 = 0x00000C9Fu, /* tcpwm[1].tr_out1[76] */ 1623 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT177 = 0x00000CA0u, /* tcpwm[1].tr_out1[77] */ 1624 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT178 = 0x00000CA1u, /* tcpwm[1].tr_out1[78] */ 1625 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT179 = 0x00000CA2u, /* tcpwm[1].tr_out1[79] */ 1626 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT180 = 0x00000CA3u, /* tcpwm[1].tr_out1[80] */ 1627 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT181 = 0x00000CA4u, /* tcpwm[1].tr_out1[81] */ 1628 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT182 = 0x00000CA5u, /* tcpwm[1].tr_out1[82] */ 1629 TRIG_IN_MUX_12_TCPWM1_16_TR_OUT183 = 0x00000CA6u, /* tcpwm[1].tr_out1[83] */ 1630 TRIG_IN_MUX_12_TCPWM1_16M_TR_OUT10 = 0x00000CA7u, /* tcpwm[1].tr_out1[256] */ 1631 TRIG_IN_MUX_12_TCPWM1_16M_TR_OUT11 = 0x00000CA8u, /* tcpwm[1].tr_out1[257] */ 1632 TRIG_IN_MUX_12_TCPWM1_16M_TR_OUT12 = 0x00000CA9u, /* tcpwm[1].tr_out1[258] */ 1633 TRIG_IN_MUX_12_TCPWM1_16M_TR_OUT13 = 0x00000CAAu, /* tcpwm[1].tr_out1[259] */ 1634 TRIG_IN_MUX_12_TCPWM1_16M_TR_OUT14 = 0x00000CABu, /* tcpwm[1].tr_out1[260] */ 1635 TRIG_IN_MUX_12_TCPWM1_16M_TR_OUT15 = 0x00000CACu, /* tcpwm[1].tr_out1[261] */ 1636 TRIG_IN_MUX_12_TCPWM1_16M_TR_OUT16 = 0x00000CADu, /* tcpwm[1].tr_out1[262] */ 1637 TRIG_IN_MUX_12_TCPWM1_16M_TR_OUT17 = 0x00000CAEu, /* tcpwm[1].tr_out1[263] */ 1638 TRIG_IN_MUX_12_TCPWM1_16M_TR_OUT18 = 0x00000CAFu, /* tcpwm[1].tr_out1[264] */ 1639 TRIG_IN_MUX_12_TCPWM1_16M_TR_OUT19 = 0x00000CB0u, /* tcpwm[1].tr_out1[265] */ 1640 TRIG_IN_MUX_12_TCPWM1_16M_TR_OUT110 = 0x00000CB1u, /* tcpwm[1].tr_out1[266] */ 1641 TRIG_IN_MUX_12_TCPWM1_16M_TR_OUT111 = 0x00000CB2u, /* tcpwm[1].tr_out1[267] */ 1642 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT10 = 0x00000CB3u, /* tcpwm[1].tr_out1[512] */ 1643 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT11 = 0x00000CB4u, /* tcpwm[1].tr_out1[513] */ 1644 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT12 = 0x00000CB5u, /* tcpwm[1].tr_out1[514] */ 1645 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT13 = 0x00000CB6u, /* tcpwm[1].tr_out1[515] */ 1646 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT14 = 0x00000CB7u, /* tcpwm[1].tr_out1[516] */ 1647 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT15 = 0x00000CB8u, /* tcpwm[1].tr_out1[517] */ 1648 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT16 = 0x00000CB9u, /* tcpwm[1].tr_out1[518] */ 1649 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT17 = 0x00000CBAu, /* tcpwm[1].tr_out1[519] */ 1650 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT18 = 0x00000CBBu, /* tcpwm[1].tr_out1[520] */ 1651 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT19 = 0x00000CBCu, /* tcpwm[1].tr_out1[521] */ 1652 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT110 = 0x00000CBDu, /* tcpwm[1].tr_out1[522] */ 1653 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT111 = 0x00000CBEu, /* tcpwm[1].tr_out1[523] */ 1654 TRIG_IN_MUX_12_TCPWM1_32_TR_OUT112 = 0x00000CBFu, /* tcpwm[1].tr_out1[524] */ 1655 TRIG_IN_MUX_12_PASS_GEN_TR_OUT0 = 0x00000CC0u, /* pass[0].tr_sar_gen_out[0] */ 1656 TRIG_IN_MUX_12_PASS_GEN_TR_OUT1 = 0x00000CC1u, /* pass[0].tr_sar_gen_out[1] */ 1657 TRIG_IN_MUX_12_PASS_GEN_TR_OUT2 = 0x00000CC2u, /* pass[0].tr_sar_gen_out[2] */ 1658 TRIG_IN_MUX_12_PASS_GEN_TR_OUT3 = 0x00000CC3u, /* pass[0].tr_sar_gen_out[3] */ 1659 TRIG_IN_MUX_12_PASS_GEN_TR_OUT4 = 0x00000CC4u, /* pass[0].tr_sar_gen_out[4] */ 1660 TRIG_IN_MUX_12_PASS_GEN_TR_OUT5 = 0x00000CC5u /* pass[0].tr_sar_gen_out[5] */ 1661 } en_trig_input_debugreduction3_t; 1662 1663 /* Trigger Group Outputs */ 1664 /* Trigger Output Group 0 - P-DMA0[0:15] Request Assignments */ 1665 typedef enum 1666 { 1667 TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ 1668 TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ 1669 TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ 1670 TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ 1671 TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ 1672 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ 1673 TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ 1674 TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u, /* cpuss.dw0_tr_in[7] */ 1675 TRIG_OUT_MUX_0_PDMA0_TR_IN8 = 0x40000008u, /* cpuss.dw0_tr_in[8] */ 1676 TRIG_OUT_MUX_0_PDMA0_TR_IN9 = 0x40000009u, /* cpuss.dw0_tr_in[9] */ 1677 TRIG_OUT_MUX_0_PDMA0_TR_IN10 = 0x4000000Au, /* cpuss.dw0_tr_in[10] */ 1678 TRIG_OUT_MUX_0_PDMA0_TR_IN11 = 0x4000000Bu, /* cpuss.dw0_tr_in[11] */ 1679 TRIG_OUT_MUX_0_PDMA0_TR_IN12 = 0x4000000Cu, /* cpuss.dw0_tr_in[12] */ 1680 TRIG_OUT_MUX_0_PDMA0_TR_IN13 = 0x4000000Du, /* cpuss.dw0_tr_in[13] */ 1681 TRIG_OUT_MUX_0_PDMA0_TR_IN14 = 0x4000000Eu, /* cpuss.dw0_tr_in[14] */ 1682 TRIG_OUT_MUX_0_PDMA0_TR_IN15 = 0x4000000Fu /* cpuss.dw0_tr_in[15] */ 1683 } en_trig_output_pdma0_tr_0_t; 1684 1685 /* Trigger Output Group 1 - P-DMA0[16:31] Request Assignments */ 1686 typedef enum 1687 { 1688 TRIG_OUT_MUX_1_PDMA0_TR_IN16 = 0x40000100u, /* cpuss.dw0_tr_in[16] */ 1689 TRIG_OUT_MUX_1_PDMA0_TR_IN17 = 0x40000101u, /* cpuss.dw0_tr_in[17] */ 1690 TRIG_OUT_MUX_1_PDMA0_TR_IN18 = 0x40000102u, /* cpuss.dw0_tr_in[18] */ 1691 TRIG_OUT_MUX_1_PDMA0_TR_IN19 = 0x40000103u, /* cpuss.dw0_tr_in[19] */ 1692 TRIG_OUT_MUX_1_PDMA0_TR_IN20 = 0x40000104u, /* cpuss.dw0_tr_in[20] */ 1693 TRIG_OUT_MUX_1_PDMA0_TR_IN21 = 0x40000105u, /* cpuss.dw0_tr_in[21] */ 1694 TRIG_OUT_MUX_1_PDMA0_TR_IN22 = 0x40000106u, /* cpuss.dw0_tr_in[22] */ 1695 TRIG_OUT_MUX_1_PDMA0_TR_IN23 = 0x40000107u, /* cpuss.dw0_tr_in[23] */ 1696 TRIG_OUT_MUX_1_PDMA0_TR_IN24 = 0x40000108u, /* cpuss.dw0_tr_in[24] */ 1697 TRIG_OUT_MUX_1_PDMA0_TR_IN25 = 0x40000109u, /* cpuss.dw0_tr_in[25] */ 1698 TRIG_OUT_MUX_1_PDMA0_TR_IN26 = 0x4000010Au, /* cpuss.dw0_tr_in[26] */ 1699 TRIG_OUT_MUX_1_PDMA0_TR_IN27 = 0x4000010Bu, /* cpuss.dw0_tr_in[27] */ 1700 TRIG_OUT_MUX_1_PDMA0_TR_IN28 = 0x4000010Cu, /* cpuss.dw0_tr_in[28] */ 1701 TRIG_OUT_MUX_1_PDMA0_TR_IN29 = 0x4000010Du, /* cpuss.dw0_tr_in[29] */ 1702 TRIG_OUT_MUX_1_PDMA0_TR_IN30 = 0x4000010Eu, /* cpuss.dw0_tr_in[30] */ 1703 TRIG_OUT_MUX_1_PDMA0_TR_IN31 = 0x4000010Fu /* cpuss.dw0_tr_in[31] */ 1704 } en_trig_output_pdma0_tr_1_t; 1705 1706 /* Trigger Output Group 2 - P-DMA1[0:15] Request Assignments */ 1707 typedef enum 1708 { 1709 TRIG_OUT_MUX_2_PDMA1_TR_IN0 = 0x40000200u, /* cpuss.dw1_tr_in[0] */ 1710 TRIG_OUT_MUX_2_PDMA1_TR_IN1 = 0x40000201u, /* cpuss.dw1_tr_in[1] */ 1711 TRIG_OUT_MUX_2_PDMA1_TR_IN2 = 0x40000202u, /* cpuss.dw1_tr_in[2] */ 1712 TRIG_OUT_MUX_2_PDMA1_TR_IN3 = 0x40000203u, /* cpuss.dw1_tr_in[3] */ 1713 TRIG_OUT_MUX_2_PDMA1_TR_IN4 = 0x40000204u, /* cpuss.dw1_tr_in[4] */ 1714 TRIG_OUT_MUX_2_PDMA1_TR_IN5 = 0x40000205u, /* cpuss.dw1_tr_in[5] */ 1715 TRIG_OUT_MUX_2_PDMA1_TR_IN6 = 0x40000206u, /* cpuss.dw1_tr_in[6] */ 1716 TRIG_OUT_MUX_2_PDMA1_TR_IN7 = 0x40000207u, /* cpuss.dw1_tr_in[7] */ 1717 TRIG_OUT_MUX_2_PDMA1_TR_IN8 = 0x40000208u, /* cpuss.dw1_tr_in[8] */ 1718 TRIG_OUT_MUX_2_PDMA1_TR_IN9 = 0x40000209u, /* cpuss.dw1_tr_in[9] */ 1719 TRIG_OUT_MUX_2_PDMA1_TR_IN10 = 0x4000020Au, /* cpuss.dw1_tr_in[10] */ 1720 TRIG_OUT_MUX_2_PDMA1_TR_IN11 = 0x4000020Bu, /* cpuss.dw1_tr_in[11] */ 1721 TRIG_OUT_MUX_2_PDMA1_TR_IN12 = 0x4000020Cu, /* cpuss.dw1_tr_in[12] */ 1722 TRIG_OUT_MUX_2_PDMA1_TR_IN13 = 0x4000020Du, /* cpuss.dw1_tr_in[13] */ 1723 TRIG_OUT_MUX_2_PDMA1_TR_IN14 = 0x4000020Eu, /* cpuss.dw1_tr_in[14] */ 1724 TRIG_OUT_MUX_2_PDMA1_TR_IN15 = 0x4000020Fu /* cpuss.dw1_tr_in[15] */ 1725 } en_trig_output_pdma1_tr_t; 1726 1727 /* Trigger Output Group 3 - M-DMA Request Assignments */ 1728 typedef enum 1729 { 1730 TRIG_OUT_MUX_3_MDMA_TR_IN0 = 0x40000300u, /* cpuss.dmac_tr_in[0] */ 1731 TRIG_OUT_MUX_3_MDMA_TR_IN1 = 0x40000301u, /* cpuss.dmac_tr_in[1] */ 1732 TRIG_OUT_MUX_3_MDMA_TR_IN2 = 0x40000302u, /* cpuss.dmac_tr_in[2] */ 1733 TRIG_OUT_MUX_3_MDMA_TR_IN3 = 0x40000303u, /* cpuss.dmac_tr_in[3] */ 1734 TRIG_OUT_MUX_3_MDMA_TR_IN4 = 0x40000304u, /* cpuss.dmac_tr_in[4] */ 1735 TRIG_OUT_MUX_3_MDMA_TR_IN5 = 0x40000305u, /* cpuss.dmac_tr_in[5] */ 1736 TRIG_OUT_MUX_3_MDMA_TR_IN6 = 0x40000306u, /* cpuss.dmac_tr_in[6] */ 1737 TRIG_OUT_MUX_3_MDMA_TR_IN7 = 0x40000307u /* cpuss.dmac_tr_in[7] */ 1738 } en_trig_output_mdma_t; 1739 1740 /* Trigger Output Group 4 - */ 1741 typedef enum 1742 { 1743 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN0 = 0x40000400u, /* tcpwm[0].tr_all_cnt_in[0] */ 1744 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN1 = 0x40000401u, /* tcpwm[0].tr_all_cnt_in[1] */ 1745 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN2 = 0x40000402u, /* tcpwm[0].tr_all_cnt_in[2] */ 1746 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN3 = 0x40000403u, /* tcpwm[0].tr_all_cnt_in[3] */ 1747 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN4 = 0x40000404u, /* tcpwm[0].tr_all_cnt_in[4] */ 1748 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN5 = 0x40000405u, /* tcpwm[0].tr_all_cnt_in[5] */ 1749 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN6 = 0x40000406u, /* tcpwm[0].tr_all_cnt_in[6] */ 1750 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN7 = 0x40000407u, /* tcpwm[0].tr_all_cnt_in[7] */ 1751 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN8 = 0x40000408u, /* tcpwm[0].tr_all_cnt_in[8] */ 1752 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN9 = 0x40000409u, /* tcpwm[0].tr_all_cnt_in[9] */ 1753 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN10 = 0x4000040Au, /* tcpwm[0].tr_all_cnt_in[10] */ 1754 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN11 = 0x4000040Bu /* tcpwm[0].tr_all_cnt_in[11] */ 1755 } en_trig_output_tcpwm0_out_t; 1756 1757 /* Trigger Output Group 5 - */ 1758 typedef enum 1759 { 1760 TRIG_OUT_MUX_5_TCPWM1_ALL_CNT_TR_IN0 = 0x40000500u, /* tcpwm[1].tr_all_cnt_in[0] */ 1761 TRIG_OUT_MUX_5_TCPWM1_ALL_CNT_TR_IN1 = 0x40000501u, /* tcpwm[1].tr_all_cnt_in[1] */ 1762 TRIG_OUT_MUX_5_TCPWM1_ALL_CNT_TR_IN2 = 0x40000502u, /* tcpwm[1].tr_all_cnt_in[2] */ 1763 TRIG_OUT_MUX_5_TCPWM1_ALL_CNT_TR_IN3 = 0x40000503u, /* tcpwm[1].tr_all_cnt_in[3] */ 1764 TRIG_OUT_MUX_5_TCPWM1_ALL_CNT_TR_IN4 = 0x40000504u, /* tcpwm[1].tr_all_cnt_in[4] */ 1765 TRIG_OUT_MUX_5_TCPWM1_ALL_CNT_TR_IN5 = 0x40000505u, /* tcpwm[1].tr_all_cnt_in[5] */ 1766 TRIG_OUT_MUX_5_TCPWM1_ALL_CNT_TR_IN6 = 0x40000506u, /* tcpwm[1].tr_all_cnt_in[6] */ 1767 TRIG_OUT_MUX_5_TCPWM1_ALL_CNT_TR_IN7 = 0x40000507u, /* tcpwm[1].tr_all_cnt_in[7] */ 1768 TRIG_OUT_MUX_5_TCPWM1_ALL_CNT_TR_IN8 = 0x40000508u, /* tcpwm[1].tr_all_cnt_in[8] */ 1769 TRIG_OUT_MUX_5_TCPWM1_ALL_CNT_TR_IN9 = 0x40000509u, /* tcpwm[1].tr_all_cnt_in[9] */ 1770 TRIG_OUT_MUX_5_TCPWM1_ALL_CNT_TR_IN10 = 0x4000050Au, /* tcpwm[1].tr_all_cnt_in[10] */ 1771 TRIG_OUT_MUX_5_TCPWM1_ALL_CNT_TR_IN11 = 0x4000050Bu /* tcpwm[1].tr_all_cnt_in[11] */ 1772 } en_trig_output_tcpwm1_out_t; 1773 1774 /* Trigger Output Group 6 - TCPWM trigger inputs */ 1775 typedef enum 1776 { 1777 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN12 = 0x40000600u, /* tcpwm[1].tr_all_cnt_in[12] */ 1778 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN13 = 0x40000601u, /* tcpwm[1].tr_all_cnt_in[13] */ 1779 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN14 = 0x40000602u, /* tcpwm[1].tr_all_cnt_in[14] */ 1780 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN15 = 0x40000603u, /* tcpwm[1].tr_all_cnt_in[15] */ 1781 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN16 = 0x40000604u, /* tcpwm[1].tr_all_cnt_in[16] */ 1782 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN17 = 0x40000605u, /* tcpwm[1].tr_all_cnt_in[17] */ 1783 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN18 = 0x40000606u, /* tcpwm[1].tr_all_cnt_in[18] */ 1784 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN19 = 0x40000607u, /* tcpwm[1].tr_all_cnt_in[19] */ 1785 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN20 = 0x40000608u, /* tcpwm[1].tr_all_cnt_in[20] */ 1786 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN21 = 0x40000609u, /* tcpwm[1].tr_all_cnt_in[21] */ 1787 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN22 = 0x4000060Au, /* tcpwm[1].tr_all_cnt_in[22] */ 1788 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN23 = 0x4000060Bu, /* tcpwm[1].tr_all_cnt_in[23] */ 1789 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN24 = 0x4000060Cu, /* tcpwm[1].tr_all_cnt_in[24] */ 1790 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN25 = 0x4000060Du, /* tcpwm[1].tr_all_cnt_in[25] */ 1791 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN26 = 0x4000060Eu, /* tcpwm[1].tr_all_cnt_in[26] */ 1792 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN27 = 0x4000060Fu, /* tcpwm[1].tr_all_cnt_in[27] */ 1793 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN28 = 0x40000610u, /* tcpwm[1].tr_all_cnt_in[28] */ 1794 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN29 = 0x40000611u, /* tcpwm[1].tr_all_cnt_in[29] */ 1795 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN30 = 0x40000612u, /* tcpwm[1].tr_all_cnt_in[30] */ 1796 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN31 = 0x40000613u, /* tcpwm[1].tr_all_cnt_in[31] */ 1797 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN32 = 0x40000614u, /* tcpwm[1].tr_all_cnt_in[32] */ 1798 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN33 = 0x40000615u, /* tcpwm[1].tr_all_cnt_in[33] */ 1799 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN34 = 0x40000616u, /* tcpwm[1].tr_all_cnt_in[34] */ 1800 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN35 = 0x40000617u, /* tcpwm[1].tr_all_cnt_in[35] */ 1801 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN36 = 0x40000618u, /* tcpwm[1].tr_all_cnt_in[36] */ 1802 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN37 = 0x40000619u, /* tcpwm[1].tr_all_cnt_in[37] */ 1803 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN38 = 0x4000061Au, /* tcpwm[1].tr_all_cnt_in[38] */ 1804 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN39 = 0x4000061Bu, /* tcpwm[1].tr_all_cnt_in[39] */ 1805 TRIG_OUT_MUX_6_TCPWM1_ALL_CNT_TR_IN40 = 0x4000061Cu /* tcpwm[1].tr_all_cnt_in[40] */ 1806 } en_trig_output_tcpwm1_in_t; 1807 1808 /* Trigger Output Group 7 - PASS trigger multiplexer */ 1809 typedef enum 1810 { 1811 TRIG_OUT_MUX_7_PASS_GEN_TR_IN0 = 0x40000700u, /* pass[0].tr_sar_gen_in[0] */ 1812 TRIG_OUT_MUX_7_PASS_GEN_TR_IN1 = 0x40000701u, /* pass[0].tr_sar_gen_in[1] */ 1813 TRIG_OUT_MUX_7_PASS_GEN_TR_IN2 = 0x40000702u, /* pass[0].tr_sar_gen_in[2] */ 1814 TRIG_OUT_MUX_7_PASS_GEN_TR_IN3 = 0x40000703u, /* pass[0].tr_sar_gen_in[3] */ 1815 TRIG_OUT_MUX_7_PASS_GEN_TR_IN4 = 0x40000704u, /* pass[0].tr_sar_gen_in[4] */ 1816 TRIG_OUT_MUX_7_PASS_GEN_TR_IN5 = 0x40000705u, /* pass[0].tr_sar_gen_in[5] */ 1817 TRIG_OUT_MUX_7_PASS_GEN_TR_IN6 = 0x40000706u, /* pass[0].tr_sar_gen_in[6] */ 1818 TRIG_OUT_MUX_7_PASS_GEN_TR_IN7 = 0x40000707u, /* pass[0].tr_sar_gen_in[7] */ 1819 TRIG_OUT_MUX_7_PASS_GEN_TR_IN8 = 0x40000708u, /* pass[0].tr_sar_gen_in[8] */ 1820 TRIG_OUT_MUX_7_PASS_GEN_TR_IN9 = 0x40000709u, /* pass[0].tr_sar_gen_in[9] */ 1821 TRIG_OUT_MUX_7_PASS_GEN_TR_IN10 = 0x4000070Au, /* pass[0].tr_sar_gen_in[10] */ 1822 TRIG_OUT_MUX_7_PASS_GEN_TR_IN11 = 0x4000070Bu /* pass[0].tr_sar_gen_in[11] */ 1823 } en_trig_output_pass_t; 1824 1825 /* Trigger Output Group 8 - CAN TT Synchronization triggers */ 1826 typedef enum 1827 { 1828 TRIG_OUT_MUX_8_CAN0_TT_TR_IN0 = 0x40000800u, /* canfd[0].tr_evt_swt_in[0] */ 1829 TRIG_OUT_MUX_8_CAN0_TT_TR_IN1 = 0x40000801u, /* canfd[0].tr_evt_swt_in[1] */ 1830 TRIG_OUT_MUX_8_CAN0_TT_TR_IN2 = 0x40000802u, /* canfd[0].tr_evt_swt_in[2] */ 1831 TRIG_OUT_MUX_8_CAN0_TT_TR_IN3 = 0x40000803u, /* canfd[0].tr_evt_swt_in[3] */ 1832 TRIG_OUT_MUX_8_CAN0_TT_TR_IN4 = 0x40000804u, /* canfd[0].tr_evt_swt_in[4] */ 1833 TRIG_OUT_MUX_8_CAN1_TT_TR_IN0 = 0x40000805u, /* canfd[1].tr_evt_swt_in[0] */ 1834 TRIG_OUT_MUX_8_CAN1_TT_TR_IN1 = 0x40000806u, /* canfd[1].tr_evt_swt_in[1] */ 1835 TRIG_OUT_MUX_8_CAN1_TT_TR_IN2 = 0x40000807u, /* canfd[1].tr_evt_swt_in[2] */ 1836 TRIG_OUT_MUX_8_CAN1_TT_TR_IN3 = 0x40000808u, /* canfd[1].tr_evt_swt_in[3] */ 1837 TRIG_OUT_MUX_8_CAN1_TT_TR_IN4 = 0x40000809u, /* canfd[1].tr_evt_swt_in[4] */ 1838 TRIG_OUT_MUX_8_FLEXRAY_TT_TR_IN = 0x4000080Au /* flexray[0].tr_stpwt_in */ 1839 } en_trig_output_cantt_t; 1840 1841 /* Trigger Output Group 9 - 2nd level MUX using input from MUX_11/12/13 */ 1842 typedef enum 1843 { 1844 TRIG_OUT_MUX_9_HSIOM_IO_OUTPUT0 = 0x40000900u, /* peri.tr_io_output[0] */ 1845 TRIG_OUT_MUX_9_HSIOM_IO_OUTPUT1 = 0x40000901u, /* peri.tr_io_output[1] */ 1846 TRIG_OUT_MUX_9_CTI_TR_IN0 = 0x40000902u, /* cpuss.cti_tr_in[0] */ 1847 TRIG_OUT_MUX_9_CTI_TR_IN1 = 0x40000903u, /* cpuss.cti_tr_in[1] */ 1848 TRIG_OUT_MUX_9_PERI_DEBUG_FREEZE_TR_IN = 0x40000904u, /* peri.tr_dbg_freeze */ 1849 TRIG_OUT_MUX_9_PASS_DEBUG_FREEZE_TR_IN = 0x40000905u, /* pass[0].tr_debug_freeze */ 1850 TRIG_OUT_MUX_9_SRSS_WDT_DEBUG_FREEZE_TR_IN = 0x40000906u, /* srss.tr_debug_freeze_wdt */ 1851 TRIG_OUT_MUX_9_SRSS_MCWDT_DEBUG_FREEZE_TR_IN2 = 0x40000907u, /* srss.tr_debug_freeze_mcwdt[2] */ 1852 TRIG_OUT_MUX_9_SRSS_MCWDT_DEBUG_FREEZE_TR_IN1 = 0x40000908u, /* srss.tr_debug_freeze_mcwdt[1] */ 1853 TRIG_OUT_MUX_9_SRSS_MCWDT_DEBUG_FREEZE_TR_IN0 = 0x40000909u, /* srss.tr_debug_freeze_mcwdt[0] */ 1854 TRIG_OUT_MUX_9_TCPWM0_DEBUG_FREEZE_TR_IN = 0x4000090Au, /* tcpwm[0].tr_debug_freeze */ 1855 TRIG_OUT_MUX_9_TCPWM1_DEBUG_FREEZE_TR_IN = 0x4000090Bu /* tcpwm[1].tr_debug_freeze */ 1856 } en_trig_output_debugmain_t; 1857 1858 /* Trigger Output Group 10 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1859 typedef enum 1860 { 1861 TRIG_OUT_MUX_10_TR_GROUP9_INPUT1 = 0x40000A00u, /* tr_group[9].input[1] */ 1862 TRIG_OUT_MUX_10_TR_GROUP9_INPUT2 = 0x40000A01u, /* tr_group[9].input[2] */ 1863 TRIG_OUT_MUX_10_TR_GROUP9_INPUT3 = 0x40000A02u, /* tr_group[9].input[3] */ 1864 TRIG_OUT_MUX_10_TR_GROUP9_INPUT4 = 0x40000A03u, /* tr_group[9].input[4] */ 1865 TRIG_OUT_MUX_10_TR_GROUP9_INPUT5 = 0x40000A04u /* tr_group[9].input[5] */ 1866 } en_trig_output_debugreduction1_t; 1867 1868 /* Trigger Output Group 11 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1869 typedef enum 1870 { 1871 TRIG_OUT_MUX_11_TR_GROUP9_INPUT6 = 0x40000B00u, /* tr_group[9].input[6] */ 1872 TRIG_OUT_MUX_11_TR_GROUP9_INPUT7 = 0x40000B01u, /* tr_group[9].input[7] */ 1873 TRIG_OUT_MUX_11_TR_GROUP9_INPUT8 = 0x40000B02u, /* tr_group[9].input[8] */ 1874 TRIG_OUT_MUX_11_TR_GROUP9_INPUT9 = 0x40000B03u, /* tr_group[9].input[9] */ 1875 TRIG_OUT_MUX_11_TR_GROUP9_INPUT10 = 0x40000B04u /* tr_group[9].input[10] */ 1876 } en_trig_output_debugreduction2_t; 1877 1878 /* Trigger Output Group 12 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1879 typedef enum 1880 { 1881 TRIG_OUT_MUX_12_TR_GROUP9_INPUT11 = 0x40000C00u, /* tr_group[9].input[11] */ 1882 TRIG_OUT_MUX_12_TR_GROUP9_INPUT12 = 0x40000C01u, /* tr_group[9].input[12] */ 1883 TRIG_OUT_MUX_12_TR_GROUP9_INPUT13 = 0x40000C02u, /* tr_group[9].input[13] */ 1884 TRIG_OUT_MUX_12_TR_GROUP9_INPUT14 = 0x40000C03u, /* tr_group[9].input[14] */ 1885 TRIG_OUT_MUX_12_TR_GROUP9_INPUT15 = 0x40000C04u /* tr_group[9].input[15] */ 1886 } en_trig_output_debugreduction3_t; 1887 1888 /* Trigger Output Group 0 - CAN DW Triggers (OneToOne) */ 1889 typedef enum 1890 { 1891 TRIG_OUT_1TO1_0_CAN0_DBG_TO_PDMA0_0 = 0x40001000u, /* From canfd[0].tr_dbg_dma_req[0] to cpuss.dw0_tr_in[32] */ 1892 TRIG_OUT_1TO1_0_CAN0_FIFO0_TO_PDMA0_0 = 0x40001001u, /* From canfd[0].tr_fifo0[0] to cpuss.dw0_tr_in[33] */ 1893 TRIG_OUT_1TO1_0_CAN0_FIFO1_TO_PDMA0_0 = 0x40001002u, /* From canfd[0].tr_fifo1[0] to cpuss.dw0_tr_in[34] */ 1894 TRIG_OUT_1TO1_0_CAN0_DBG_TO_PDMA0_1 = 0x40001003u, /* From canfd[0].tr_dbg_dma_req[1] to cpuss.dw0_tr_in[35] */ 1895 TRIG_OUT_1TO1_0_CAN0_FIFO0_TO_PDMA0_1 = 0x40001004u, /* From canfd[0].tr_fifo0[1] to cpuss.dw0_tr_in[36] */ 1896 TRIG_OUT_1TO1_0_CAN0_FIFO1_TO_PDMA0_1 = 0x40001005u, /* From canfd[0].tr_fifo1[1] to cpuss.dw0_tr_in[37] */ 1897 TRIG_OUT_1TO1_0_CAN0_DBG_TO_PDMA0_2 = 0x40001006u, /* From canfd[0].tr_dbg_dma_req[2] to cpuss.dw0_tr_in[38] */ 1898 TRIG_OUT_1TO1_0_CAN0_FIFO0_TO_PDMA0_2 = 0x40001007u, /* From canfd[0].tr_fifo0[2] to cpuss.dw0_tr_in[39] */ 1899 TRIG_OUT_1TO1_0_CAN0_FIFO1_TO_PDMA0_2 = 0x40001008u, /* From canfd[0].tr_fifo1[2] to cpuss.dw0_tr_in[40] */ 1900 TRIG_OUT_1TO1_0_CAN0_DBG_TO_PDMA0_3 = 0x40001009u, /* From canfd[0].tr_dbg_dma_req[3] to cpuss.dw0_tr_in[41] */ 1901 TRIG_OUT_1TO1_0_CAN0_FIFO0_TO_PDMA0_3 = 0x4000100Au, /* From canfd[0].tr_fifo0[3] to cpuss.dw0_tr_in[42] */ 1902 TRIG_OUT_1TO1_0_CAN0_FIFO1_TO_PDMA0_3 = 0x4000100Bu, /* From canfd[0].tr_fifo1[3] to cpuss.dw0_tr_in[43] */ 1903 TRIG_OUT_1TO1_0_CAN0_DBG_TO_PDMA0_4 = 0x4000100Cu, /* From canfd[0].tr_dbg_dma_req[4] to cpuss.dw0_tr_in[44] */ 1904 TRIG_OUT_1TO1_0_CAN0_FIFO0_TO_PDMA0_4 = 0x4000100Du, /* From canfd[0].tr_fifo0[4] to cpuss.dw0_tr_in[45] */ 1905 TRIG_OUT_1TO1_0_CAN0_FIFO1_TO_PDMA0_4 = 0x4000100Eu /* From canfd[0].tr_fifo1[4] to cpuss.dw0_tr_in[46] */ 1906 } en_trig_output_1to1_can0_dw0_tr_t; 1907 1908 /* Trigger Output Group 1 - PASS to DW0 direct connect (OneToOne) */ 1909 typedef enum 1910 { 1911 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA00 = 0x40001100u, /* From pass[0].tr_sar_ch_done[0] to cpuss.dw0_tr_in[47] */ 1912 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA01 = 0x40001101u, /* From pass[0].tr_sar_ch_done[1] to cpuss.dw0_tr_in[48] */ 1913 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA02 = 0x40001102u, /* From pass[0].tr_sar_ch_done[2] to cpuss.dw0_tr_in[49] */ 1914 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA03 = 0x40001103u, /* From pass[0].tr_sar_ch_done[3] to cpuss.dw0_tr_in[50] */ 1915 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA04 = 0x40001104u, /* From pass[0].tr_sar_ch_done[4] to cpuss.dw0_tr_in[51] */ 1916 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA05 = 0x40001105u, /* From pass[0].tr_sar_ch_done[5] to cpuss.dw0_tr_in[52] */ 1917 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA06 = 0x40001106u, /* From pass[0].tr_sar_ch_done[6] to cpuss.dw0_tr_in[53] */ 1918 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA07 = 0x40001107u, /* From pass[0].tr_sar_ch_done[7] to cpuss.dw0_tr_in[54] */ 1919 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA08 = 0x40001108u, /* From pass[0].tr_sar_ch_done[8] to cpuss.dw0_tr_in[55] */ 1920 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA09 = 0x40001109u, /* From pass[0].tr_sar_ch_done[9] to cpuss.dw0_tr_in[56] */ 1921 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA010 = 0x4000110Au, /* From pass[0].tr_sar_ch_done[10] to cpuss.dw0_tr_in[57] */ 1922 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA011 = 0x4000110Bu, /* From pass[0].tr_sar_ch_done[11] to cpuss.dw0_tr_in[58] */ 1923 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA012 = 0x4000110Cu, /* From pass[0].tr_sar_ch_done[12] to cpuss.dw0_tr_in[59] */ 1924 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA013 = 0x4000110Du, /* From pass[0].tr_sar_ch_done[13] to cpuss.dw0_tr_in[60] */ 1925 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA014 = 0x4000110Eu, /* From pass[0].tr_sar_ch_done[14] to cpuss.dw0_tr_in[61] */ 1926 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA015 = 0x4000110Fu, /* From pass[0].tr_sar_ch_done[15] to cpuss.dw0_tr_in[62] */ 1927 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA016 = 0x40001110u, /* From pass[0].tr_sar_ch_done[16] to cpuss.dw0_tr_in[63] */ 1928 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA017 = 0x40001111u, /* From pass[0].tr_sar_ch_done[17] to cpuss.dw0_tr_in[64] */ 1929 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA018 = 0x40001112u, /* From pass[0].tr_sar_ch_done[18] to cpuss.dw0_tr_in[65] */ 1930 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA019 = 0x40001113u, /* From pass[0].tr_sar_ch_done[19] to cpuss.dw0_tr_in[66] */ 1931 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA020 = 0x40001114u, /* From pass[0].tr_sar_ch_done[20] to cpuss.dw0_tr_in[67] */ 1932 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA021 = 0x40001115u, /* From pass[0].tr_sar_ch_done[21] to cpuss.dw0_tr_in[68] */ 1933 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA022 = 0x40001116u, /* From pass[0].tr_sar_ch_done[22] to cpuss.dw0_tr_in[69] */ 1934 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA023 = 0x40001117u, /* From pass[0].tr_sar_ch_done[23] to cpuss.dw0_tr_in[70] */ 1935 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA024 = 0x40001118u, /* From pass[0].tr_sar_ch_done[24] to cpuss.dw0_tr_in[71] */ 1936 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA025 = 0x40001119u, /* From pass[0].tr_sar_ch_done[25] to cpuss.dw0_tr_in[72] */ 1937 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA026 = 0x4000111Au, /* From pass[0].tr_sar_ch_done[26] to cpuss.dw0_tr_in[73] */ 1938 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA027 = 0x4000111Bu, /* From pass[0].tr_sar_ch_done[27] to cpuss.dw0_tr_in[74] */ 1939 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA028 = 0x4000111Cu, /* From pass[0].tr_sar_ch_done[28] to cpuss.dw0_tr_in[75] */ 1940 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA029 = 0x4000111Du, /* From pass[0].tr_sar_ch_done[29] to cpuss.dw0_tr_in[76] */ 1941 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA030 = 0x4000111Eu, /* From pass[0].tr_sar_ch_done[30] to cpuss.dw0_tr_in[77] */ 1942 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA031 = 0x4000111Fu, /* From pass[0].tr_sar_ch_done[31] to cpuss.dw0_tr_in[78] */ 1943 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA032 = 0x40001120u, /* From pass[0].tr_sar_ch_done[32] to cpuss.dw0_tr_in[79] */ 1944 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA033 = 0x40001121u, /* From pass[0].tr_sar_ch_done[33] to cpuss.dw0_tr_in[80] */ 1945 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA034 = 0x40001122u, /* From pass[0].tr_sar_ch_done[34] to cpuss.dw0_tr_in[81] */ 1946 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA035 = 0x40001123u, /* From pass[0].tr_sar_ch_done[35] to cpuss.dw0_tr_in[82] */ 1947 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA036 = 0x40001124u, /* From pass[0].tr_sar_ch_done[36] to cpuss.dw0_tr_in[83] */ 1948 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA037 = 0x40001125u, /* From pass[0].tr_sar_ch_done[37] to cpuss.dw0_tr_in[84] */ 1949 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA038 = 0x40001126u, /* From pass[0].tr_sar_ch_done[38] to cpuss.dw0_tr_in[85] */ 1950 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA039 = 0x40001127u, /* From pass[0].tr_sar_ch_done[39] to cpuss.dw0_tr_in[86] */ 1951 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA040 = 0x40001128u, /* From pass[0].tr_sar_ch_done[40] to cpuss.dw0_tr_in[87] */ 1952 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA041 = 0x40001129u, /* From pass[0].tr_sar_ch_done[41] to cpuss.dw0_tr_in[88] */ 1953 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA042 = 0x4000112Au, /* From pass[0].tr_sar_ch_done[42] to cpuss.dw0_tr_in[89] */ 1954 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA043 = 0x4000112Bu, /* From pass[0].tr_sar_ch_done[43] to cpuss.dw0_tr_in[90] */ 1955 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA044 = 0x4000112Cu, /* From pass[0].tr_sar_ch_done[44] to cpuss.dw0_tr_in[91] */ 1956 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA045 = 0x4000112Du, /* From pass[0].tr_sar_ch_done[45] to cpuss.dw0_tr_in[92] */ 1957 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA046 = 0x4000112Eu, /* From pass[0].tr_sar_ch_done[46] to cpuss.dw0_tr_in[93] */ 1958 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA047 = 0x4000112Fu, /* From pass[0].tr_sar_ch_done[47] to cpuss.dw0_tr_in[94] */ 1959 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA048 = 0x40001130u, /* From pass[0].tr_sar_ch_done[48] to cpuss.dw0_tr_in[95] */ 1960 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA049 = 0x40001131u, /* From pass[0].tr_sar_ch_done[49] to cpuss.dw0_tr_in[96] */ 1961 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA050 = 0x40001132u, /* From pass[0].tr_sar_ch_done[50] to cpuss.dw0_tr_in[97] */ 1962 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA051 = 0x40001133u, /* From pass[0].tr_sar_ch_done[51] to cpuss.dw0_tr_in[98] */ 1963 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA052 = 0x40001134u, /* From pass[0].tr_sar_ch_done[52] to cpuss.dw0_tr_in[99] */ 1964 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA053 = 0x40001135u, /* From pass[0].tr_sar_ch_done[53] to cpuss.dw0_tr_in[100] */ 1965 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA054 = 0x40001136u, /* From pass[0].tr_sar_ch_done[54] to cpuss.dw0_tr_in[101] */ 1966 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA055 = 0x40001137u, /* From pass[0].tr_sar_ch_done[55] to cpuss.dw0_tr_in[102] */ 1967 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA056 = 0x40001138u, /* From pass[0].tr_sar_ch_done[56] to cpuss.dw0_tr_in[103] */ 1968 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA057 = 0x40001139u, /* From pass[0].tr_sar_ch_done[57] to cpuss.dw0_tr_in[104] */ 1969 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA058 = 0x4000113Au, /* From pass[0].tr_sar_ch_done[58] to cpuss.dw0_tr_in[105] */ 1970 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA059 = 0x4000113Bu, /* From pass[0].tr_sar_ch_done[59] to cpuss.dw0_tr_in[106] */ 1971 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA060 = 0x4000113Cu, /* From pass[0].tr_sar_ch_done[60] to cpuss.dw0_tr_in[107] */ 1972 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA061 = 0x4000113Du, /* From pass[0].tr_sar_ch_done[61] to cpuss.dw0_tr_in[108] */ 1973 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA062 = 0x4000113Eu, /* From pass[0].tr_sar_ch_done[62] to cpuss.dw0_tr_in[109] */ 1974 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA063 = 0x4000113Fu, /* From pass[0].tr_sar_ch_done[63] to cpuss.dw0_tr_in[110] */ 1975 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA064 = 0x40001140u, /* From pass[0].tr_sar_ch_done[64] to cpuss.dw0_tr_in[111] */ 1976 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA065 = 0x40001141u, /* From pass[0].tr_sar_ch_done[65] to cpuss.dw0_tr_in[112] */ 1977 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA066 = 0x40001142u, /* From pass[0].tr_sar_ch_done[66] to cpuss.dw0_tr_in[113] */ 1978 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA067 = 0x40001143u, /* From pass[0].tr_sar_ch_done[67] to cpuss.dw0_tr_in[114] */ 1979 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA068 = 0x40001144u, /* From pass[0].tr_sar_ch_done[68] to cpuss.dw0_tr_in[115] */ 1980 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA069 = 0x40001145u, /* From pass[0].tr_sar_ch_done[69] to cpuss.dw0_tr_in[116] */ 1981 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA070 = 0x40001146u, /* From pass[0].tr_sar_ch_done[70] to cpuss.dw0_tr_in[117] */ 1982 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA071 = 0x40001147u, /* From pass[0].tr_sar_ch_done[71] to cpuss.dw0_tr_in[118] */ 1983 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA072 = 0x40001148u, /* From pass[0].tr_sar_ch_done[72] to cpuss.dw0_tr_in[119] */ 1984 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA073 = 0x40001149u, /* From pass[0].tr_sar_ch_done[73] to cpuss.dw0_tr_in[120] */ 1985 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA074 = 0x4000114Au, /* From pass[0].tr_sar_ch_done[74] to cpuss.dw0_tr_in[121] */ 1986 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA075 = 0x4000114Bu, /* From pass[0].tr_sar_ch_done[75] to cpuss.dw0_tr_in[122] */ 1987 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA076 = 0x4000114Cu, /* From pass[0].tr_sar_ch_done[76] to cpuss.dw0_tr_in[123] */ 1988 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA077 = 0x4000114Du, /* From pass[0].tr_sar_ch_done[77] to cpuss.dw0_tr_in[124] */ 1989 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA078 = 0x4000114Eu, /* From pass[0].tr_sar_ch_done[78] to cpuss.dw0_tr_in[125] */ 1990 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA079 = 0x4000114Fu, /* From pass[0].tr_sar_ch_done[79] to cpuss.dw0_tr_in[126] */ 1991 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA080 = 0x40001150u, /* From pass[0].tr_sar_ch_done[80] to cpuss.dw0_tr_in[127] */ 1992 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA081 = 0x40001151u, /* From pass[0].tr_sar_ch_done[81] to cpuss.dw0_tr_in[128] */ 1993 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA082 = 0x40001152u, /* From pass[0].tr_sar_ch_done[82] to cpuss.dw0_tr_in[129] */ 1994 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA083 = 0x40001153u, /* From pass[0].tr_sar_ch_done[83] to cpuss.dw0_tr_in[130] */ 1995 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA084 = 0x40001154u, /* From pass[0].tr_sar_ch_done[84] to cpuss.dw0_tr_in[131] */ 1996 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA085 = 0x40001155u, /* From pass[0].tr_sar_ch_done[85] to cpuss.dw0_tr_in[132] */ 1997 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA086 = 0x40001156u, /* From pass[0].tr_sar_ch_done[86] to cpuss.dw0_tr_in[133] */ 1998 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA087 = 0x40001157u, /* From pass[0].tr_sar_ch_done[87] to cpuss.dw0_tr_in[134] */ 1999 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA088 = 0x40001158u, /* From pass[0].tr_sar_ch_done[88] to cpuss.dw0_tr_in[135] */ 2000 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA089 = 0x40001159u, /* From pass[0].tr_sar_ch_done[89] to cpuss.dw0_tr_in[136] */ 2001 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA090 = 0x4000115Au, /* From pass[0].tr_sar_ch_done[90] to cpuss.dw0_tr_in[137] */ 2002 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA091 = 0x4000115Bu, /* From pass[0].tr_sar_ch_done[91] to cpuss.dw0_tr_in[138] */ 2003 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA092 = 0x4000115Cu, /* From pass[0].tr_sar_ch_done[92] to cpuss.dw0_tr_in[139] */ 2004 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA093 = 0x4000115Du, /* From pass[0].tr_sar_ch_done[93] to cpuss.dw0_tr_in[140] */ 2005 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA094 = 0x4000115Eu, /* From pass[0].tr_sar_ch_done[94] to cpuss.dw0_tr_in[141] */ 2006 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA095 = 0x4000115Fu /* From pass[0].tr_sar_ch_done[95] to cpuss.dw0_tr_in[142] */ 2007 } en_trig_output_1to1_pass_to_dw0_t; 2008 2009 /* Trigger Output Group 2 - SCB DW Triggers (OneToOne) */ 2010 typedef enum 2011 { 2012 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA10 = 0x40001200u, /* From scb[0].tr_tx_req to cpuss.dw1_tr_in[16] */ 2013 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA10 = 0x40001201u, /* From scb[0].tr_rx_req to cpuss.dw1_tr_in[17] */ 2014 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA11 = 0x40001202u, /* From scb[1].tr_tx_req to cpuss.dw1_tr_in[18] */ 2015 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA11 = 0x40001203u, /* From scb[1].tr_rx_req to cpuss.dw1_tr_in[19] */ 2016 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA12 = 0x40001204u, /* From scb[2].tr_tx_req to cpuss.dw1_tr_in[20] */ 2017 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA12 = 0x40001205u, /* From scb[2].tr_rx_req to cpuss.dw1_tr_in[21] */ 2018 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA13 = 0x40001206u, /* From scb[3].tr_tx_req to cpuss.dw1_tr_in[22] */ 2019 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA13 = 0x40001207u, /* From scb[3].tr_rx_req to cpuss.dw1_tr_in[23] */ 2020 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA14 = 0x40001208u, /* From scb[4].tr_tx_req to cpuss.dw1_tr_in[24] */ 2021 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA14 = 0x40001209u, /* From scb[4].tr_rx_req to cpuss.dw1_tr_in[25] */ 2022 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA15 = 0x4000120Au, /* From scb[5].tr_tx_req to cpuss.dw1_tr_in[26] */ 2023 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA15 = 0x4000120Bu, /* From scb[5].tr_rx_req to cpuss.dw1_tr_in[27] */ 2024 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA16 = 0x4000120Cu, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[28] */ 2025 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA16 = 0x4000120Du, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[29] */ 2026 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA17 = 0x4000120Eu, /* From scb[7].tr_tx_req to cpuss.dw1_tr_in[30] */ 2027 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA17 = 0x4000120Fu, /* From scb[7].tr_rx_req to cpuss.dw1_tr_in[31] */ 2028 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA18 = 0x40001210u, /* From scb[8].tr_tx_req to cpuss.dw1_tr_in[32] */ 2029 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA18 = 0x40001211u, /* From scb[8].tr_rx_req to cpuss.dw1_tr_in[33] */ 2030 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA19 = 0x40001212u, /* From scb[9].tr_tx_req to cpuss.dw1_tr_in[34] */ 2031 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA19 = 0x40001213u, /* From scb[9].tr_rx_req to cpuss.dw1_tr_in[35] */ 2032 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA110 = 0x40001214u, /* From scb[10].tr_tx_req to cpuss.dw1_tr_in[36] */ 2033 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA110 = 0x40001215u /* From scb[10].tr_rx_req to cpuss.dw1_tr_in[37] */ 2034 } en_trig_output_1to1_scb_dw1_tr_t; 2035 2036 /* Trigger Output Group 3 - SMIF DW Triggers (OneToOne) */ 2037 typedef enum 2038 { 2039 TRIG_OUT_1TO1_3_SMIF_TX_TO_PDMA1 = 0x40001300u, /* From smif[0].tr_tx_req to cpuss.dw1_tr_in[53] */ 2040 TRIG_OUT_1TO1_3_SMIF_RX_TO_PDMA1 = 0x40001301u /* From smif[0].tr_rx_req to cpuss.dw1_tr_in[54] */ 2041 } en_trig_output_1to1_smif_dw1_tr_t; 2042 2043 /* Trigger Output Group 4 - More CAN DW triggers (on DW1 for max BW) (OneToOne) */ 2044 typedef enum 2045 { 2046 TRIG_OUT_1TO1_4_CAN1_DBG_TO_PDMA1_0 = 0x40001400u, /* From canfd[1].tr_dbg_dma_req[0] to cpuss.dw1_tr_in[38] */ 2047 TRIG_OUT_1TO1_4_CAN1_FIFO0_TO_PDMA1_0 = 0x40001401u, /* From canfd[1].tr_fifo0[0] to cpuss.dw1_tr_in[39] */ 2048 TRIG_OUT_1TO1_4_CAN1_FIFO1_TO_PDMA1_0 = 0x40001402u, /* From canfd[1].tr_fifo1[0] to cpuss.dw1_tr_in[40] */ 2049 TRIG_OUT_1TO1_4_CAN1_DBG_TO_PDMA1_1 = 0x40001403u, /* From canfd[1].tr_dbg_dma_req[1] to cpuss.dw1_tr_in[41] */ 2050 TRIG_OUT_1TO1_4_CAN1_FIFO0_TO_PDMA1_1 = 0x40001404u, /* From canfd[1].tr_fifo0[1] to cpuss.dw1_tr_in[42] */ 2051 TRIG_OUT_1TO1_4_CAN1_FIFO1_TO_PDMA1_1 = 0x40001405u, /* From canfd[1].tr_fifo1[1] to cpuss.dw1_tr_in[43] */ 2052 TRIG_OUT_1TO1_4_CAN1_DBG_TO_PDMA1_2 = 0x40001406u, /* From canfd[1].tr_dbg_dma_req[2] to cpuss.dw1_tr_in[44] */ 2053 TRIG_OUT_1TO1_4_CAN1_FIFO0_TO_PDMA1_2 = 0x40001407u, /* From canfd[1].tr_fifo0[2] to cpuss.dw1_tr_in[45] */ 2054 TRIG_OUT_1TO1_4_CAN1_FIFO1_TO_PDMA1_2 = 0x40001408u, /* From canfd[1].tr_fifo1[2] to cpuss.dw1_tr_in[46] */ 2055 TRIG_OUT_1TO1_4_CAN1_DBG_TO_PDMA1_3 = 0x40001409u, /* From canfd[1].tr_dbg_dma_req[3] to cpuss.dw1_tr_in[47] */ 2056 TRIG_OUT_1TO1_4_CAN1_FIFO0_TO_PDMA1_3 = 0x4000140Au, /* From canfd[1].tr_fifo0[3] to cpuss.dw1_tr_in[48] */ 2057 TRIG_OUT_1TO1_4_CAN1_FIFO1_TO_PDMA1_3 = 0x4000140Bu, /* From canfd[1].tr_fifo1[3] to cpuss.dw1_tr_in[49] */ 2058 TRIG_OUT_1TO1_4_CAN1_DBG_TO_PDMA1_4 = 0x4000140Cu, /* From canfd[1].tr_dbg_dma_req[4] to cpuss.dw1_tr_in[50] */ 2059 TRIG_OUT_1TO1_4_CAN1_FIFO0_TO_PDMA1_4 = 0x4000140Du, /* From canfd[1].tr_fifo0[4] to cpuss.dw1_tr_in[51] */ 2060 TRIG_OUT_1TO1_4_CAN1_FIFO1_TO_PDMA1_4 = 0x4000140Eu /* From canfd[1].tr_fifo1[4] to cpuss.dw1_tr_in[52] */ 2061 } en_trig_output_1to1_can1_dw1_tr_t; 2062 2063 /* Trigger Output Group 5 - I2S DW Triggers (OneToOne) */ 2064 typedef enum 2065 { 2066 TRIG_OUT_1TO1_5_I2S_TX_TO_PDMA10 = 0x40001500u, /* From audioss[0].tr_i2s_tx_req to cpuss.dw1_tr_in[55] */ 2067 TRIG_OUT_1TO1_5_I2S_RX_TO_PDMA10 = 0x40001501u, /* From audioss[0].tr_i2s_rx_req to cpuss.dw1_tr_in[56] */ 2068 TRIG_OUT_1TO1_5_I2S_TX_TO_PDMA11 = 0x40001502u, /* From audioss[1].tr_i2s_tx_req to cpuss.dw1_tr_in[57] */ 2069 TRIG_OUT_1TO1_5_I2S_RX_TO_PDMA11 = 0x40001503u, /* From audioss[1].tr_i2s_rx_req to cpuss.dw1_tr_in[58] */ 2070 TRIG_OUT_1TO1_5_I2S_TX_TO_PDMA12 = 0x40001504u, /* From audioss[2].tr_i2s_tx_req to cpuss.dw1_tr_in[59] */ 2071 TRIG_OUT_1TO1_5_I2S_RX_TO_PDMA12 = 0x40001505u /* From audioss[2].tr_i2s_rx_req to cpuss.dw1_tr_in[60] */ 2072 } en_trig_output_1to1_i2s_dw1_tr_t; 2073 2074 /* Trigger Output Group 6 - PASS to PWM direct connect (OneToOne) */ 2075 typedef enum 2076 { 2077 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL0 = 0x40001600u, /* From pass[0].tr_sar_ch_rangevio[0] to tcpwm[1].tr_one_cnt_in[770] */ 2078 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL1 = 0x40001601u, /* From pass[0].tr_sar_ch_rangevio[1] to tcpwm[1].tr_one_cnt_in[779] */ 2079 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL2 = 0x40001602u, /* From pass[0].tr_sar_ch_rangevio[2] to tcpwm[1].tr_one_cnt_in[788] */ 2080 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL3 = 0x40001603u, /* From pass[0].tr_sar_ch_rangevio[3] to tcpwm[1].tr_one_cnt_in[797] */ 2081 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL4 = 0x40001604u, /* From pass[0].tr_sar_ch_rangevio[4] to tcpwm[1].tr_one_cnt_in[2] */ 2082 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL5 = 0x40001605u, /* From pass[0].tr_sar_ch_rangevio[5] to tcpwm[1].tr_one_cnt_in[5] */ 2083 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL6 = 0x40001606u, /* From pass[0].tr_sar_ch_rangevio[6] to tcpwm[1].tr_one_cnt_in[8] */ 2084 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL7 = 0x40001607u, /* From pass[0].tr_sar_ch_rangevio[7] to tcpwm[1].tr_one_cnt_in[11] */ 2085 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL8 = 0x40001608u, /* From pass[0].tr_sar_ch_rangevio[8] to tcpwm[1].tr_one_cnt_in[14] */ 2086 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL9 = 0x40001609u, /* From pass[0].tr_sar_ch_rangevio[9] to tcpwm[1].tr_one_cnt_in[17] */ 2087 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL10 = 0x4000160Au, /* From pass[0].tr_sar_ch_rangevio[10] to tcpwm[1].tr_one_cnt_in[20] */ 2088 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL11 = 0x4000160Bu, /* From pass[0].tr_sar_ch_rangevio[11] to tcpwm[1].tr_one_cnt_in[23] */ 2089 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL12 = 0x4000160Cu, /* From pass[0].tr_sar_ch_rangevio[12] to tcpwm[1].tr_one_cnt_in[26] */ 2090 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL13 = 0x4000160Du, /* From pass[0].tr_sar_ch_rangevio[13] to tcpwm[1].tr_one_cnt_in[29] */ 2091 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL14 = 0x4000160Eu, /* From pass[0].tr_sar_ch_rangevio[14] to tcpwm[1].tr_one_cnt_in[32] */ 2092 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL15 = 0x4000160Fu, /* From pass[0].tr_sar_ch_rangevio[15] to tcpwm[1].tr_one_cnt_in[35] */ 2093 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL16 = 0x40001610u, /* From pass[0].tr_sar_ch_rangevio[16] to tcpwm[1].tr_one_cnt_in[38] */ 2094 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL17 = 0x40001611u, /* From pass[0].tr_sar_ch_rangevio[17] to tcpwm[1].tr_one_cnt_in[41] */ 2095 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL18 = 0x40001612u, /* From pass[0].tr_sar_ch_rangevio[18] to tcpwm[1].tr_one_cnt_in[44] */ 2096 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL19 = 0x40001613u, /* From pass[0].tr_sar_ch_rangevio[19] to tcpwm[1].tr_one_cnt_in[47] */ 2097 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL20 = 0x40001614u, /* From pass[0].tr_sar_ch_rangevio[20] to tcpwm[1].tr_one_cnt_in[50] */ 2098 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL21 = 0x40001615u, /* From pass[0].tr_sar_ch_rangevio[21] to tcpwm[1].tr_one_cnt_in[53] */ 2099 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL22 = 0x40001616u, /* From pass[0].tr_sar_ch_rangevio[22] to tcpwm[1].tr_one_cnt_in[56] */ 2100 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL23 = 0x40001617u, /* From pass[0].tr_sar_ch_rangevio[23] to tcpwm[1].tr_one_cnt_in[59] */ 2101 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL24 = 0x40001618u, /* From pass[0].tr_sar_ch_rangevio[24] to tcpwm[1].tr_one_cnt_in[62] */ 2102 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL25 = 0x40001619u, /* From pass[0].tr_sar_ch_rangevio[25] to tcpwm[1].tr_one_cnt_in[65] */ 2103 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL26 = 0x4000161Au, /* From pass[0].tr_sar_ch_rangevio[26] to tcpwm[1].tr_one_cnt_in[68] */ 2104 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL27 = 0x4000161Bu, /* From pass[0].tr_sar_ch_rangevio[27] to tcpwm[1].tr_one_cnt_in[71] */ 2105 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL28 = 0x4000161Cu, /* From pass[0].tr_sar_ch_rangevio[28] to tcpwm[1].tr_one_cnt_in[74] */ 2106 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL29 = 0x4000161Du, /* From pass[0].tr_sar_ch_rangevio[29] to tcpwm[1].tr_one_cnt_in[77] */ 2107 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL30 = 0x4000161Eu, /* From pass[0].tr_sar_ch_rangevio[30] to tcpwm[1].tr_one_cnt_in[80] */ 2108 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL31 = 0x4000161Fu, /* From pass[0].tr_sar_ch_rangevio[31] to tcpwm[1].tr_one_cnt_in[83] */ 2109 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL32 = 0x40001620u, /* From pass[0].tr_sar_ch_rangevio[32] to tcpwm[1].tr_one_cnt_in[773] */ 2110 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL33 = 0x40001621u, /* From pass[0].tr_sar_ch_rangevio[33] to tcpwm[1].tr_one_cnt_in[782] */ 2111 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL34 = 0x40001622u, /* From pass[0].tr_sar_ch_rangevio[34] to tcpwm[1].tr_one_cnt_in[791] */ 2112 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL35 = 0x40001623u, /* From pass[0].tr_sar_ch_rangevio[35] to tcpwm[1].tr_one_cnt_in[800] */ 2113 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL36 = 0x40001624u, /* From pass[0].tr_sar_ch_rangevio[36] to tcpwm[1].tr_one_cnt_in[86] */ 2114 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL37 = 0x40001625u, /* From pass[0].tr_sar_ch_rangevio[37] to tcpwm[1].tr_one_cnt_in[89] */ 2115 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL38 = 0x40001626u, /* From pass[0].tr_sar_ch_rangevio[38] to tcpwm[1].tr_one_cnt_in[92] */ 2116 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL39 = 0x40001627u, /* From pass[0].tr_sar_ch_rangevio[39] to tcpwm[1].tr_one_cnt_in[95] */ 2117 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL40 = 0x40001628u, /* From pass[0].tr_sar_ch_rangevio[40] to tcpwm[1].tr_one_cnt_in[98] */ 2118 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL41 = 0x40001629u, /* From pass[0].tr_sar_ch_rangevio[41] to tcpwm[1].tr_one_cnt_in[101] */ 2119 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL42 = 0x4000162Au, /* From pass[0].tr_sar_ch_rangevio[42] to tcpwm[1].tr_one_cnt_in[104] */ 2120 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL43 = 0x4000162Bu, /* From pass[0].tr_sar_ch_rangevio[43] to tcpwm[1].tr_one_cnt_in[107] */ 2121 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL44 = 0x4000162Cu, /* From pass[0].tr_sar_ch_rangevio[44] to tcpwm[1].tr_one_cnt_in[110] */ 2122 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL45 = 0x4000162Du, /* From pass[0].tr_sar_ch_rangevio[45] to tcpwm[1].tr_one_cnt_in[113] */ 2123 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL46 = 0x4000162Eu, /* From pass[0].tr_sar_ch_rangevio[46] to tcpwm[1].tr_one_cnt_in[116] */ 2124 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL47 = 0x4000162Fu, /* From pass[0].tr_sar_ch_rangevio[47] to tcpwm[1].tr_one_cnt_in[119] */ 2125 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL48 = 0x40001630u, /* From pass[0].tr_sar_ch_rangevio[48] to tcpwm[1].tr_one_cnt_in[122] */ 2126 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL49 = 0x40001631u, /* From pass[0].tr_sar_ch_rangevio[49] to tcpwm[1].tr_one_cnt_in[125] */ 2127 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL50 = 0x40001632u, /* From pass[0].tr_sar_ch_rangevio[50] to tcpwm[1].tr_one_cnt_in[128] */ 2128 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL51 = 0x40001633u, /* From pass[0].tr_sar_ch_rangevio[51] to tcpwm[1].tr_one_cnt_in[131] */ 2129 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL52 = 0x40001634u, /* From pass[0].tr_sar_ch_rangevio[52] to tcpwm[1].tr_one_cnt_in[134] */ 2130 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL53 = 0x40001635u, /* From pass[0].tr_sar_ch_rangevio[53] to tcpwm[1].tr_one_cnt_in[137] */ 2131 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL54 = 0x40001636u, /* From pass[0].tr_sar_ch_rangevio[54] to tcpwm[1].tr_one_cnt_in[140] */ 2132 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL55 = 0x40001637u, /* From pass[0].tr_sar_ch_rangevio[55] to tcpwm[1].tr_one_cnt_in[143] */ 2133 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL56 = 0x40001638u, /* From pass[0].tr_sar_ch_rangevio[56] to tcpwm[1].tr_one_cnt_in[146] */ 2134 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL57 = 0x40001639u, /* From pass[0].tr_sar_ch_rangevio[57] to tcpwm[1].tr_one_cnt_in[149] */ 2135 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL58 = 0x4000163Au, /* From pass[0].tr_sar_ch_rangevio[58] to tcpwm[1].tr_one_cnt_in[152] */ 2136 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL59 = 0x4000163Bu, /* From pass[0].tr_sar_ch_rangevio[59] to tcpwm[1].tr_one_cnt_in[155] */ 2137 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL60 = 0x4000163Cu, /* From pass[0].tr_sar_ch_rangevio[60] to tcpwm[1].tr_one_cnt_in[158] */ 2138 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL61 = 0x4000163Du, /* From pass[0].tr_sar_ch_rangevio[61] to tcpwm[1].tr_one_cnt_in[161] */ 2139 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL62 = 0x4000163Eu, /* From pass[0].tr_sar_ch_rangevio[62] to tcpwm[1].tr_one_cnt_in[164] */ 2140 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL63 = 0x4000163Fu, /* From pass[0].tr_sar_ch_rangevio[63] to tcpwm[1].tr_one_cnt_in[167] */ 2141 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL64 = 0x40001640u, /* From pass[0].tr_sar_ch_rangevio[64] to tcpwm[1].tr_one_cnt_in[776] */ 2142 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL65 = 0x40001641u, /* From pass[0].tr_sar_ch_rangevio[65] to tcpwm[1].tr_one_cnt_in[785] */ 2143 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL66 = 0x40001642u, /* From pass[0].tr_sar_ch_rangevio[66] to tcpwm[1].tr_one_cnt_in[794] */ 2144 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL67 = 0x40001643u, /* From pass[0].tr_sar_ch_rangevio[67] to tcpwm[1].tr_one_cnt_in[803] */ 2145 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL68 = 0x40001644u, /* From pass[0].tr_sar_ch_rangevio[68] to tcpwm[1].tr_one_cnt_in[170] */ 2146 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL69 = 0x40001645u, /* From pass[0].tr_sar_ch_rangevio[69] to tcpwm[1].tr_one_cnt_in[173] */ 2147 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL70 = 0x40001646u, /* From pass[0].tr_sar_ch_rangevio[70] to tcpwm[1].tr_one_cnt_in[176] */ 2148 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL71 = 0x40001647u, /* From pass[0].tr_sar_ch_rangevio[71] to tcpwm[1].tr_one_cnt_in[179] */ 2149 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL72 = 0x40001648u, /* From pass[0].tr_sar_ch_rangevio[72] to tcpwm[1].tr_one_cnt_in[182] */ 2150 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL73 = 0x40001649u, /* From pass[0].tr_sar_ch_rangevio[73] to tcpwm[1].tr_one_cnt_in[185] */ 2151 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL74 = 0x4000164Au, /* From pass[0].tr_sar_ch_rangevio[74] to tcpwm[1].tr_one_cnt_in[188] */ 2152 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL75 = 0x4000164Bu, /* From pass[0].tr_sar_ch_rangevio[75] to tcpwm[1].tr_one_cnt_in[191] */ 2153 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL76 = 0x4000164Cu, /* From pass[0].tr_sar_ch_rangevio[76] to tcpwm[1].tr_one_cnt_in[194] */ 2154 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL77 = 0x4000164Du, /* From pass[0].tr_sar_ch_rangevio[77] to tcpwm[1].tr_one_cnt_in[197] */ 2155 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL78 = 0x4000164Eu, /* From pass[0].tr_sar_ch_rangevio[78] to tcpwm[1].tr_one_cnt_in[200] */ 2156 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL79 = 0x4000164Fu, /* From pass[0].tr_sar_ch_rangevio[79] to tcpwm[1].tr_one_cnt_in[203] */ 2157 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL80 = 0x40001650u, /* From pass[0].tr_sar_ch_rangevio[80] to tcpwm[1].tr_one_cnt_in[206] */ 2158 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL81 = 0x40001651u, /* From pass[0].tr_sar_ch_rangevio[81] to tcpwm[1].tr_one_cnt_in[209] */ 2159 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL82 = 0x40001652u, /* From pass[0].tr_sar_ch_rangevio[82] to tcpwm[1].tr_one_cnt_in[212] */ 2160 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL83 = 0x40001653u, /* From pass[0].tr_sar_ch_rangevio[83] to tcpwm[1].tr_one_cnt_in[215] */ 2161 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL84 = 0x40001654u, /* From pass[0].tr_sar_ch_rangevio[84] to tcpwm[1].tr_one_cnt_in[218] */ 2162 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL85 = 0x40001655u, /* From pass[0].tr_sar_ch_rangevio[85] to tcpwm[1].tr_one_cnt_in[221] */ 2163 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL86 = 0x40001656u, /* From pass[0].tr_sar_ch_rangevio[86] to tcpwm[1].tr_one_cnt_in[224] */ 2164 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL87 = 0x40001657u, /* From pass[0].tr_sar_ch_rangevio[87] to tcpwm[1].tr_one_cnt_in[227] */ 2165 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL88 = 0x40001658u, /* From pass[0].tr_sar_ch_rangevio[88] to tcpwm[1].tr_one_cnt_in[230] */ 2166 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL89 = 0x40001659u, /* From pass[0].tr_sar_ch_rangevio[89] to tcpwm[1].tr_one_cnt_in[233] */ 2167 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL90 = 0x4000165Au, /* From pass[0].tr_sar_ch_rangevio[90] to tcpwm[1].tr_one_cnt_in[236] */ 2168 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL91 = 0x4000165Bu, /* From pass[0].tr_sar_ch_rangevio[91] to tcpwm[1].tr_one_cnt_in[239] */ 2169 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL92 = 0x4000165Cu, /* From pass[0].tr_sar_ch_rangevio[92] to tcpwm[1].tr_one_cnt_in[242] */ 2170 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL93 = 0x4000165Du, /* From pass[0].tr_sar_ch_rangevio[93] to tcpwm[1].tr_one_cnt_in[245] */ 2171 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL94 = 0x4000165Eu, /* From pass[0].tr_sar_ch_rangevio[94] to tcpwm[1].tr_one_cnt_in[248] */ 2172 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL95 = 0x4000165Fu /* From pass[0].tr_sar_ch_rangevio[95] to tcpwm[1].tr_one_cnt_in[251] */ 2173 } en_trig_output_1to1_pass_to_pwm_t; 2174 2175 /* Trigger Output Group 7 - (OneToOne) */ 2176 typedef enum 2177 { 2178 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR0 = 0x40001700u, /* From tcpwm[1].tr_out1[256] to pass[0].tr_sar_ch_in[0] */ 2179 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR1 = 0x40001701u, /* From tcpwm[1].tr_out1[259] to pass[0].tr_sar_ch_in[1] */ 2180 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR2 = 0x40001702u, /* From tcpwm[1].tr_out1[262] to pass[0].tr_sar_ch_in[2] */ 2181 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR3 = 0x40001703u, /* From tcpwm[1].tr_out1[265] to pass[0].tr_sar_ch_in[3] */ 2182 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR4 = 0x40001704u, /* From tcpwm[1].tr_out1[0] to pass[0].tr_sar_ch_in[4] */ 2183 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR5 = 0x40001705u, /* From tcpwm[1].tr_out1[1] to pass[0].tr_sar_ch_in[5] */ 2184 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR6 = 0x40001706u, /* From tcpwm[1].tr_out1[2] to pass[0].tr_sar_ch_in[6] */ 2185 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR7 = 0x40001707u, /* From tcpwm[1].tr_out1[3] to pass[0].tr_sar_ch_in[7] */ 2186 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR8 = 0x40001708u, /* From tcpwm[1].tr_out1[4] to pass[0].tr_sar_ch_in[8] */ 2187 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR9 = 0x40001709u, /* From tcpwm[1].tr_out1[5] to pass[0].tr_sar_ch_in[9] */ 2188 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR10 = 0x4000170Au, /* From tcpwm[1].tr_out1[6] to pass[0].tr_sar_ch_in[10] */ 2189 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR11 = 0x4000170Bu, /* From tcpwm[1].tr_out1[7] to pass[0].tr_sar_ch_in[11] */ 2190 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR12 = 0x4000170Cu, /* From tcpwm[1].tr_out1[8] to pass[0].tr_sar_ch_in[12] */ 2191 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR13 = 0x4000170Du, /* From tcpwm[1].tr_out1[9] to pass[0].tr_sar_ch_in[13] */ 2192 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR14 = 0x4000170Eu, /* From tcpwm[1].tr_out1[10] to pass[0].tr_sar_ch_in[14] */ 2193 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR15 = 0x4000170Fu, /* From tcpwm[1].tr_out1[11] to pass[0].tr_sar_ch_in[15] */ 2194 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR16 = 0x40001710u, /* From tcpwm[1].tr_out1[12] to pass[0].tr_sar_ch_in[16] */ 2195 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR17 = 0x40001711u, /* From tcpwm[1].tr_out1[13] to pass[0].tr_sar_ch_in[17] */ 2196 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR18 = 0x40001712u, /* From tcpwm[1].tr_out1[14] to pass[0].tr_sar_ch_in[18] */ 2197 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR19 = 0x40001713u, /* From tcpwm[1].tr_out1[15] to pass[0].tr_sar_ch_in[19] */ 2198 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR20 = 0x40001714u, /* From tcpwm[1].tr_out1[16] to pass[0].tr_sar_ch_in[20] */ 2199 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR21 = 0x40001715u, /* From tcpwm[1].tr_out1[17] to pass[0].tr_sar_ch_in[21] */ 2200 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR22 = 0x40001716u, /* From tcpwm[1].tr_out1[18] to pass[0].tr_sar_ch_in[22] */ 2201 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR23 = 0x40001717u, /* From tcpwm[1].tr_out1[19] to pass[0].tr_sar_ch_in[23] */ 2202 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR24 = 0x40001718u, /* From tcpwm[1].tr_out1[20] to pass[0].tr_sar_ch_in[24] */ 2203 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR25 = 0x40001719u, /* From tcpwm[1].tr_out1[21] to pass[0].tr_sar_ch_in[25] */ 2204 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR26 = 0x4000171Au, /* From tcpwm[1].tr_out1[22] to pass[0].tr_sar_ch_in[26] */ 2205 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR27 = 0x4000171Bu, /* From tcpwm[1].tr_out1[23] to pass[0].tr_sar_ch_in[27] */ 2206 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR28 = 0x4000171Cu, /* From tcpwm[1].tr_out1[24] to pass[0].tr_sar_ch_in[28] */ 2207 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR29 = 0x4000171Du, /* From tcpwm[1].tr_out1[25] to pass[0].tr_sar_ch_in[29] */ 2208 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR30 = 0x4000171Eu, /* From tcpwm[1].tr_out1[26] to pass[0].tr_sar_ch_in[30] */ 2209 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR31 = 0x4000171Fu, /* From tcpwm[1].tr_out1[27] to pass[0].tr_sar_ch_in[31] */ 2210 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR32 = 0x40001720u, /* From tcpwm[1].tr_out1[257] to pass[0].tr_sar_ch_in[32] */ 2211 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR33 = 0x40001721u, /* From tcpwm[1].tr_out1[260] to pass[0].tr_sar_ch_in[33] */ 2212 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR34 = 0x40001722u, /* From tcpwm[1].tr_out1[263] to pass[0].tr_sar_ch_in[34] */ 2213 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR35 = 0x40001723u, /* From tcpwm[1].tr_out1[266] to pass[0].tr_sar_ch_in[35] */ 2214 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR36 = 0x40001724u, /* From tcpwm[1].tr_out1[28] to pass[0].tr_sar_ch_in[36] */ 2215 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR37 = 0x40001725u, /* From tcpwm[1].tr_out1[29] to pass[0].tr_sar_ch_in[37] */ 2216 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR38 = 0x40001726u, /* From tcpwm[1].tr_out1[30] to pass[0].tr_sar_ch_in[38] */ 2217 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR39 = 0x40001727u, /* From tcpwm[1].tr_out1[31] to pass[0].tr_sar_ch_in[39] */ 2218 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR40 = 0x40001728u, /* From tcpwm[1].tr_out1[32] to pass[0].tr_sar_ch_in[40] */ 2219 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR41 = 0x40001729u, /* From tcpwm[1].tr_out1[33] to pass[0].tr_sar_ch_in[41] */ 2220 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR42 = 0x4000172Au, /* From tcpwm[1].tr_out1[34] to pass[0].tr_sar_ch_in[42] */ 2221 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR43 = 0x4000172Bu, /* From tcpwm[1].tr_out1[35] to pass[0].tr_sar_ch_in[43] */ 2222 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR44 = 0x4000172Cu, /* From tcpwm[1].tr_out1[36] to pass[0].tr_sar_ch_in[44] */ 2223 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR45 = 0x4000172Du, /* From tcpwm[1].tr_out1[37] to pass[0].tr_sar_ch_in[45] */ 2224 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR46 = 0x4000172Eu, /* From tcpwm[1].tr_out1[38] to pass[0].tr_sar_ch_in[46] */ 2225 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR47 = 0x4000172Fu, /* From tcpwm[1].tr_out1[39] to pass[0].tr_sar_ch_in[47] */ 2226 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR48 = 0x40001730u, /* From tcpwm[1].tr_out1[40] to pass[0].tr_sar_ch_in[48] */ 2227 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR49 = 0x40001731u, /* From tcpwm[1].tr_out1[41] to pass[0].tr_sar_ch_in[49] */ 2228 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR50 = 0x40001732u, /* From tcpwm[1].tr_out1[42] to pass[0].tr_sar_ch_in[50] */ 2229 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR51 = 0x40001733u, /* From tcpwm[1].tr_out1[43] to pass[0].tr_sar_ch_in[51] */ 2230 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR52 = 0x40001734u, /* From tcpwm[1].tr_out1[44] to pass[0].tr_sar_ch_in[52] */ 2231 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR53 = 0x40001735u, /* From tcpwm[1].tr_out1[45] to pass[0].tr_sar_ch_in[53] */ 2232 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR54 = 0x40001736u, /* From tcpwm[1].tr_out1[46] to pass[0].tr_sar_ch_in[54] */ 2233 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR55 = 0x40001737u, /* From tcpwm[1].tr_out1[47] to pass[0].tr_sar_ch_in[55] */ 2234 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR56 = 0x40001738u, /* From tcpwm[1].tr_out1[48] to pass[0].tr_sar_ch_in[56] */ 2235 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR57 = 0x40001739u, /* From tcpwm[1].tr_out1[49] to pass[0].tr_sar_ch_in[57] */ 2236 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR58 = 0x4000173Au, /* From tcpwm[1].tr_out1[50] to pass[0].tr_sar_ch_in[58] */ 2237 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR59 = 0x4000173Bu, /* From tcpwm[1].tr_out1[51] to pass[0].tr_sar_ch_in[59] */ 2238 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR60 = 0x4000173Cu, /* From tcpwm[1].tr_out1[52] to pass[0].tr_sar_ch_in[60] */ 2239 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR61 = 0x4000173Du, /* From tcpwm[1].tr_out1[53] to pass[0].tr_sar_ch_in[61] */ 2240 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR62 = 0x4000173Eu, /* From tcpwm[1].tr_out1[54] to pass[0].tr_sar_ch_in[62] */ 2241 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR63 = 0x4000173Fu, /* From tcpwm[1].tr_out1[55] to pass[0].tr_sar_ch_in[63] */ 2242 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR64 = 0x40001740u, /* From tcpwm[1].tr_out1[258] to pass[0].tr_sar_ch_in[64] */ 2243 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR65 = 0x40001741u, /* From tcpwm[1].tr_out1[261] to pass[0].tr_sar_ch_in[65] */ 2244 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR66 = 0x40001742u, /* From tcpwm[1].tr_out1[264] to pass[0].tr_sar_ch_in[66] */ 2245 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR67 = 0x40001743u, /* From tcpwm[1].tr_out1[267] to pass[0].tr_sar_ch_in[67] */ 2246 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR68 = 0x40001744u, /* From tcpwm[1].tr_out1[56] to pass[0].tr_sar_ch_in[68] */ 2247 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR69 = 0x40001745u, /* From tcpwm[1].tr_out1[57] to pass[0].tr_sar_ch_in[69] */ 2248 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR70 = 0x40001746u, /* From tcpwm[1].tr_out1[58] to pass[0].tr_sar_ch_in[70] */ 2249 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR71 = 0x40001747u, /* From tcpwm[1].tr_out1[59] to pass[0].tr_sar_ch_in[71] */ 2250 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR72 = 0x40001748u, /* From tcpwm[1].tr_out1[60] to pass[0].tr_sar_ch_in[72] */ 2251 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR73 = 0x40001749u, /* From tcpwm[1].tr_out1[61] to pass[0].tr_sar_ch_in[73] */ 2252 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR74 = 0x4000174Au, /* From tcpwm[1].tr_out1[62] to pass[0].tr_sar_ch_in[74] */ 2253 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR75 = 0x4000174Bu, /* From tcpwm[1].tr_out1[63] to pass[0].tr_sar_ch_in[75] */ 2254 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR76 = 0x4000174Cu, /* From tcpwm[1].tr_out1[64] to pass[0].tr_sar_ch_in[76] */ 2255 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR77 = 0x4000174Du, /* From tcpwm[1].tr_out1[65] to pass[0].tr_sar_ch_in[77] */ 2256 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR78 = 0x4000174Eu, /* From tcpwm[1].tr_out1[66] to pass[0].tr_sar_ch_in[78] */ 2257 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR79 = 0x4000174Fu, /* From tcpwm[1].tr_out1[67] to pass[0].tr_sar_ch_in[79] */ 2258 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR80 = 0x40001750u, /* From tcpwm[1].tr_out1[68] to pass[0].tr_sar_ch_in[80] */ 2259 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR81 = 0x40001751u, /* From tcpwm[1].tr_out1[69] to pass[0].tr_sar_ch_in[81] */ 2260 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR82 = 0x40001752u, /* From tcpwm[1].tr_out1[70] to pass[0].tr_sar_ch_in[82] */ 2261 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR83 = 0x40001753u, /* From tcpwm[1].tr_out1[71] to pass[0].tr_sar_ch_in[83] */ 2262 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR84 = 0x40001754u, /* From tcpwm[1].tr_out1[72] to pass[0].tr_sar_ch_in[84] */ 2263 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR85 = 0x40001755u, /* From tcpwm[1].tr_out1[73] to pass[0].tr_sar_ch_in[85] */ 2264 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR86 = 0x40001756u, /* From tcpwm[1].tr_out1[74] to pass[0].tr_sar_ch_in[86] */ 2265 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR87 = 0x40001757u, /* From tcpwm[1].tr_out1[75] to pass[0].tr_sar_ch_in[87] */ 2266 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR88 = 0x40001758u, /* From tcpwm[1].tr_out1[76] to pass[0].tr_sar_ch_in[88] */ 2267 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR89 = 0x40001759u, /* From tcpwm[1].tr_out1[77] to pass[0].tr_sar_ch_in[89] */ 2268 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR90 = 0x4000175Au, /* From tcpwm[1].tr_out1[78] to pass[0].tr_sar_ch_in[90] */ 2269 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR91 = 0x4000175Bu, /* From tcpwm[1].tr_out1[79] to pass[0].tr_sar_ch_in[91] */ 2270 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR92 = 0x4000175Cu, /* From tcpwm[1].tr_out1[80] to pass[0].tr_sar_ch_in[92] */ 2271 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR93 = 0x4000175Du, /* From tcpwm[1].tr_out1[81] to pass[0].tr_sar_ch_in[93] */ 2272 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR94 = 0x4000175Eu, /* From tcpwm[1].tr_out1[82] to pass[0].tr_sar_ch_in[94] */ 2273 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR95 = 0x4000175Fu /* From tcpwm[1].tr_out1[83] to pass[0].tr_sar_ch_in[95] */ 2274 } en_trig_output_1to1_pwm_to_pass_t; 2275 2276 /* Trigger Output Group 8 - Acknowledge triggers from DW1 to CAN (OneToOne) */ 2277 typedef enum 2278 { 2279 TRIG_OUT_1TO1_8_PDMA1_ACK_TO_CAN1_0 = 0x40001800u, /* From cpuss.dw1_tr_out[38] to canfd[1].tr_dbg_dma_ack[0] */ 2280 TRIG_OUT_1TO1_8_PDMA1_ACK_TO_CAN1_1 = 0x40001801u, /* From cpuss.dw1_tr_out[41] to canfd[1].tr_dbg_dma_ack[1] */ 2281 TRIG_OUT_1TO1_8_PDMA1_ACK_TO_CAN1_2 = 0x40001802u, /* From cpuss.dw1_tr_out[44] to canfd[1].tr_dbg_dma_ack[2] */ 2282 TRIG_OUT_1TO1_8_PDMA1_ACK_TO_CAN1_3 = 0x40001803u, /* From cpuss.dw1_tr_out[47] to canfd[1].tr_dbg_dma_ack[3] */ 2283 TRIG_OUT_1TO1_8_PDMA1_ACK_TO_CAN1_4 = 0x40001804u /* From cpuss.dw1_tr_out[50] to canfd[1].tr_dbg_dma_ack[4] */ 2284 } en_trig_output_1to1_can1_dw1_ack_t; 2285 2286 /* Trigger Output Group 9 - Acknowledge triggers from DW0 to CAN (OneToOne) */ 2287 typedef enum 2288 { 2289 TRIG_OUT_1TO1_9_PDMA0_ACK_TO_CAN0_0 = 0x40001900u, /* From cpuss.dw0_tr_out[32] to canfd[0].tr_dbg_dma_ack[0] */ 2290 TRIG_OUT_1TO1_9_PDMA0_ACK_TO_CAN0_1 = 0x40001901u, /* From cpuss.dw0_tr_out[35] to canfd[0].tr_dbg_dma_ack[1] */ 2291 TRIG_OUT_1TO1_9_PDMA0_ACK_TO_CAN0_2 = 0x40001902u, /* From cpuss.dw0_tr_out[38] to canfd[0].tr_dbg_dma_ack[2] */ 2292 TRIG_OUT_1TO1_9_PDMA0_ACK_TO_CAN0_3 = 0x40001903u, /* From cpuss.dw0_tr_out[41] to canfd[0].tr_dbg_dma_ack[3] */ 2293 TRIG_OUT_1TO1_9_PDMA0_ACK_TO_CAN0_4 = 0x40001904u /* From cpuss.dw0_tr_out[44] to canfd[0].tr_dbg_dma_ack[4] */ 2294 } en_trig_output_1to1_can0_dw0_ack_t; 2295 2296 /* Trigger Output Group 10 - (OneToOne) */ 2297 typedef enum 2298 { 2299 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR0 = 0x40001A00u, /* From tcpwm[1].tr_out0[0] to lin[0].tr_cmd_tx_header[0] */ 2300 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR1 = 0x40001A01u, /* From tcpwm[1].tr_out0[1] to lin[0].tr_cmd_tx_header[1] */ 2301 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR2 = 0x40001A02u, /* From tcpwm[1].tr_out0[2] to lin[0].tr_cmd_tx_header[2] */ 2302 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR3 = 0x40001A03u, /* From tcpwm[1].tr_out0[3] to lin[0].tr_cmd_tx_header[3] */ 2303 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR4 = 0x40001A04u, /* From tcpwm[1].tr_out0[4] to lin[0].tr_cmd_tx_header[4] */ 2304 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR5 = 0x40001A05u, /* From tcpwm[1].tr_out0[5] to lin[0].tr_cmd_tx_header[5] */ 2305 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR6 = 0x40001A06u, /* From tcpwm[1].tr_out0[6] to lin[0].tr_cmd_tx_header[6] */ 2306 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR7 = 0x40001A07u, /* From tcpwm[1].tr_out0[7] to lin[0].tr_cmd_tx_header[7] */ 2307 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR8 = 0x40001A08u, /* From tcpwm[1].tr_out0[8] to lin[0].tr_cmd_tx_header[8] */ 2308 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR9 = 0x40001A09u, /* From tcpwm[1].tr_out0[9] to lin[0].tr_cmd_tx_header[9] */ 2309 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR10 = 0x40001A0Au, /* From tcpwm[1].tr_out0[10] to lin[0].tr_cmd_tx_header[10] */ 2310 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR11 = 0x40001A0Bu, /* From tcpwm[1].tr_out0[11] to lin[0].tr_cmd_tx_header[11] */ 2311 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR12 = 0x40001A0Cu, /* From tcpwm[1].tr_out0[12] to lin[0].tr_cmd_tx_header[12] */ 2312 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR13 = 0x40001A0Du, /* From tcpwm[1].tr_out0[13] to lin[0].tr_cmd_tx_header[13] */ 2313 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR14 = 0x40001A0Eu, /* From tcpwm[1].tr_out0[14] to lin[0].tr_cmd_tx_header[14] */ 2314 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR15 = 0x40001A0Fu, /* From tcpwm[1].tr_out0[15] to lin[0].tr_cmd_tx_header[15] */ 2315 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR16 = 0x40001A10u, /* From tcpwm[1].tr_out0[16] to lin[0].tr_cmd_tx_header[16] */ 2316 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR17 = 0x40001A11u, /* From tcpwm[1].tr_out0[17] to lin[0].tr_cmd_tx_header[17] */ 2317 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR18 = 0x40001A12u, /* From tcpwm[1].tr_out0[18] to lin[0].tr_cmd_tx_header[18] */ 2318 TRIG_OUT_1TO1_10_TCPWM1_TO_LIN_TR19 = 0x40001A13u /* From tcpwm[1].tr_out0[19] to lin[0].tr_cmd_tx_header[19] */ 2319 } en_trig_output_1to1_tcpwm_to_lin_t; 2320 2321 /* Trigger Output Group 11 - (OneToOne) */ 2322 typedef enum 2323 { 2324 TRIG_OUT_1TO1_11_FLEXRAY_IBF_TR_TO_PDMA1 = 0x40001B00u, /* From flexray[0].tr_ibf_out to cpuss.dw1_tr_in[61] */ 2325 TRIG_OUT_1TO1_11_FLEXRAY_OBF_TR_TO_PDMA1 = 0x40001B01u /* From flexray[0].tr_obf_out to cpuss.dw1_tr_in[62] */ 2326 } en_trig_output_1to1_flexyray_dw1_tr_t; 2327 2328 /* Trigger Output Group 12 - (OneToOne) */ 2329 typedef enum 2330 { 2331 TRIG_OUT_1TO1_12_PDMA1_61_TO_PDMA1_63 = 0x40001C00u, /* From cpuss.dw1_tr_out[61] to cpuss.dw1_tr_in[63] */ 2332 TRIG_OUT_1TO1_12_PDMA1_62_TO_PDMA1_64 = 0x40001C01u /* From cpuss.dw1_tr_out[62] to cpuss.dw1_tr_in[64] */ 2333 } en_trig_output_1to1_dw1_dw1_tr_t; 2334 2335 /* Trigger Output Group 13 - (OneToOne) */ 2336 typedef enum 2337 { 2338 TRIG_OUT_1TO1_13_PDMA1_TO_FLEXRAY_IBF_TR = 0x40001D00u, /* From cpuss.dw1_tr_out[63] to flexray[0].tr_ibf_in */ 2339 TRIG_OUT_1TO1_13_PDMA1_TO_FLEXRAY_OBF_TR = 0x40001D01u /* From cpuss.dw1_tr_out[64] to flexray[0].tr_obf_in */ 2340 } en_trig_output_1to1_dw1_flexray_tr_t; 2341 2342 /* Level or edge detection setting for a trigger mux */ 2343 typedef enum 2344 { 2345 /* The trigger is a simple level output */ 2346 TRIGGER_TYPE_LEVEL = 0u, 2347 /* The trigger is synchronized to the consumer blocks clock 2348 and a two cycle pulse is generated on this clock */ 2349 TRIGGER_TYPE_EDGE = 1u 2350 } en_trig_type_t; 2351 2352 /* Trigger Type Defines */ 2353 /* AUDIOSS Trigger Types */ 2354 #define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL 2355 #define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL 2356 /* CANFD Trigger Types */ 2357 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE 2358 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL 2359 #define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE 2360 #define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL 2361 #define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL 2362 #define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE 2363 /* CPUSS Trigger Types */ 2364 #define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE 2365 #define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE 2366 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 2367 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE 2368 #define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE 2369 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 2370 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE 2371 #define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE 2372 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 2373 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE 2374 #define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE 2375 #define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE 2376 /* FLEXRAY Trigger Types */ 2377 #define TRIGGER_TYPE_FLEXRAY_TR_IBF_IN TRIGGER_TYPE_EDGE 2378 #define TRIGGER_TYPE_FLEXRAY_TR_IBF_OUT TRIGGER_TYPE_EDGE 2379 #define TRIGGER_TYPE_FLEXRAY_TR_OBF_IN TRIGGER_TYPE_EDGE 2380 #define TRIGGER_TYPE_FLEXRAY_TR_OBF_OUT TRIGGER_TYPE_EDGE 2381 #define TRIGGER_TYPE_FLEXRAY_TR_STPWT_IN TRIGGER_TYPE_EDGE 2382 #define TRIGGER_TYPE_FLEXRAY_TR_TINT0_OUT TRIGGER_TYPE_EDGE 2383 /* LIN Trigger Types */ 2384 #define TRIGGER_TYPE_LIN_TR_CMD_TX_HEADER TRIGGER_TYPE_EDGE 2385 /* PASS Trigger Types */ 2386 #define TRIGGER_TYPE_PASS_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 2387 #define TRIGGER_TYPE_PASS_TR_SAR_CH_DONE__LEVEL TRIGGER_TYPE_LEVEL 2388 #define TRIGGER_TYPE_PASS_TR_SAR_CH_DONE__EDGE TRIGGER_TYPE_EDGE 2389 #define TRIGGER_TYPE_PASS_TR_SAR_CH_IN__LEVEL TRIGGER_TYPE_LEVEL 2390 #define TRIGGER_TYPE_PASS_TR_SAR_CH_IN__EDGE TRIGGER_TYPE_EDGE 2391 #define TRIGGER_TYPE_PASS_TR_SAR_CH_RANGEVIO TRIGGER_TYPE_EDGE 2392 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_IN__LEVEL TRIGGER_TYPE_LEVEL 2393 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_IN__EDGE TRIGGER_TYPE_EDGE 2394 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_OUT__LEVEL TRIGGER_TYPE_LEVEL 2395 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_OUT__EDGE TRIGGER_TYPE_EDGE 2396 /* PERI Trigger Types */ 2397 #define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 2398 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL 2399 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE 2400 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 2401 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE 2402 /* SCB Trigger Types */ 2403 #define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL 2404 #define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL 2405 #define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL 2406 /* SMIF Trigger Types */ 2407 #define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL 2408 #define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL 2409 /* SRSS Trigger Types */ 2410 #define TRIGGER_TYPE_SRSS_TR_DEBUG_FREEZE_MCWDT TRIGGER_TYPE_LEVEL 2411 #define TRIGGER_TYPE_SRSS_TR_DEBUG_FREEZE_WDT TRIGGER_TYPE_LEVEL 2412 /* TCPWM Trigger Types */ 2413 #define TRIGGER_TYPE_TCPWM_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 2414 /* TR_GROUP Trigger Types */ 2415 #define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 2416 #define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE 2417 #define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL TRIGGER_TYPE_LEVEL 2418 #define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE TRIGGER_TYPE_EDGE 2419 2420 /* Fault connections */ 2421 typedef enum 2422 { 2423 CPUSS_MPU_VIO_0 = 0x0000u, 2424 CPUSS_MPU_VIO_1 = 0x0001u, 2425 CPUSS_MPU_VIO_2 = 0x0002u, 2426 CPUSS_MPU_VIO_3 = 0x0003u, 2427 CPUSS_MPU_VIO_4 = 0x0004u, 2428 CPUSS_MPU_VIO_5 = 0x0005u, 2429 CPUSS_MPU_VIO_9 = 0x0009u, 2430 CPUSS_MPU_VIO_10 = 0x000Au, 2431 CPUSS_MPU_VIO_13 = 0x000Du, 2432 CPUSS_MPU_VIO_14 = 0x000Eu, 2433 CPUSS_MPU_VIO_15 = 0x000Fu, 2434 CPUSS_CM7_1_TCM_C_ECC = 0x0010u, 2435 CPUSS_CM7_1_TCM_NC_ECC = 0x0011u, 2436 CPUSS_CM7_0_CACHE_C_ECC = 0x0012u, 2437 CPUSS_CM7_0_CACHE_NC_ECC = 0x0013u, 2438 CPUSS_CM7_1_CACHE_C_ECC = 0x0014u, 2439 CPUSS_CM7_1_CACHE_NC_ECC = 0x0015u, 2440 PERI_MS_VIO_4 = 0x0019u, 2441 PERI_PERI_C_ECC = 0x001Au, 2442 PERI_PERI_NC_ECC = 0x001Bu, 2443 PERI_MS_VIO_0 = 0x001Cu, 2444 PERI_MS_VIO_1 = 0x001Du, 2445 PERI_MS_VIO_2 = 0x001Eu, 2446 PERI_MS_VIO_3 = 0x001Fu, 2447 PERI_GROUP_VIO_0 = 0x0020u, 2448 PERI_GROUP_VIO_1 = 0x0021u, 2449 PERI_GROUP_VIO_2 = 0x0022u, 2450 PERI_GROUP_VIO_3 = 0x0023u, 2451 PERI_GROUP_VIO_4 = 0x0024u, 2452 PERI_GROUP_VIO_5 = 0x0025u, 2453 PERI_GROUP_VIO_6 = 0x0026u, 2454 PERI_GROUP_VIO_8 = 0x0028u, 2455 PERI_GROUP_VIO_9 = 0x0029u, 2456 CPUSS_FLASHC_MAIN_BUS_ERR = 0x0030u, 2457 CPUSS_FLASHC_MAIN_C_ECC = 0x0031u, 2458 CPUSS_FLASHC_MAIN_NC_ECC = 0x0032u, 2459 CPUSS_FLASHC_WORK_BUS_ERR = 0x0033u, 2460 CPUSS_FLASHC_WORK_C_ECC = 0x0034u, 2461 CPUSS_FLASHC_WORK_NC_ECC = 0x0035u, 2462 CPUSS_FLASHC_CM0_CA_C_ECC = 0x0036u, 2463 CPUSS_FLASHC_CM0_CA_NC_ECC = 0x0037u, 2464 CPUSS_CM7_0_TCM_C_ECC = 0x0038u, 2465 CPUSS_CM7_0_TCM_NC_ECC = 0x0039u, 2466 CPUSS_RAMC0_C_ECC = 0x003Au, 2467 CPUSS_RAMC0_NC_ECC = 0x003Bu, 2468 CPUSS_RAMC1_C_ECC = 0x003Cu, 2469 CPUSS_RAMC1_NC_ECC = 0x003Du, 2470 CPUSS_RAMC2_C_ECC = 0x003Eu, 2471 CPUSS_RAMC2_NC_ECC = 0x003Fu, 2472 CPUSS_CRYPTO_C_ECC = 0x0040u, 2473 CPUSS_CRYPTO_NC_ECC = 0x0041u, 2474 CPUSS_DW0_C_ECC = 0x0046u, 2475 CPUSS_DW0_NC_ECC = 0x0047u, 2476 CPUSS_DW1_C_ECC = 0x0048u, 2477 CPUSS_DW1_NC_ECC = 0x0049u, 2478 CPUSS_FM_SRAM_C_ECC = 0x004Au, 2479 CPUSS_FM_SRAM_NC_ECC = 0x004Bu, 2480 CANFD_0_CAN_C_ECC = 0x0050u, 2481 CANFD_0_CAN_NC_ECC = 0x0051u, 2482 CANFD_1_CAN_C_ECC = 0x0052u, 2483 CANFD_1_CAN_NC_ECC = 0x0053u, 2484 SRSS_FAULT_CSV = 0x005Au, 2485 SRSS_FAULT_SSV = 0x005Bu, 2486 SRSS_FAULT_MCWDT0 = 0x005Cu, 2487 SRSS_FAULT_MCWDT1 = 0x005Du, 2488 SRSS_FAULT_MCWDT2 = 0x005Eu 2489 } en_sysfault_source_t; 2490 2491 /* Bus masters */ 2492 typedef enum 2493 { 2494 CPUSS_MS_ID_CM0 = 0, 2495 CPUSS_MS_ID_CRYPTO = 1, 2496 CPUSS_MS_ID_DW0 = 2, 2497 CPUSS_MS_ID_DW1 = 3, 2498 CPUSS_MS_ID_DMAC = 4, 2499 CPUSS_MS_ID_SLOW0 = 5, 2500 CPUSS_MS_ID_SLOW1 = 6, 2501 CPUSS_MS_ID_FAST0 = 9, 2502 CPUSS_MS_ID_FAST1 = 10, 2503 CPUSS_MS_ID_FAST2 = 11, 2504 CPUSS_MS_ID_FAST3 = 12, 2505 CPUSS_MS_ID_CM7_1 = 13, 2506 CPUSS_MS_ID_CM7_0 = 14, 2507 CPUSS_MS_ID_TC = 15 2508 } en_prot_master_t; 2509 2510 /* Include IP definitions */ 2511 #include "ip/cyip_sflash_xmc7200.h" 2512 #include "ip/cyip_peri_v3.h" 2513 #include "ip/cyip_peri_ms_v3.h" 2514 #include "ip/cyip_peri_pclk_v3.h" 2515 #include "ip/cyip_crypto_v2.h" 2516 #include "ip/cyip_cpuss.h" 2517 #include "ip/cyip_fault.h" 2518 #include "ip/cyip_ipc.h" 2519 #include "ip/cyip_prot.h" 2520 #include "ip/cyip_flashc_ect.h" 2521 #include "ip/cyip_srss_v3_2.h" 2522 #include "ip/cyip_backup_v3_2.h" 2523 #include "ip/cyip_dw.h" 2524 #include "ip/cyip_dmac.h" 2525 #include "ip/cyip_efuse_v2.h" 2526 #include "ip/cyip_efuse_data_v2_xmc7200.h" 2527 #include "ip/cyip_hsiom_v3.h" 2528 #include "ip/cyip_gpio_v3.h" 2529 #include "ip/cyip_smartio_v3.h" 2530 #include "ip/cyip_tcpwm_v2.h" 2531 #include "ip/cyip_evtgen.h" 2532 #include "ip/cyip_smif_v2.h" 2533 #include "ip/cyip_sdhc.h" 2534 #include "ip/cyip_eth.h" 2535 #include "ip/cyip_lin.h" 2536 #include "ip/cyip_canfd.h" 2537 #include "ip/cyip_flexray.h" 2538 #include "ip/cyip_scb_v2.h" 2539 #include "ip/cyip_i2s_v2.h" 2540 #include "ip/cyip_pass.h" 2541 2542 /* IP type definitions */ 2543 typedef CRYPTO_V2_Type CRYPTO_Type; 2544 2545 /* Parameter Defines */ 2546 /* I2S capable? (0=No,1=Yes) */ 2547 #define AUDIOSS0_I2S_I2S 1u 2548 /* I2S instantiates both RX and TX. 0=TX Only 1=RX Plus TX present */ 2549 #define AUDIOSS0_I2S_I2S_RX_TX 1u 2550 /* PDM capable? (0=No,1=Yes) */ 2551 #define AUDIOSS0_PDM_PDM 0u 2552 /* I2S capable? (0=No,1=Yes) */ 2553 #define AUDIOSS1_I2S_I2S 1u 2554 /* I2S instantiates both RX and TX. 0=TX Only 1=RX Plus TX present */ 2555 #define AUDIOSS1_I2S_I2S_RX_TX 1u 2556 /* PDM capable? (0=No,1=Yes) */ 2557 #define AUDIOSS1_PDM_PDM 0u 2558 /* I2S capable? (0=No,1=Yes) */ 2559 #define AUDIOSS2_I2S_I2S 1u 2560 /* I2S instantiates both RX and TX. 0=TX Only 1=RX Plus TX present */ 2561 #define AUDIOSS2_I2S_I2S_RX_TX 1u 2562 /* PDM capable? (0=No,1=Yes) */ 2563 #define AUDIOSS2_PDM_PDM 0u 2564 /* Number of TTCAN instances */ 2565 #define CANFD0_CAN_NR 5u 2566 /* ECC logic present or not */ 2567 #define CANFD0_ECC_PRESENT 1u 2568 /* address included in ECC logic or not */ 2569 #define CANFD0_ECC_ADDR_PRESENT 1u 2570 /* Time Stamp counter present or not (required for instance 0, otherwise not 2571 allowed) */ 2572 #define CANFD0_TS_PRESENT 1u 2573 /* Message RAM size in KB */ 2574 #define CANFD0_MRAM_SIZE 40u 2575 /* Message RAM address width */ 2576 #define CANFD0_MRAM_ADDR_WIDTH 14u 2577 /* Number of TTCAN instances */ 2578 #define CANFD1_CAN_NR 5u 2579 /* ECC logic present or not */ 2580 #define CANFD1_ECC_PRESENT 1u 2581 /* address included in ECC logic or not */ 2582 #define CANFD1_ECC_ADDR_PRESENT 1u 2583 /* Time Stamp counter present or not (required for instance 0, otherwise not 2584 allowed) */ 2585 #define CANFD1_TS_PRESENT 0u 2586 /* Message RAM size in KB */ 2587 #define CANFD1_MRAM_SIZE 40u 2588 /* Message RAM address width */ 2589 #define CANFD1_MRAM_ADDR_WIDTH 14u 2590 /* UDB present or not ('0': no, '1': yes) */ 2591 #define CPUSS_UDB_PRESENT 0u 2592 /* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the 2593 chips which doesn't use mxdft. */ 2594 #define CPUSS_MBIST_MMIO_PRESENT 0u 2595 /* System RAM 0 size in KB */ 2596 #define CPUSS_SRAM0_SIZE 512u 2597 /* Number of macros used to implement system RAM 0. Example: 8 if 256 KB system 2598 SRAM 0 is implemented with 8 32KB macros. */ 2599 #define CPUSS_RAMC0_MACRO_NR 16u 2600 /* System RAM 1 present or not ('0': no, '1': yes) */ 2601 #define CPUSS_RAMC1_PRESENT 1u 2602 /* System RAM 1 size in KB */ 2603 #define CPUSS_SRAM1_SIZE 256u 2604 /* Number of macros used to implement system RAM 1. */ 2605 #define CPUSS_RAMC1_MACRO_NR 8u 2606 /* System RAM 2 present or not ('0': no, '1': yes) */ 2607 #define CPUSS_RAMC2_PRESENT 1u 2608 /* System RAM 2 size in KB */ 2609 #define CPUSS_SRAM2_SIZE 256u 2610 /* Number of macros used to implement System RAM 2. */ 2611 #define CPUSS_RAMC2_MACRO_NR 8u 2612 /* System SRAM(s) ECC present or not ('0': no, '1': yes) */ 2613 #define CPUSS_RAMC_ECC_PRESENT 1u 2614 /* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ 2615 #define CPUSS_RAMC_ECC_ADDR_PRESENT 1u 2616 /* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ 2617 #define CPUSS_ECC_PRESENT 1u 2618 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 2619 #define CPUSS_DW_ECC_PRESENT 1u 2620 /* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ 2621 #define CPUSS_DW_ECC_ADDR_PRESENT 1u 2622 /* System ROM size in KB */ 2623 #define CPUSS_ROM_SIZE 64u 2624 /* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM 2625 is implemented with 4 128KB macros. */ 2626 #define CPUSS_ROMC_MACRO_NR 1u 2627 /* Flash memory present or not ('0': no, '1': yes) */ 2628 #define CPUSS_FLASHC_PRESENT 1u 2629 /* Flash memory type ('0' : SONOS, '1': ECT) */ 2630 #define CPUSS_FLASHC_ECT 1u 2631 /* Flash main region size in KB */ 2632 #define CPUSS_FLASH_SIZE 0x00002000u 2633 /* Flash work region size in KB (EEPROM emulation, data) */ 2634 #define CPUSS_WFLASH_SIZE 256u 2635 /* Flash supervisory region size in KB */ 2636 #define CPUSS_SFLASH_SIZE 32u 2637 /* Flash data output word size (in Bits) Example: 256 for 256-bit Flash data 2638 output */ 2639 #define CPUSS_FLASHC_MAIN_DATA_WIDTH 256u 2640 /* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special 2641 sectors present in Flash. Part of main sector 0 is allowcated for Supervisory 2642 Flash, and no Work Flash present. */ 2643 #define CPUSS_FLASHC_SONOS_RWW 0u 2644 /* SONOS Flash, number of main sectors. */ 2645 #define CPUSS_FLASHC_SONOS_MAIN_SECTORS 0u 2646 /* SONOS Flash, number of rows per main sector. */ 2647 #define CPUSS_FLASHC_SONOS_MAIN_ROWS 0u 2648 /* SONOS Flash, number of words per row of main sector. */ 2649 #define CPUSS_FLASHC_SONOS_MAIN_WORDS 0u 2650 /* SONOS Flash, number of special sectors. */ 2651 #define CPUSS_FLASHC_SONOS_SPL_SECTORS 0u 2652 /* SONOS Flash, number of rows per special sector. */ 2653 #define CPUSS_FLASHC_SONOS_SPL_ROWS 0u 2654 /* Flash memory ECC present or not ('0': no, '1': yes) */ 2655 #define CPUSS_FLASHC_FLASH_ECC_PRESENT 1u 2656 /* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ 2657 #define CPUSS_FLASHC_RAM_ECC_PRESENT 1u 2658 /* Number of external AHB-Lite slaves directly connected to slow AHB-Lite 2659 infrastructure. Maximum nubmer of slave supported is 6. Width of this 2660 parameter is 6-bits. 1-bit mask for each slave indicating present or not. 2661 Example: 6'b00_0011 - slave 0 and slave 1 are present. Note: The 2662 SLOW_SLx_ADDR and SLOW_SLx_MASK parameters (for the slaves present) should be 2663 derived from the Memory Map. */ 2664 #define CPUSS_SLOW_SL_PRESENT 1u 2665 /* Number of external AXI slaves directly connected to fast AXI infrastructure. 2666 Maximum nubmer of slave supported is 8. Width of this parameter is 8-bits. 2667 1-bit mask for each slave indicating present or not. Example: 8'b0000_0011 - 2668 slave 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK 2669 parameters (for the slaves present) should be derived from the Memory Map. */ 2670 #define CPUSS_FAST_SL_PRESENT 1u 2671 /* Number of external AHB-Lite masters driving the slow AHB-Lite infrastructure. 2672 Maximum number of masters supported is 2. Width of this parameter is 2-bits. 2673 1-bit mask for each master indicating present or not. Example: 2'b01 - master 2674 0 is present. */ 2675 #define CPUSS_SLOW_MS_PRESENT 1u 2676 /* Number of external AXI masters driving the fast AXI infrastructure. Maximum 2677 number of masters supported is 4. Width of this parameter is 4-bits. 1-bit 2678 mask for each master indicating present or not. Example: 4'b0001 - master 0 2679 is present. */ 2680 #define CPUSS_FAST_MS_PRESENT 3u 2681 /* Retain 'protection context' (PC), 'privileged' (P), 'Non Secure' (NS) 2682 attributes coming from external AXI master or use it from CPUSS protection 2683 MMIO (PROT_MPU.MS_CTL.PC, PROT_SMPU.MSx_CTL.P, PROT_SMPU.MSx_CTL.NS). Width 2684 of this parameter is 4-bits. 1-bit mask for each master indicating retain PC 2685 or not. */ 2686 #define CPUSS_AXIM_RETAIN_PROT 0u 2687 /* Width of external AXI master ID signals. Legal range [3,8] */ 2688 #define CPUSS_AXIM_ID_WIDTH 3u 2689 /* Width of external AXI slave ID signals (AXIM_ID_WIDTH + MASTER_WIDTH + 1). 2690 Legal range [12,17] */ 2691 #define CPUSS_AXIS_ID_WIDTH 12u 2692 /* IRQ expander present ('0': no, '1': yes) */ 2693 #define CPUSS_SYSTEM_IRQ_PRESENT 1u 2694 /* Number of system interrupt inputs to CPUSS */ 2695 #define CPUSS_SYSTEM_INT_NR 567u 2696 /* Number of DeepSleep system interrupt inputs to CPUSS */ 2697 #define CPUSS_SYSTEM_DPSLP_INT_NR 51u 2698 /* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 2699 levels of priority 8 = 256 levels of priority */ 2700 #define CPUSS_CM7_LVL_WIDTH 3u 2701 /* Number of CM7 CPU Interrupts. Legal values 8 or 16. */ 2702 #define CPUSS_CM7_INT_NR 8u 2703 /* CM7 Cache SRAMs ECC present or not ('0': no, '1': yes) */ 2704 #define CPUSS_CM7_CACHE_ECC_PRESENT 1u 2705 /* CM7 TCM SRAMs ECC present or not ('0': no, '1': yes) */ 2706 #define CPUSS_CM7_TCM_ECC_PRESENT 1u 2707 /* CM7 TCM SRAMs address ECC present or not ('0': no, '1': yes) */ 2708 #define CPUSS_CM7_TCM_ECC_ADDR_PRESENT 0u 2709 /* CM7_0 Floating point unit configuration. Legal range [0,2] 0 - No FPU 1 - 2710 Single precision FPU 2 - Single and Double precision FPU */ 2711 #define CPUSS_CM7_0_FPU_LVL 2u 2712 /* Number of MPU regions in CM7_0. Legal values [0, 8, 16] */ 2713 #define CPUSS_CM7_0_MPU_NR 16u 2714 /* CM7_0 Instruction cache (ICACHE) size in KB */ 2715 #define CPUSS_CM7_0_ICACHE_SIZE 16u 2716 /* CM7_0 Data cache size (DCACHE) in KB */ 2717 #define CPUSS_CM7_0_DCACHE_SIZE 16u 2718 /* CM7_0 Instruction TCM (ITCM) size in KB */ 2719 #define CPUSS_CM7_0_ITCM_SIZE 16u 2720 /* CM7_0 Data TCM (DTCM) size in KB */ 2721 #define CPUSS_CM7_0_DTCM_SIZE 16u 2722 /* CM7_1 CPU present or not ('0': no, '1': yes) */ 2723 #define CPUSS_CM7_1_PRESENT 1u 2724 /* System interrupt functionality present or not ('0': no; '1': yes) for CM7_1. 2725 Not used for CM0+ CPU, which always uses system interrupt functionality. */ 2726 #define CPUSS_CM7_1_SYSTEM_IRQ_PRESENT 1u 2727 /* CM7_1 Floating point unit configuration. Legal range [0,2] 0 - No FPU 1 - 2728 Single precision FPU 2 - Single and Double precision FPU */ 2729 #define CPUSS_CM7_1_FPU_LVL 2u 2730 /* Number of MPU regions in CM7_1. Legal values [0, 8, 16] */ 2731 #define CPUSS_CM7_1_MPU_NR 16u 2732 /* CM7_1 Instruction cache (ICACHE) size in KB */ 2733 #define CPUSS_CM7_1_ICACHE_SIZE 16u 2734 /* CM7_1 Data cache size (DCACHE) in KB */ 2735 #define CPUSS_CM7_1_DCACHE_SIZE 16u 2736 /* CM7_1 Instruction TCM (ITCM) size in KB */ 2737 #define CPUSS_CM7_1_ITCM_SIZE 16u 2738 /* CM7_1 Data TCM (DTCM) size in KB */ 2739 #define CPUSS_CM7_1_DTCM_SIZE 16u 2740 /* Debug level. Legal range [0,3] */ 2741 #define CPUSS_DEBUG_LVL 3u 2742 /* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3 2743 for trace level is not supported in CPUSS. // CPUSS_TRACE_LVL: // 0 = no 2744 tracing // 1 = only ITM source and TPIU sink (no ETM, Funnel, Replicator or 2745 ETB) // 2 = ITM and ETM sources, Funnel and TPIU (no Replicator or ETB) // 3 2746 = ITM and ETM sources, Funnel, Replicator, TPIU and ET */ 2747 #define CPUSS_TRACE_LVL 2u 2748 /* Embedded Trace Buffer present or not ('0': no, '1': yes) */ 2749 #define CPUSS_ETB_PRESENT 1u 2750 /* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 2751 #define CPUSS_MTB_SRAM_SIZE 4u 2752 /* CM7 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 2753 #define CPUSS_ETB_SRAM_SIZE 8u 2754 /* PTM interface present (0=No, 1=Yes) */ 2755 #define CPUSS_PTM_PRESENT 0u 2756 /* Width of the PTM interface in bits ([2,32]) */ 2757 #define CPUSS_PTM_WIDTH 1u 2758 /* Width of the TPIU interface in bits ([1,4]) */ 2759 #define CPUSS_TPIU_WIDTH 4u 2760 /* CoreSight Part Identification Number */ 2761 #define CPUSS_JEPID 52u 2762 /* CoreSight Part Identification Number */ 2763 #define CPUSS_JEPCONTINUATION 0u 2764 /* CoreSight Part Identification Number */ 2765 #define CPUSS_FAMILYID 259u 2766 /* ROM trim register width (for ARM 3, for Synopsys 5) */ 2767 #define CPUSS_ROM_TRIM_WIDTH 3u 2768 /* ROM trim register default (for both ARM and Synopsys 0x0000_0002) */ 2769 #define CPUSS_ROM_TRIM_DEFAULT 2u 2770 /* RAM trim register width (for ARM 8, for Synopsys 15) */ 2771 #define CPUSS_RAM_TRIM_WIDTH 8u 2772 /* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ 2773 #define CPUSS_RAM_TRIM_DEFAULT 98u 2774 /* Cryptography IP present or not ('0': no, '1': yes) */ 2775 #define CPUSS_CRYPTO_PRESENT 1u 2776 /* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 2777 #define CPUSS_SW_TR_PRESENT 1u 2778 /* DataWire 0 present or not ('0': no, '1': yes) */ 2779 #define CPUSS_DW0_PRESENT 1u 2780 /* Number of DataWire 0 channels ([1, 1024]) */ 2781 #define CPUSS_DW0_CH_NR 143u 2782 /* DataWire 1 present or not ('0': no, '1': yes) */ 2783 #define CPUSS_DW1_PRESENT 1u 2784 /* Number of DataWire 1 channels ([1, 1024]) */ 2785 #define CPUSS_DW1_CH_NR 65u 2786 /* DMA controller present or not ('0': no, '1': yes) */ 2787 #define CPUSS_DMAC_PRESENT 1u 2788 /* Number of DMA controller channels ([1, 8]) */ 2789 #define CPUSS_DMAC_CH_NR 8u 2790 /* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 2791 #define CPUSS_CH_SW_TR_PRESENT 1u 2792 /* See MMIO2 instantiation or not */ 2793 #define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u 2794 /* ETAS Calibration support pin out present (automotive only) */ 2795 #define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 1u 2796 /* TRACE_LVL>0 */ 2797 #define CPUSS_CHIP_TOP_TRACE_PRESENT 1u 2798 /* PTM_PRESENT ? PTM_WIDTH : 0 */ 2799 #define CPUSS_CHIP_TOP_PTM_PRESENT_WIDTH 0u 2800 /* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ 2801 #define CPUSS_CH_STRUCT_SW_TR_PRESENT 1u 2802 /* Number of DataWire controllers present (max 2) (same as DW.NR above) */ 2803 #define CPUSS_CPUSS_DW_DW_NR 2u 2804 /* Number of channels in each DataWire controller */ 2805 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 143u 2806 /* Width of a channel number in bits */ 2807 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 8u 2808 /* Number of channels in each DataWire controller */ 2809 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 65u 2810 /* Width of a channel number in bits */ 2811 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 7u 2812 /* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ 2813 #define CPUSS_CRYPTO_ECC_PRESENT 1u 2814 /* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ 2815 #define CPUSS_CRYPTO_ECC_ADDR_PRESENT 1u 2816 /* AES cipher support ('0': no, '1': yes) */ 2817 #define CPUSS_CRYPTO_AES 1u 2818 /* (Tripple) DES cipher support ('0': no, '1': yes) */ 2819 #define CPUSS_CRYPTO_DES 1u 2820 /* Chacha support ('0': no, '1': yes) */ 2821 #define CPUSS_CRYPTO_CHACHA 1u 2822 /* Pseudo random number generation support ('0': no, '1': yes) */ 2823 #define CPUSS_CRYPTO_PR 1u 2824 /* SHA1 hash support ('0': no, '1': yes) */ 2825 #define CPUSS_CRYPTO_SHA1 1u 2826 /* SHA2 hash support ('0': no, '1': yes) */ 2827 #define CPUSS_CRYPTO_SHA2 1u 2828 /* SHA3 hash support ('0': no, '1': yes) */ 2829 #define CPUSS_CRYPTO_SHA3 1u 2830 /* Cyclic Redundancy Check support ('0': no, '1': yes) */ 2831 #define CPUSS_CRYPTO_CRC 1u 2832 /* True random number generation support ('0': no, '1': yes) */ 2833 #define CPUSS_CRYPTO_TR 1u 2834 /* Vector unit support ('0': no, '1': yes) */ 2835 #define CPUSS_CRYPTO_VU 1u 2836 /* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ 2837 #define CPUSS_CRYPTO_GCM 1u 2838 /* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, 2839 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 2840 kB and 16 kB memory buffer) */ 2841 #define CPUSS_CRYPTO_BUFF_SIZE 2048u 2842 /* Number of DMA controller channels ([1, 8]) */ 2843 #define CPUSS_DMAC_CH_NR 8u 2844 /* Number of DataWire controllers present (max 2) */ 2845 #define CPUSS_DW_NR 2u 2846 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 2847 #define CPUSS_DW_ECC_PRESENT 1u 2848 /* Number of fault structures. Legal range [1, 4] */ 2849 #define CPUSS_FAULT_FAULT_NR 4u 2850 /* Number of Flash BIST_DATA registers */ 2851 #define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 8u 2852 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ 2853 #define CPUSS_FLASHC_PA_SIZE 128u 2854 /* SONOS Flash is used or not ('0': no, '1': yes) */ 2855 #define CPUSS_FLASHC_FLASHC_IS_SONOS 0u 2856 /* eCT Flash is used or not ('0': no, '1': yes) */ 2857 #define CPUSS_FLASHC_FLASHC_IS_ECT 1u 2858 /* Sequential Work Flash read feature for the FLASHC AXI port present or not ('0': 2859 no, '1': yes) */ 2860 #define CPUSS_FLASHC_FLASHC_WORK_SEQ_PRESENT 1u 2861 /* CM7_1 CPU present or not ('0': no, '1': yes) */ 2862 #define CPUSS_FLASHC_CM7_1_PRESENT 1u 2863 /* External AHB-Lite master0 Present */ 2864 #define CPUSS_FLASHC_SLOW0_MS_PRESENT 1u 2865 /* External AHB-Lite master1 Present */ 2866 #define CPUSS_FLASHC_SLOW1_MS_PRESENT 0u 2867 /* Number of IPC structures. Legal range [1, 16] */ 2868 #define CPUSS_IPC_IPC_NR 8u 2869 /* Number of IPC interrupt structures. Legal range [1, 16] */ 2870 #define CPUSS_IPC_IPC_IRQ_NR 8u 2871 /* Master 0 protect contexts minus one */ 2872 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u 2873 /* Master 1 protect contexts minus one */ 2874 #define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u 2875 /* Master 2 protect contexts minus one */ 2876 #define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u 2877 /* Master 3 protect contexts minus one */ 2878 #define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u 2879 /* Master 4 protect contexts minus one */ 2880 #define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u 2881 /* Master 5 protect contexts minus one */ 2882 #define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u 2883 /* Master 6 protect contexts minus one */ 2884 #define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u 2885 /* Master 7 protect contexts minus one */ 2886 #define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u 2887 /* Master 8 protect contexts minus one */ 2888 #define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u 2889 /* Master 9 protect contexts minus one */ 2890 #define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 7u 2891 /* Master 10 protect contexts minus one */ 2892 #define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 7u 2893 /* Master 11 protect contexts minus one */ 2894 #define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u 2895 /* Master 12 protect contexts minus one */ 2896 #define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u 2897 /* Master 13 protect contexts minus one */ 2898 #define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 7u 2899 /* Master 14 protect contexts minus one */ 2900 #define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u 2901 /* Master 15 protect contexts minus one */ 2902 #define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u 2903 /* Number of SMPU protection structures */ 2904 #define CPUSS_PROT_SMPU_STRUCT_NR 16u 2905 /* Number of protection contexts supported minus 1. Legal range [1,16] */ 2906 #define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u 2907 /* Number of HFCLK roots present. Must be > 0. Must be same as set for SRSS */ 2908 #define DFT_NUM_HFROOT 8u 2909 /* Width of clk_occ_fast output bus (number of external OCCs) */ 2910 #define DFT_EXT_OCC 2u 2911 /* Number of MBIST controllers with corresponding mbist(pg)_done and mbist(pg)_go 2912 signals. Value defined by CIC during Pass 1 */ 2913 #define DFT_MBIST_C_NUM 11u 2914 /* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ 2915 #define EFUSE_EFUSE_NR 4u 2916 /* TX Packet Buffer Size (jumbo frame size is 1.5KB): 00: 16KB to support four 2917 queues with capacity for two jumbo frames; 01: 8KB to support two queues with 2918 capacity for two jumbo frames or four queues with capacity for one jumbo 2919 frame; 10: 4KB to support one queue with capacity for two jumbo frames or two 2920 queues with capacity for one jumbo frame; 11: 2KB to support one queue with 2921 capacity for one jumbo frame; */ 2922 #define ETH0_TX_PACKET_BUFFER_SIZE 1u 2923 /* RX Packet Buffer Size (jumbo frame size is 1.5KB): 00: 4KB to support capacity 2924 for two jumbo frames; 01: 2KB to support capacity for one jumbo frames; */ 2925 #define ETH0_RX_PACKET_BUFFER_SIZE 0u 2926 /* Selects the clock source to use for the tsu_clk. A value of 0=Internal PCLK, , 2927 1=clk_hf */ 2928 #define ETH0_TSU_CLK_SOURCE 1u 2929 /* This parameter is used to specify if mxeth should contain a clock divider. The 2930 clock divider is useful for chips where multiple mxeth are instantiated as it 2931 allows a single source PLL to be used 0=No Divider, ref_clk_int_in is used as 2932 is 1=Divider instantiated, ref_clk_int_in should be 125MHz */ 2933 #define ETH0_SRC_CLOCK_DIVIDER 1u 2934 /* Set to 1 if IP will instantiate spares (0=None, 1=Max, 2=Min) */ 2935 #define ETH0_SPARE_EN 1u 2936 /* Number of Priority Queues. */ 2937 #define ETH0_ETH_NPQ 3u 2938 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2939 #define ETH0_MASTER_WIDTH 8u 2940 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 2941 #define ETH0_PLATFORM_VARIANT 2u 2942 /* RAM vendor (0=CYP, 1=SNPS, 2=ARM) */ 2943 #define ETH0_RAM_VEND 2u 2944 /* Width of external AXI master ID signals. Legal range [3,8] */ 2945 #define ETH0_AXIM_ID_WIDTH 3u 2946 /* TX Packet Buffer Size (jumbo frame size is 1.5KB): 00: 16KB to support four 2947 queues with capacity for two jumbo frames; 01: 8KB to support two queues with 2948 capacity for two jumbo frames or four queues with capacity for one jumbo 2949 frame; 10: 4KB to support one queue with capacity for two jumbo frames or two 2950 queues with capacity for one jumbo frame; 11: 2KB to support one queue with 2951 capacity for one jumbo frame; */ 2952 #define ETH1_TX_PACKET_BUFFER_SIZE 1u 2953 /* RX Packet Buffer Size (jumbo frame size is 1.5KB): 00: 4KB to support capacity 2954 for two jumbo frames; 01: 2KB to support capacity for one jumbo frames; */ 2955 #define ETH1_RX_PACKET_BUFFER_SIZE 0u 2956 /* Selects the clock source to use for the tsu_clk. A value of 0=Internal PCLK, , 2957 1=clk_hf */ 2958 #define ETH1_TSU_CLK_SOURCE 1u 2959 /* This parameter is used to specify if mxeth should contain a clock divider. The 2960 clock divider is useful for chips where multiple mxeth are instantiated as it 2961 allows a single source PLL to be used 0=No Divider, ref_clk_int_in is used as 2962 is 1=Divider instantiated, ref_clk_int_in should be 125MHz */ 2963 #define ETH1_SRC_CLOCK_DIVIDER 1u 2964 /* Set to 1 if IP will instantiate spares (0=None, 1=Max, 2=Min) */ 2965 #define ETH1_SPARE_EN 1u 2966 /* Number of Priority Queues. */ 2967 #define ETH1_ETH_NPQ 3u 2968 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2969 #define ETH1_MASTER_WIDTH 8u 2970 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 2971 #define ETH1_PLATFORM_VARIANT 2u 2972 /* RAM vendor (0=CYP, 1=SNPS, 2=ARM) */ 2973 #define ETH1_RAM_VEND 2u 2974 /* Width of external AXI master ID signals. Legal range [3,8] */ 2975 #define ETH1_AXIM_ID_WIDTH 3u 2976 /* Number of comparator structures ([1, 32]) */ 2977 #define EVTGEN_COMP_STRUCT_NR 16u 2978 /* Spare Enable (0=no spare, 1=max, 2=min) */ 2979 #define FLEXRAY_SPARE_EN 1u 2980 /* Number of GPIO ports in range 0..31 */ 2981 #define IOSS_GPIO_GPIO_PORT_NR_0_31 32u 2982 /* Number of GPIO ports in range 32..63 */ 2983 #define IOSS_GPIO_GPIO_PORT_NR_32_63 3u 2984 /* Number of GPIO ports in range 64..95 */ 2985 #define IOSS_GPIO_GPIO_PORT_NR_64_95 0u 2986 /* Number of GPIO ports in range 96..127 */ 2987 #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u 2988 /* Number of GPIO ports in device */ 2989 #define IOSS_GPIO_GPIO_PORT_NR 35u 2990 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2991 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u 2992 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2993 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u 2994 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2995 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 1u 2996 /* Indicates that pin #0 exists for this port with slew control feature */ 2997 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 1u 2998 /* Indicates that pin #1 exists for this port with slew control feature */ 2999 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 1u 3000 /* Indicates that pin #2 exists for this port with slew control feature */ 3001 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 1u 3002 /* Indicates that pin #3 exists for this port with slew control feature */ 3003 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 1u 3004 /* Indicates that pin #4 exists for this port with slew control feature */ 3005 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 0u 3006 /* Indicates that pin #5 exists for this port with slew control feature */ 3007 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 0u 3008 /* Indicates that pin #6 exists for this port with slew control feature */ 3009 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u 3010 /* Indicates that pin #7 exists for this port with slew control feature */ 3011 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u 3012 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3013 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u 3014 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3015 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u 3016 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3017 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 1u 3018 /* Indicates that pin #0 exists for this port with slew control feature */ 3019 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 0u 3020 /* Indicates that pin #1 exists for this port with slew control feature */ 3021 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 0u 3022 /* Indicates that pin #2 exists for this port with slew control feature */ 3023 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 0u 3024 /* Indicates that pin #3 exists for this port with slew control feature */ 3025 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u 3026 /* Indicates that pin #4 exists for this port with slew control feature */ 3027 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u 3028 /* Indicates that pin #5 exists for this port with slew control feature */ 3029 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u 3030 /* Indicates that pin #6 exists for this port with slew control feature */ 3031 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u 3032 /* Indicates that pin #7 exists for this port with slew control feature */ 3033 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u 3034 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3035 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u 3036 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3037 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u 3038 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3039 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 1u 3040 /* Indicates that pin #0 exists for this port with slew control feature */ 3041 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 0u 3042 /* Indicates that pin #1 exists for this port with slew control feature */ 3043 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 0u 3044 /* Indicates that pin #2 exists for this port with slew control feature */ 3045 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 0u 3046 /* Indicates that pin #3 exists for this port with slew control feature */ 3047 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 0u 3048 /* Indicates that pin #4 exists for this port with slew control feature */ 3049 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 0u 3050 /* Indicates that pin #5 exists for this port with slew control feature */ 3051 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 0u 3052 /* Indicates that pin #6 exists for this port with slew control feature */ 3053 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 0u 3054 /* Indicates that pin #7 exists for this port with slew control feature */ 3055 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 0u 3056 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3057 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u 3058 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3059 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u 3060 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3061 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 1u 3062 /* Indicates that pin #0 exists for this port with slew control feature */ 3063 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 0u 3064 /* Indicates that pin #1 exists for this port with slew control feature */ 3065 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 0u 3066 /* Indicates that pin #2 exists for this port with slew control feature */ 3067 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u 3068 /* Indicates that pin #3 exists for this port with slew control feature */ 3069 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u 3070 /* Indicates that pin #4 exists for this port with slew control feature */ 3071 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u 3072 /* Indicates that pin #5 exists for this port with slew control feature */ 3073 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u 3074 /* Indicates that pin #6 exists for this port with slew control feature */ 3075 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u 3076 /* Indicates that pin #7 exists for this port with slew control feature */ 3077 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u 3078 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3079 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 1u 3080 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3081 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u 3082 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3083 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 1u 3084 /* Indicates that pin #0 exists for this port with slew control feature */ 3085 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 0u 3086 /* Indicates that pin #1 exists for this port with slew control feature */ 3087 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 0u 3088 /* Indicates that pin #2 exists for this port with slew control feature */ 3089 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u 3090 /* Indicates that pin #3 exists for this port with slew control feature */ 3091 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u 3092 /* Indicates that pin #4 exists for this port with slew control feature */ 3093 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u 3094 /* Indicates that pin #5 exists for this port with slew control feature */ 3095 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u 3096 /* Indicates that pin #6 exists for this port with slew control feature */ 3097 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u 3098 /* Indicates that pin #7 exists for this port with slew control feature */ 3099 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u 3100 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3101 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u 3102 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3103 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u 3104 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3105 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 1u 3106 /* Indicates that pin #0 exists for this port with slew control feature */ 3107 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 0u 3108 /* Indicates that pin #1 exists for this port with slew control feature */ 3109 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 0u 3110 /* Indicates that pin #2 exists for this port with slew control feature */ 3111 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 0u 3112 /* Indicates that pin #3 exists for this port with slew control feature */ 3113 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u 3114 /* Indicates that pin #4 exists for this port with slew control feature */ 3115 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u 3116 /* Indicates that pin #5 exists for this port with slew control feature */ 3117 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u 3118 /* Indicates that pin #6 exists for this port with slew control feature */ 3119 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 0u 3120 /* Indicates that pin #7 exists for this port with slew control feature */ 3121 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 0u 3122 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3123 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u 3124 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3125 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u 3126 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3127 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 1u 3128 /* Indicates that pin #0 exists for this port with slew control feature */ 3129 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 0u 3130 /* Indicates that pin #1 exists for this port with slew control feature */ 3131 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 0u 3132 /* Indicates that pin #2 exists for this port with slew control feature */ 3133 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 0u 3134 /* Indicates that pin #3 exists for this port with slew control feature */ 3135 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 0u 3136 /* Indicates that pin #4 exists for this port with slew control feature */ 3137 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 0u 3138 /* Indicates that pin #5 exists for this port with slew control feature */ 3139 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 0u 3140 /* Indicates that pin #6 exists for this port with slew control feature */ 3141 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 0u 3142 /* Indicates that pin #7 exists for this port with slew control feature */ 3143 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 0u 3144 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3145 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u 3146 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3147 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u 3148 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3149 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 1u 3150 /* Indicates that pin #0 exists for this port with slew control feature */ 3151 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 0u 3152 /* Indicates that pin #1 exists for this port with slew control feature */ 3153 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 0u 3154 /* Indicates that pin #2 exists for this port with slew control feature */ 3155 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 0u 3156 /* Indicates that pin #3 exists for this port with slew control feature */ 3157 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 0u 3158 /* Indicates that pin #4 exists for this port with slew control feature */ 3159 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 0u 3160 /* Indicates that pin #5 exists for this port with slew control feature */ 3161 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 0u 3162 /* Indicates that pin #6 exists for this port with slew control feature */ 3163 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 0u 3164 /* Indicates that pin #7 exists for this port with slew control feature */ 3165 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 0u 3166 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3167 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u 3168 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3169 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u 3170 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3171 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 1u 3172 /* Indicates that pin #0 exists for this port with slew control feature */ 3173 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 0u 3174 /* Indicates that pin #1 exists for this port with slew control feature */ 3175 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 0u 3176 /* Indicates that pin #2 exists for this port with slew control feature */ 3177 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 0u 3178 /* Indicates that pin #3 exists for this port with slew control feature */ 3179 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 0u 3180 /* Indicates that pin #4 exists for this port with slew control feature */ 3181 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 0u 3182 /* Indicates that pin #5 exists for this port with slew control feature */ 3183 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 0u 3184 /* Indicates that pin #6 exists for this port with slew control feature */ 3185 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 0u 3186 /* Indicates that pin #7 exists for this port with slew control feature */ 3187 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 0u 3188 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3189 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u 3190 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3191 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u 3192 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3193 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 1u 3194 /* Indicates that pin #0 exists for this port with slew control feature */ 3195 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 0u 3196 /* Indicates that pin #1 exists for this port with slew control feature */ 3197 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 0u 3198 /* Indicates that pin #2 exists for this port with slew control feature */ 3199 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 0u 3200 /* Indicates that pin #3 exists for this port with slew control feature */ 3201 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 0u 3202 /* Indicates that pin #4 exists for this port with slew control feature */ 3203 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 0u 3204 /* Indicates that pin #5 exists for this port with slew control feature */ 3205 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 0u 3206 /* Indicates that pin #6 exists for this port with slew control feature */ 3207 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 0u 3208 /* Indicates that pin #7 exists for this port with slew control feature */ 3209 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 0u 3210 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3211 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u 3212 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3213 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u 3214 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3215 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 1u 3216 /* Indicates that pin #0 exists for this port with slew control feature */ 3217 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 0u 3218 /* Indicates that pin #1 exists for this port with slew control feature */ 3219 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 0u 3220 /* Indicates that pin #2 exists for this port with slew control feature */ 3221 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 0u 3222 /* Indicates that pin #3 exists for this port with slew control feature */ 3223 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 0u 3224 /* Indicates that pin #4 exists for this port with slew control feature */ 3225 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 0u 3226 /* Indicates that pin #5 exists for this port with slew control feature */ 3227 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 0u 3228 /* Indicates that pin #6 exists for this port with slew control feature */ 3229 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 0u 3230 /* Indicates that pin #7 exists for this port with slew control feature */ 3231 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 0u 3232 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3233 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u 3234 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3235 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u 3236 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3237 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 1u 3238 /* Indicates that pin #0 exists for this port with slew control feature */ 3239 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 0u 3240 /* Indicates that pin #1 exists for this port with slew control feature */ 3241 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 0u 3242 /* Indicates that pin #2 exists for this port with slew control feature */ 3243 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 0u 3244 /* Indicates that pin #3 exists for this port with slew control feature */ 3245 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 0u 3246 /* Indicates that pin #4 exists for this port with slew control feature */ 3247 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 0u 3248 /* Indicates that pin #5 exists for this port with slew control feature */ 3249 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 0u 3250 /* Indicates that pin #6 exists for this port with slew control feature */ 3251 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 0u 3252 /* Indicates that pin #7 exists for this port with slew control feature */ 3253 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 0u 3254 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3255 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 1u 3256 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3257 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u 3258 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3259 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 1u 3260 /* Indicates that pin #0 exists for this port with slew control feature */ 3261 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 0u 3262 /* Indicates that pin #1 exists for this port with slew control feature */ 3263 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 0u 3264 /* Indicates that pin #2 exists for this port with slew control feature */ 3265 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 0u 3266 /* Indicates that pin #3 exists for this port with slew control feature */ 3267 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 0u 3268 /* Indicates that pin #4 exists for this port with slew control feature */ 3269 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 0u 3270 /* Indicates that pin #5 exists for this port with slew control feature */ 3271 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 0u 3272 /* Indicates that pin #6 exists for this port with slew control feature */ 3273 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 0u 3274 /* Indicates that pin #7 exists for this port with slew control feature */ 3275 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 0u 3276 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3277 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 1u 3278 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3279 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u 3280 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3281 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 1u 3282 /* Indicates that pin #0 exists for this port with slew control feature */ 3283 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 0u 3284 /* Indicates that pin #1 exists for this port with slew control feature */ 3285 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 0u 3286 /* Indicates that pin #2 exists for this port with slew control feature */ 3287 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 0u 3288 /* Indicates that pin #3 exists for this port with slew control feature */ 3289 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 0u 3290 /* Indicates that pin #4 exists for this port with slew control feature */ 3291 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 0u 3292 /* Indicates that pin #5 exists for this port with slew control feature */ 3293 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 0u 3294 /* Indicates that pin #6 exists for this port with slew control feature */ 3295 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 0u 3296 /* Indicates that pin #7 exists for this port with slew control feature */ 3297 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 0u 3298 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3299 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_GPIO 1u 3300 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3301 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SIO 0u 3302 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3303 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_AUTOLVL 1u 3304 /* Indicates that pin #0 exists for this port with slew control feature */ 3305 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO0 0u 3306 /* Indicates that pin #1 exists for this port with slew control feature */ 3307 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO1 0u 3308 /* Indicates that pin #2 exists for this port with slew control feature */ 3309 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO2 0u 3310 /* Indicates that pin #3 exists for this port with slew control feature */ 3311 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO3 0u 3312 /* Indicates that pin #4 exists for this port with slew control feature */ 3313 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO4 0u 3314 /* Indicates that pin #5 exists for this port with slew control feature */ 3315 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO5 0u 3316 /* Indicates that pin #6 exists for this port with slew control feature */ 3317 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u 3318 /* Indicates that pin #7 exists for this port with slew control feature */ 3319 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u 3320 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3321 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_GPIO 1u 3322 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3323 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SIO 0u 3324 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3325 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_AUTOLVL 1u 3326 /* Indicates that pin #0 exists for this port with slew control feature */ 3327 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO0 0u 3328 /* Indicates that pin #1 exists for this port with slew control feature */ 3329 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO1 0u 3330 /* Indicates that pin #2 exists for this port with slew control feature */ 3331 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO2 0u 3332 /* Indicates that pin #3 exists for this port with slew control feature */ 3333 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO3 0u 3334 /* Indicates that pin #4 exists for this port with slew control feature */ 3335 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO4 0u 3336 /* Indicates that pin #5 exists for this port with slew control feature */ 3337 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO5 0u 3338 /* Indicates that pin #6 exists for this port with slew control feature */ 3339 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO6 0u 3340 /* Indicates that pin #7 exists for this port with slew control feature */ 3341 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO7 0u 3342 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3343 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_GPIO 1u 3344 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3345 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SIO 0u 3346 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3347 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_AUTOLVL 1u 3348 /* Indicates that pin #0 exists for this port with slew control feature */ 3349 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO0 0u 3350 /* Indicates that pin #1 exists for this port with slew control feature */ 3351 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO1 0u 3352 /* Indicates that pin #2 exists for this port with slew control feature */ 3353 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO2 0u 3354 /* Indicates that pin #3 exists for this port with slew control feature */ 3355 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO3 0u 3356 /* Indicates that pin #4 exists for this port with slew control feature */ 3357 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO4 0u 3358 /* Indicates that pin #5 exists for this port with slew control feature */ 3359 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO5 0u 3360 /* Indicates that pin #6 exists for this port with slew control feature */ 3361 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO6 0u 3362 /* Indicates that pin #7 exists for this port with slew control feature */ 3363 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO7 0u 3364 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3365 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_GPIO 1u 3366 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3367 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SIO 0u 3368 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3369 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_AUTOLVL 1u 3370 /* Indicates that pin #0 exists for this port with slew control feature */ 3371 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO0 0u 3372 /* Indicates that pin #1 exists for this port with slew control feature */ 3373 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO1 0u 3374 /* Indicates that pin #2 exists for this port with slew control feature */ 3375 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO2 0u 3376 /* Indicates that pin #3 exists for this port with slew control feature */ 3377 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO3 0u 3378 /* Indicates that pin #4 exists for this port with slew control feature */ 3379 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO4 0u 3380 /* Indicates that pin #5 exists for this port with slew control feature */ 3381 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO5 0u 3382 /* Indicates that pin #6 exists for this port with slew control feature */ 3383 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO6 0u 3384 /* Indicates that pin #7 exists for this port with slew control feature */ 3385 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO7 0u 3386 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3387 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_GPIO 1u 3388 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3389 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SIO 0u 3390 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3391 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_AUTOLVL 1u 3392 /* Indicates that pin #0 exists for this port with slew control feature */ 3393 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO0 0u 3394 /* Indicates that pin #1 exists for this port with slew control feature */ 3395 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO1 0u 3396 /* Indicates that pin #2 exists for this port with slew control feature */ 3397 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO2 0u 3398 /* Indicates that pin #3 exists for this port with slew control feature */ 3399 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO3 0u 3400 /* Indicates that pin #4 exists for this port with slew control feature */ 3401 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO4 0u 3402 /* Indicates that pin #5 exists for this port with slew control feature */ 3403 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO5 0u 3404 /* Indicates that pin #6 exists for this port with slew control feature */ 3405 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO6 0u 3406 /* Indicates that pin #7 exists for this port with slew control feature */ 3407 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO7 0u 3408 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3409 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_GPIO 1u 3410 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3411 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SIO 0u 3412 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3413 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_AUTOLVL 1u 3414 /* Indicates that pin #0 exists for this port with slew control feature */ 3415 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO0 0u 3416 /* Indicates that pin #1 exists for this port with slew control feature */ 3417 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO1 0u 3418 /* Indicates that pin #2 exists for this port with slew control feature */ 3419 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO2 0u 3420 /* Indicates that pin #3 exists for this port with slew control feature */ 3421 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO3 0u 3422 /* Indicates that pin #4 exists for this port with slew control feature */ 3423 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO4 0u 3424 /* Indicates that pin #5 exists for this port with slew control feature */ 3425 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO5 0u 3426 /* Indicates that pin #6 exists for this port with slew control feature */ 3427 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO6 0u 3428 /* Indicates that pin #7 exists for this port with slew control feature */ 3429 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO7 0u 3430 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3431 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_GPIO 1u 3432 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3433 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SIO 0u 3434 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3435 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_AUTOLVL 1u 3436 /* Indicates that pin #0 exists for this port with slew control feature */ 3437 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO0 0u 3438 /* Indicates that pin #1 exists for this port with slew control feature */ 3439 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO1 0u 3440 /* Indicates that pin #2 exists for this port with slew control feature */ 3441 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO2 0u 3442 /* Indicates that pin #3 exists for this port with slew control feature */ 3443 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO3 0u 3444 /* Indicates that pin #4 exists for this port with slew control feature */ 3445 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO4 0u 3446 /* Indicates that pin #5 exists for this port with slew control feature */ 3447 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO5 0u 3448 /* Indicates that pin #6 exists for this port with slew control feature */ 3449 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO6 0u 3450 /* Indicates that pin #7 exists for this port with slew control feature */ 3451 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO7 0u 3452 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3453 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_GPIO 1u 3454 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3455 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SIO 0u 3456 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3457 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_AUTOLVL 1u 3458 /* Indicates that pin #0 exists for this port with slew control feature */ 3459 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO0 0u 3460 /* Indicates that pin #1 exists for this port with slew control feature */ 3461 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO1 0u 3462 /* Indicates that pin #2 exists for this port with slew control feature */ 3463 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO2 0u 3464 /* Indicates that pin #3 exists for this port with slew control feature */ 3465 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO3 0u 3466 /* Indicates that pin #4 exists for this port with slew control feature */ 3467 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO4 0u 3468 /* Indicates that pin #5 exists for this port with slew control feature */ 3469 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO5 0u 3470 /* Indicates that pin #6 exists for this port with slew control feature */ 3471 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO6 0u 3472 /* Indicates that pin #7 exists for this port with slew control feature */ 3473 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO7 0u 3474 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3475 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_GPIO 1u 3476 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3477 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SIO 0u 3478 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3479 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_AUTOLVL 1u 3480 /* Indicates that pin #0 exists for this port with slew control feature */ 3481 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO0 0u 3482 /* Indicates that pin #1 exists for this port with slew control feature */ 3483 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO1 0u 3484 /* Indicates that pin #2 exists for this port with slew control feature */ 3485 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO2 0u 3486 /* Indicates that pin #3 exists for this port with slew control feature */ 3487 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO3 0u 3488 /* Indicates that pin #4 exists for this port with slew control feature */ 3489 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO4 0u 3490 /* Indicates that pin #5 exists for this port with slew control feature */ 3491 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO5 0u 3492 /* Indicates that pin #6 exists for this port with slew control feature */ 3493 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO6 0u 3494 /* Indicates that pin #7 exists for this port with slew control feature */ 3495 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO7 0u 3496 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3497 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_GPIO 1u 3498 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3499 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SIO 0u 3500 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3501 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_AUTOLVL 1u 3502 /* Indicates that pin #0 exists for this port with slew control feature */ 3503 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO0 0u 3504 /* Indicates that pin #1 exists for this port with slew control feature */ 3505 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO1 0u 3506 /* Indicates that pin #2 exists for this port with slew control feature */ 3507 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO2 0u 3508 /* Indicates that pin #3 exists for this port with slew control feature */ 3509 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO3 0u 3510 /* Indicates that pin #4 exists for this port with slew control feature */ 3511 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO4 0u 3512 /* Indicates that pin #5 exists for this port with slew control feature */ 3513 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO5 0u 3514 /* Indicates that pin #6 exists for this port with slew control feature */ 3515 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO6 0u 3516 /* Indicates that pin #7 exists for this port with slew control feature */ 3517 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO7 0u 3518 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3519 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_GPIO 1u 3520 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3521 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SIO 0u 3522 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3523 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_AUTOLVL 1u 3524 /* Indicates that pin #0 exists for this port with slew control feature */ 3525 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO0 0u 3526 /* Indicates that pin #1 exists for this port with slew control feature */ 3527 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO1 0u 3528 /* Indicates that pin #2 exists for this port with slew control feature */ 3529 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO2 0u 3530 /* Indicates that pin #3 exists for this port with slew control feature */ 3531 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO3 0u 3532 /* Indicates that pin #4 exists for this port with slew control feature */ 3533 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO4 0u 3534 /* Indicates that pin #5 exists for this port with slew control feature */ 3535 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO5 0u 3536 /* Indicates that pin #6 exists for this port with slew control feature */ 3537 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO6 0u 3538 /* Indicates that pin #7 exists for this port with slew control feature */ 3539 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO7 0u 3540 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3541 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_GPIO 1u 3542 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3543 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SIO 0u 3544 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3545 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_AUTOLVL 1u 3546 /* Indicates that pin #0 exists for this port with slew control feature */ 3547 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO0 0u 3548 /* Indicates that pin #1 exists for this port with slew control feature */ 3549 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO1 0u 3550 /* Indicates that pin #2 exists for this port with slew control feature */ 3551 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO2 0u 3552 /* Indicates that pin #3 exists for this port with slew control feature */ 3553 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO3 0u 3554 /* Indicates that pin #4 exists for this port with slew control feature */ 3555 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO4 0u 3556 /* Indicates that pin #5 exists for this port with slew control feature */ 3557 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO5 0u 3558 /* Indicates that pin #6 exists for this port with slew control feature */ 3559 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO6 0u 3560 /* Indicates that pin #7 exists for this port with slew control feature */ 3561 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO7 0u 3562 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3563 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_GPIO 1u 3564 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3565 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SIO 0u 3566 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3567 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_AUTOLVL 1u 3568 /* Indicates that pin #0 exists for this port with slew control feature */ 3569 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO0 0u 3570 /* Indicates that pin #1 exists for this port with slew control feature */ 3571 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO1 0u 3572 /* Indicates that pin #2 exists for this port with slew control feature */ 3573 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO2 0u 3574 /* Indicates that pin #3 exists for this port with slew control feature */ 3575 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO3 0u 3576 /* Indicates that pin #4 exists for this port with slew control feature */ 3577 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO4 0u 3578 /* Indicates that pin #5 exists for this port with slew control feature */ 3579 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO5 0u 3580 /* Indicates that pin #6 exists for this port with slew control feature */ 3581 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO6 0u 3582 /* Indicates that pin #7 exists for this port with slew control feature */ 3583 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO7 0u 3584 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3585 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_GPIO 1u 3586 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3587 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SIO 0u 3588 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3589 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_AUTOLVL 1u 3590 /* Indicates that pin #0 exists for this port with slew control feature */ 3591 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO0 0u 3592 /* Indicates that pin #1 exists for this port with slew control feature */ 3593 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO1 0u 3594 /* Indicates that pin #2 exists for this port with slew control feature */ 3595 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO2 0u 3596 /* Indicates that pin #3 exists for this port with slew control feature */ 3597 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO3 0u 3598 /* Indicates that pin #4 exists for this port with slew control feature */ 3599 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO4 0u 3600 /* Indicates that pin #5 exists for this port with slew control feature */ 3601 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO5 0u 3602 /* Indicates that pin #6 exists for this port with slew control feature */ 3603 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO6 0u 3604 /* Indicates that pin #7 exists for this port with slew control feature */ 3605 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO7 0u 3606 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3607 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_GPIO 1u 3608 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3609 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SIO 0u 3610 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3611 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_AUTOLVL 1u 3612 /* Indicates that pin #0 exists for this port with slew control feature */ 3613 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO0 0u 3614 /* Indicates that pin #1 exists for this port with slew control feature */ 3615 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO1 0u 3616 /* Indicates that pin #2 exists for this port with slew control feature */ 3617 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO2 0u 3618 /* Indicates that pin #3 exists for this port with slew control feature */ 3619 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO3 0u 3620 /* Indicates that pin #4 exists for this port with slew control feature */ 3621 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO4 0u 3622 /* Indicates that pin #5 exists for this port with slew control feature */ 3623 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO5 0u 3624 /* Indicates that pin #6 exists for this port with slew control feature */ 3625 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO6 0u 3626 /* Indicates that pin #7 exists for this port with slew control feature */ 3627 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO7 0u 3628 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3629 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_GPIO 1u 3630 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3631 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SIO 0u 3632 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3633 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_AUTOLVL 1u 3634 /* Indicates that pin #0 exists for this port with slew control feature */ 3635 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO0 0u 3636 /* Indicates that pin #1 exists for this port with slew control feature */ 3637 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO1 0u 3638 /* Indicates that pin #2 exists for this port with slew control feature */ 3639 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO2 0u 3640 /* Indicates that pin #3 exists for this port with slew control feature */ 3641 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO3 0u 3642 /* Indicates that pin #4 exists for this port with slew control feature */ 3643 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO4 0u 3644 /* Indicates that pin #5 exists for this port with slew control feature */ 3645 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO5 0u 3646 /* Indicates that pin #6 exists for this port with slew control feature */ 3647 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO6 0u 3648 /* Indicates that pin #7 exists for this port with slew control feature */ 3649 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO7 0u 3650 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3651 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_GPIO 1u 3652 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3653 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SIO 0u 3654 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3655 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_AUTOLVL 1u 3656 /* Indicates that pin #0 exists for this port with slew control feature */ 3657 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO0 0u 3658 /* Indicates that pin #1 exists for this port with slew control feature */ 3659 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO1 0u 3660 /* Indicates that pin #2 exists for this port with slew control feature */ 3661 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO2 0u 3662 /* Indicates that pin #3 exists for this port with slew control feature */ 3663 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO3 0u 3664 /* Indicates that pin #4 exists for this port with slew control feature */ 3665 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO4 0u 3666 /* Indicates that pin #5 exists for this port with slew control feature */ 3667 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO5 0u 3668 /* Indicates that pin #6 exists for this port with slew control feature */ 3669 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO6 0u 3670 /* Indicates that pin #7 exists for this port with slew control feature */ 3671 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO7 0u 3672 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3673 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_GPIO 1u 3674 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3675 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SIO 0u 3676 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3677 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_AUTOLVL 1u 3678 /* Indicates that pin #0 exists for this port with slew control feature */ 3679 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO0 0u 3680 /* Indicates that pin #1 exists for this port with slew control feature */ 3681 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO1 0u 3682 /* Indicates that pin #2 exists for this port with slew control feature */ 3683 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO2 0u 3684 /* Indicates that pin #3 exists for this port with slew control feature */ 3685 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO3 0u 3686 /* Indicates that pin #4 exists for this port with slew control feature */ 3687 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO4 0u 3688 /* Indicates that pin #5 exists for this port with slew control feature */ 3689 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO5 0u 3690 /* Indicates that pin #6 exists for this port with slew control feature */ 3691 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO6 0u 3692 /* Indicates that pin #7 exists for this port with slew control feature */ 3693 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO7 0u 3694 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3695 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_GPIO 1u 3696 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3697 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SIO 0u 3698 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3699 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_AUTOLVL 1u 3700 /* Indicates that pin #0 exists for this port with slew control feature */ 3701 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO0 0u 3702 /* Indicates that pin #1 exists for this port with slew control feature */ 3703 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO1 0u 3704 /* Indicates that pin #2 exists for this port with slew control feature */ 3705 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO2 0u 3706 /* Indicates that pin #3 exists for this port with slew control feature */ 3707 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO3 0u 3708 /* Indicates that pin #4 exists for this port with slew control feature */ 3709 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO4 0u 3710 /* Indicates that pin #5 exists for this port with slew control feature */ 3711 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO5 0u 3712 /* Indicates that pin #6 exists for this port with slew control feature */ 3713 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO6 0u 3714 /* Indicates that pin #7 exists for this port with slew control feature */ 3715 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO7 0u 3716 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3717 #define IOSS_GPIO_GPIO_PORT_NR33_GPIO_PRT_GPIO 1u 3718 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3719 #define IOSS_GPIO_GPIO_PORT_NR33_GPIO_PRT_SIO 0u 3720 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3721 #define IOSS_GPIO_GPIO_PORT_NR33_GPIO_PRT_AUTOLVL 1u 3722 /* Indicates that pin #0 exists for this port with slew control feature */ 3723 #define IOSS_GPIO_GPIO_PORT_NR33_GPIO_PRT_SLOW_IO0 0u 3724 /* Indicates that pin #1 exists for this port with slew control feature */ 3725 #define IOSS_GPIO_GPIO_PORT_NR33_GPIO_PRT_SLOW_IO1 0u 3726 /* Indicates that pin #2 exists for this port with slew control feature */ 3727 #define IOSS_GPIO_GPIO_PORT_NR33_GPIO_PRT_SLOW_IO2 0u 3728 /* Indicates that pin #3 exists for this port with slew control feature */ 3729 #define IOSS_GPIO_GPIO_PORT_NR33_GPIO_PRT_SLOW_IO3 0u 3730 /* Indicates that pin #4 exists for this port with slew control feature */ 3731 #define IOSS_GPIO_GPIO_PORT_NR33_GPIO_PRT_SLOW_IO4 0u 3732 /* Indicates that pin #5 exists for this port with slew control feature */ 3733 #define IOSS_GPIO_GPIO_PORT_NR33_GPIO_PRT_SLOW_IO5 0u 3734 /* Indicates that pin #6 exists for this port with slew control feature */ 3735 #define IOSS_GPIO_GPIO_PORT_NR33_GPIO_PRT_SLOW_IO6 0u 3736 /* Indicates that pin #7 exists for this port with slew control feature */ 3737 #define IOSS_GPIO_GPIO_PORT_NR33_GPIO_PRT_SLOW_IO7 0u 3738 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3739 #define IOSS_GPIO_GPIO_PORT_NR34_GPIO_PRT_GPIO 1u 3740 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3741 #define IOSS_GPIO_GPIO_PORT_NR34_GPIO_PRT_SIO 0u 3742 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3743 #define IOSS_GPIO_GPIO_PORT_NR34_GPIO_PRT_AUTOLVL 1u 3744 /* Indicates that pin #0 exists for this port with slew control feature */ 3745 #define IOSS_GPIO_GPIO_PORT_NR34_GPIO_PRT_SLOW_IO0 0u 3746 /* Indicates that pin #1 exists for this port with slew control feature */ 3747 #define IOSS_GPIO_GPIO_PORT_NR34_GPIO_PRT_SLOW_IO1 0u 3748 /* Indicates that pin #2 exists for this port with slew control feature */ 3749 #define IOSS_GPIO_GPIO_PORT_NR34_GPIO_PRT_SLOW_IO2 0u 3750 /* Indicates that pin #3 exists for this port with slew control feature */ 3751 #define IOSS_GPIO_GPIO_PORT_NR34_GPIO_PRT_SLOW_IO3 0u 3752 /* Indicates that pin #4 exists for this port with slew control feature */ 3753 #define IOSS_GPIO_GPIO_PORT_NR34_GPIO_PRT_SLOW_IO4 0u 3754 /* Indicates that pin #5 exists for this port with slew control feature */ 3755 #define IOSS_GPIO_GPIO_PORT_NR34_GPIO_PRT_SLOW_IO5 0u 3756 /* Indicates that pin #6 exists for this port with slew control feature */ 3757 #define IOSS_GPIO_GPIO_PORT_NR34_GPIO_PRT_SLOW_IO6 0u 3758 /* Indicates that pin #7 exists for this port with slew control feature */ 3759 #define IOSS_GPIO_GPIO_PORT_NR34_GPIO_PRT_SLOW_IO7 0u 3760 /* Number of AMUX splitter cells */ 3761 #define IOSS_HSIOM_AMUX_SPLIT_NR 4u 3762 /* Number of HSIOM ports in device */ 3763 #define IOSS_HSIOM_HSIOM_PORT_NR 35u 3764 /* Number of PWR/GND MONITOR CELLs in the device */ 3765 #define IOSS_HSIOM_MONITOR_NR 26u 3766 /* Number of PWR/GND MONITOR CELLs in range 0..31 */ 3767 #define IOSS_HSIOM_MONITOR_NR_0_31 26u 3768 /* Number of PWR/GND MONITOR CELLs in range 32..63 */ 3769 #define IOSS_HSIOM_MONITOR_NR_32_63 0u 3770 /* Number of PWR/GND MONITOR CELLs in range 64..95 */ 3771 #define IOSS_HSIOM_MONITOR_NR_64_95 0u 3772 /* Number of PWR/GND MONITOR CELLs in range 96..127 */ 3773 #define IOSS_HSIOM_MONITOR_NR_96_127 0u 3774 /* Indicates the presence of alternate JTAG interface */ 3775 #define IOSS_HSIOM_ALTJTAG_PRESENT 1u 3776 /* Mask of SMARTIO instances presence */ 3777 #define IOSS_SMARTIO_SMARTIO_MASK 0x0002F000u 3778 /* Number of LIN channels ([2, 32]). For test functionality (two channels are 3779 connected), the minimal number of LIN channels is 2. */ 3780 #define LIN_CH_NR 20u 3781 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3782 #define LIN_MASTER_WIDTH 8u 3783 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 3784 #define LIN_CHIP_TOP_PLATFORM_VARIANT 2u 3785 /* Number of SAR blocks */ 3786 #define PASS_SAR_ADC_NR 3u 3787 /* Number of ADC slices. Each slice will contain one SARMUX block and optionally a 3788 SAR and associated sequencer logic. */ 3789 #define PASS_SAR_SLICE_NR 3u 3790 /* Number of SAR sequencer channels (per SAR) */ 3791 #define PASS_SAR_SLICE_NR0_SAR_SAR_CHAN_NR 32u 3792 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 */ 3793 #define PASS_SAR_SLICE_NR0_SAR_SAR_MUX_IN 32u 3794 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 3795 that lower numbered slices contain the ADCs that are present. */ 3796 #define PASS_SAR_SLICE_NR0_SAR_SAR_ADC_PRESENT 1u 3797 /* Averaging logic present in SAR */ 3798 #define PASS_SAR_SLICE_NR0_SAR_SAR_AVERAGE 1u 3799 /* Range detect logic present in SAR */ 3800 #define PASS_SAR_SLICE_NR0_SAR_SAR_RANGEDET 1u 3801 /* Pulse detect logic present in SAR */ 3802 #define PASS_SAR_SLICE_NR0_SAR_SAR_PULSEDET 1u 3803 /* Number of SAR sequencer channels (per SAR) */ 3804 #define PASS_SAR_SLICE_NR1_SAR_SAR_CHAN_NR 32u 3805 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 */ 3806 #define PASS_SAR_SLICE_NR1_SAR_SAR_MUX_IN 32u 3807 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 3808 that lower numbered slices contain the ADCs that are present. */ 3809 #define PASS_SAR_SLICE_NR1_SAR_SAR_ADC_PRESENT 1u 3810 /* Averaging logic present in SAR */ 3811 #define PASS_SAR_SLICE_NR1_SAR_SAR_AVERAGE 1u 3812 /* Range detect logic present in SAR */ 3813 #define PASS_SAR_SLICE_NR1_SAR_SAR_RANGEDET 1u 3814 /* Pulse detect logic present in SAR */ 3815 #define PASS_SAR_SLICE_NR1_SAR_SAR_PULSEDET 1u 3816 /* Number of SAR sequencer channels (per SAR) */ 3817 #define PASS_SAR_SLICE_NR2_SAR_SAR_CHAN_NR 32u 3818 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 */ 3819 #define PASS_SAR_SLICE_NR2_SAR_SAR_MUX_IN 32u 3820 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 3821 that lower numbered slices contain the ADCs that are present. */ 3822 #define PASS_SAR_SLICE_NR2_SAR_SAR_ADC_PRESENT 1u 3823 /* Averaging logic present in SAR */ 3824 #define PASS_SAR_SLICE_NR2_SAR_SAR_AVERAGE 1u 3825 /* Range detect logic present in SAR */ 3826 #define PASS_SAR_SLICE_NR2_SAR_SAR_RANGEDET 1u 3827 /* Pulse detect logic present in SAR */ 3828 #define PASS_SAR_SLICE_NR2_SAR_SAR_PULSEDET 1u 3829 /* Parameter that is 1 for ADC0 only if ADC1 or, if SAR_SLICE_NR > SAR_ADC_NR */ 3830 #define PASS_SAR_SAR_ADC0 1u 3831 /* The number of protection contexts ([2, 16]). */ 3832 #define PERI_PC_NR 8u 3833 /* Master interface presence mask (5 bits) */ 3834 #define PERI_MS_PRESENT 31u 3835 /* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ 3836 #define PERI_ECC_PRESENT 1u 3837 /* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ 3838 #define PERI_ECC_ADDR_PRESENT 1u 3839 /* Peripheral group PCLK root select */ 3840 #define PERI_GROUP_PRESENT0_PERI_GROUP_PCLK_ROOT_SEL 0u 3841 /* Clock control functionality present ('0': no, '1': yes) */ 3842 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3843 /* Slave present ('0': no, '1': yes) */ 3844 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3845 /* Slave present ('0': no, '1': yes) */ 3846 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3847 /* Slave present ('0': no, '1': yes) */ 3848 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3849 /* Slave present ('0': no, '1': yes) */ 3850 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3851 /* Slave present ('0': no, '1': yes) */ 3852 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3853 /* Slave present ('0': no, '1': yes) */ 3854 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3855 /* Slave present ('0': no, '1': yes) */ 3856 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3857 /* Slave present ('0': no, '1': yes) */ 3858 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3859 /* Slave present ('0': no, '1': yes) */ 3860 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3861 /* Slave present ('0': no, '1': yes) */ 3862 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3863 /* Slave present ('0': no, '1': yes) */ 3864 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3865 /* Slave present ('0': no, '1': yes) */ 3866 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3867 /* Slave present ('0': no, '1': yes) */ 3868 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3869 /* Slave present ('0': no, '1': yes) */ 3870 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3871 /* Slave present ('0': no, '1': yes) */ 3872 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3873 /* Slave present ('0': no, '1': yes) */ 3874 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3875 /* Peripheral group PCLK root select */ 3876 #define PERI_GROUP_PRESENT1_PERI_GROUP_PCLK_ROOT_SEL 0u 3877 /* Clock control functionality present ('0': no, '1': yes) */ 3878 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3879 /* Slave present ('0': no, '1': yes) */ 3880 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3881 /* Slave present ('0': no, '1': yes) */ 3882 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3883 /* Slave present ('0': no, '1': yes) */ 3884 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3885 /* Slave present ('0': no, '1': yes) */ 3886 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3887 /* Slave present ('0': no, '1': yes) */ 3888 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3889 /* Slave present ('0': no, '1': yes) */ 3890 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3891 /* Slave present ('0': no, '1': yes) */ 3892 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3893 /* Slave present ('0': no, '1': yes) */ 3894 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3895 /* Slave present ('0': no, '1': yes) */ 3896 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3897 /* Slave present ('0': no, '1': yes) */ 3898 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3899 /* Slave present ('0': no, '1': yes) */ 3900 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3901 /* Slave present ('0': no, '1': yes) */ 3902 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3903 /* Slave present ('0': no, '1': yes) */ 3904 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3905 /* Slave present ('0': no, '1': yes) */ 3906 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3907 /* Slave present ('0': no, '1': yes) */ 3908 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3909 /* Slave present ('0': no, '1': yes) */ 3910 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3911 /* Peripheral group PCLK root select */ 3912 #define PERI_GROUP_PRESENT2_PERI_GROUP_PCLK_ROOT_SEL 0u 3913 /* Clock control functionality present ('0': no, '1': yes) */ 3914 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3915 /* Slave present ('0': no, '1': yes) */ 3916 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3917 /* Slave present ('0': no, '1': yes) */ 3918 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3919 /* Slave present ('0': no, '1': yes) */ 3920 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3921 /* Slave present ('0': no, '1': yes) */ 3922 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3923 /* Slave present ('0': no, '1': yes) */ 3924 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u 3925 /* Slave present ('0': no, '1': yes) */ 3926 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 1u 3927 /* Slave present ('0': no, '1': yes) */ 3928 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u 3929 /* Slave present ('0': no, '1': yes) */ 3930 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u 3931 /* Slave present ('0': no, '1': yes) */ 3932 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u 3933 /* Slave present ('0': no, '1': yes) */ 3934 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u 3935 /* Slave present ('0': no, '1': yes) */ 3936 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u 3937 /* Slave present ('0': no, '1': yes) */ 3938 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 1u 3939 /* Slave present ('0': no, '1': yes) */ 3940 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3941 /* Slave present ('0': no, '1': yes) */ 3942 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3943 /* Slave present ('0': no, '1': yes) */ 3944 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3945 /* Slave present ('0': no, '1': yes) */ 3946 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3947 /* Peripheral group PCLK root select */ 3948 #define PERI_GROUP_PRESENT3_PERI_GROUP_PCLK_ROOT_SEL 0u 3949 /* Clock control functionality present ('0': no, '1': yes) */ 3950 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3951 /* Slave present ('0': no, '1': yes) */ 3952 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3953 /* Slave present ('0': no, '1': yes) */ 3954 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3955 /* Slave present ('0': no, '1': yes) */ 3956 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3957 /* Slave present ('0': no, '1': yes) */ 3958 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3959 /* Slave present ('0': no, '1': yes) */ 3960 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 1u 3961 /* Slave present ('0': no, '1': yes) */ 3962 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3963 /* Slave present ('0': no, '1': yes) */ 3964 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3965 /* Slave present ('0': no, '1': yes) */ 3966 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3967 /* Slave present ('0': no, '1': yes) */ 3968 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3969 /* Slave present ('0': no, '1': yes) */ 3970 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3971 /* Slave present ('0': no, '1': yes) */ 3972 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3973 /* Slave present ('0': no, '1': yes) */ 3974 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3975 /* Slave present ('0': no, '1': yes) */ 3976 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3977 /* Slave present ('0': no, '1': yes) */ 3978 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3979 /* Slave present ('0': no, '1': yes) */ 3980 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3981 /* Slave present ('0': no, '1': yes) */ 3982 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3983 /* Peripheral group PCLK root select */ 3984 #define PERI_GROUP_PRESENT4_PERI_GROUP_PCLK_ROOT_SEL 0u 3985 /* Clock control functionality present ('0': no, '1': yes) */ 3986 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3987 /* Slave present ('0': no, '1': yes) */ 3988 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3989 /* Slave present ('0': no, '1': yes) */ 3990 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3991 /* Slave present ('0': no, '1': yes) */ 3992 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3993 /* Slave present ('0': no, '1': yes) */ 3994 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3995 /* Slave present ('0': no, '1': yes) */ 3996 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3997 /* Slave present ('0': no, '1': yes) */ 3998 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3999 /* Slave present ('0': no, '1': yes) */ 4000 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4001 /* Slave present ('0': no, '1': yes) */ 4002 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4003 /* Slave present ('0': no, '1': yes) */ 4004 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4005 /* Slave present ('0': no, '1': yes) */ 4006 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4007 /* Slave present ('0': no, '1': yes) */ 4008 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4009 /* Slave present ('0': no, '1': yes) */ 4010 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4011 /* Slave present ('0': no, '1': yes) */ 4012 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4013 /* Slave present ('0': no, '1': yes) */ 4014 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4015 /* Slave present ('0': no, '1': yes) */ 4016 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4017 /* Slave present ('0': no, '1': yes) */ 4018 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4019 /* Peripheral group PCLK root select */ 4020 #define PERI_GROUP_PRESENT5_PERI_GROUP_PCLK_ROOT_SEL 1u 4021 /* Clock control functionality present ('0': no, '1': yes) */ 4022 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 4023 /* Slave present ('0': no, '1': yes) */ 4024 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 1u 4025 /* Slave present ('0': no, '1': yes) */ 4026 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 1u 4027 /* Slave present ('0': no, '1': yes) */ 4028 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 1u 4029 /* Slave present ('0': no, '1': yes) */ 4030 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 1u 4031 /* Slave present ('0': no, '1': yes) */ 4032 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 1u 4033 /* Slave present ('0': no, '1': yes) */ 4034 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4035 /* Slave present ('0': no, '1': yes) */ 4036 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4037 /* Slave present ('0': no, '1': yes) */ 4038 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4039 /* Slave present ('0': no, '1': yes) */ 4040 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4041 /* Slave present ('0': no, '1': yes) */ 4042 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4043 /* Slave present ('0': no, '1': yes) */ 4044 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4045 /* Slave present ('0': no, '1': yes) */ 4046 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4047 /* Slave present ('0': no, '1': yes) */ 4048 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4049 /* Slave present ('0': no, '1': yes) */ 4050 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4051 /* Slave present ('0': no, '1': yes) */ 4052 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4053 /* Slave present ('0': no, '1': yes) */ 4054 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4055 /* Peripheral group PCLK root select */ 4056 #define PERI_GROUP_PRESENT6_PERI_GROUP_PCLK_ROOT_SEL 1u 4057 /* Clock control functionality present ('0': no, '1': yes) */ 4058 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 4059 /* Slave present ('0': no, '1': yes) */ 4060 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u 4061 /* Slave present ('0': no, '1': yes) */ 4062 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u 4063 /* Slave present ('0': no, '1': yes) */ 4064 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u 4065 /* Slave present ('0': no, '1': yes) */ 4066 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u 4067 /* Slave present ('0': no, '1': yes) */ 4068 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u 4069 /* Slave present ('0': no, '1': yes) */ 4070 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u 4071 /* Slave present ('0': no, '1': yes) */ 4072 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u 4073 /* Slave present ('0': no, '1': yes) */ 4074 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 1u 4075 /* Slave present ('0': no, '1': yes) */ 4076 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 1u 4077 /* Slave present ('0': no, '1': yes) */ 4078 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 1u 4079 /* Slave present ('0': no, '1': yes) */ 4080 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 1u 4081 /* Slave present ('0': no, '1': yes) */ 4082 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4083 /* Slave present ('0': no, '1': yes) */ 4084 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4085 /* Slave present ('0': no, '1': yes) */ 4086 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4087 /* Slave present ('0': no, '1': yes) */ 4088 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4089 /* Slave present ('0': no, '1': yes) */ 4090 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4091 /* Peripheral group PCLK root select */ 4092 #define PERI_GROUP_PRESENT7_PERI_GROUP_PCLK_ROOT_SEL 0u 4093 /* Clock control functionality present ('0': no, '1': yes) */ 4094 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 4095 /* Slave present ('0': no, '1': yes) */ 4096 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u 4097 /* Slave present ('0': no, '1': yes) */ 4098 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4099 /* Slave present ('0': no, '1': yes) */ 4100 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4101 /* Slave present ('0': no, '1': yes) */ 4102 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4103 /* Slave present ('0': no, '1': yes) */ 4104 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4105 /* Slave present ('0': no, '1': yes) */ 4106 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4107 /* Slave present ('0': no, '1': yes) */ 4108 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4109 /* Slave present ('0': no, '1': yes) */ 4110 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4111 /* Slave present ('0': no, '1': yes) */ 4112 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4113 /* Slave present ('0': no, '1': yes) */ 4114 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4115 /* Slave present ('0': no, '1': yes) */ 4116 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4117 /* Slave present ('0': no, '1': yes) */ 4118 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4119 /* Slave present ('0': no, '1': yes) */ 4120 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4121 /* Slave present ('0': no, '1': yes) */ 4122 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4123 /* Slave present ('0': no, '1': yes) */ 4124 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4125 /* Slave present ('0': no, '1': yes) */ 4126 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4127 /* Peripheral group PCLK root select */ 4128 #define PERI_GROUP_PRESENT8_PERI_GROUP_PCLK_ROOT_SEL 0u 4129 /* Clock control functionality present ('0': no, '1': yes) */ 4130 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 4131 /* Slave present ('0': no, '1': yes) */ 4132 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 1u 4133 /* Slave present ('0': no, '1': yes) */ 4134 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 1u 4135 /* Slave present ('0': no, '1': yes) */ 4136 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 1u 4137 /* Slave present ('0': no, '1': yes) */ 4138 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4139 /* Slave present ('0': no, '1': yes) */ 4140 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4141 /* Slave present ('0': no, '1': yes) */ 4142 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4143 /* Slave present ('0': no, '1': yes) */ 4144 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4145 /* Slave present ('0': no, '1': yes) */ 4146 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4147 /* Slave present ('0': no, '1': yes) */ 4148 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4149 /* Slave present ('0': no, '1': yes) */ 4150 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4151 /* Slave present ('0': no, '1': yes) */ 4152 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4153 /* Slave present ('0': no, '1': yes) */ 4154 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4155 /* Slave present ('0': no, '1': yes) */ 4156 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4157 /* Slave present ('0': no, '1': yes) */ 4158 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4159 /* Slave present ('0': no, '1': yes) */ 4160 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4161 /* Slave present ('0': no, '1': yes) */ 4162 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4163 /* Peripheral group PCLK root select */ 4164 #define PERI_GROUP_PRESENT9_PERI_GROUP_PCLK_ROOT_SEL 1u 4165 /* Clock control functionality present ('0': no, '1': yes) */ 4166 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 4167 /* Slave present ('0': no, '1': yes) */ 4168 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u 4169 /* Slave present ('0': no, '1': yes) */ 4170 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4171 /* Slave present ('0': no, '1': yes) */ 4172 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4173 /* Slave present ('0': no, '1': yes) */ 4174 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4175 /* Slave present ('0': no, '1': yes) */ 4176 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4177 /* Slave present ('0': no, '1': yes) */ 4178 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4179 /* Slave present ('0': no, '1': yes) */ 4180 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4181 /* Slave present ('0': no, '1': yes) */ 4182 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4183 /* Slave present ('0': no, '1': yes) */ 4184 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4185 /* Slave present ('0': no, '1': yes) */ 4186 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4187 /* Slave present ('0': no, '1': yes) */ 4188 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4189 /* Slave present ('0': no, '1': yes) */ 4190 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4191 /* Slave present ('0': no, '1': yes) */ 4192 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4193 /* Slave present ('0': no, '1': yes) */ 4194 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4195 /* Slave present ('0': no, '1': yes) */ 4196 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4197 /* Slave present ('0': no, '1': yes) */ 4198 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4199 /* Peripheral group PCLK root select */ 4200 #define PERI_GROUP_PRESENT10_PERI_GROUP_PCLK_ROOT_SEL 0u 4201 /* Clock control functionality present ('0': no, '1': yes) */ 4202 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 4203 /* Slave present ('0': no, '1': yes) */ 4204 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 0u 4205 /* Slave present ('0': no, '1': yes) */ 4206 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4207 /* Slave present ('0': no, '1': yes) */ 4208 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4209 /* Slave present ('0': no, '1': yes) */ 4210 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4211 /* Slave present ('0': no, '1': yes) */ 4212 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4213 /* Slave present ('0': no, '1': yes) */ 4214 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4215 /* Slave present ('0': no, '1': yes) */ 4216 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4217 /* Slave present ('0': no, '1': yes) */ 4218 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4219 /* Slave present ('0': no, '1': yes) */ 4220 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4221 /* Slave present ('0': no, '1': yes) */ 4222 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4223 /* Slave present ('0': no, '1': yes) */ 4224 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4225 /* Slave present ('0': no, '1': yes) */ 4226 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4227 /* Slave present ('0': no, '1': yes) */ 4228 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4229 /* Slave present ('0': no, '1': yes) */ 4230 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4231 /* Slave present ('0': no, '1': yes) */ 4232 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4233 /* Slave present ('0': no, '1': yes) */ 4234 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4235 /* Peripheral group PCLK root select */ 4236 #define PERI_GROUP_PRESENT11_PERI_GROUP_PCLK_ROOT_SEL 0u 4237 /* Clock control functionality present ('0': no, '1': yes) */ 4238 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 4239 /* Slave present ('0': no, '1': yes) */ 4240 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u 4241 /* Slave present ('0': no, '1': yes) */ 4242 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4243 /* Slave present ('0': no, '1': yes) */ 4244 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4245 /* Slave present ('0': no, '1': yes) */ 4246 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4247 /* Slave present ('0': no, '1': yes) */ 4248 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4249 /* Slave present ('0': no, '1': yes) */ 4250 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4251 /* Slave present ('0': no, '1': yes) */ 4252 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4253 /* Slave present ('0': no, '1': yes) */ 4254 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4255 /* Slave present ('0': no, '1': yes) */ 4256 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4257 /* Slave present ('0': no, '1': yes) */ 4258 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4259 /* Slave present ('0': no, '1': yes) */ 4260 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4261 /* Slave present ('0': no, '1': yes) */ 4262 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4263 /* Slave present ('0': no, '1': yes) */ 4264 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4265 /* Slave present ('0': no, '1': yes) */ 4266 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4267 /* Slave present ('0': no, '1': yes) */ 4268 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4269 /* Slave present ('0': no, '1': yes) */ 4270 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4271 /* Peripheral group PCLK root select */ 4272 #define PERI_GROUP_PRESENT12_PERI_GROUP_PCLK_ROOT_SEL 0u 4273 /* Clock control functionality present ('0': no, '1': yes) */ 4274 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 4275 /* Slave present ('0': no, '1': yes) */ 4276 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u 4277 /* Slave present ('0': no, '1': yes) */ 4278 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4279 /* Slave present ('0': no, '1': yes) */ 4280 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4281 /* Slave present ('0': no, '1': yes) */ 4282 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4283 /* Slave present ('0': no, '1': yes) */ 4284 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4285 /* Slave present ('0': no, '1': yes) */ 4286 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4287 /* Slave present ('0': no, '1': yes) */ 4288 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4289 /* Slave present ('0': no, '1': yes) */ 4290 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4291 /* Slave present ('0': no, '1': yes) */ 4292 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4293 /* Slave present ('0': no, '1': yes) */ 4294 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4295 /* Slave present ('0': no, '1': yes) */ 4296 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4297 /* Slave present ('0': no, '1': yes) */ 4298 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4299 /* Slave present ('0': no, '1': yes) */ 4300 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4301 /* Slave present ('0': no, '1': yes) */ 4302 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4303 /* Slave present ('0': no, '1': yes) */ 4304 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4305 /* Slave present ('0': no, '1': yes) */ 4306 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4307 /* Peripheral group PCLK root select */ 4308 #define PERI_GROUP_PRESENT13_PERI_GROUP_PCLK_ROOT_SEL 0u 4309 /* Clock control functionality present ('0': no, '1': yes) */ 4310 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 4311 /* Slave present ('0': no, '1': yes) */ 4312 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u 4313 /* Slave present ('0': no, '1': yes) */ 4314 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4315 /* Slave present ('0': no, '1': yes) */ 4316 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4317 /* Slave present ('0': no, '1': yes) */ 4318 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4319 /* Slave present ('0': no, '1': yes) */ 4320 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4321 /* Slave present ('0': no, '1': yes) */ 4322 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4323 /* Slave present ('0': no, '1': yes) */ 4324 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4325 /* Slave present ('0': no, '1': yes) */ 4326 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4327 /* Slave present ('0': no, '1': yes) */ 4328 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4329 /* Slave present ('0': no, '1': yes) */ 4330 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4331 /* Slave present ('0': no, '1': yes) */ 4332 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4333 /* Slave present ('0': no, '1': yes) */ 4334 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4335 /* Slave present ('0': no, '1': yes) */ 4336 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4337 /* Slave present ('0': no, '1': yes) */ 4338 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4339 /* Slave present ('0': no, '1': yes) */ 4340 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4341 /* Slave present ('0': no, '1': yes) */ 4342 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4343 /* Peripheral group PCLK root select */ 4344 #define PERI_GROUP_PRESENT14_PERI_GROUP_PCLK_ROOT_SEL 0u 4345 /* Clock control functionality present ('0': no, '1': yes) */ 4346 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 4347 /* Slave present ('0': no, '1': yes) */ 4348 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u 4349 /* Slave present ('0': no, '1': yes) */ 4350 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4351 /* Slave present ('0': no, '1': yes) */ 4352 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4353 /* Slave present ('0': no, '1': yes) */ 4354 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4355 /* Slave present ('0': no, '1': yes) */ 4356 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4357 /* Slave present ('0': no, '1': yes) */ 4358 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4359 /* Slave present ('0': no, '1': yes) */ 4360 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4361 /* Slave present ('0': no, '1': yes) */ 4362 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4363 /* Slave present ('0': no, '1': yes) */ 4364 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4365 /* Slave present ('0': no, '1': yes) */ 4366 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4367 /* Slave present ('0': no, '1': yes) */ 4368 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4369 /* Slave present ('0': no, '1': yes) */ 4370 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4371 /* Slave present ('0': no, '1': yes) */ 4372 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4373 /* Slave present ('0': no, '1': yes) */ 4374 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4375 /* Slave present ('0': no, '1': yes) */ 4376 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4377 /* Slave present ('0': no, '1': yes) */ 4378 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4379 /* Peripheral group PCLK root select */ 4380 #define PERI_GROUP_PRESENT15_PERI_GROUP_PCLK_ROOT_SEL 0u 4381 /* Clock control functionality present ('0': no, '1': yes) */ 4382 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 4383 /* Slave present ('0': no, '1': yes) */ 4384 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u 4385 /* Slave present ('0': no, '1': yes) */ 4386 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4387 /* Slave present ('0': no, '1': yes) */ 4388 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4389 /* Slave present ('0': no, '1': yes) */ 4390 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4391 /* Slave present ('0': no, '1': yes) */ 4392 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4393 /* Slave present ('0': no, '1': yes) */ 4394 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4395 /* Slave present ('0': no, '1': yes) */ 4396 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4397 /* Slave present ('0': no, '1': yes) */ 4398 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4399 /* Slave present ('0': no, '1': yes) */ 4400 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4401 /* Slave present ('0': no, '1': yes) */ 4402 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4403 /* Slave present ('0': no, '1': yes) */ 4404 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4405 /* Slave present ('0': no, '1': yes) */ 4406 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4407 /* Slave present ('0': no, '1': yes) */ 4408 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4409 /* Slave present ('0': no, '1': yes) */ 4410 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4411 /* Slave present ('0': no, '1': yes) */ 4412 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4413 /* Slave present ('0': no, '1': yes) */ 4414 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4415 /* Number of asynchronous PCLK groups */ 4416 #define PERI_PCLK_GROUP_NR 2u 4417 /* Timeout functionality present ('0': no, '1': yes) */ 4418 #define PERI_TIMEOUT_PRESENT 1u 4419 /* Trigger module present ('0': no, '1': yes) */ 4420 #define PERI_TR 1u 4421 /* Number of trigger groups */ 4422 #define PERI_TR_GROUP_NR 13u 4423 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4424 #define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4425 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4426 #define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4427 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4428 #define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4429 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4430 #define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4431 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4432 #define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4433 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4434 #define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4435 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4436 #define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4437 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4438 #define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4439 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4440 #define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4441 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4442 #define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4443 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4444 #define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 0u 4445 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4446 #define PERI_TR_GROUP_NR11_TR_GROUP_TR_MANIPULATION_PRESENT 0u 4447 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4448 #define PERI_TR_GROUP_NR12_TR_GROUP_TR_MANIPULATION_PRESENT 0u 4449 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4450 #define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4451 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4452 #define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4453 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4454 #define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4455 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4456 #define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4457 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4458 #define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4459 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4460 #define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4461 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4462 #define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4463 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4464 #define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4465 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4466 #define PERI_TR_1TO1_GROUP_NR8_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4467 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4468 #define PERI_TR_1TO1_GROUP_NR9_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4469 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4470 #define PERI_TR_1TO1_GROUP_NR10_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4471 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4472 #define PERI_TR_1TO1_GROUP_NR11_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4473 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4474 #define PERI_TR_1TO1_GROUP_NR12_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4475 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4476 #define PERI_TR_1TO1_GROUP_NR13_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4477 /* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ 4478 #define PERI_GR_DIV_ADDR_WIDTH 5u 4479 /* Number of asynchronous PCLK groups */ 4480 #define PERI_PERI_PCLK_PCLK_GROUP_NR 2u 4481 /* Number of 8.0 dividers */ 4482 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT 4u 4483 /* Number of 16.0 dividers */ 4484 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT 3u 4485 /* Number of 16.5 (fractional) dividers */ 4486 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT 0u 4487 /* Number of 24.5 (fractional) dividers */ 4488 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT 1u 4489 /* Number of programmable clocks [1, 256] */ 4490 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_CLOCK_VECT 15u 4491 /* Number of 8.0 dividers */ 4492 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT 19u 4493 /* Number of 16.0 dividers */ 4494 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT 20u 4495 /* Number of 16.5 (fractional) dividers */ 4496 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT 0u 4497 /* Number of 24.5 (fractional) dividers */ 4498 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT 21u 4499 /* Number of programmable clocks [1, 256] */ 4500 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_CLOCK_VECT 154u 4501 /* DeepSleep support ('0':no, '1': yes) */ 4502 #define SCB0_DEEPSLEEP 1u 4503 /* Externally clocked support? ('0': no, '1': yes) */ 4504 #define SCB0_EC 1u 4505 /* I2C master support? ('0': no, '1': yes) */ 4506 #define SCB0_I2C_M 1u 4507 /* I2C slave support? ('0': no, '1': yes) */ 4508 #define SCB0_I2C_S 1u 4509 /* I2C glitch filters present? ('0': no, '1': yes) */ 4510 #define SCB0_I2C_GLITCH 1u 4511 /* I2C support? (I2C_M | I2C_S) */ 4512 #define SCB0_I2C 1u 4513 /* I2C externally clocked support? ('0': no, '1': yes) */ 4514 #define SCB0_I2C_EC 1u 4515 /* I2C master and slave support? (I2C_M & I2C_S) */ 4516 #define SCB0_I2C_M_S 1u 4517 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4518 #define SCB0_I2C_S_EC 1u 4519 /* SPI master support? ('0': no, '1': yes) */ 4520 #define SCB0_SPI_M 1u 4521 /* SPI slave support? ('0': no, '1': yes) */ 4522 #define SCB0_SPI_S 1u 4523 /* SPI support? (SPI_M | SPI_S) */ 4524 #define SCB0_SPI 1u 4525 /* SPI externally clocked support? ('0': no, '1': yes) */ 4526 #define SCB0_SPI_EC 1u 4527 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4528 #define SCB0_SPI_S_EC 1u 4529 /* UART support? ('0': no, '1': yes) */ 4530 #define SCB0_UART 1u 4531 /* SPI or UART (SPI | UART) */ 4532 #define SCB0_SPI_UART 1u 4533 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4534 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4535 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4536 #define SCB0_EZ_DATA_NR 256u 4537 /* Command/response mode support? ('0': no, '1': yes) */ 4538 #define SCB0_CMD_RESP 1u 4539 /* EZ mode support? ('0': no, '1': yes) */ 4540 #define SCB0_EZ 1u 4541 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4542 #define SCB0_EZ_CMD_RESP 1u 4543 /* I2C slave with EZ mode (I2C_S & EZ) */ 4544 #define SCB0_I2C_S_EZ 1u 4545 /* SPI slave with EZ mode (SPI_S & EZ) */ 4546 #define SCB0_SPI_S_EZ 1u 4547 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4548 #define SCB0_MASTER_WIDTH 8u 4549 /* Number of used spi_select signals (max 4) */ 4550 #define SCB0_CHIP_TOP_SPI_SEL_NR 4u 4551 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4552 #define SCB0_CHIP_TOP_I2C_FAST_PLUS 1u 4553 /* DeepSleep support ('0':no, '1': yes) */ 4554 #define SCB1_DEEPSLEEP 0u 4555 /* Externally clocked support? ('0': no, '1': yes) */ 4556 #define SCB1_EC 1u 4557 /* I2C master support? ('0': no, '1': yes) */ 4558 #define SCB1_I2C_M 1u 4559 /* I2C slave support? ('0': no, '1': yes) */ 4560 #define SCB1_I2C_S 1u 4561 /* I2C glitch filters present? ('0': no, '1': yes) */ 4562 #define SCB1_I2C_GLITCH 1u 4563 /* I2C support? (I2C_M | I2C_S) */ 4564 #define SCB1_I2C 1u 4565 /* I2C externally clocked support? ('0': no, '1': yes) */ 4566 #define SCB1_I2C_EC 0u 4567 /* I2C master and slave support? (I2C_M & I2C_S) */ 4568 #define SCB1_I2C_M_S 1u 4569 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4570 #define SCB1_I2C_S_EC 0u 4571 /* SPI master support? ('0': no, '1': yes) */ 4572 #define SCB1_SPI_M 1u 4573 /* SPI slave support? ('0': no, '1': yes) */ 4574 #define SCB1_SPI_S 1u 4575 /* SPI support? (SPI_M | SPI_S) */ 4576 #define SCB1_SPI 1u 4577 /* SPI externally clocked support? ('0': no, '1': yes) */ 4578 #define SCB1_SPI_EC 1u 4579 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4580 #define SCB1_SPI_S_EC 1u 4581 /* UART support? ('0': no, '1': yes) */ 4582 #define SCB1_UART 1u 4583 /* SPI or UART (SPI | UART) */ 4584 #define SCB1_SPI_UART 1u 4585 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4586 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4587 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4588 #define SCB1_EZ_DATA_NR 256u 4589 /* Command/response mode support? ('0': no, '1': yes) */ 4590 #define SCB1_CMD_RESP 0u 4591 /* EZ mode support? ('0': no, '1': yes) */ 4592 #define SCB1_EZ 1u 4593 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4594 #define SCB1_EZ_CMD_RESP 1u 4595 /* I2C slave with EZ mode (I2C_S & EZ) */ 4596 #define SCB1_I2C_S_EZ 1u 4597 /* SPI slave with EZ mode (SPI_S & EZ) */ 4598 #define SCB1_SPI_S_EZ 1u 4599 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4600 #define SCB1_MASTER_WIDTH 8u 4601 /* Number of used spi_select signals (max 4) */ 4602 #define SCB1_CHIP_TOP_SPI_SEL_NR 4u 4603 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4604 #define SCB1_CHIP_TOP_I2C_FAST_PLUS 1u 4605 /* DeepSleep support ('0':no, '1': yes) */ 4606 #define SCB2_DEEPSLEEP 0u 4607 /* Externally clocked support? ('0': no, '1': yes) */ 4608 #define SCB2_EC 1u 4609 /* I2C master support? ('0': no, '1': yes) */ 4610 #define SCB2_I2C_M 1u 4611 /* I2C slave support? ('0': no, '1': yes) */ 4612 #define SCB2_I2C_S 1u 4613 /* I2C glitch filters present? ('0': no, '1': yes) */ 4614 #define SCB2_I2C_GLITCH 1u 4615 /* I2C support? (I2C_M | I2C_S) */ 4616 #define SCB2_I2C 1u 4617 /* I2C externally clocked support? ('0': no, '1': yes) */ 4618 #define SCB2_I2C_EC 0u 4619 /* I2C master and slave support? (I2C_M & I2C_S) */ 4620 #define SCB2_I2C_M_S 1u 4621 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4622 #define SCB2_I2C_S_EC 0u 4623 /* SPI master support? ('0': no, '1': yes) */ 4624 #define SCB2_SPI_M 1u 4625 /* SPI slave support? ('0': no, '1': yes) */ 4626 #define SCB2_SPI_S 1u 4627 /* SPI support? (SPI_M | SPI_S) */ 4628 #define SCB2_SPI 1u 4629 /* SPI externally clocked support? ('0': no, '1': yes) */ 4630 #define SCB2_SPI_EC 1u 4631 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4632 #define SCB2_SPI_S_EC 1u 4633 /* UART support? ('0': no, '1': yes) */ 4634 #define SCB2_UART 1u 4635 /* SPI or UART (SPI | UART) */ 4636 #define SCB2_SPI_UART 1u 4637 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4638 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4639 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4640 #define SCB2_EZ_DATA_NR 256u 4641 /* Command/response mode support? ('0': no, '1': yes) */ 4642 #define SCB2_CMD_RESP 0u 4643 /* EZ mode support? ('0': no, '1': yes) */ 4644 #define SCB2_EZ 1u 4645 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4646 #define SCB2_EZ_CMD_RESP 1u 4647 /* I2C slave with EZ mode (I2C_S & EZ) */ 4648 #define SCB2_I2C_S_EZ 1u 4649 /* SPI slave with EZ mode (SPI_S & EZ) */ 4650 #define SCB2_SPI_S_EZ 1u 4651 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4652 #define SCB2_MASTER_WIDTH 8u 4653 /* Number of used spi_select signals (max 4) */ 4654 #define SCB2_CHIP_TOP_SPI_SEL_NR 4u 4655 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4656 #define SCB2_CHIP_TOP_I2C_FAST_PLUS 1u 4657 /* DeepSleep support ('0':no, '1': yes) */ 4658 #define SCB3_DEEPSLEEP 0u 4659 /* Externally clocked support? ('0': no, '1': yes) */ 4660 #define SCB3_EC 1u 4661 /* I2C master support? ('0': no, '1': yes) */ 4662 #define SCB3_I2C_M 1u 4663 /* I2C slave support? ('0': no, '1': yes) */ 4664 #define SCB3_I2C_S 1u 4665 /* I2C glitch filters present? ('0': no, '1': yes) */ 4666 #define SCB3_I2C_GLITCH 1u 4667 /* I2C support? (I2C_M | I2C_S) */ 4668 #define SCB3_I2C 1u 4669 /* I2C externally clocked support? ('0': no, '1': yes) */ 4670 #define SCB3_I2C_EC 0u 4671 /* I2C master and slave support? (I2C_M & I2C_S) */ 4672 #define SCB3_I2C_M_S 1u 4673 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4674 #define SCB3_I2C_S_EC 0u 4675 /* SPI master support? ('0': no, '1': yes) */ 4676 #define SCB3_SPI_M 1u 4677 /* SPI slave support? ('0': no, '1': yes) */ 4678 #define SCB3_SPI_S 1u 4679 /* SPI support? (SPI_M | SPI_S) */ 4680 #define SCB3_SPI 1u 4681 /* SPI externally clocked support? ('0': no, '1': yes) */ 4682 #define SCB3_SPI_EC 1u 4683 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4684 #define SCB3_SPI_S_EC 1u 4685 /* UART support? ('0': no, '1': yes) */ 4686 #define SCB3_UART 1u 4687 /* SPI or UART (SPI | UART) */ 4688 #define SCB3_SPI_UART 1u 4689 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4690 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4691 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4692 #define SCB3_EZ_DATA_NR 256u 4693 /* Command/response mode support? ('0': no, '1': yes) */ 4694 #define SCB3_CMD_RESP 0u 4695 /* EZ mode support? ('0': no, '1': yes) */ 4696 #define SCB3_EZ 1u 4697 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4698 #define SCB3_EZ_CMD_RESP 1u 4699 /* I2C slave with EZ mode (I2C_S & EZ) */ 4700 #define SCB3_I2C_S_EZ 1u 4701 /* SPI slave with EZ mode (SPI_S & EZ) */ 4702 #define SCB3_SPI_S_EZ 1u 4703 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4704 #define SCB3_MASTER_WIDTH 8u 4705 /* Number of used spi_select signals (max 4) */ 4706 #define SCB3_CHIP_TOP_SPI_SEL_NR 4u 4707 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4708 #define SCB3_CHIP_TOP_I2C_FAST_PLUS 1u 4709 /* DeepSleep support ('0':no, '1': yes) */ 4710 #define SCB4_DEEPSLEEP 0u 4711 /* Externally clocked support? ('0': no, '1': yes) */ 4712 #define SCB4_EC 1u 4713 /* I2C master support? ('0': no, '1': yes) */ 4714 #define SCB4_I2C_M 1u 4715 /* I2C slave support? ('0': no, '1': yes) */ 4716 #define SCB4_I2C_S 1u 4717 /* I2C glitch filters present? ('0': no, '1': yes) */ 4718 #define SCB4_I2C_GLITCH 1u 4719 /* I2C support? (I2C_M | I2C_S) */ 4720 #define SCB4_I2C 1u 4721 /* I2C externally clocked support? ('0': no, '1': yes) */ 4722 #define SCB4_I2C_EC 0u 4723 /* I2C master and slave support? (I2C_M & I2C_S) */ 4724 #define SCB4_I2C_M_S 1u 4725 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4726 #define SCB4_I2C_S_EC 0u 4727 /* SPI master support? ('0': no, '1': yes) */ 4728 #define SCB4_SPI_M 1u 4729 /* SPI slave support? ('0': no, '1': yes) */ 4730 #define SCB4_SPI_S 1u 4731 /* SPI support? (SPI_M | SPI_S) */ 4732 #define SCB4_SPI 1u 4733 /* SPI externally clocked support? ('0': no, '1': yes) */ 4734 #define SCB4_SPI_EC 1u 4735 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4736 #define SCB4_SPI_S_EC 1u 4737 /* UART support? ('0': no, '1': yes) */ 4738 #define SCB4_UART 1u 4739 /* SPI or UART (SPI | UART) */ 4740 #define SCB4_SPI_UART 1u 4741 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4742 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4743 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4744 #define SCB4_EZ_DATA_NR 256u 4745 /* Command/response mode support? ('0': no, '1': yes) */ 4746 #define SCB4_CMD_RESP 0u 4747 /* EZ mode support? ('0': no, '1': yes) */ 4748 #define SCB4_EZ 1u 4749 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4750 #define SCB4_EZ_CMD_RESP 1u 4751 /* I2C slave with EZ mode (I2C_S & EZ) */ 4752 #define SCB4_I2C_S_EZ 1u 4753 /* SPI slave with EZ mode (SPI_S & EZ) */ 4754 #define SCB4_SPI_S_EZ 1u 4755 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4756 #define SCB4_MASTER_WIDTH 8u 4757 /* Number of used spi_select signals (max 4) */ 4758 #define SCB4_CHIP_TOP_SPI_SEL_NR 4u 4759 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4760 #define SCB4_CHIP_TOP_I2C_FAST_PLUS 1u 4761 /* DeepSleep support ('0':no, '1': yes) */ 4762 #define SCB5_DEEPSLEEP 0u 4763 /* Externally clocked support? ('0': no, '1': yes) */ 4764 #define SCB5_EC 1u 4765 /* I2C master support? ('0': no, '1': yes) */ 4766 #define SCB5_I2C_M 1u 4767 /* I2C slave support? ('0': no, '1': yes) */ 4768 #define SCB5_I2C_S 1u 4769 /* I2C glitch filters present? ('0': no, '1': yes) */ 4770 #define SCB5_I2C_GLITCH 1u 4771 /* I2C support? (I2C_M | I2C_S) */ 4772 #define SCB5_I2C 1u 4773 /* I2C externally clocked support? ('0': no, '1': yes) */ 4774 #define SCB5_I2C_EC 0u 4775 /* I2C master and slave support? (I2C_M & I2C_S) */ 4776 #define SCB5_I2C_M_S 1u 4777 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4778 #define SCB5_I2C_S_EC 0u 4779 /* SPI master support? ('0': no, '1': yes) */ 4780 #define SCB5_SPI_M 1u 4781 /* SPI slave support? ('0': no, '1': yes) */ 4782 #define SCB5_SPI_S 1u 4783 /* SPI support? (SPI_M | SPI_S) */ 4784 #define SCB5_SPI 1u 4785 /* SPI externally clocked support? ('0': no, '1': yes) */ 4786 #define SCB5_SPI_EC 1u 4787 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4788 #define SCB5_SPI_S_EC 1u 4789 /* UART support? ('0': no, '1': yes) */ 4790 #define SCB5_UART 1u 4791 /* SPI or UART (SPI | UART) */ 4792 #define SCB5_SPI_UART 1u 4793 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4794 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4795 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4796 #define SCB5_EZ_DATA_NR 256u 4797 /* Command/response mode support? ('0': no, '1': yes) */ 4798 #define SCB5_CMD_RESP 0u 4799 /* EZ mode support? ('0': no, '1': yes) */ 4800 #define SCB5_EZ 1u 4801 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4802 #define SCB5_EZ_CMD_RESP 1u 4803 /* I2C slave with EZ mode (I2C_S & EZ) */ 4804 #define SCB5_I2C_S_EZ 1u 4805 /* SPI slave with EZ mode (SPI_S & EZ) */ 4806 #define SCB5_SPI_S_EZ 1u 4807 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4808 #define SCB5_MASTER_WIDTH 8u 4809 /* Number of used spi_select signals (max 4) */ 4810 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u 4811 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4812 #define SCB5_CHIP_TOP_I2C_FAST_PLUS 1u 4813 /* DeepSleep support ('0':no, '1': yes) */ 4814 #define SCB6_DEEPSLEEP 0u 4815 /* Externally clocked support? ('0': no, '1': yes) */ 4816 #define SCB6_EC 1u 4817 /* I2C master support? ('0': no, '1': yes) */ 4818 #define SCB6_I2C_M 1u 4819 /* I2C slave support? ('0': no, '1': yes) */ 4820 #define SCB6_I2C_S 1u 4821 /* I2C glitch filters present? ('0': no, '1': yes) */ 4822 #define SCB6_I2C_GLITCH 1u 4823 /* I2C support? (I2C_M | I2C_S) */ 4824 #define SCB6_I2C 1u 4825 /* I2C externally clocked support? ('0': no, '1': yes) */ 4826 #define SCB6_I2C_EC 0u 4827 /* I2C master and slave support? (I2C_M & I2C_S) */ 4828 #define SCB6_I2C_M_S 1u 4829 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4830 #define SCB6_I2C_S_EC 0u 4831 /* SPI master support? ('0': no, '1': yes) */ 4832 #define SCB6_SPI_M 1u 4833 /* SPI slave support? ('0': no, '1': yes) */ 4834 #define SCB6_SPI_S 1u 4835 /* SPI support? (SPI_M | SPI_S) */ 4836 #define SCB6_SPI 1u 4837 /* SPI externally clocked support? ('0': no, '1': yes) */ 4838 #define SCB6_SPI_EC 1u 4839 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4840 #define SCB6_SPI_S_EC 1u 4841 /* UART support? ('0': no, '1': yes) */ 4842 #define SCB6_UART 1u 4843 /* SPI or UART (SPI | UART) */ 4844 #define SCB6_SPI_UART 1u 4845 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4846 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4847 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4848 #define SCB6_EZ_DATA_NR 256u 4849 /* Command/response mode support? ('0': no, '1': yes) */ 4850 #define SCB6_CMD_RESP 0u 4851 /* EZ mode support? ('0': no, '1': yes) */ 4852 #define SCB6_EZ 1u 4853 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4854 #define SCB6_EZ_CMD_RESP 1u 4855 /* I2C slave with EZ mode (I2C_S & EZ) */ 4856 #define SCB6_I2C_S_EZ 1u 4857 /* SPI slave with EZ mode (SPI_S & EZ) */ 4858 #define SCB6_SPI_S_EZ 1u 4859 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4860 #define SCB6_MASTER_WIDTH 8u 4861 /* Number of used spi_select signals (max 4) */ 4862 #define SCB6_CHIP_TOP_SPI_SEL_NR 4u 4863 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4864 #define SCB6_CHIP_TOP_I2C_FAST_PLUS 1u 4865 /* DeepSleep support ('0':no, '1': yes) */ 4866 #define SCB7_DEEPSLEEP 0u 4867 /* Externally clocked support? ('0': no, '1': yes) */ 4868 #define SCB7_EC 1u 4869 /* I2C master support? ('0': no, '1': yes) */ 4870 #define SCB7_I2C_M 1u 4871 /* I2C slave support? ('0': no, '1': yes) */ 4872 #define SCB7_I2C_S 1u 4873 /* I2C glitch filters present? ('0': no, '1': yes) */ 4874 #define SCB7_I2C_GLITCH 1u 4875 /* I2C support? (I2C_M | I2C_S) */ 4876 #define SCB7_I2C 1u 4877 /* I2C externally clocked support? ('0': no, '1': yes) */ 4878 #define SCB7_I2C_EC 0u 4879 /* I2C master and slave support? (I2C_M & I2C_S) */ 4880 #define SCB7_I2C_M_S 1u 4881 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4882 #define SCB7_I2C_S_EC 0u 4883 /* SPI master support? ('0': no, '1': yes) */ 4884 #define SCB7_SPI_M 1u 4885 /* SPI slave support? ('0': no, '1': yes) */ 4886 #define SCB7_SPI_S 1u 4887 /* SPI support? (SPI_M | SPI_S) */ 4888 #define SCB7_SPI 1u 4889 /* SPI externally clocked support? ('0': no, '1': yes) */ 4890 #define SCB7_SPI_EC 1u 4891 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4892 #define SCB7_SPI_S_EC 1u 4893 /* UART support? ('0': no, '1': yes) */ 4894 #define SCB7_UART 1u 4895 /* SPI or UART (SPI | UART) */ 4896 #define SCB7_SPI_UART 1u 4897 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4898 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4899 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4900 #define SCB7_EZ_DATA_NR 256u 4901 /* Command/response mode support? ('0': no, '1': yes) */ 4902 #define SCB7_CMD_RESP 0u 4903 /* EZ mode support? ('0': no, '1': yes) */ 4904 #define SCB7_EZ 1u 4905 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4906 #define SCB7_EZ_CMD_RESP 1u 4907 /* I2C slave with EZ mode (I2C_S & EZ) */ 4908 #define SCB7_I2C_S_EZ 1u 4909 /* SPI slave with EZ mode (SPI_S & EZ) */ 4910 #define SCB7_SPI_S_EZ 1u 4911 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4912 #define SCB7_MASTER_WIDTH 8u 4913 /* Number of used spi_select signals (max 4) */ 4914 #define SCB7_CHIP_TOP_SPI_SEL_NR 4u 4915 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4916 #define SCB7_CHIP_TOP_I2C_FAST_PLUS 1u 4917 /* DeepSleep support ('0':no, '1': yes) */ 4918 #define SCB8_DEEPSLEEP 0u 4919 /* Externally clocked support? ('0': no, '1': yes) */ 4920 #define SCB8_EC 1u 4921 /* I2C master support? ('0': no, '1': yes) */ 4922 #define SCB8_I2C_M 1u 4923 /* I2C slave support? ('0': no, '1': yes) */ 4924 #define SCB8_I2C_S 1u 4925 /* I2C glitch filters present? ('0': no, '1': yes) */ 4926 #define SCB8_I2C_GLITCH 1u 4927 /* I2C support? (I2C_M | I2C_S) */ 4928 #define SCB8_I2C 1u 4929 /* I2C externally clocked support? ('0': no, '1': yes) */ 4930 #define SCB8_I2C_EC 0u 4931 /* I2C master and slave support? (I2C_M & I2C_S) */ 4932 #define SCB8_I2C_M_S 1u 4933 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4934 #define SCB8_I2C_S_EC 0u 4935 /* SPI master support? ('0': no, '1': yes) */ 4936 #define SCB8_SPI_M 1u 4937 /* SPI slave support? ('0': no, '1': yes) */ 4938 #define SCB8_SPI_S 1u 4939 /* SPI support? (SPI_M | SPI_S) */ 4940 #define SCB8_SPI 1u 4941 /* SPI externally clocked support? ('0': no, '1': yes) */ 4942 #define SCB8_SPI_EC 1u 4943 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4944 #define SCB8_SPI_S_EC 1u 4945 /* UART support? ('0': no, '1': yes) */ 4946 #define SCB8_UART 1u 4947 /* SPI or UART (SPI | UART) */ 4948 #define SCB8_SPI_UART 1u 4949 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4950 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4951 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4952 #define SCB8_EZ_DATA_NR 256u 4953 /* Command/response mode support? ('0': no, '1': yes) */ 4954 #define SCB8_CMD_RESP 0u 4955 /* EZ mode support? ('0': no, '1': yes) */ 4956 #define SCB8_EZ 1u 4957 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4958 #define SCB8_EZ_CMD_RESP 1u 4959 /* I2C slave with EZ mode (I2C_S & EZ) */ 4960 #define SCB8_I2C_S_EZ 1u 4961 /* SPI slave with EZ mode (SPI_S & EZ) */ 4962 #define SCB8_SPI_S_EZ 1u 4963 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4964 #define SCB8_MASTER_WIDTH 8u 4965 /* Number of used spi_select signals (max 4) */ 4966 #define SCB8_CHIP_TOP_SPI_SEL_NR 4u 4967 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4968 #define SCB8_CHIP_TOP_I2C_FAST_PLUS 1u 4969 /* DeepSleep support ('0':no, '1': yes) */ 4970 #define SCB9_DEEPSLEEP 0u 4971 /* Externally clocked support? ('0': no, '1': yes) */ 4972 #define SCB9_EC 1u 4973 /* I2C master support? ('0': no, '1': yes) */ 4974 #define SCB9_I2C_M 1u 4975 /* I2C slave support? ('0': no, '1': yes) */ 4976 #define SCB9_I2C_S 1u 4977 /* I2C glitch filters present? ('0': no, '1': yes) */ 4978 #define SCB9_I2C_GLITCH 1u 4979 /* I2C support? (I2C_M | I2C_S) */ 4980 #define SCB9_I2C 1u 4981 /* I2C externally clocked support? ('0': no, '1': yes) */ 4982 #define SCB9_I2C_EC 0u 4983 /* I2C master and slave support? (I2C_M & I2C_S) */ 4984 #define SCB9_I2C_M_S 1u 4985 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4986 #define SCB9_I2C_S_EC 0u 4987 /* SPI master support? ('0': no, '1': yes) */ 4988 #define SCB9_SPI_M 1u 4989 /* SPI slave support? ('0': no, '1': yes) */ 4990 #define SCB9_SPI_S 1u 4991 /* SPI support? (SPI_M | SPI_S) */ 4992 #define SCB9_SPI 1u 4993 /* SPI externally clocked support? ('0': no, '1': yes) */ 4994 #define SCB9_SPI_EC 1u 4995 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4996 #define SCB9_SPI_S_EC 1u 4997 /* UART support? ('0': no, '1': yes) */ 4998 #define SCB9_UART 1u 4999 /* SPI or UART (SPI | UART) */ 5000 #define SCB9_SPI_UART 1u 5001 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 5002 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 5003 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 5004 #define SCB9_EZ_DATA_NR 256u 5005 /* Command/response mode support? ('0': no, '1': yes) */ 5006 #define SCB9_CMD_RESP 0u 5007 /* EZ mode support? ('0': no, '1': yes) */ 5008 #define SCB9_EZ 1u 5009 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 5010 #define SCB9_EZ_CMD_RESP 1u 5011 /* I2C slave with EZ mode (I2C_S & EZ) */ 5012 #define SCB9_I2C_S_EZ 1u 5013 /* SPI slave with EZ mode (SPI_S & EZ) */ 5014 #define SCB9_SPI_S_EZ 1u 5015 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 5016 #define SCB9_MASTER_WIDTH 8u 5017 /* Number of used spi_select signals (max 4) */ 5018 #define SCB9_CHIP_TOP_SPI_SEL_NR 4u 5019 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 5020 #define SCB9_CHIP_TOP_I2C_FAST_PLUS 1u 5021 /* DeepSleep support ('0':no, '1': yes) */ 5022 #define SCB10_DEEPSLEEP 0u 5023 /* Externally clocked support? ('0': no, '1': yes) */ 5024 #define SCB10_EC 1u 5025 /* I2C master support? ('0': no, '1': yes) */ 5026 #define SCB10_I2C_M 1u 5027 /* I2C slave support? ('0': no, '1': yes) */ 5028 #define SCB10_I2C_S 1u 5029 /* I2C glitch filters present? ('0': no, '1': yes) */ 5030 #define SCB10_I2C_GLITCH 1u 5031 /* I2C support? (I2C_M | I2C_S) */ 5032 #define SCB10_I2C 1u 5033 /* I2C externally clocked support? ('0': no, '1': yes) */ 5034 #define SCB10_I2C_EC 0u 5035 /* I2C master and slave support? (I2C_M & I2C_S) */ 5036 #define SCB10_I2C_M_S 1u 5037 /* I2C slave with EC? (I2C_S & I2C_EC) */ 5038 #define SCB10_I2C_S_EC 0u 5039 /* SPI master support? ('0': no, '1': yes) */ 5040 #define SCB10_SPI_M 1u 5041 /* SPI slave support? ('0': no, '1': yes) */ 5042 #define SCB10_SPI_S 1u 5043 /* SPI support? (SPI_M | SPI_S) */ 5044 #define SCB10_SPI 1u 5045 /* SPI externally clocked support? ('0': no, '1': yes) */ 5046 #define SCB10_SPI_EC 1u 5047 /* SPI slave with EC? (SPI_S & SPI_EC) */ 5048 #define SCB10_SPI_S_EC 1u 5049 /* UART support? ('0': no, '1': yes) */ 5050 #define SCB10_UART 1u 5051 /* SPI or UART (SPI | UART) */ 5052 #define SCB10_SPI_UART 1u 5053 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 5054 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 5055 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 5056 #define SCB10_EZ_DATA_NR 256u 5057 /* Command/response mode support? ('0': no, '1': yes) */ 5058 #define SCB10_CMD_RESP 0u 5059 /* EZ mode support? ('0': no, '1': yes) */ 5060 #define SCB10_EZ 1u 5061 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 5062 #define SCB10_EZ_CMD_RESP 1u 5063 /* I2C slave with EZ mode (I2C_S & EZ) */ 5064 #define SCB10_I2C_S_EZ 1u 5065 /* SPI slave with EZ mode (SPI_S & EZ) */ 5066 #define SCB10_SPI_S_EZ 1u 5067 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 5068 #define SCB10_MASTER_WIDTH 8u 5069 /* Number of used spi_select signals (max 4) */ 5070 #define SCB10_CHIP_TOP_SPI_SEL_NR 4u 5071 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 5072 #define SCB10_CHIP_TOP_I2C_FAST_PLUS 1u 5073 /* Basically the max packet size, which gets double buffered in RAM 0: 512B 5074 (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for 5075 data) */ 5076 #define SDHC_MAX_BLK_SIZE 0u 5077 /* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this 5078 adds 288 bytes of space to the RAM for this purpose. */ 5079 #define SDHC_CQE_PRESENT 0u 5080 /* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have 5081 the Retention flag (Note, CTL.ENABLE is always retained irrespective of this 5082 parameter) */ 5083 #define SDHC_RETENTION_PRESENT 0u 5084 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data 5085 pins) */ 5086 #define SDHC_CHIP_TOP_DATA8_PRESENT 1u 5087 /* Chip top connect card_detect */ 5088 #define SDHC_CHIP_TOP_CARD_DETECT_PRESENT 1u 5089 /* Chip top connect card_mech_write_prot_in */ 5090 #define SDHC_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u 5091 /* Chip top connect led_ctrl_out and led_ctrl_out_en */ 5092 #define SDHC_CHIP_TOP_LED_CTRL_PRESENT 0u 5093 /* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ 5094 #define SDHC_CHIP_TOP_IO_VOLT_SEL_PRESENT 0u 5095 /* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ 5096 #define SDHC_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u 5097 /* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ 5098 #define SDHC_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u 5099 /* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ 5100 #define SDHC_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u 5101 /* Chip top connect interrupt_wakeup (not used for eMMC) */ 5102 #define SDHC_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u 5103 /* Basically the max packet size, which gets double buffered in RAM 0: 512B 5104 (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for 5105 data) */ 5106 #define SDHC_CORE_MAX_BLK_SIZE 0u 5107 /* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this 5108 adds 288 bytes of space to the RAM for this purpose. */ 5109 #define SDHC_CORE_CQE_PRESENT 0u 5110 /* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have 5111 the Retention flag (Note, CTL.ENABLE is always retained irrespective of this 5112 parameter) */ 5113 #define SDHC_CORE_RETENTION_PRESENT 0u 5114 /* SONOS Flash is used or not ('0': no, '1': yes) */ 5115 #define SFLASH_FLASHC_IS_SONOS 0u 5116 /* WOUND_PRESENT or not ('0': no, '1': yes) */ 5117 #define SFLASH_WOUND_PRESENT 1u 5118 /* Base address of the SMIF XIP memory region. This address must be a multiple of 5119 the SMIF XIP memory capacity. This address must be a multiple of the SMIF XIP 5120 memory region capacity (see SMIP_XIP_MASK below). The SMIF XIP memory region 5121 should NOT overlap with other memory regions. This adress must be in the 5122 [0x0000:0000, 0xffff:0000] memory region. However, for MXS40 CM4 based 5123 platform variant, this address must be in the [0x0000:0000, 0x1fff:0000] 5124 memory region (to ensure a connection to the ARM CM4 CPU ICode/DCode memory 5125 region [0x0000:0000, 0x1fff:ffff]). The external memory devices are located 5126 within the SMIF XIP memory region. */ 5127 #define SMIF_SMIF_XIP_ADDR 0x60000000u 5128 /* Capacity of the SMIF XIP memory region. The capacity must be a power of 2 and 5129 greater or equal than 64 KB). The more significant bits of this parameter are 5130 '1' and the lesser significant bits of this parameter are '0'. E.g., 5131 0xfff0:0000 specifies a 1 MB memory region. Legal values are {0xffff:0000, 5132 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, 0xffe0:0000, ..., 5133 0x8000:0000, 0x0000:0000}. */ 5134 #define SMIF_SMIF_XIP_MASK 0xF8000000u 5135 /* Cryptography (AES) support. This is a 1-bit parameter: '0' = no support, '1' = 5136 support. */ 5137 #define SMIF_CRYPTO 1u 5138 /* Bus CRC support is present ([0,1]) Note: In MXS40 SMIF version 2 this option is 5139 currently not available (BUS_CRC_PRESENT=0). Based on project schedules this 5140 feature may be added already to MXS40 SMIF version 2 or to a later SMIF 5141 version. */ 5142 #define SMIF_BUS_CRC_PRESENT 0u 5143 /* Number of external memory devices supported. This parameter is in the range 5144 [1,4]. */ 5145 #define SMIF_DEVICE_NR 2u 5146 /* External memory devices write support. This is a 4-bit field. Each external 5147 memory device has a dedicated bit. E.g., if bit 2 is '1', external device 2 5148 has write support. */ 5149 #define SMIF_DEVICE_WR_EN 3u 5150 /* Number of delay lines ([1..8]). */ 5151 #define SMIF_DELAY_LINES_NR 4u 5152 /* Number of delay taps in clock delay line. */ 5153 #define SMIF_DELAY_TAPS_NR 32u 5154 /* AXI ID width. Legal range [11,16] */ 5155 #define SMIF_AXIS_ID_WIDTH 12u 5156 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 5157 #define SMIF_MASTER_WIDTH 8u 5158 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data 5159 pins) */ 5160 #define SMIF_CHIP_TOP_DATA8_PRESENT 1u 5161 /* Number of used spi_select signals (max 4) */ 5162 #define SMIF_CHIP_TOP_SPI_SEL_NR 2u 5163 /* ULP variant. Must be 1 when targeting S40S and 0 otherwise. */ 5164 #define SRSS_ULP_VARIANT 0u 5165 /* HT variant. Must be 1 when targeting S40E and 0 otherwise. */ 5166 #define SRSS_HT_VARIANT 1u 5167 /* Number of regulator modules instantiated within SRSS. Must be > 0. */ 5168 #define SRSS_NUM_ACTREG_PWRMOD 6u 5169 /* Number of shorting switches between vccd and vccact. Must be > 0. */ 5170 #define SRSS_NUM_ACTIVE_SWITCH 6u 5171 /* ULP linear regulator system is present */ 5172 #define SRSS_ULPLINREG_PRESENT 0u 5173 /* HT linear regulator system is present */ 5174 #define SRSS_HTLINREG_PRESENT 1u 5175 /* SIMO buck core regulator is present. Only compatible with ULP linear regulator 5176 system (ULPLINREG_PRESENT==1). */ 5177 #define SRSS_SIMOBUCK_PRESENT 0u 5178 /* Precision ILO (PILO) is present */ 5179 #define SRSS_PILO_PRESENT 0u 5180 /* External Crystal Oscillator is present (high frequency) */ 5181 #define SRSS_ECO_PRESENT 1u 5182 /* System Buck-Boost is present */ 5183 #define SRSS_SYSBB_PRESENT 0u 5184 /* Number of PWR_HIB_DATA registers. Min is zero. */ 5185 #define SRSS_NUM_HIBDATA 1u 5186 /* Number of clock paths. Must be > 0. Recommend 5187 NUM_CLKPATH>=NUM_TOTAL_PLL+CSV_PRESENT+2. CSV and FLL requires special paths, 5188 and one extra is recommended for programming flexibility. */ 5189 #define SRSS_NUM_CLKPATH 7u 5190 /* Number of 200MHz PLLs present. */ 5191 #define SRSS_NUM_PLL 2u 5192 /* Number of HFCLK roots present. Must be > 0. Recommend NUM_HFROOT=<# chipwide 5193 roots>+CSV_PRESENT. */ 5194 #define SRSS_NUM_HFROOT 8u 5195 /* Number of DSI inputs into clock muxes. This is used for logic optimization. 5196 Must be > 0 */ 5197 #define SRSS_NUM_DSI 0u 5198 /* Alternate high-frequency clock is present. This is used for logic optimization. */ 5199 #define SRSS_ALTHF_PRESENT 0u 5200 /* Alternate low-frequency clock is present. This is used for logic optimization. */ 5201 #define SRSS_ALTLF_PRESENT 0u 5202 /* Backup domain is present. See VBCK_PRESENT for whether it is supplied by vddd 5203 or by an independent vbackup supply. */ 5204 #define SRSS_BACKUP_PRESENT 1u 5205 /* CSV present. User must add one NUM_CLKPATH and one NUM_HFROOT to monitor ILO0 5206 with CSV_HF_REF clock. */ 5207 #define SRSS_CSV_PRESENT 1u 5208 /* Number of multi-counter watchdog timers. Min is zero. */ 5209 #define SRSS_NUM_MCWDT 3u 5210 /* Use the hardened clkactfllmux block */ 5211 #define SRSS_USE_HARD_CLKACTFLLMUX 1u 5212 /* Number of clock paths, including direct paths in hardened clkactfllmux block */ 5213 #define SRSS_HARD_CLKPATH 8u 5214 /* Number of clock paths with muxes in hardened clkactfllmux block */ 5215 #define SRSS_HARD_CLKPATHMUX 8u 5216 /* Number of HFCLKS present in hardened clkactfllmux block */ 5217 #define SRSS_HARD_HFROOT 8u 5218 /* ECO mux is present in hardened clkactfllmux block */ 5219 #define SRSS_HARD_ECOMUX_PRESENT 1u 5220 /* ALTHF mux is present in hardened clkactfllmux block */ 5221 #define SRSS_HARD_ALTHFMUX_PRESENT 1u 5222 /* POR present. */ 5223 #define SRSS_POR_PRESENT 1u 5224 /* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT 5225 or SIMOBUCK_PRESENT. */ 5226 #define SRSS_BUCKCTL_PRESENT 0u 5227 /* Low-current SISO buck core regulator is present. Only compatible with ULP 5228 linear regulator system (ULPLINREG_PRESENT==1). */ 5229 #define SRSS_S40S_SISOBUCKLC_PRESENT 0u 5230 /* HT linear regulator system is present */ 5231 #define SRSS_S40E_HTREGHC_PRESENT 1u 5232 /* LPECO mux is present in hardened clkactfllmux block */ 5233 #define SRSS_HARD_LPECOMUX_PRESENT 1u 5234 /* Number of 400MHz PLLs present. */ 5235 #define SRSS_NUM_PLL400M 2u 5236 /* Mask of DIRECT_MUX defaults. For each clock root i, if bit[i] is low the 5237 DIRECT_MUX defaults to IMO. If bit[0] is high, the DIRECT_MUX selects the 5238 output of ROOT_MUX. For backward compatibility, M4 systems can have all mask 5239 bits high. BootROM needs either Bit0 high or a code change to pick predivider 5240 output before using the FLL. */ 5241 #define SRSS_MASK_DIRECTMUX_DEF 1u 5242 /* Mask of which HFCLK roots are enabled when the debugger requests power up 5243 (CDBGPWRUPREQ). For each clock root i, SRSS enables the clock in response to 5244 CDBGPWRUPREQ, if bit[i] of mask is high. SRSS automatically enables clk_hf0, 5245 regardless of setting of mask bit0. */ 5246 #define SRSS_MASK_DEBUG_CLK 0x0000FFFFu 5247 /* Total number of PLLs present. Must be calculated (NUM_PLL+NUM_PLL400M). Cannot 5248 exceed max or NUM_CLKPATH. */ 5249 #define SRSS_NUM_TOTAL_PLL 4u 5250 /* PMIC control of vccd is present (without REGHC). */ 5251 #define SRSS_S40E_PMIC_PRESENT 0u 5252 /* Separate power supply Vbackup is present (only used when BACKUP_PRESENT==1) */ 5253 #define SRSS_BACKUP_VBCK_PRESENT 0u 5254 /* Alarm1 present in RTC */ 5255 #define SRSS_BACKUP_ALM1_PRESENT 1u 5256 /* Alarm2 present in RTC */ 5257 #define SRSS_BACKUP_ALM2_PRESENT 1u 5258 /* Backup memory is present (only used when BACKUP_PRESENT==1) */ 5259 #define SRSS_BACKUP_BMEM_PRESENT 0u 5260 /* Number of Backup registers to include (each is 32b). Only used when 5261 BACKUP_PRESENT==1. Approximate size is 850squm per register. */ 5262 #define SRSS_BACKUP_NUM_BREG 4u 5263 /* Low power external crystal oscillator (LPECO) is present. */ 5264 #define SRSS_BACKUP_S40E_LPECO_PRESENT 0u 5265 /* ULP variant. Must be 1 when targeting S40S and 0 otherwise. */ 5266 #define SRSS_CLK_TRIM_PLL400M_ULP_VARIANT 0u 5267 /* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of 5268 mask indicates presence of a CSV. */ 5269 #define SRSS_CSV_HF_MASK_HFCSV 255u 5270 /* Number of input triggers per counter only routed to one counter (0..8) */ 5271 #define TCPWM0_TR_ONE_CNT_NR 3u 5272 /* Number of input triggers routed to all counters (0..254), 5273 NR_TR_ONE_CNT+NR_TR_ALL CNT <= 254 */ 5274 #define TCPWM0_TR_ALL_CNT_NR 12u 5275 /* Number of TCPWM counter groups (1..4) */ 5276 #define TCPWM0_GRP_NR 3u 5277 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 5278 #define TCPWM0_GRP_NR0_CNT_GRP_CNT_WIDTH 16u 5279 /* Second Capture / Compare Unit is present (0, 1) */ 5280 #define TCPWM0_GRP_NR0_CNT_GRP_CC1_PRESENT 1u 5281 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 5282 GRP_CC1_PRESENT = 1 */ 5283 #define TCPWM0_GRP_NR0_CNT_GRP_AMC_PRESENT 0u 5284 /* Stepper Motor Control features are present (0, 1). */ 5285 #define TCPWM0_GRP_NR0_CNT_GRP_SMC_PRESENT 0u 5286 /* Number of counters per TCPWM group (1..256) */ 5287 #define TCPWM0_GRP_NR0_GRP_GRP_CNT_NR 3u 5288 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 5289 #define TCPWM0_GRP_NR1_CNT_GRP_CNT_WIDTH 16u 5290 /* Second Capture / Compare Unit is present (0, 1) */ 5291 #define TCPWM0_GRP_NR1_CNT_GRP_CC1_PRESENT 1u 5292 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 5293 GRP_CC1_PRESENT = 1 */ 5294 #define TCPWM0_GRP_NR1_CNT_GRP_AMC_PRESENT 1u 5295 /* Stepper Motor Control features are present (0, 1). */ 5296 #define TCPWM0_GRP_NR1_CNT_GRP_SMC_PRESENT 1u 5297 /* Number of counters per TCPWM group (1..256) */ 5298 #define TCPWM0_GRP_NR1_GRP_GRP_CNT_NR 3u 5299 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 5300 #define TCPWM0_GRP_NR2_CNT_GRP_CNT_WIDTH 32u 5301 /* Second Capture / Compare Unit is present (0, 1) */ 5302 #define TCPWM0_GRP_NR2_CNT_GRP_CC1_PRESENT 1u 5303 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 5304 GRP_CC1_PRESENT = 1 */ 5305 #define TCPWM0_GRP_NR2_CNT_GRP_AMC_PRESENT 0u 5306 /* Stepper Motor Control features are present (0, 1). */ 5307 #define TCPWM0_GRP_NR2_CNT_GRP_SMC_PRESENT 0u 5308 /* Number of counters per TCPWM group (1..256) */ 5309 #define TCPWM0_GRP_NR2_GRP_GRP_CNT_NR 3u 5310 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 5311 #define TCPWM0_MASTER_WIDTH 8u 5312 /* Number of input triggers per counter only routed to one counter (0..8) */ 5313 #define TCPWM1_TR_ONE_CNT_NR 3u 5314 /* Number of input triggers routed to all counters (0..254), 5315 NR_TR_ONE_CNT+NR_TR_ALL CNT <= 254 */ 5316 #define TCPWM1_TR_ALL_CNT_NR 41u 5317 /* Number of TCPWM counter groups (1..4) */ 5318 #define TCPWM1_GRP_NR 3u 5319 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 5320 #define TCPWM1_GRP_NR0_CNT_GRP_CNT_WIDTH 16u 5321 /* Second Capture / Compare Unit is present (0, 1) */ 5322 #define TCPWM1_GRP_NR0_CNT_GRP_CC1_PRESENT 1u 5323 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 5324 GRP_CC1_PRESENT = 1 */ 5325 #define TCPWM1_GRP_NR0_CNT_GRP_AMC_PRESENT 0u 5326 /* Stepper Motor Control features are present (0, 1). */ 5327 #define TCPWM1_GRP_NR0_CNT_GRP_SMC_PRESENT 0u 5328 /* Number of counters per TCPWM group (1..256) */ 5329 #define TCPWM1_GRP_NR0_GRP_GRP_CNT_NR 84u 5330 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 5331 #define TCPWM1_GRP_NR1_CNT_GRP_CNT_WIDTH 16u 5332 /* Second Capture / Compare Unit is present (0, 1) */ 5333 #define TCPWM1_GRP_NR1_CNT_GRP_CC1_PRESENT 1u 5334 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 5335 GRP_CC1_PRESENT = 1 */ 5336 #define TCPWM1_GRP_NR1_CNT_GRP_AMC_PRESENT 1u 5337 /* Stepper Motor Control features are present (0, 1). */ 5338 #define TCPWM1_GRP_NR1_CNT_GRP_SMC_PRESENT 1u 5339 /* Number of counters per TCPWM group (1..256) */ 5340 #define TCPWM1_GRP_NR1_GRP_GRP_CNT_NR 12u 5341 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 5342 #define TCPWM1_GRP_NR2_CNT_GRP_CNT_WIDTH 32u 5343 /* Second Capture / Compare Unit is present (0, 1) */ 5344 #define TCPWM1_GRP_NR2_CNT_GRP_CC1_PRESENT 1u 5345 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 5346 GRP_CC1_PRESENT = 1 */ 5347 #define TCPWM1_GRP_NR2_CNT_GRP_AMC_PRESENT 0u 5348 /* Stepper Motor Control features are present (0, 1). */ 5349 #define TCPWM1_GRP_NR2_CNT_GRP_SMC_PRESENT 0u 5350 /* Number of counters per TCPWM group (1..256) */ 5351 #define TCPWM1_GRP_NR2_GRP_GRP_CNT_NR 13u 5352 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 5353 #define TCPWM1_MASTER_WIDTH 8u 5354 5355 /* MMIO Targets Defines */ 5356 /* MMIO1.CRYPTO */ 5357 #define CY_MMIO_CRYPTO_GROUP_NR 1u 5358 #define CY_MMIO_CRYPTO_SLAVE_NR 0u 5359 /* MMIO2.CPUSS */ 5360 #define CY_MMIO_CPUSS_GROUP_NR 2u 5361 #define CY_MMIO_CPUSS_SLAVE_NR 0u 5362 /* MMIO2.FAULT */ 5363 #define CY_MMIO_FAULT_GROUP_NR 2u 5364 #define CY_MMIO_FAULT_SLAVE_NR 1u 5365 /* MMIO2.IPC */ 5366 #define CY_MMIO_IPC_GROUP_NR 2u 5367 #define CY_MMIO_IPC_SLAVE_NR 2u 5368 /* MMIO2.PROT */ 5369 #define CY_MMIO_PROT_GROUP_NR 2u 5370 #define CY_MMIO_PROT_SLAVE_NR 3u 5371 /* MMIO2.FLASHC */ 5372 #define CY_MMIO_FLASHC_GROUP_NR 2u 5373 #define CY_MMIO_FLASHC_SLAVE_NR 4u 5374 /* MMIO2.SRSS */ 5375 #define CY_MMIO_SRSS_GROUP_NR 2u 5376 #define CY_MMIO_SRSS_SLAVE_NR 5u 5377 /* MMIO2.BACKUP */ 5378 #define CY_MMIO_BACKUP_GROUP_NR 2u 5379 #define CY_MMIO_BACKUP_SLAVE_NR 6u 5380 /* MMIO2.DW */ 5381 #define CY_MMIO_DW_GROUP_NR 2u 5382 #define CY_MMIO_DW_SLAVE_NR 7u 5383 /* MMIO2.DMAC */ 5384 #define CY_MMIO_DMAC_GROUP_NR 2u 5385 #define CY_MMIO_DMAC_SLAVE_NR 9u 5386 /* MMIO2.EFUSE */ 5387 #define CY_MMIO_EFUSE_GROUP_NR 2u 5388 #define CY_MMIO_EFUSE_SLAVE_NR 10u 5389 /* MMIO2.DFT */ 5390 #define CY_MMIO_DFT_GROUP_NR 2u 5391 #define CY_MMIO_DFT_SLAVE_NR 11u 5392 /* MMIO3.HSIOM */ 5393 #define CY_MMIO_HSIOM_GROUP_NR 3u 5394 #define CY_MMIO_HSIOM_SLAVE_NR 0u 5395 /* MMIO3.GPIO */ 5396 #define CY_MMIO_GPIO_GROUP_NR 3u 5397 #define CY_MMIO_GPIO_SLAVE_NR 1u 5398 /* MMIO3.SMARTIO */ 5399 #define CY_MMIO_SMARTIO_GROUP_NR 3u 5400 #define CY_MMIO_SMARTIO_SLAVE_NR 2u 5401 /* MMIO3.TCPWM0 */ 5402 #define CY_MMIO_TCPWM0_GROUP_NR 3u 5403 #define CY_MMIO_TCPWM0_SLAVE_NR 3u 5404 /* MMIO3.EVTGEN0 */ 5405 #define CY_MMIO_EVTGEN0_GROUP_NR 3u 5406 #define CY_MMIO_EVTGEN0_SLAVE_NR 4u 5407 /* MMIO4.SMIF0 */ 5408 #define CY_MMIO_SMIF0_GROUP_NR 4u 5409 #define CY_MMIO_SMIF0_SLAVE_NR 0u 5410 /* MMIO4.SDHC0 */ 5411 #define CY_MMIO_SDHC0_GROUP_NR 4u 5412 #define CY_MMIO_SDHC0_SLAVE_NR 1u 5413 /* MMIO4.ETH0 */ 5414 #define CY_MMIO_ETH0_GROUP_NR 4u 5415 #define CY_MMIO_ETH0_SLAVE_NR 2u 5416 /* MMIO4.ETH1 */ 5417 #define CY_MMIO_ETH1_GROUP_NR 4u 5418 #define CY_MMIO_ETH1_SLAVE_NR 3u 5419 /* MMIO5.LIN0 */ 5420 #define CY_MMIO_LIN0_GROUP_NR 5u 5421 #define CY_MMIO_LIN0_SLAVE_NR 0u 5422 /* MMIO5.CANFD0 */ 5423 #define CY_MMIO_CANFD0_GROUP_NR 5u 5424 #define CY_MMIO_CANFD0_SLAVE_NR 1u 5425 /* MMIO5.CANFD1 */ 5426 #define CY_MMIO_CANFD1_GROUP_NR 5u 5427 #define CY_MMIO_CANFD1_SLAVE_NR 2u 5428 /* MMIO5.FLEXRAY0 */ 5429 #define CY_MMIO_FLEXRAY0_GROUP_NR 5u 5430 #define CY_MMIO_FLEXRAY0_SLAVE_NR 3u 5431 /* MMIO5.TCPWM1 */ 5432 #define CY_MMIO_TCPWM1_GROUP_NR 5u 5433 #define CY_MMIO_TCPWM1_SLAVE_NR 4u 5434 /* MMIO6.SCB0 */ 5435 #define CY_MMIO_SCB0_GROUP_NR 6u 5436 #define CY_MMIO_SCB0_SLAVE_NR 0u 5437 /* MMIO6.SCB1 */ 5438 #define CY_MMIO_SCB1_GROUP_NR 6u 5439 #define CY_MMIO_SCB1_SLAVE_NR 1u 5440 /* MMIO6.SCB2 */ 5441 #define CY_MMIO_SCB2_GROUP_NR 6u 5442 #define CY_MMIO_SCB2_SLAVE_NR 2u 5443 /* MMIO6.SCB3 */ 5444 #define CY_MMIO_SCB3_GROUP_NR 6u 5445 #define CY_MMIO_SCB3_SLAVE_NR 3u 5446 /* MMIO6.SCB4 */ 5447 #define CY_MMIO_SCB4_GROUP_NR 6u 5448 #define CY_MMIO_SCB4_SLAVE_NR 4u 5449 /* MMIO6.SCB5 */ 5450 #define CY_MMIO_SCB5_GROUP_NR 6u 5451 #define CY_MMIO_SCB5_SLAVE_NR 5u 5452 /* MMIO6.SCB6 */ 5453 #define CY_MMIO_SCB6_GROUP_NR 6u 5454 #define CY_MMIO_SCB6_SLAVE_NR 6u 5455 /* MMIO6.SCB7 */ 5456 #define CY_MMIO_SCB7_GROUP_NR 6u 5457 #define CY_MMIO_SCB7_SLAVE_NR 7u 5458 /* MMIO6.SCB8 */ 5459 #define CY_MMIO_SCB8_GROUP_NR 6u 5460 #define CY_MMIO_SCB8_SLAVE_NR 8u 5461 /* MMIO6.SCB9 */ 5462 #define CY_MMIO_SCB9_GROUP_NR 6u 5463 #define CY_MMIO_SCB9_SLAVE_NR 9u 5464 /* MMIO6.SCB10 */ 5465 #define CY_MMIO_SCB10_GROUP_NR 6u 5466 #define CY_MMIO_SCB10_SLAVE_NR 10u 5467 /* MMIO8.I2S0 */ 5468 #define CY_MMIO_I2S0_GROUP_NR 8u 5469 #define CY_MMIO_I2S0_SLAVE_NR 0u 5470 /* MMIO8.I2S1 */ 5471 #define CY_MMIO_I2S1_GROUP_NR 8u 5472 #define CY_MMIO_I2S1_SLAVE_NR 1u 5473 /* MMIO8.I2S2 */ 5474 #define CY_MMIO_I2S2_GROUP_NR 8u 5475 #define CY_MMIO_I2S2_SLAVE_NR 2u 5476 /* MMIO9.PASS0 */ 5477 #define CY_MMIO_PASS0_GROUP_NR 9u 5478 #define CY_MMIO_PASS0_SLAVE_NR 0u 5479 5480 /* Protection regions */ 5481 typedef enum 5482 { 5483 PROT_PERI_MAIN = 0, /* Address 0x40000200, size 0x00000040 */ 5484 PROT_PERI_SECURE = 1, /* Address 0x40002000, size 0x00000004 */ 5485 PROT_PERI_GR0_GROUP = 2, /* Address 0x40004010, size 0x00000004 */ 5486 PROT_PERI_GR1_GROUP = 3, /* Address 0x40004050, size 0x00000004 */ 5487 PROT_PERI_GR2_GROUP = 4, /* Address 0x40004090, size 0x00000004 */ 5488 PROT_PERI_GR3_GROUP = 5, /* Address 0x400040c0, size 0x00000020 */ 5489 PROT_PERI_GR4_GROUP = 6, /* Address 0x40004100, size 0x00000020 */ 5490 PROT_PERI_GR5_GROUP = 7, /* Address 0x40004140, size 0x00000020 */ 5491 PROT_PERI_GR6_GROUP = 8, /* Address 0x40004180, size 0x00000020 */ 5492 PROT_PERI_GR8_GROUP = 9, /* Address 0x40004200, size 0x00000020 */ 5493 PROT_PERI_GR9_GROUP = 10, /* Address 0x40004240, size 0x00000020 */ 5494 PROT_PERI_GR0_BOOT = 11, /* Address 0x40004020, size 0x00000004 */ 5495 PROT_PERI_GR1_BOOT = 12, /* Address 0x40004060, size 0x00000004 */ 5496 PROT_PERI_GR2_BOOT = 13, /* Address 0x400040a0, size 0x00000004 */ 5497 PROT_PERI_GR3_BOOT = 14, /* Address 0x400040e0, size 0x00000004 */ 5498 PROT_PERI_GR4_BOOT = 15, /* Address 0x40004120, size 0x00000004 */ 5499 PROT_PERI_GR5_BOOT = 16, /* Address 0x40004160, size 0x00000004 */ 5500 PROT_PERI_GR6_BOOT = 17, /* Address 0x400041a0, size 0x00000004 */ 5501 PROT_PERI_GR8_BOOT = 18, /* Address 0x40004220, size 0x00000004 */ 5502 PROT_PERI_GR9_BOOT = 19, /* Address 0x40004260, size 0x00000004 */ 5503 PROT_PERI_TR = 20, /* Address 0x40008000, size 0x00008000 */ 5504 PROT_PERI_MS_BOOT = 21, /* Address 0x40030000, size 0x00001000 */ 5505 PROT_PERI_PCLK_MAIN = 22, /* Address 0x40040000, size 0x00004000 */ 5506 PROT_CRYPTO_MAIN = 23, /* Address 0x40100000, size 0x00000400 */ 5507 PROT_CRYPTO_CRYPTO = 24, /* Address 0x40101000, size 0x00000800 */ 5508 PROT_CRYPTO_BOOT = 25, /* Address 0x40102000, size 0x00000100 */ 5509 PROT_CRYPTO_KEY0 = 26, /* Address 0x40102100, size 0x00000004 */ 5510 PROT_CRYPTO_KEY1 = 27, /* Address 0x40102120, size 0x00000004 */ 5511 PROT_CRYPTO_BUF = 28, /* Address 0x40108000, size 0x00002000 */ 5512 PROT_CPUSS_CM7_0 = 29, /* Address 0x40200000, size 0x00000400 */ 5513 PROT_CPUSS_CM7_1 = 30, /* Address 0x40200400, size 0x00000400 */ 5514 PROT_CPUSS_CM0 = 31, /* Address 0x40201000, size 0x00001000 */ 5515 PROT_CPUSS_BOOT = 32, /* Address 0x40202000, size 0x00000200 */ 5516 PROT_CPUSS_CM0_INT = 33, /* Address 0x40208000, size 0x00001000 */ 5517 PROT_CPUSS_CM7_0_INT = 34, /* Address 0x4020a000, size 0x00001000 */ 5518 PROT_CPUSS_CM7_1_INT = 35, /* Address 0x4020c000, size 0x00001000 */ 5519 PROT_FAULT_STRUCT0_MAIN = 36, /* Address 0x40210000, size 0x00000100 */ 5520 PROT_FAULT_STRUCT1_MAIN = 37, /* Address 0x40210100, size 0x00000100 */ 5521 PROT_FAULT_STRUCT2_MAIN = 38, /* Address 0x40210200, size 0x00000100 */ 5522 PROT_FAULT_STRUCT3_MAIN = 39, /* Address 0x40210300, size 0x00000100 */ 5523 PROT_IPC_STRUCT0_IPC = 40, /* Address 0x40220000, size 0x00000020 */ 5524 PROT_IPC_STRUCT1_IPC = 41, /* Address 0x40220020, size 0x00000020 */ 5525 PROT_IPC_STRUCT2_IPC = 42, /* Address 0x40220040, size 0x00000020 */ 5526 PROT_IPC_STRUCT3_IPC = 43, /* Address 0x40220060, size 0x00000020 */ 5527 PROT_IPC_STRUCT4_IPC = 44, /* Address 0x40220080, size 0x00000020 */ 5528 PROT_IPC_STRUCT5_IPC = 45, /* Address 0x402200a0, size 0x00000020 */ 5529 PROT_IPC_STRUCT6_IPC = 46, /* Address 0x402200c0, size 0x00000020 */ 5530 PROT_IPC_STRUCT7_IPC = 47, /* Address 0x402200e0, size 0x00000020 */ 5531 PROT_IPC_INTR_STRUCT0_INTR = 48, /* Address 0x40221000, size 0x00000010 */ 5532 PROT_IPC_INTR_STRUCT1_INTR = 49, /* Address 0x40221020, size 0x00000010 */ 5533 PROT_IPC_INTR_STRUCT2_INTR = 50, /* Address 0x40221040, size 0x00000010 */ 5534 PROT_IPC_INTR_STRUCT3_INTR = 51, /* Address 0x40221060, size 0x00000010 */ 5535 PROT_IPC_INTR_STRUCT4_INTR = 52, /* Address 0x40221080, size 0x00000010 */ 5536 PROT_IPC_INTR_STRUCT5_INTR = 53, /* Address 0x402210a0, size 0x00000010 */ 5537 PROT_IPC_INTR_STRUCT6_INTR = 54, /* Address 0x402210c0, size 0x00000010 */ 5538 PROT_IPC_INTR_STRUCT7_INTR = 55, /* Address 0x402210e0, size 0x00000010 */ 5539 PROT_PROT_SMPU_MAIN = 56, /* Address 0x40230000, size 0x00000040 */ 5540 PROT_PROT_MPU0_MAIN = 57, /* Address 0x40234000, size 0x00000004 */ 5541 PROT_PROT_MPU5_MAIN = 58, /* Address 0x40235400, size 0x00000400 */ 5542 PROT_PROT_MPU9_MAIN = 59, /* Address 0x40236400, size 0x00000400 */ 5543 PROT_PROT_MPU10_MAIN = 60, /* Address 0x40236800, size 0x00000400 */ 5544 PROT_PROT_MPU13_MAIN = 61, /* Address 0x40237400, size 0x00000004 */ 5545 PROT_PROT_MPU14_MAIN = 62, /* Address 0x40237800, size 0x00000004 */ 5546 PROT_PROT_MPU15_MAIN = 63, /* Address 0x40237c00, size 0x00000400 */ 5547 PROT_FLASHC_MAIN = 64, /* Address 0x40240000, size 0x00000008 */ 5548 PROT_FLASHC_CMD = 65, /* Address 0x40240008, size 0x00000004 */ 5549 PROT_FLASHC_DFT = 66, /* Address 0x40240200, size 0x00000100 */ 5550 PROT_FLASHC_CM0 = 67, /* Address 0x40240400, size 0x00000080 */ 5551 PROT_FLASHC_CM7_0 = 68, /* Address 0x402404e0, size 0x00000004 */ 5552 PROT_FLASHC_CM7_1 = 69, /* Address 0x40240560, size 0x00000004 */ 5553 PROT_FLASHC_CRYPTO = 70, /* Address 0x40240580, size 0x00000004 */ 5554 PROT_FLASHC_DW0 = 71, /* Address 0x40240600, size 0x00000004 */ 5555 PROT_FLASHC_DW1 = 72, /* Address 0x40240680, size 0x00000004 */ 5556 PROT_FLASHC_DMAC = 73, /* Address 0x40240700, size 0x00000004 */ 5557 PROT_FLASHC_SLOW0 = 74, /* Address 0x40240780, size 0x00000004 */ 5558 PROT_FLASHC_FlashMgmt = 75, /* Address 0x4024f000, size 0x00000080 */ 5559 PROT_FLASHC_MainSafety = 76, /* Address 0x4024f400, size 0x00000008 */ 5560 PROT_FLASHC_WorkSafety = 77, /* Address 0x4024f500, size 0x00000004 */ 5561 PROT_SRSS_GENERAL = 78, /* Address 0x40260000, size 0x00000400 */ 5562 PROT_SRSS_MAIN = 79, /* Address 0x40261000, size 0x00001000 */ 5563 PROT_SRSS_SECURE = 80, /* Address 0x40262000, size 0x00002000 */ 5564 PROT_MCWDT0_CONFIG = 81, /* Address 0x40268000, size 0x00000080 */ 5565 PROT_MCWDT1_CONFIG = 82, /* Address 0x40268100, size 0x00000080 */ 5566 PROT_MCWDT2_CONFIG = 83, /* Address 0x40268200, size 0x00000080 */ 5567 PROT_MCWDT0_MAIN = 84, /* Address 0x40268080, size 0x00000040 */ 5568 PROT_MCWDT1_MAIN = 85, /* Address 0x40268180, size 0x00000040 */ 5569 PROT_MCWDT2_MAIN = 86, /* Address 0x40268280, size 0x00000040 */ 5570 PROT_WDT_CONFIG = 87, /* Address 0x4026c000, size 0x00000020 */ 5571 PROT_WDT_MAIN = 88, /* Address 0x4026c040, size 0x00000020 */ 5572 PROT_BACKUP_BACKUP = 89, /* Address 0x40270000, size 0x00010000 */ 5573 PROT_DW0_DW = 90, /* Address 0x40280000, size 0x00000100 */ 5574 PROT_DW1_DW = 91, /* Address 0x40290000, size 0x00000100 */ 5575 PROT_DW0_DW_CRC = 92, /* Address 0x40280100, size 0x00000080 */ 5576 PROT_DW1_DW_CRC = 93, /* Address 0x40290100, size 0x00000080 */ 5577 PROT_DW0_CH_STRUCT0_CH = 94, /* Address 0x40288000, size 0x00000040 */ 5578 PROT_DW0_CH_STRUCT1_CH = 95, /* Address 0x40288040, size 0x00000040 */ 5579 PROT_DW0_CH_STRUCT2_CH = 96, /* Address 0x40288080, size 0x00000040 */ 5580 PROT_DW0_CH_STRUCT3_CH = 97, /* Address 0x402880c0, size 0x00000040 */ 5581 PROT_DW0_CH_STRUCT4_CH = 98, /* Address 0x40288100, size 0x00000040 */ 5582 PROT_DW0_CH_STRUCT5_CH = 99, /* Address 0x40288140, size 0x00000040 */ 5583 PROT_DW0_CH_STRUCT6_CH = 100, /* Address 0x40288180, size 0x00000040 */ 5584 PROT_DW0_CH_STRUCT7_CH = 101, /* Address 0x402881c0, size 0x00000040 */ 5585 PROT_DW0_CH_STRUCT8_CH = 102, /* Address 0x40288200, size 0x00000040 */ 5586 PROT_DW0_CH_STRUCT9_CH = 103, /* Address 0x40288240, size 0x00000040 */ 5587 PROT_DW0_CH_STRUCT10_CH = 104, /* Address 0x40288280, size 0x00000040 */ 5588 PROT_DW0_CH_STRUCT11_CH = 105, /* Address 0x402882c0, size 0x00000040 */ 5589 PROT_DW0_CH_STRUCT12_CH = 106, /* Address 0x40288300, size 0x00000040 */ 5590 PROT_DW0_CH_STRUCT13_CH = 107, /* Address 0x40288340, size 0x00000040 */ 5591 PROT_DW0_CH_STRUCT14_CH = 108, /* Address 0x40288380, size 0x00000040 */ 5592 PROT_DW0_CH_STRUCT15_CH = 109, /* Address 0x402883c0, size 0x00000040 */ 5593 PROT_DW0_CH_STRUCT16_CH = 110, /* Address 0x40288400, size 0x00000040 */ 5594 PROT_DW0_CH_STRUCT17_CH = 111, /* Address 0x40288440, size 0x00000040 */ 5595 PROT_DW0_CH_STRUCT18_CH = 112, /* Address 0x40288480, size 0x00000040 */ 5596 PROT_DW0_CH_STRUCT19_CH = 113, /* Address 0x402884c0, size 0x00000040 */ 5597 PROT_DW0_CH_STRUCT20_CH = 114, /* Address 0x40288500, size 0x00000040 */ 5598 PROT_DW0_CH_STRUCT21_CH = 115, /* Address 0x40288540, size 0x00000040 */ 5599 PROT_DW0_CH_STRUCT22_CH = 116, /* Address 0x40288580, size 0x00000040 */ 5600 PROT_DW0_CH_STRUCT23_CH = 117, /* Address 0x402885c0, size 0x00000040 */ 5601 PROT_DW0_CH_STRUCT24_CH = 118, /* Address 0x40288600, size 0x00000040 */ 5602 PROT_DW0_CH_STRUCT25_CH = 119, /* Address 0x40288640, size 0x00000040 */ 5603 PROT_DW0_CH_STRUCT26_CH = 120, /* Address 0x40288680, size 0x00000040 */ 5604 PROT_DW0_CH_STRUCT27_CH = 121, /* Address 0x402886c0, size 0x00000040 */ 5605 PROT_DW0_CH_STRUCT28_CH = 122, /* Address 0x40288700, size 0x00000040 */ 5606 PROT_DW0_CH_STRUCT29_CH = 123, /* Address 0x40288740, size 0x00000040 */ 5607 PROT_DW0_CH_STRUCT30_CH = 124, /* Address 0x40288780, size 0x00000040 */ 5608 PROT_DW0_CH_STRUCT31_CH = 125, /* Address 0x402887c0, size 0x00000040 */ 5609 PROT_DW0_CH_STRUCT32_CH = 126, /* Address 0x40288800, size 0x00000040 */ 5610 PROT_DW0_CH_STRUCT33_CH = 127, /* Address 0x40288840, size 0x00000040 */ 5611 PROT_DW0_CH_STRUCT34_CH = 128, /* Address 0x40288880, size 0x00000040 */ 5612 PROT_DW0_CH_STRUCT35_CH = 129, /* Address 0x402888c0, size 0x00000040 */ 5613 PROT_DW0_CH_STRUCT36_CH = 130, /* Address 0x40288900, size 0x00000040 */ 5614 PROT_DW0_CH_STRUCT37_CH = 131, /* Address 0x40288940, size 0x00000040 */ 5615 PROT_DW0_CH_STRUCT38_CH = 132, /* Address 0x40288980, size 0x00000040 */ 5616 PROT_DW0_CH_STRUCT39_CH = 133, /* Address 0x402889c0, size 0x00000040 */ 5617 PROT_DW0_CH_STRUCT40_CH = 134, /* Address 0x40288a00, size 0x00000040 */ 5618 PROT_DW0_CH_STRUCT41_CH = 135, /* Address 0x40288a40, size 0x00000040 */ 5619 PROT_DW0_CH_STRUCT42_CH = 136, /* Address 0x40288a80, size 0x00000040 */ 5620 PROT_DW0_CH_STRUCT43_CH = 137, /* Address 0x40288ac0, size 0x00000040 */ 5621 PROT_DW0_CH_STRUCT44_CH = 138, /* Address 0x40288b00, size 0x00000040 */ 5622 PROT_DW0_CH_STRUCT45_CH = 139, /* Address 0x40288b40, size 0x00000040 */ 5623 PROT_DW0_CH_STRUCT46_CH = 140, /* Address 0x40288b80, size 0x00000040 */ 5624 PROT_DW0_CH_STRUCT47_CH = 141, /* Address 0x40288bc0, size 0x00000040 */ 5625 PROT_DW0_CH_STRUCT48_CH = 142, /* Address 0x40288c00, size 0x00000040 */ 5626 PROT_DW0_CH_STRUCT49_CH = 143, /* Address 0x40288c40, size 0x00000040 */ 5627 PROT_DW0_CH_STRUCT50_CH = 144, /* Address 0x40288c80, size 0x00000040 */ 5628 PROT_DW0_CH_STRUCT51_CH = 145, /* Address 0x40288cc0, size 0x00000040 */ 5629 PROT_DW0_CH_STRUCT52_CH = 146, /* Address 0x40288d00, size 0x00000040 */ 5630 PROT_DW0_CH_STRUCT53_CH = 147, /* Address 0x40288d40, size 0x00000040 */ 5631 PROT_DW0_CH_STRUCT54_CH = 148, /* Address 0x40288d80, size 0x00000040 */ 5632 PROT_DW0_CH_STRUCT55_CH = 149, /* Address 0x40288dc0, size 0x00000040 */ 5633 PROT_DW0_CH_STRUCT56_CH = 150, /* Address 0x40288e00, size 0x00000040 */ 5634 PROT_DW0_CH_STRUCT57_CH = 151, /* Address 0x40288e40, size 0x00000040 */ 5635 PROT_DW0_CH_STRUCT58_CH = 152, /* Address 0x40288e80, size 0x00000040 */ 5636 PROT_DW0_CH_STRUCT59_CH = 153, /* Address 0x40288ec0, size 0x00000040 */ 5637 PROT_DW0_CH_STRUCT60_CH = 154, /* Address 0x40288f00, size 0x00000040 */ 5638 PROT_DW0_CH_STRUCT61_CH = 155, /* Address 0x40288f40, size 0x00000040 */ 5639 PROT_DW0_CH_STRUCT62_CH = 156, /* Address 0x40288f80, size 0x00000040 */ 5640 PROT_DW0_CH_STRUCT63_CH = 157, /* Address 0x40288fc0, size 0x00000040 */ 5641 PROT_DW0_CH_STRUCT64_CH = 158, /* Address 0x40289000, size 0x00000040 */ 5642 PROT_DW0_CH_STRUCT65_CH = 159, /* Address 0x40289040, size 0x00000040 */ 5643 PROT_DW0_CH_STRUCT66_CH = 160, /* Address 0x40289080, size 0x00000040 */ 5644 PROT_DW0_CH_STRUCT67_CH = 161, /* Address 0x402890c0, size 0x00000040 */ 5645 PROT_DW0_CH_STRUCT68_CH = 162, /* Address 0x40289100, size 0x00000040 */ 5646 PROT_DW0_CH_STRUCT69_CH = 163, /* Address 0x40289140, size 0x00000040 */ 5647 PROT_DW0_CH_STRUCT70_CH = 164, /* Address 0x40289180, size 0x00000040 */ 5648 PROT_DW0_CH_STRUCT71_CH = 165, /* Address 0x402891c0, size 0x00000040 */ 5649 PROT_DW0_CH_STRUCT72_CH = 166, /* Address 0x40289200, size 0x00000040 */ 5650 PROT_DW0_CH_STRUCT73_CH = 167, /* Address 0x40289240, size 0x00000040 */ 5651 PROT_DW0_CH_STRUCT74_CH = 168, /* Address 0x40289280, size 0x00000040 */ 5652 PROT_DW0_CH_STRUCT75_CH = 169, /* Address 0x402892c0, size 0x00000040 */ 5653 PROT_DW0_CH_STRUCT76_CH = 170, /* Address 0x40289300, size 0x00000040 */ 5654 PROT_DW0_CH_STRUCT77_CH = 171, /* Address 0x40289340, size 0x00000040 */ 5655 PROT_DW0_CH_STRUCT78_CH = 172, /* Address 0x40289380, size 0x00000040 */ 5656 PROT_DW0_CH_STRUCT79_CH = 173, /* Address 0x402893c0, size 0x00000040 */ 5657 PROT_DW0_CH_STRUCT80_CH = 174, /* Address 0x40289400, size 0x00000040 */ 5658 PROT_DW0_CH_STRUCT81_CH = 175, /* Address 0x40289440, size 0x00000040 */ 5659 PROT_DW0_CH_STRUCT82_CH = 176, /* Address 0x40289480, size 0x00000040 */ 5660 PROT_DW0_CH_STRUCT83_CH = 177, /* Address 0x402894c0, size 0x00000040 */ 5661 PROT_DW0_CH_STRUCT84_CH = 178, /* Address 0x40289500, size 0x00000040 */ 5662 PROT_DW0_CH_STRUCT85_CH = 179, /* Address 0x40289540, size 0x00000040 */ 5663 PROT_DW0_CH_STRUCT86_CH = 180, /* Address 0x40289580, size 0x00000040 */ 5664 PROT_DW0_CH_STRUCT87_CH = 181, /* Address 0x402895c0, size 0x00000040 */ 5665 PROT_DW0_CH_STRUCT88_CH = 182, /* Address 0x40289600, size 0x00000040 */ 5666 PROT_DW0_CH_STRUCT89_CH = 183, /* Address 0x40289640, size 0x00000040 */ 5667 PROT_DW0_CH_STRUCT90_CH = 184, /* Address 0x40289680, size 0x00000040 */ 5668 PROT_DW0_CH_STRUCT91_CH = 185, /* Address 0x402896c0, size 0x00000040 */ 5669 PROT_DW0_CH_STRUCT92_CH = 186, /* Address 0x40289700, size 0x00000040 */ 5670 PROT_DW0_CH_STRUCT93_CH = 187, /* Address 0x40289740, size 0x00000040 */ 5671 PROT_DW0_CH_STRUCT94_CH = 188, /* Address 0x40289780, size 0x00000040 */ 5672 PROT_DW0_CH_STRUCT95_CH = 189, /* Address 0x402897c0, size 0x00000040 */ 5673 PROT_DW0_CH_STRUCT96_CH = 190, /* Address 0x40289800, size 0x00000040 */ 5674 PROT_DW0_CH_STRUCT97_CH = 191, /* Address 0x40289840, size 0x00000040 */ 5675 PROT_DW0_CH_STRUCT98_CH = 192, /* Address 0x40289880, size 0x00000040 */ 5676 PROT_DW0_CH_STRUCT99_CH = 193, /* Address 0x402898c0, size 0x00000040 */ 5677 PROT_DW0_CH_STRUCT100_CH = 194, /* Address 0x40289900, size 0x00000040 */ 5678 PROT_DW0_CH_STRUCT101_CH = 195, /* Address 0x40289940, size 0x00000040 */ 5679 PROT_DW0_CH_STRUCT102_CH = 196, /* Address 0x40289980, size 0x00000040 */ 5680 PROT_DW0_CH_STRUCT103_CH = 197, /* Address 0x402899c0, size 0x00000040 */ 5681 PROT_DW0_CH_STRUCT104_CH = 198, /* Address 0x40289a00, size 0x00000040 */ 5682 PROT_DW0_CH_STRUCT105_CH = 199, /* Address 0x40289a40, size 0x00000040 */ 5683 PROT_DW0_CH_STRUCT106_CH = 200, /* Address 0x40289a80, size 0x00000040 */ 5684 PROT_DW0_CH_STRUCT107_CH = 201, /* Address 0x40289ac0, size 0x00000040 */ 5685 PROT_DW0_CH_STRUCT108_CH = 202, /* Address 0x40289b00, size 0x00000040 */ 5686 PROT_DW0_CH_STRUCT109_CH = 203, /* Address 0x40289b40, size 0x00000040 */ 5687 PROT_DW0_CH_STRUCT110_CH = 204, /* Address 0x40289b80, size 0x00000040 */ 5688 PROT_DW0_CH_STRUCT111_CH = 205, /* Address 0x40289bc0, size 0x00000040 */ 5689 PROT_DW0_CH_STRUCT112_CH = 206, /* Address 0x40289c00, size 0x00000040 */ 5690 PROT_DW0_CH_STRUCT113_CH = 207, /* Address 0x40289c40, size 0x00000040 */ 5691 PROT_DW0_CH_STRUCT114_CH = 208, /* Address 0x40289c80, size 0x00000040 */ 5692 PROT_DW0_CH_STRUCT115_CH = 209, /* Address 0x40289cc0, size 0x00000040 */ 5693 PROT_DW0_CH_STRUCT116_CH = 210, /* Address 0x40289d00, size 0x00000040 */ 5694 PROT_DW0_CH_STRUCT117_CH = 211, /* Address 0x40289d40, size 0x00000040 */ 5695 PROT_DW0_CH_STRUCT118_CH = 212, /* Address 0x40289d80, size 0x00000040 */ 5696 PROT_DW0_CH_STRUCT119_CH = 213, /* Address 0x40289dc0, size 0x00000040 */ 5697 PROT_DW0_CH_STRUCT120_CH = 214, /* Address 0x40289e00, size 0x00000040 */ 5698 PROT_DW0_CH_STRUCT121_CH = 215, /* Address 0x40289e40, size 0x00000040 */ 5699 PROT_DW0_CH_STRUCT122_CH = 216, /* Address 0x40289e80, size 0x00000040 */ 5700 PROT_DW0_CH_STRUCT123_CH = 217, /* Address 0x40289ec0, size 0x00000040 */ 5701 PROT_DW0_CH_STRUCT124_CH = 218, /* Address 0x40289f00, size 0x00000040 */ 5702 PROT_DW0_CH_STRUCT125_CH = 219, /* Address 0x40289f40, size 0x00000040 */ 5703 PROT_DW0_CH_STRUCT126_CH = 220, /* Address 0x40289f80, size 0x00000040 */ 5704 PROT_DW0_CH_STRUCT127_CH = 221, /* Address 0x40289fc0, size 0x00000040 */ 5705 PROT_DW0_CH_STRUCT128_CH = 222, /* Address 0x4028a000, size 0x00000040 */ 5706 PROT_DW0_CH_STRUCT129_CH = 223, /* Address 0x4028a040, size 0x00000040 */ 5707 PROT_DW0_CH_STRUCT130_CH = 224, /* Address 0x4028a080, size 0x00000040 */ 5708 PROT_DW0_CH_STRUCT131_CH = 225, /* Address 0x4028a0c0, size 0x00000040 */ 5709 PROT_DW0_CH_STRUCT132_CH = 226, /* Address 0x4028a100, size 0x00000040 */ 5710 PROT_DW0_CH_STRUCT133_CH = 227, /* Address 0x4028a140, size 0x00000040 */ 5711 PROT_DW0_CH_STRUCT134_CH = 228, /* Address 0x4028a180, size 0x00000040 */ 5712 PROT_DW0_CH_STRUCT135_CH = 229, /* Address 0x4028a1c0, size 0x00000040 */ 5713 PROT_DW0_CH_STRUCT136_CH = 230, /* Address 0x4028a200, size 0x00000040 */ 5714 PROT_DW0_CH_STRUCT137_CH = 231, /* Address 0x4028a240, size 0x00000040 */ 5715 PROT_DW0_CH_STRUCT138_CH = 232, /* Address 0x4028a280, size 0x00000040 */ 5716 PROT_DW0_CH_STRUCT139_CH = 233, /* Address 0x4028a2c0, size 0x00000040 */ 5717 PROT_DW0_CH_STRUCT140_CH = 234, /* Address 0x4028a300, size 0x00000040 */ 5718 PROT_DW0_CH_STRUCT141_CH = 235, /* Address 0x4028a340, size 0x00000040 */ 5719 PROT_DW0_CH_STRUCT142_CH = 236, /* Address 0x4028a380, size 0x00000040 */ 5720 PROT_DW1_CH_STRUCT0_CH = 237, /* Address 0x40298000, size 0x00000040 */ 5721 PROT_DW1_CH_STRUCT1_CH = 238, /* Address 0x40298040, size 0x00000040 */ 5722 PROT_DW1_CH_STRUCT2_CH = 239, /* Address 0x40298080, size 0x00000040 */ 5723 PROT_DW1_CH_STRUCT3_CH = 240, /* Address 0x402980c0, size 0x00000040 */ 5724 PROT_DW1_CH_STRUCT4_CH = 241, /* Address 0x40298100, size 0x00000040 */ 5725 PROT_DW1_CH_STRUCT5_CH = 242, /* Address 0x40298140, size 0x00000040 */ 5726 PROT_DW1_CH_STRUCT6_CH = 243, /* Address 0x40298180, size 0x00000040 */ 5727 PROT_DW1_CH_STRUCT7_CH = 244, /* Address 0x402981c0, size 0x00000040 */ 5728 PROT_DW1_CH_STRUCT8_CH = 245, /* Address 0x40298200, size 0x00000040 */ 5729 PROT_DW1_CH_STRUCT9_CH = 246, /* Address 0x40298240, size 0x00000040 */ 5730 PROT_DW1_CH_STRUCT10_CH = 247, /* Address 0x40298280, size 0x00000040 */ 5731 PROT_DW1_CH_STRUCT11_CH = 248, /* Address 0x402982c0, size 0x00000040 */ 5732 PROT_DW1_CH_STRUCT12_CH = 249, /* Address 0x40298300, size 0x00000040 */ 5733 PROT_DW1_CH_STRUCT13_CH = 250, /* Address 0x40298340, size 0x00000040 */ 5734 PROT_DW1_CH_STRUCT14_CH = 251, /* Address 0x40298380, size 0x00000040 */ 5735 PROT_DW1_CH_STRUCT15_CH = 252, /* Address 0x402983c0, size 0x00000040 */ 5736 PROT_DW1_CH_STRUCT16_CH = 253, /* Address 0x40298400, size 0x00000040 */ 5737 PROT_DW1_CH_STRUCT17_CH = 254, /* Address 0x40298440, size 0x00000040 */ 5738 PROT_DW1_CH_STRUCT18_CH = 255, /* Address 0x40298480, size 0x00000040 */ 5739 PROT_DW1_CH_STRUCT19_CH = 256, /* Address 0x402984c0, size 0x00000040 */ 5740 PROT_DW1_CH_STRUCT20_CH = 257, /* Address 0x40298500, size 0x00000040 */ 5741 PROT_DW1_CH_STRUCT21_CH = 258, /* Address 0x40298540, size 0x00000040 */ 5742 PROT_DW1_CH_STRUCT22_CH = 259, /* Address 0x40298580, size 0x00000040 */ 5743 PROT_DW1_CH_STRUCT23_CH = 260, /* Address 0x402985c0, size 0x00000040 */ 5744 PROT_DW1_CH_STRUCT24_CH = 261, /* Address 0x40298600, size 0x00000040 */ 5745 PROT_DW1_CH_STRUCT25_CH = 262, /* Address 0x40298640, size 0x00000040 */ 5746 PROT_DW1_CH_STRUCT26_CH = 263, /* Address 0x40298680, size 0x00000040 */ 5747 PROT_DW1_CH_STRUCT27_CH = 264, /* Address 0x402986c0, size 0x00000040 */ 5748 PROT_DW1_CH_STRUCT28_CH = 265, /* Address 0x40298700, size 0x00000040 */ 5749 PROT_DW1_CH_STRUCT29_CH = 266, /* Address 0x40298740, size 0x00000040 */ 5750 PROT_DW1_CH_STRUCT30_CH = 267, /* Address 0x40298780, size 0x00000040 */ 5751 PROT_DW1_CH_STRUCT31_CH = 268, /* Address 0x402987c0, size 0x00000040 */ 5752 PROT_DW1_CH_STRUCT32_CH = 269, /* Address 0x40298800, size 0x00000040 */ 5753 PROT_DW1_CH_STRUCT33_CH = 270, /* Address 0x40298840, size 0x00000040 */ 5754 PROT_DW1_CH_STRUCT34_CH = 271, /* Address 0x40298880, size 0x00000040 */ 5755 PROT_DW1_CH_STRUCT35_CH = 272, /* Address 0x402988c0, size 0x00000040 */ 5756 PROT_DW1_CH_STRUCT36_CH = 273, /* Address 0x40298900, size 0x00000040 */ 5757 PROT_DW1_CH_STRUCT37_CH = 274, /* Address 0x40298940, size 0x00000040 */ 5758 PROT_DW1_CH_STRUCT38_CH = 275, /* Address 0x40298980, size 0x00000040 */ 5759 PROT_DW1_CH_STRUCT39_CH = 276, /* Address 0x402989c0, size 0x00000040 */ 5760 PROT_DW1_CH_STRUCT40_CH = 277, /* Address 0x40298a00, size 0x00000040 */ 5761 PROT_DW1_CH_STRUCT41_CH = 278, /* Address 0x40298a40, size 0x00000040 */ 5762 PROT_DW1_CH_STRUCT42_CH = 279, /* Address 0x40298a80, size 0x00000040 */ 5763 PROT_DW1_CH_STRUCT43_CH = 280, /* Address 0x40298ac0, size 0x00000040 */ 5764 PROT_DW1_CH_STRUCT44_CH = 281, /* Address 0x40298b00, size 0x00000040 */ 5765 PROT_DW1_CH_STRUCT45_CH = 282, /* Address 0x40298b40, size 0x00000040 */ 5766 PROT_DW1_CH_STRUCT46_CH = 283, /* Address 0x40298b80, size 0x00000040 */ 5767 PROT_DW1_CH_STRUCT47_CH = 284, /* Address 0x40298bc0, size 0x00000040 */ 5768 PROT_DW1_CH_STRUCT48_CH = 285, /* Address 0x40298c00, size 0x00000040 */ 5769 PROT_DW1_CH_STRUCT49_CH = 286, /* Address 0x40298c40, size 0x00000040 */ 5770 PROT_DW1_CH_STRUCT50_CH = 287, /* Address 0x40298c80, size 0x00000040 */ 5771 PROT_DW1_CH_STRUCT51_CH = 288, /* Address 0x40298cc0, size 0x00000040 */ 5772 PROT_DW1_CH_STRUCT52_CH = 289, /* Address 0x40298d00, size 0x00000040 */ 5773 PROT_DW1_CH_STRUCT53_CH = 290, /* Address 0x40298d40, size 0x00000040 */ 5774 PROT_DW1_CH_STRUCT54_CH = 291, /* Address 0x40298d80, size 0x00000040 */ 5775 PROT_DW1_CH_STRUCT55_CH = 292, /* Address 0x40298dc0, size 0x00000040 */ 5776 PROT_DW1_CH_STRUCT56_CH = 293, /* Address 0x40298e00, size 0x00000040 */ 5777 PROT_DW1_CH_STRUCT57_CH = 294, /* Address 0x40298e40, size 0x00000040 */ 5778 PROT_DW1_CH_STRUCT58_CH = 295, /* Address 0x40298e80, size 0x00000040 */ 5779 PROT_DW1_CH_STRUCT59_CH = 296, /* Address 0x40298ec0, size 0x00000040 */ 5780 PROT_DW1_CH_STRUCT60_CH = 297, /* Address 0x40298f00, size 0x00000040 */ 5781 PROT_DW1_CH_STRUCT61_CH = 298, /* Address 0x40298f40, size 0x00000040 */ 5782 PROT_DW1_CH_STRUCT62_CH = 299, /* Address 0x40298f80, size 0x00000040 */ 5783 PROT_DW1_CH_STRUCT63_CH = 300, /* Address 0x40298fc0, size 0x00000040 */ 5784 PROT_DW1_CH_STRUCT64_CH = 301, /* Address 0x40299000, size 0x00000040 */ 5785 PROT_DMAC_TOP = 302, /* Address 0x402a0000, size 0x00000010 */ 5786 PROT_DMAC_CH0_CH = 303, /* Address 0x402a1000, size 0x00000100 */ 5787 PROT_DMAC_CH1_CH = 304, /* Address 0x402a1100, size 0x00000100 */ 5788 PROT_DMAC_CH2_CH = 305, /* Address 0x402a1200, size 0x00000100 */ 5789 PROT_DMAC_CH3_CH = 306, /* Address 0x402a1300, size 0x00000100 */ 5790 PROT_DMAC_CH4_CH = 307, /* Address 0x402a1400, size 0x00000100 */ 5791 PROT_DMAC_CH5_CH = 308, /* Address 0x402a1500, size 0x00000100 */ 5792 PROT_DMAC_CH6_CH = 309, /* Address 0x402a1600, size 0x00000100 */ 5793 PROT_DMAC_CH7_CH = 310, /* Address 0x402a1700, size 0x00000100 */ 5794 PROT_EFUSE_CTL = 311, /* Address 0x402c0000, size 0x00000200 */ 5795 PROT_EFUSE_DATA = 312, /* Address 0x402c0800, size 0x00000200 */ 5796 PROT_BIST = 313, /* Address 0x402f0000, size 0x00001000 */ 5797 PROT_HSIOM_PRT0_PRT = 314, /* Address 0x40300000, size 0x00000008 */ 5798 PROT_HSIOM_PRT1_PRT = 315, /* Address 0x40300010, size 0x00000008 */ 5799 PROT_HSIOM_PRT2_PRT = 316, /* Address 0x40300020, size 0x00000008 */ 5800 PROT_HSIOM_PRT3_PRT = 317, /* Address 0x40300030, size 0x00000008 */ 5801 PROT_HSIOM_PRT4_PRT = 318, /* Address 0x40300040, size 0x00000008 */ 5802 PROT_HSIOM_PRT5_PRT = 319, /* Address 0x40300050, size 0x00000008 */ 5803 PROT_HSIOM_PRT6_PRT = 320, /* Address 0x40300060, size 0x00000008 */ 5804 PROT_HSIOM_PRT7_PRT = 321, /* Address 0x40300070, size 0x00000008 */ 5805 PROT_HSIOM_PRT8_PRT = 322, /* Address 0x40300080, size 0x00000008 */ 5806 PROT_HSIOM_PRT9_PRT = 323, /* Address 0x40300090, size 0x00000008 */ 5807 PROT_HSIOM_PRT10_PRT = 324, /* Address 0x403000a0, size 0x00000008 */ 5808 PROT_HSIOM_PRT11_PRT = 325, /* Address 0x403000b0, size 0x00000008 */ 5809 PROT_HSIOM_PRT12_PRT = 326, /* Address 0x403000c0, size 0x00000008 */ 5810 PROT_HSIOM_PRT13_PRT = 327, /* Address 0x403000d0, size 0x00000008 */ 5811 PROT_HSIOM_PRT14_PRT = 328, /* Address 0x403000e0, size 0x00000008 */ 5812 PROT_HSIOM_PRT15_PRT = 329, /* Address 0x403000f0, size 0x00000008 */ 5813 PROT_HSIOM_PRT16_PRT = 330, /* Address 0x40300100, size 0x00000008 */ 5814 PROT_HSIOM_PRT17_PRT = 331, /* Address 0x40300110, size 0x00000008 */ 5815 PROT_HSIOM_PRT18_PRT = 332, /* Address 0x40300120, size 0x00000008 */ 5816 PROT_HSIOM_PRT19_PRT = 333, /* Address 0x40300130, size 0x00000008 */ 5817 PROT_HSIOM_PRT20_PRT = 334, /* Address 0x40300140, size 0x00000008 */ 5818 PROT_HSIOM_PRT21_PRT = 335, /* Address 0x40300150, size 0x00000008 */ 5819 PROT_HSIOM_PRT22_PRT = 336, /* Address 0x40300160, size 0x00000008 */ 5820 PROT_HSIOM_PRT23_PRT = 337, /* Address 0x40300170, size 0x00000008 */ 5821 PROT_HSIOM_PRT24_PRT = 338, /* Address 0x40300180, size 0x00000008 */ 5822 PROT_HSIOM_PRT25_PRT = 339, /* Address 0x40300190, size 0x00000008 */ 5823 PROT_HSIOM_PRT26_PRT = 340, /* Address 0x403001a0, size 0x00000008 */ 5824 PROT_HSIOM_PRT27_PRT = 341, /* Address 0x403001b0, size 0x00000008 */ 5825 PROT_HSIOM_PRT28_PRT = 342, /* Address 0x403001c0, size 0x00000008 */ 5826 PROT_HSIOM_PRT29_PRT = 343, /* Address 0x403001d0, size 0x00000008 */ 5827 PROT_HSIOM_PRT30_PRT = 344, /* Address 0x403001e0, size 0x00000008 */ 5828 PROT_HSIOM_PRT31_PRT = 345, /* Address 0x403001f0, size 0x00000008 */ 5829 PROT_HSIOM_PRT32_PRT = 346, /* Address 0x40300200, size 0x00000008 */ 5830 PROT_HSIOM_PRT33_PRT = 347, /* Address 0x40300210, size 0x00000008 */ 5831 PROT_HSIOM_PRT34_PRT = 348, /* Address 0x40300220, size 0x00000008 */ 5832 PROT_HSIOM_AMUX = 349, /* Address 0x40302000, size 0x00000010 */ 5833 PROT_HSIOM_MON = 350, /* Address 0x40302200, size 0x00000010 */ 5834 PROT_HSIOM_ALTJTAG = 351, /* Address 0x40302240, size 0x00000004 */ 5835 PROT_GPIO_PRT0_PRT = 352, /* Address 0x40310000, size 0x00000040 */ 5836 PROT_GPIO_PRT1_PRT = 353, /* Address 0x40310080, size 0x00000040 */ 5837 PROT_GPIO_PRT2_PRT = 354, /* Address 0x40310100, size 0x00000040 */ 5838 PROT_GPIO_PRT3_PRT = 355, /* Address 0x40310180, size 0x00000040 */ 5839 PROT_GPIO_PRT4_PRT = 356, /* Address 0x40310200, size 0x00000040 */ 5840 PROT_GPIO_PRT5_PRT = 357, /* Address 0x40310280, size 0x00000040 */ 5841 PROT_GPIO_PRT6_PRT = 358, /* Address 0x40310300, size 0x00000040 */ 5842 PROT_GPIO_PRT7_PRT = 359, /* Address 0x40310380, size 0x00000040 */ 5843 PROT_GPIO_PRT8_PRT = 360, /* Address 0x40310400, size 0x00000040 */ 5844 PROT_GPIO_PRT9_PRT = 361, /* Address 0x40310480, size 0x00000040 */ 5845 PROT_GPIO_PRT10_PRT = 362, /* Address 0x40310500, size 0x00000040 */ 5846 PROT_GPIO_PRT11_PRT = 363, /* Address 0x40310580, size 0x00000040 */ 5847 PROT_GPIO_PRT12_PRT = 364, /* Address 0x40310600, size 0x00000040 */ 5848 PROT_GPIO_PRT13_PRT = 365, /* Address 0x40310680, size 0x00000040 */ 5849 PROT_GPIO_PRT14_PRT = 366, /* Address 0x40310700, size 0x00000040 */ 5850 PROT_GPIO_PRT15_PRT = 367, /* Address 0x40310780, size 0x00000040 */ 5851 PROT_GPIO_PRT16_PRT = 368, /* Address 0x40310800, size 0x00000040 */ 5852 PROT_GPIO_PRT17_PRT = 369, /* Address 0x40310880, size 0x00000040 */ 5853 PROT_GPIO_PRT18_PRT = 370, /* Address 0x40310900, size 0x00000040 */ 5854 PROT_GPIO_PRT19_PRT = 371, /* Address 0x40310980, size 0x00000040 */ 5855 PROT_GPIO_PRT20_PRT = 372, /* Address 0x40310a00, size 0x00000040 */ 5856 PROT_GPIO_PRT21_PRT = 373, /* Address 0x40310a80, size 0x00000040 */ 5857 PROT_GPIO_PRT22_PRT = 374, /* Address 0x40310b00, size 0x00000040 */ 5858 PROT_GPIO_PRT23_PRT = 375, /* Address 0x40310b80, size 0x00000040 */ 5859 PROT_GPIO_PRT24_PRT = 376, /* Address 0x40310c00, size 0x00000040 */ 5860 PROT_GPIO_PRT25_PRT = 377, /* Address 0x40310c80, size 0x00000040 */ 5861 PROT_GPIO_PRT26_PRT = 378, /* Address 0x40310d00, size 0x00000040 */ 5862 PROT_GPIO_PRT27_PRT = 379, /* Address 0x40310d80, size 0x00000040 */ 5863 PROT_GPIO_PRT28_PRT = 380, /* Address 0x40310e00, size 0x00000040 */ 5864 PROT_GPIO_PRT29_PRT = 381, /* Address 0x40310e80, size 0x00000040 */ 5865 PROT_GPIO_PRT30_PRT = 382, /* Address 0x40310f00, size 0x00000040 */ 5866 PROT_GPIO_PRT31_PRT = 383, /* Address 0x40310f80, size 0x00000040 */ 5867 PROT_GPIO_PRT32_PRT = 384, /* Address 0x40311000, size 0x00000040 */ 5868 PROT_GPIO_PRT33_PRT = 385, /* Address 0x40311080, size 0x00000040 */ 5869 PROT_GPIO_PRT34_PRT = 386, /* Address 0x40311100, size 0x00000040 */ 5870 PROT_GPIO_PRT0_CFG = 387, /* Address 0x40310040, size 0x00000020 */ 5871 PROT_GPIO_PRT1_CFG = 388, /* Address 0x403100c0, size 0x00000020 */ 5872 PROT_GPIO_PRT2_CFG = 389, /* Address 0x40310140, size 0x00000020 */ 5873 PROT_GPIO_PRT3_CFG = 390, /* Address 0x403101c0, size 0x00000020 */ 5874 PROT_GPIO_PRT4_CFG = 391, /* Address 0x40310240, size 0x00000020 */ 5875 PROT_GPIO_PRT5_CFG = 392, /* Address 0x403102c0, size 0x00000020 */ 5876 PROT_GPIO_PRT6_CFG = 393, /* Address 0x40310340, size 0x00000020 */ 5877 PROT_GPIO_PRT7_CFG = 394, /* Address 0x403103c0, size 0x00000020 */ 5878 PROT_GPIO_PRT8_CFG = 395, /* Address 0x40310440, size 0x00000020 */ 5879 PROT_GPIO_PRT9_CFG = 396, /* Address 0x403104c0, size 0x00000020 */ 5880 PROT_GPIO_PRT10_CFG = 397, /* Address 0x40310540, size 0x00000020 */ 5881 PROT_GPIO_PRT11_CFG = 398, /* Address 0x403105c0, size 0x00000020 */ 5882 PROT_GPIO_PRT12_CFG = 399, /* Address 0x40310640, size 0x00000020 */ 5883 PROT_GPIO_PRT13_CFG = 400, /* Address 0x403106c0, size 0x00000020 */ 5884 PROT_GPIO_PRT14_CFG = 401, /* Address 0x40310740, size 0x00000020 */ 5885 PROT_GPIO_PRT15_CFG = 402, /* Address 0x403107c0, size 0x00000020 */ 5886 PROT_GPIO_PRT16_CFG = 403, /* Address 0x40310840, size 0x00000020 */ 5887 PROT_GPIO_PRT17_CFG = 404, /* Address 0x403108c0, size 0x00000020 */ 5888 PROT_GPIO_PRT18_CFG = 405, /* Address 0x40310940, size 0x00000020 */ 5889 PROT_GPIO_PRT19_CFG = 406, /* Address 0x403109c0, size 0x00000020 */ 5890 PROT_GPIO_PRT20_CFG = 407, /* Address 0x40310a40, size 0x00000020 */ 5891 PROT_GPIO_PRT21_CFG = 408, /* Address 0x40310ac0, size 0x00000020 */ 5892 PROT_GPIO_PRT22_CFG = 409, /* Address 0x40310b40, size 0x00000020 */ 5893 PROT_GPIO_PRT23_CFG = 410, /* Address 0x40310bc0, size 0x00000020 */ 5894 PROT_GPIO_PRT24_CFG = 411, /* Address 0x40310c40, size 0x00000020 */ 5895 PROT_GPIO_PRT25_CFG = 412, /* Address 0x40310cc0, size 0x00000020 */ 5896 PROT_GPIO_PRT26_CFG = 413, /* Address 0x40310d40, size 0x00000020 */ 5897 PROT_GPIO_PRT27_CFG = 414, /* Address 0x40310dc0, size 0x00000020 */ 5898 PROT_GPIO_PRT28_CFG = 415, /* Address 0x40310e40, size 0x00000020 */ 5899 PROT_GPIO_PRT29_CFG = 416, /* Address 0x40310ec0, size 0x00000020 */ 5900 PROT_GPIO_PRT30_CFG = 417, /* Address 0x40310f40, size 0x00000020 */ 5901 PROT_GPIO_PRT31_CFG = 418, /* Address 0x40310fc0, size 0x00000020 */ 5902 PROT_GPIO_PRT32_CFG = 419, /* Address 0x40311040, size 0x00000020 */ 5903 PROT_GPIO_PRT33_CFG = 420, /* Address 0x403110c0, size 0x00000020 */ 5904 PROT_GPIO_PRT34_CFG = 421, /* Address 0x40311140, size 0x00000020 */ 5905 PROT_GPIO_GPIO = 422, /* Address 0x40314000, size 0x00000040 */ 5906 PROT_GPIO_TEST = 423, /* Address 0x40315000, size 0x00000008 */ 5907 PROT_SMARTIO_PRT12_PRT = 424, /* Address 0x40320c00, size 0x00000100 */ 5908 PROT_SMARTIO_PRT13_PRT = 425, /* Address 0x40320d00, size 0x00000100 */ 5909 PROT_SMARTIO_PRT14_PRT = 426, /* Address 0x40320e00, size 0x00000100 */ 5910 PROT_SMARTIO_PRT15_PRT = 427, /* Address 0x40320f00, size 0x00000100 */ 5911 PROT_SMARTIO_PRT17_PRT = 428, /* Address 0x40321100, size 0x00000100 */ 5912 PROT_TCPWM0_GRP0_CNT0_CNT = 429, /* Address 0x40380000, size 0x00000080 */ 5913 PROT_TCPWM0_GRP0_CNT1_CNT = 430, /* Address 0x40380080, size 0x00000080 */ 5914 PROT_TCPWM0_GRP0_CNT2_CNT = 431, /* Address 0x40380100, size 0x00000080 */ 5915 PROT_TCPWM0_GRP1_CNT0_CNT = 432, /* Address 0x40388000, size 0x00000080 */ 5916 PROT_TCPWM0_GRP1_CNT1_CNT = 433, /* Address 0x40388080, size 0x00000080 */ 5917 PROT_TCPWM0_GRP1_CNT2_CNT = 434, /* Address 0x40388100, size 0x00000080 */ 5918 PROT_TCPWM0_GRP2_CNT0_CNT = 435, /* Address 0x40390000, size 0x00000080 */ 5919 PROT_TCPWM0_GRP2_CNT1_CNT = 436, /* Address 0x40390080, size 0x00000080 */ 5920 PROT_TCPWM0_GRP2_CNT2_CNT = 437, /* Address 0x40390100, size 0x00000080 */ 5921 PROT_TCPWM1_GRP0_CNT0_CNT = 438, /* Address 0x40580000, size 0x00000080 */ 5922 PROT_TCPWM1_GRP0_CNT1_CNT = 439, /* Address 0x40580080, size 0x00000080 */ 5923 PROT_TCPWM1_GRP0_CNT2_CNT = 440, /* Address 0x40580100, size 0x00000080 */ 5924 PROT_TCPWM1_GRP0_CNT3_CNT = 441, /* Address 0x40580180, size 0x00000080 */ 5925 PROT_TCPWM1_GRP0_CNT4_CNT = 442, /* Address 0x40580200, size 0x00000080 */ 5926 PROT_TCPWM1_GRP0_CNT5_CNT = 443, /* Address 0x40580280, size 0x00000080 */ 5927 PROT_TCPWM1_GRP0_CNT6_CNT = 444, /* Address 0x40580300, size 0x00000080 */ 5928 PROT_TCPWM1_GRP0_CNT7_CNT = 445, /* Address 0x40580380, size 0x00000080 */ 5929 PROT_TCPWM1_GRP0_CNT8_CNT = 446, /* Address 0x40580400, size 0x00000080 */ 5930 PROT_TCPWM1_GRP0_CNT9_CNT = 447, /* Address 0x40580480, size 0x00000080 */ 5931 PROT_TCPWM1_GRP0_CNT10_CNT = 448, /* Address 0x40580500, size 0x00000080 */ 5932 PROT_TCPWM1_GRP0_CNT11_CNT = 449, /* Address 0x40580580, size 0x00000080 */ 5933 PROT_TCPWM1_GRP0_CNT12_CNT = 450, /* Address 0x40580600, size 0x00000080 */ 5934 PROT_TCPWM1_GRP0_CNT13_CNT = 451, /* Address 0x40580680, size 0x00000080 */ 5935 PROT_TCPWM1_GRP0_CNT14_CNT = 452, /* Address 0x40580700, size 0x00000080 */ 5936 PROT_TCPWM1_GRP0_CNT15_CNT = 453, /* Address 0x40580780, size 0x00000080 */ 5937 PROT_TCPWM1_GRP0_CNT16_CNT = 454, /* Address 0x40580800, size 0x00000080 */ 5938 PROT_TCPWM1_GRP0_CNT17_CNT = 455, /* Address 0x40580880, size 0x00000080 */ 5939 PROT_TCPWM1_GRP0_CNT18_CNT = 456, /* Address 0x40580900, size 0x00000080 */ 5940 PROT_TCPWM1_GRP0_CNT19_CNT = 457, /* Address 0x40580980, size 0x00000080 */ 5941 PROT_TCPWM1_GRP0_CNT20_CNT = 458, /* Address 0x40580a00, size 0x00000080 */ 5942 PROT_TCPWM1_GRP0_CNT21_CNT = 459, /* Address 0x40580a80, size 0x00000080 */ 5943 PROT_TCPWM1_GRP0_CNT22_CNT = 460, /* Address 0x40580b00, size 0x00000080 */ 5944 PROT_TCPWM1_GRP0_CNT23_CNT = 461, /* Address 0x40580b80, size 0x00000080 */ 5945 PROT_TCPWM1_GRP0_CNT24_CNT = 462, /* Address 0x40580c00, size 0x00000080 */ 5946 PROT_TCPWM1_GRP0_CNT25_CNT = 463, /* Address 0x40580c80, size 0x00000080 */ 5947 PROT_TCPWM1_GRP0_CNT26_CNT = 464, /* Address 0x40580d00, size 0x00000080 */ 5948 PROT_TCPWM1_GRP0_CNT27_CNT = 465, /* Address 0x40580d80, size 0x00000080 */ 5949 PROT_TCPWM1_GRP0_CNT28_CNT = 466, /* Address 0x40580e00, size 0x00000080 */ 5950 PROT_TCPWM1_GRP0_CNT29_CNT = 467, /* Address 0x40580e80, size 0x00000080 */ 5951 PROT_TCPWM1_GRP0_CNT30_CNT = 468, /* Address 0x40580f00, size 0x00000080 */ 5952 PROT_TCPWM1_GRP0_CNT31_CNT = 469, /* Address 0x40580f80, size 0x00000080 */ 5953 PROT_TCPWM1_GRP0_CNT32_CNT = 470, /* Address 0x40581000, size 0x00000080 */ 5954 PROT_TCPWM1_GRP0_CNT33_CNT = 471, /* Address 0x40581080, size 0x00000080 */ 5955 PROT_TCPWM1_GRP0_CNT34_CNT = 472, /* Address 0x40581100, size 0x00000080 */ 5956 PROT_TCPWM1_GRP0_CNT35_CNT = 473, /* Address 0x40581180, size 0x00000080 */ 5957 PROT_TCPWM1_GRP0_CNT36_CNT = 474, /* Address 0x40581200, size 0x00000080 */ 5958 PROT_TCPWM1_GRP0_CNT37_CNT = 475, /* Address 0x40581280, size 0x00000080 */ 5959 PROT_TCPWM1_GRP0_CNT38_CNT = 476, /* Address 0x40581300, size 0x00000080 */ 5960 PROT_TCPWM1_GRP0_CNT39_CNT = 477, /* Address 0x40581380, size 0x00000080 */ 5961 PROT_TCPWM1_GRP0_CNT40_CNT = 478, /* Address 0x40581400, size 0x00000080 */ 5962 PROT_TCPWM1_GRP0_CNT41_CNT = 479, /* Address 0x40581480, size 0x00000080 */ 5963 PROT_TCPWM1_GRP0_CNT42_CNT = 480, /* Address 0x40581500, size 0x00000080 */ 5964 PROT_TCPWM1_GRP0_CNT43_CNT = 481, /* Address 0x40581580, size 0x00000080 */ 5965 PROT_TCPWM1_GRP0_CNT44_CNT = 482, /* Address 0x40581600, size 0x00000080 */ 5966 PROT_TCPWM1_GRP0_CNT45_CNT = 483, /* Address 0x40581680, size 0x00000080 */ 5967 PROT_TCPWM1_GRP0_CNT46_CNT = 484, /* Address 0x40581700, size 0x00000080 */ 5968 PROT_TCPWM1_GRP0_CNT47_CNT = 485, /* Address 0x40581780, size 0x00000080 */ 5969 PROT_TCPWM1_GRP0_CNT48_CNT = 486, /* Address 0x40581800, size 0x00000080 */ 5970 PROT_TCPWM1_GRP0_CNT49_CNT = 487, /* Address 0x40581880, size 0x00000080 */ 5971 PROT_TCPWM1_GRP0_CNT50_CNT = 488, /* Address 0x40581900, size 0x00000080 */ 5972 PROT_TCPWM1_GRP0_CNT51_CNT = 489, /* Address 0x40581980, size 0x00000080 */ 5973 PROT_TCPWM1_GRP0_CNT52_CNT = 490, /* Address 0x40581a00, size 0x00000080 */ 5974 PROT_TCPWM1_GRP0_CNT53_CNT = 491, /* Address 0x40581a80, size 0x00000080 */ 5975 PROT_TCPWM1_GRP0_CNT54_CNT = 492, /* Address 0x40581b00, size 0x00000080 */ 5976 PROT_TCPWM1_GRP0_CNT55_CNT = 493, /* Address 0x40581b80, size 0x00000080 */ 5977 PROT_TCPWM1_GRP0_CNT56_CNT = 494, /* Address 0x40581c00, size 0x00000080 */ 5978 PROT_TCPWM1_GRP0_CNT57_CNT = 495, /* Address 0x40581c80, size 0x00000080 */ 5979 PROT_TCPWM1_GRP0_CNT58_CNT = 496, /* Address 0x40581d00, size 0x00000080 */ 5980 PROT_TCPWM1_GRP0_CNT59_CNT = 497, /* Address 0x40581d80, size 0x00000080 */ 5981 PROT_TCPWM1_GRP0_CNT60_CNT = 498, /* Address 0x40581e00, size 0x00000080 */ 5982 PROT_TCPWM1_GRP0_CNT61_CNT = 499, /* Address 0x40581e80, size 0x00000080 */ 5983 PROT_TCPWM1_GRP0_CNT62_CNT = 500, /* Address 0x40581f00, size 0x00000080 */ 5984 PROT_TCPWM1_GRP0_CNT63_CNT = 501, /* Address 0x40581f80, size 0x00000080 */ 5985 PROT_TCPWM1_GRP0_CNT64_CNT = 502, /* Address 0x40582000, size 0x00000080 */ 5986 PROT_TCPWM1_GRP0_CNT65_CNT = 503, /* Address 0x40582080, size 0x00000080 */ 5987 PROT_TCPWM1_GRP0_CNT66_CNT = 504, /* Address 0x40582100, size 0x00000080 */ 5988 PROT_TCPWM1_GRP0_CNT67_CNT = 505, /* Address 0x40582180, size 0x00000080 */ 5989 PROT_TCPWM1_GRP0_CNT68_CNT = 506, /* Address 0x40582200, size 0x00000080 */ 5990 PROT_TCPWM1_GRP0_CNT69_CNT = 507, /* Address 0x40582280, size 0x00000080 */ 5991 PROT_TCPWM1_GRP0_CNT70_CNT = 508, /* Address 0x40582300, size 0x00000080 */ 5992 PROT_TCPWM1_GRP0_CNT71_CNT = 509, /* Address 0x40582380, size 0x00000080 */ 5993 PROT_TCPWM1_GRP0_CNT72_CNT = 510, /* Address 0x40582400, size 0x00000080 */ 5994 PROT_TCPWM1_GRP0_CNT73_CNT = 511, /* Address 0x40582480, size 0x00000080 */ 5995 PROT_TCPWM1_GRP0_CNT74_CNT = 512, /* Address 0x40582500, size 0x00000080 */ 5996 PROT_TCPWM1_GRP0_CNT75_CNT = 513, /* Address 0x40582580, size 0x00000080 */ 5997 PROT_TCPWM1_GRP0_CNT76_CNT = 514, /* Address 0x40582600, size 0x00000080 */ 5998 PROT_TCPWM1_GRP0_CNT77_CNT = 515, /* Address 0x40582680, size 0x00000080 */ 5999 PROT_TCPWM1_GRP0_CNT78_CNT = 516, /* Address 0x40582700, size 0x00000080 */ 6000 PROT_TCPWM1_GRP0_CNT79_CNT = 517, /* Address 0x40582780, size 0x00000080 */ 6001 PROT_TCPWM1_GRP0_CNT80_CNT = 518, /* Address 0x40582800, size 0x00000080 */ 6002 PROT_TCPWM1_GRP0_CNT81_CNT = 519, /* Address 0x40582880, size 0x00000080 */ 6003 PROT_TCPWM1_GRP0_CNT82_CNT = 520, /* Address 0x40582900, size 0x00000080 */ 6004 PROT_TCPWM1_GRP0_CNT83_CNT = 521, /* Address 0x40582980, size 0x00000080 */ 6005 PROT_TCPWM1_GRP1_CNT0_CNT = 522, /* Address 0x40588000, size 0x00000080 */ 6006 PROT_TCPWM1_GRP1_CNT1_CNT = 523, /* Address 0x40588080, size 0x00000080 */ 6007 PROT_TCPWM1_GRP1_CNT2_CNT = 524, /* Address 0x40588100, size 0x00000080 */ 6008 PROT_TCPWM1_GRP1_CNT3_CNT = 525, /* Address 0x40588180, size 0x00000080 */ 6009 PROT_TCPWM1_GRP1_CNT4_CNT = 526, /* Address 0x40588200, size 0x00000080 */ 6010 PROT_TCPWM1_GRP1_CNT5_CNT = 527, /* Address 0x40588280, size 0x00000080 */ 6011 PROT_TCPWM1_GRP1_CNT6_CNT = 528, /* Address 0x40588300, size 0x00000080 */ 6012 PROT_TCPWM1_GRP1_CNT7_CNT = 529, /* Address 0x40588380, size 0x00000080 */ 6013 PROT_TCPWM1_GRP1_CNT8_CNT = 530, /* Address 0x40588400, size 0x00000080 */ 6014 PROT_TCPWM1_GRP1_CNT9_CNT = 531, /* Address 0x40588480, size 0x00000080 */ 6015 PROT_TCPWM1_GRP1_CNT10_CNT = 532, /* Address 0x40588500, size 0x00000080 */ 6016 PROT_TCPWM1_GRP1_CNT11_CNT = 533, /* Address 0x40588580, size 0x00000080 */ 6017 PROT_TCPWM1_GRP2_CNT0_CNT = 534, /* Address 0x40590000, size 0x00000080 */ 6018 PROT_TCPWM1_GRP2_CNT1_CNT = 535, /* Address 0x40590080, size 0x00000080 */ 6019 PROT_TCPWM1_GRP2_CNT2_CNT = 536, /* Address 0x40590100, size 0x00000080 */ 6020 PROT_TCPWM1_GRP2_CNT3_CNT = 537, /* Address 0x40590180, size 0x00000080 */ 6021 PROT_TCPWM1_GRP2_CNT4_CNT = 538, /* Address 0x40590200, size 0x00000080 */ 6022 PROT_TCPWM1_GRP2_CNT5_CNT = 539, /* Address 0x40590280, size 0x00000080 */ 6023 PROT_TCPWM1_GRP2_CNT6_CNT = 540, /* Address 0x40590300, size 0x00000080 */ 6024 PROT_TCPWM1_GRP2_CNT7_CNT = 541, /* Address 0x40590380, size 0x00000080 */ 6025 PROT_TCPWM1_GRP2_CNT8_CNT = 542, /* Address 0x40590400, size 0x00000080 */ 6026 PROT_TCPWM1_GRP2_CNT9_CNT = 543, /* Address 0x40590480, size 0x00000080 */ 6027 PROT_TCPWM1_GRP2_CNT10_CNT = 544, /* Address 0x40590500, size 0x00000080 */ 6028 PROT_TCPWM1_GRP2_CNT11_CNT = 545, /* Address 0x40590580, size 0x00000080 */ 6029 PROT_TCPWM1_GRP2_CNT12_CNT = 546, /* Address 0x40590600, size 0x00000080 */ 6030 PROT_EVTGEN0 = 547, /* Address 0x403f0000, size 0x00001000 */ 6031 PROT_SMIF0 = 548, /* Address 0x40420000, size 0x00010000 */ 6032 PROT_SDHC0 = 549, /* Address 0x40460000, size 0x00010000 */ 6033 PROT_ETH0 = 550, /* Address 0x40480000, size 0x00010000 */ 6034 PROT_ETH1 = 551, /* Address 0x40490000, size 0x00010000 */ 6035 PROT_LIN0_MAIN = 552, /* Address 0x40500000, size 0x00000008 */ 6036 PROT_LIN0_CH0_CH = 553, /* Address 0x40508000, size 0x00000100 */ 6037 PROT_LIN0_CH1_CH = 554, /* Address 0x40508100, size 0x00000100 */ 6038 PROT_LIN0_CH2_CH = 555, /* Address 0x40508200, size 0x00000100 */ 6039 PROT_LIN0_CH3_CH = 556, /* Address 0x40508300, size 0x00000100 */ 6040 PROT_LIN0_CH4_CH = 557, /* Address 0x40508400, size 0x00000100 */ 6041 PROT_LIN0_CH5_CH = 558, /* Address 0x40508500, size 0x00000100 */ 6042 PROT_LIN0_CH6_CH = 559, /* Address 0x40508600, size 0x00000100 */ 6043 PROT_LIN0_CH7_CH = 560, /* Address 0x40508700, size 0x00000100 */ 6044 PROT_LIN0_CH8_CH = 561, /* Address 0x40508800, size 0x00000100 */ 6045 PROT_LIN0_CH9_CH = 562, /* Address 0x40508900, size 0x00000100 */ 6046 PROT_LIN0_CH10_CH = 563, /* Address 0x40508a00, size 0x00000100 */ 6047 PROT_LIN0_CH11_CH = 564, /* Address 0x40508b00, size 0x00000100 */ 6048 PROT_LIN0_CH12_CH = 565, /* Address 0x40508c00, size 0x00000100 */ 6049 PROT_LIN0_CH13_CH = 566, /* Address 0x40508d00, size 0x00000100 */ 6050 PROT_LIN0_CH14_CH = 567, /* Address 0x40508e00, size 0x00000100 */ 6051 PROT_LIN0_CH15_CH = 568, /* Address 0x40508f00, size 0x00000100 */ 6052 PROT_LIN0_CH16_CH = 569, /* Address 0x40509000, size 0x00000100 */ 6053 PROT_LIN0_CH17_CH = 570, /* Address 0x40509100, size 0x00000100 */ 6054 PROT_LIN0_CH18_CH = 571, /* Address 0x40509200, size 0x00000100 */ 6055 PROT_LIN0_CH19_CH = 572, /* Address 0x40509300, size 0x00000100 */ 6056 PROT_CANFD0_CH0_CH = 573, /* Address 0x40520000, size 0x00000200 */ 6057 PROT_CANFD0_CH1_CH = 574, /* Address 0x40520200, size 0x00000200 */ 6058 PROT_CANFD0_CH2_CH = 575, /* Address 0x40520400, size 0x00000200 */ 6059 PROT_CANFD0_CH3_CH = 576, /* Address 0x40520600, size 0x00000200 */ 6060 PROT_CANFD0_CH4_CH = 577, /* Address 0x40520800, size 0x00000200 */ 6061 PROT_CANFD1_CH0_CH = 578, /* Address 0x40540000, size 0x00000200 */ 6062 PROT_CANFD1_CH1_CH = 579, /* Address 0x40540200, size 0x00000200 */ 6063 PROT_CANFD1_CH2_CH = 580, /* Address 0x40540400, size 0x00000200 */ 6064 PROT_CANFD1_CH3_CH = 581, /* Address 0x40540600, size 0x00000200 */ 6065 PROT_CANFD1_CH4_CH = 582, /* Address 0x40540800, size 0x00000200 */ 6066 PROT_CANFD0_MAIN = 583, /* Address 0x40521000, size 0x00000100 */ 6067 PROT_CANFD1_MAIN = 584, /* Address 0x40541000, size 0x00000100 */ 6068 PROT_CANFD0_BUF = 585, /* Address 0x40530000, size 0x00010000 */ 6069 PROT_CANFD1_BUF = 586, /* Address 0x40550000, size 0x00010000 */ 6070 PROT_FLEXRAY0 = 587, /* Address 0x40560000, size 0x00001000 */ 6071 PROT_SCB0 = 588, /* Address 0x40600000, size 0x00010000 */ 6072 PROT_SCB1 = 589, /* Address 0x40610000, size 0x00010000 */ 6073 PROT_SCB2 = 590, /* Address 0x40620000, size 0x00010000 */ 6074 PROT_SCB3 = 591, /* Address 0x40630000, size 0x00010000 */ 6075 PROT_SCB4 = 592, /* Address 0x40640000, size 0x00010000 */ 6076 PROT_SCB5 = 593, /* Address 0x40650000, size 0x00010000 */ 6077 PROT_SCB6 = 594, /* Address 0x40660000, size 0x00010000 */ 6078 PROT_SCB7 = 595, /* Address 0x40670000, size 0x00010000 */ 6079 PROT_SCB8 = 596, /* Address 0x40680000, size 0x00010000 */ 6080 PROT_SCB9 = 597, /* Address 0x40690000, size 0x00010000 */ 6081 PROT_SCB10 = 598, /* Address 0x406a0000, size 0x00010000 */ 6082 PROT_I2S0 = 599, /* Address 0x40800000, size 0x00001000 */ 6083 PROT_I2S1 = 600, /* Address 0x40801000, size 0x00001000 */ 6084 PROT_I2S2 = 601, /* Address 0x40802000, size 0x00001000 */ 6085 PROT_PASS0_SAR0_SAR = 602, /* Address 0x40900000, size 0x00000400 */ 6086 PROT_PASS0_SAR1_SAR = 603, /* Address 0x40901000, size 0x00000400 */ 6087 PROT_PASS0_SAR2_SAR = 604, /* Address 0x40902000, size 0x00000400 */ 6088 PROT_PASS0_SAR0_CH0_CH = 605, /* Address 0x40900800, size 0x00000040 */ 6089 PROT_PASS0_SAR0_CH1_CH = 606, /* Address 0x40900840, size 0x00000040 */ 6090 PROT_PASS0_SAR0_CH2_CH = 607, /* Address 0x40900880, size 0x00000040 */ 6091 PROT_PASS0_SAR0_CH3_CH = 608, /* Address 0x409008c0, size 0x00000040 */ 6092 PROT_PASS0_SAR0_CH4_CH = 609, /* Address 0x40900900, size 0x00000040 */ 6093 PROT_PASS0_SAR0_CH5_CH = 610, /* Address 0x40900940, size 0x00000040 */ 6094 PROT_PASS0_SAR0_CH6_CH = 611, /* Address 0x40900980, size 0x00000040 */ 6095 PROT_PASS0_SAR0_CH7_CH = 612, /* Address 0x409009c0, size 0x00000040 */ 6096 PROT_PASS0_SAR0_CH8_CH = 613, /* Address 0x40900a00, size 0x00000040 */ 6097 PROT_PASS0_SAR0_CH9_CH = 614, /* Address 0x40900a40, size 0x00000040 */ 6098 PROT_PASS0_SAR0_CH10_CH = 615, /* Address 0x40900a80, size 0x00000040 */ 6099 PROT_PASS0_SAR0_CH11_CH = 616, /* Address 0x40900ac0, size 0x00000040 */ 6100 PROT_PASS0_SAR0_CH12_CH = 617, /* Address 0x40900b00, size 0x00000040 */ 6101 PROT_PASS0_SAR0_CH13_CH = 618, /* Address 0x40900b40, size 0x00000040 */ 6102 PROT_PASS0_SAR0_CH14_CH = 619, /* Address 0x40900b80, size 0x00000040 */ 6103 PROT_PASS0_SAR0_CH15_CH = 620, /* Address 0x40900bc0, size 0x00000040 */ 6104 PROT_PASS0_SAR0_CH16_CH = 621, /* Address 0x40900c00, size 0x00000040 */ 6105 PROT_PASS0_SAR0_CH17_CH = 622, /* Address 0x40900c40, size 0x00000040 */ 6106 PROT_PASS0_SAR0_CH18_CH = 623, /* Address 0x40900c80, size 0x00000040 */ 6107 PROT_PASS0_SAR0_CH19_CH = 624, /* Address 0x40900cc0, size 0x00000040 */ 6108 PROT_PASS0_SAR0_CH20_CH = 625, /* Address 0x40900d00, size 0x00000040 */ 6109 PROT_PASS0_SAR0_CH21_CH = 626, /* Address 0x40900d40, size 0x00000040 */ 6110 PROT_PASS0_SAR0_CH22_CH = 627, /* Address 0x40900d80, size 0x00000040 */ 6111 PROT_PASS0_SAR0_CH23_CH = 628, /* Address 0x40900dc0, size 0x00000040 */ 6112 PROT_PASS0_SAR0_CH24_CH = 629, /* Address 0x40900e00, size 0x00000040 */ 6113 PROT_PASS0_SAR0_CH25_CH = 630, /* Address 0x40900e40, size 0x00000040 */ 6114 PROT_PASS0_SAR0_CH26_CH = 631, /* Address 0x40900e80, size 0x00000040 */ 6115 PROT_PASS0_SAR0_CH27_CH = 632, /* Address 0x40900ec0, size 0x00000040 */ 6116 PROT_PASS0_SAR0_CH28_CH = 633, /* Address 0x40900f00, size 0x00000040 */ 6117 PROT_PASS0_SAR0_CH29_CH = 634, /* Address 0x40900f40, size 0x00000040 */ 6118 PROT_PASS0_SAR0_CH30_CH = 635, /* Address 0x40900f80, size 0x00000040 */ 6119 PROT_PASS0_SAR0_CH31_CH = 636, /* Address 0x40900fc0, size 0x00000040 */ 6120 PROT_PASS0_SAR1_CH0_CH = 637, /* Address 0x40901800, size 0x00000040 */ 6121 PROT_PASS0_SAR1_CH1_CH = 638, /* Address 0x40901840, size 0x00000040 */ 6122 PROT_PASS0_SAR1_CH2_CH = 639, /* Address 0x40901880, size 0x00000040 */ 6123 PROT_PASS0_SAR1_CH3_CH = 640, /* Address 0x409018c0, size 0x00000040 */ 6124 PROT_PASS0_SAR1_CH4_CH = 641, /* Address 0x40901900, size 0x00000040 */ 6125 PROT_PASS0_SAR1_CH5_CH = 642, /* Address 0x40901940, size 0x00000040 */ 6126 PROT_PASS0_SAR1_CH6_CH = 643, /* Address 0x40901980, size 0x00000040 */ 6127 PROT_PASS0_SAR1_CH7_CH = 644, /* Address 0x409019c0, size 0x00000040 */ 6128 PROT_PASS0_SAR1_CH8_CH = 645, /* Address 0x40901a00, size 0x00000040 */ 6129 PROT_PASS0_SAR1_CH9_CH = 646, /* Address 0x40901a40, size 0x00000040 */ 6130 PROT_PASS0_SAR1_CH10_CH = 647, /* Address 0x40901a80, size 0x00000040 */ 6131 PROT_PASS0_SAR1_CH11_CH = 648, /* Address 0x40901ac0, size 0x00000040 */ 6132 PROT_PASS0_SAR1_CH12_CH = 649, /* Address 0x40901b00, size 0x00000040 */ 6133 PROT_PASS0_SAR1_CH13_CH = 650, /* Address 0x40901b40, size 0x00000040 */ 6134 PROT_PASS0_SAR1_CH14_CH = 651, /* Address 0x40901b80, size 0x00000040 */ 6135 PROT_PASS0_SAR1_CH15_CH = 652, /* Address 0x40901bc0, size 0x00000040 */ 6136 PROT_PASS0_SAR1_CH16_CH = 653, /* Address 0x40901c00, size 0x00000040 */ 6137 PROT_PASS0_SAR1_CH17_CH = 654, /* Address 0x40901c40, size 0x00000040 */ 6138 PROT_PASS0_SAR1_CH18_CH = 655, /* Address 0x40901c80, size 0x00000040 */ 6139 PROT_PASS0_SAR1_CH19_CH = 656, /* Address 0x40901cc0, size 0x00000040 */ 6140 PROT_PASS0_SAR1_CH20_CH = 657, /* Address 0x40901d00, size 0x00000040 */ 6141 PROT_PASS0_SAR1_CH21_CH = 658, /* Address 0x40901d40, size 0x00000040 */ 6142 PROT_PASS0_SAR1_CH22_CH = 659, /* Address 0x40901d80, size 0x00000040 */ 6143 PROT_PASS0_SAR1_CH23_CH = 660, /* Address 0x40901dc0, size 0x00000040 */ 6144 PROT_PASS0_SAR1_CH24_CH = 661, /* Address 0x40901e00, size 0x00000040 */ 6145 PROT_PASS0_SAR1_CH25_CH = 662, /* Address 0x40901e40, size 0x00000040 */ 6146 PROT_PASS0_SAR1_CH26_CH = 663, /* Address 0x40901e80, size 0x00000040 */ 6147 PROT_PASS0_SAR1_CH27_CH = 664, /* Address 0x40901ec0, size 0x00000040 */ 6148 PROT_PASS0_SAR1_CH28_CH = 665, /* Address 0x40901f00, size 0x00000040 */ 6149 PROT_PASS0_SAR1_CH29_CH = 666, /* Address 0x40901f40, size 0x00000040 */ 6150 PROT_PASS0_SAR1_CH30_CH = 667, /* Address 0x40901f80, size 0x00000040 */ 6151 PROT_PASS0_SAR1_CH31_CH = 668, /* Address 0x40901fc0, size 0x00000040 */ 6152 PROT_PASS0_SAR2_CH0_CH = 669, /* Address 0x40902800, size 0x00000040 */ 6153 PROT_PASS0_SAR2_CH1_CH = 670, /* Address 0x40902840, size 0x00000040 */ 6154 PROT_PASS0_SAR2_CH2_CH = 671, /* Address 0x40902880, size 0x00000040 */ 6155 PROT_PASS0_SAR2_CH3_CH = 672, /* Address 0x409028c0, size 0x00000040 */ 6156 PROT_PASS0_SAR2_CH4_CH = 673, /* Address 0x40902900, size 0x00000040 */ 6157 PROT_PASS0_SAR2_CH5_CH = 674, /* Address 0x40902940, size 0x00000040 */ 6158 PROT_PASS0_SAR2_CH6_CH = 675, /* Address 0x40902980, size 0x00000040 */ 6159 PROT_PASS0_SAR2_CH7_CH = 676, /* Address 0x409029c0, size 0x00000040 */ 6160 PROT_PASS0_SAR2_CH8_CH = 677, /* Address 0x40902a00, size 0x00000040 */ 6161 PROT_PASS0_SAR2_CH9_CH = 678, /* Address 0x40902a40, size 0x00000040 */ 6162 PROT_PASS0_SAR2_CH10_CH = 679, /* Address 0x40902a80, size 0x00000040 */ 6163 PROT_PASS0_SAR2_CH11_CH = 680, /* Address 0x40902ac0, size 0x00000040 */ 6164 PROT_PASS0_SAR2_CH12_CH = 681, /* Address 0x40902b00, size 0x00000040 */ 6165 PROT_PASS0_SAR2_CH13_CH = 682, /* Address 0x40902b40, size 0x00000040 */ 6166 PROT_PASS0_SAR2_CH14_CH = 683, /* Address 0x40902b80, size 0x00000040 */ 6167 PROT_PASS0_SAR2_CH15_CH = 684, /* Address 0x40902bc0, size 0x00000040 */ 6168 PROT_PASS0_SAR2_CH16_CH = 685, /* Address 0x40902c00, size 0x00000040 */ 6169 PROT_PASS0_SAR2_CH17_CH = 686, /* Address 0x40902c40, size 0x00000040 */ 6170 PROT_PASS0_SAR2_CH18_CH = 687, /* Address 0x40902c80, size 0x00000040 */ 6171 PROT_PASS0_SAR2_CH19_CH = 688, /* Address 0x40902cc0, size 0x00000040 */ 6172 PROT_PASS0_SAR2_CH20_CH = 689, /* Address 0x40902d00, size 0x00000040 */ 6173 PROT_PASS0_SAR2_CH21_CH = 690, /* Address 0x40902d40, size 0x00000040 */ 6174 PROT_PASS0_SAR2_CH22_CH = 691, /* Address 0x40902d80, size 0x00000040 */ 6175 PROT_PASS0_SAR2_CH23_CH = 692, /* Address 0x40902dc0, size 0x00000040 */ 6176 PROT_PASS0_SAR2_CH24_CH = 693, /* Address 0x40902e00, size 0x00000040 */ 6177 PROT_PASS0_SAR2_CH25_CH = 694, /* Address 0x40902e40, size 0x00000040 */ 6178 PROT_PASS0_SAR2_CH26_CH = 695, /* Address 0x40902e80, size 0x00000040 */ 6179 PROT_PASS0_SAR2_CH27_CH = 696, /* Address 0x40902ec0, size 0x00000040 */ 6180 PROT_PASS0_SAR2_CH28_CH = 697, /* Address 0x40902f00, size 0x00000040 */ 6181 PROT_PASS0_SAR2_CH29_CH = 698, /* Address 0x40902f40, size 0x00000040 */ 6182 PROT_PASS0_SAR2_CH30_CH = 699, /* Address 0x40902f80, size 0x00000040 */ 6183 PROT_PASS0_SAR2_CH31_CH = 700, /* Address 0x40902fc0, size 0x00000040 */ 6184 PROT_PASS0_TOP = 701 /* Address 0x409f0000, size 0x00001000 */ 6185 } cy_en_prot_region_t; 6186 6187 #endif /* _XMC7200_CONFIG_H_ */ 6188 6189 6190 /* [] END OF FILE */ 6191
