1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_TEMPSENSE.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_TEMPSENSE 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_TEMPSENSE_H_) /* Check if memory map has not been already included */ 58 #define S32K344_TEMPSENSE_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- TEMPSENSE Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup TEMPSENSE_Peripheral_Access_Layer TEMPSENSE Peripheral Access Layer 68 * @{ 69 */ 70 71 /** TEMPSENSE - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t ETSCTL; /**< ETS Control, offset: 0x0 */ 74 uint8_t RESERVED_0[4]; 75 __I uint32_t TCA0; /**< Temperature Coefficient, offset: 0x8 */ 76 __I uint32_t TCA1; /**< Temperature Coefficient, offset: 0xC */ 77 __I uint32_t TCA2; /**< Temperature Coefficient, offset: 0x10 */ 78 } TEMPSENSE_Type, *TEMPSENSE_MemMapPtr; 79 80 /** Number of instances of the TEMPSENSE module. */ 81 #define TEMPSENSE_INSTANCE_COUNT (1u) 82 83 /* TEMPSENSE - Peripheral instance base addresses */ 84 /** Peripheral TEMPSENSE base address */ 85 #define IP_TEMPSENSE_BASE (0x4037C000u) 86 /** Peripheral TEMPSENSE base pointer */ 87 #define IP_TEMPSENSE ((TEMPSENSE_Type *)IP_TEMPSENSE_BASE) 88 /** Array initializer of TEMPSENSE peripheral base addresses */ 89 #define IP_TEMPSENSE_BASE_ADDRS { IP_TEMPSENSE_BASE } 90 /** Array initializer of TEMPSENSE peripheral base pointers */ 91 #define IP_TEMPSENSE_BASE_PTRS { IP_TEMPSENSE } 92 93 /* ---------------------------------------------------------------------------- 94 -- TEMPSENSE Register Masks 95 ---------------------------------------------------------------------------- */ 96 97 /*! 98 * @addtogroup TEMPSENSE_Register_Masks TEMPSENSE Register Masks 99 * @{ 100 */ 101 102 /*! @name ETSCTL - ETS Control */ 103 /*! @{ */ 104 105 #define TEMPSENSE_ETSCTL_ETS_EN_MASK (0x1U) 106 #define TEMPSENSE_ETSCTL_ETS_EN_SHIFT (0U) 107 #define TEMPSENSE_ETSCTL_ETS_EN_WIDTH (1U) 108 #define TEMPSENSE_ETSCTL_ETS_EN(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_ETSCTL_ETS_EN_SHIFT)) & TEMPSENSE_ETSCTL_ETS_EN_MASK) 109 110 #define TEMPSENSE_ETSCTL_GNDSEL_MASK (0x2U) 111 #define TEMPSENSE_ETSCTL_GNDSEL_SHIFT (1U) 112 #define TEMPSENSE_ETSCTL_GNDSEL_WIDTH (1U) 113 #define TEMPSENSE_ETSCTL_GNDSEL(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_ETSCTL_GNDSEL_SHIFT)) & TEMPSENSE_ETSCTL_GNDSEL_MASK) 114 /*! @} */ 115 116 /*! @name TCA0 - Temperature Coefficient */ 117 /*! @{ */ 118 119 #define TEMPSENSE_TCA0_TCA0_MASK (0xFFFFU) 120 #define TEMPSENSE_TCA0_TCA0_SHIFT (0U) 121 #define TEMPSENSE_TCA0_TCA0_WIDTH (16U) 122 #define TEMPSENSE_TCA0_TCA0(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_TCA0_TCA0_SHIFT)) & TEMPSENSE_TCA0_TCA0_MASK) 123 /*! @} */ 124 125 /*! @name TCA1 - Temperature Coefficient */ 126 /*! @{ */ 127 128 #define TEMPSENSE_TCA1_TCA1_MASK (0xFFFFU) 129 #define TEMPSENSE_TCA1_TCA1_SHIFT (0U) 130 #define TEMPSENSE_TCA1_TCA1_WIDTH (16U) 131 #define TEMPSENSE_TCA1_TCA1(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_TCA1_TCA1_SHIFT)) & TEMPSENSE_TCA1_TCA1_MASK) 132 /*! @} */ 133 134 /*! @name TCA2 - Temperature Coefficient */ 135 /*! @{ */ 136 137 #define TEMPSENSE_TCA2_TCA2_MASK (0xFFFFU) 138 #define TEMPSENSE_TCA2_TCA2_SHIFT (0U) 139 #define TEMPSENSE_TCA2_TCA2_WIDTH (16U) 140 #define TEMPSENSE_TCA2_TCA2(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_TCA2_TCA2_SHIFT)) & TEMPSENSE_TCA2_TCA2_MASK) 141 /*! @} */ 142 143 /*! 144 * @} 145 */ /* end of group TEMPSENSE_Register_Masks */ 146 147 /*! 148 * @} 149 */ /* end of group TEMPSENSE_Peripheral_Access_Layer */ 150 151 #endif /* #if !defined(S32K344_TEMPSENSE_H_) */ 152
