1 /**************************************************************************//** 2 * @file tamper_reg.h 3 * @version V1.00 4 * @brief Tamper register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __TAMPER_REG_H__ 10 #define __TAMPER_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 19 /*---------------------------- Tamper Controller ----------------------------*/ 20 /** 21 @addtogroup Tamper Controller(TAMPER) 22 Memory Mapped Structure for Tamper Controller 23 @{ 24 */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var TAMPER_T::INIT 32 * Offset: 0x00 Tamper Function Initiation Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |TCORERST |Tamper Core Reset 37 * | | |0 = Write 0x5500; the Tamper core block reset will be released. 38 * | | |1 = Write 0x55AA; the Tamper core block will be reset. 39 * |[31] |TLDORDY |Voltage Regulator Power Ready (Read Only) 40 * | | |0 = The power status of voltage regulator is not ready. 41 * | | |1 = The power status of voltage regulator is ready. 42 * @var TAMPER_T::FUNEN 43 * Offset: 0x04 Tamper Block Function Enable Register 44 * --------------------------------------------------------------------------------------------------- 45 * |Bits |Field |Descriptions 46 * | :----: | :----: | :---- | 47 * |[0] |LXTDETEN |LXT Clock Detection Enable Bit 48 * | | |0 = Write 0x40; the LXT clock detection Disabled. 49 * | | |1 = Write 0x44; the LXT clock detection Enabled. 50 * |[13:8] |TMPIOSEL |Tamper I/O Detection Selection Bit 51 * | | |0 = Write 0x90/0xA0/0xB0/0xC0/0xD0/0xE0 for tamper I/O 0~5; the I/O tamper function is detected through RTC block. 52 * | | |1 = Write 0x94/0xA4/0xB4/0xC4/0xD4/0xE4 for tamper I/O 0~5; the I/O tamper function is detected through Tamper block. 53 * |[23:16] |HIRC48MEN |HIRC48M Enable Bit 54 * | | |The HIRC48M is disabled when these bits equal 0x5A, otherwise it will be enabled with any other values. 55 * |[24] |VGCHEN0 |Voltage Glitch Channel 0 Enable Bit 56 * | | |0 = Voltage glitch channel 0 Disabled. 57 * | | |1 = Voltage glitch channel 0 Enabled. 58 * | | |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled. 59 * |[25] |VGCHEN1 |Voltage Glitch Channel 1 Enable Bit 60 * | | |0 = Voltage glitch channel 1 Disabled. 61 * | | |1 = Voltage glitch channel 1 Enabled. 62 * | | |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled. 63 * |[26] |VGCHEN2 |Voltage Glitch Channel 2 Enable Bit 64 * | | |0 = Voltage glitch channel 2 Disabled. 65 * | | |1 = Voltage glitch channel 2 Enabled. 66 * | | |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled. 67 * |[27] |VGCHEN3 |Voltage Glitch Channel 3 Enable Bit 68 * | | |0 = Voltage glitch channel 3 Disabled. 69 * | | |1 = Voltage glitch channel 3 Enabled. 70 * | | |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled. 71 * @var TAMPER_T::TRIEN 72 * Offset: 0x08 Tamper Trigger Enable Register 73 * --------------------------------------------------------------------------------------------------- 74 * |Bits |Field |Descriptions 75 * | :----: | :----: | :---- | 76 * |[1] |KSTRIGEN |Key Store Trigger Enable Bit 77 * | | |0 = Tamper event is detected and to trigger Key Store Disabled. 78 * | | |1 = Tamper event is detected and to trigger Key Store Enabled. 79 * |[2] |WAKEUPEN |Wakeup Enable Bit 80 * | | |0 = Tamper wakeup event Disabled. 81 * | | |1 = Tamper wakeup event Enabled. 82 * |[3] |CRYPTOEN |Crypto Enable Bit 83 * | | |0 = Tamper event clear Crypto Disabled. 84 * | | |1 = Tamper event clear Crypto Enabled. 85 * |[4] |CHIPRSTEN |Chip Reset Enable Bit 86 * | | |0 = Tamper event trigger chip reset Disabled. 87 * | | |1 = Tamper event trigger chip reset Enabled. 88 * |[5] |RTCSPCLREN|RTC Spare Register Clear Enable Bit 89 * | | |0 = Tamper event trigger RTC spare register reset Disabled. 90 * | | |1 = Tamper event trigger RTC spare register reset Enabled. 91 * @var TAMPER_T::INTEN 92 * Offset: 0x0C Tamper Event Interrupt Enable Register 93 * --------------------------------------------------------------------------------------------------- 94 * |Bits |Field |Descriptions 95 * | :----: | :----: | :---- | 96 * |[0] |TAMP0IEN |Tamper 0 Event Interrupt Enable Bit 97 * | | |0 = Tamper 0 event interrupt Disabled. 98 * | | |1 = Tamper 0 event interrupt Enabled. 99 * |[1] |TAMP1IEN |Tamper 1 or Pair 0 Event Interrupt Enable Bit 100 * | | |0 = Tamper 1 or Pair 0 event interrupt Disabled. 101 * | | |1 = Tamper 1 or Pair 0 event interrupt Enabled. 102 * |[2] |TAMP2IEN |Tamper 2 Event Interrupt Enable Bit 103 * | | |0 = Tamper 2 event interrupt Disabled. 104 * | | |1 = Tamper 2 event interrupt Enabled. 105 * |[3] |TAMP3IEN |Tamper 3 or Pair 1 Event Interrupt Enable Bit 106 * | | |0 = Tamper 3 or Pair 1 event interrupt Disabled. 107 * | | |1 = Tamper 3 or Pair 1 event interrupt Enabled. 108 * |[4] |TAMP4IEN |Tamper 4 Event Interrupt Enable Bit 109 * | | |0 = Tamper 4 event interrupt Disabled. 110 * | | |1 = Tamper 4 event interrupt Enabled. 111 * |[5] |TAMP5IEN |Tamper 5 or Pair 2 Event Interrupt Enable Bit 112 * | | |0 = Tamper 5 or Pair 2 event interrupt Disabled. 113 * | | |1 = Tamper 5 or Pair 2 event interrupt Enabled. 114 * |[6] |CLKFIEN |LXT Clock Frequency Monitor Fail Event Interrupt Enable Bit 115 * | | |0 = LXT frequency fail event interrupt Disabled. 116 * | | |1 = LXT frequency fail event interrupt Enabled. 117 * |[7] |CLKSTOPIEN|LXT Clock Frequency Monitor Stop Event Interrupt Enable Bit 118 * | | |0 = LXT frequency stop event interrupt Disabled. 119 * | | |1 = LXT frequency stop event interrupt Enabled. 120 * |[8] |OVPIEN |VDD Over Voltage Protect Detection Interrupt Enable Bit 121 * | | |0 = Detect VDD over voltage protect detection interrupt Disabled. 122 * | | |1 = Detect VDD over voltage protect detection interrupt Enabled. 123 * | | |Note: The function enable of the over voltage detection is defined in system manager. 124 * |[9] |VGPIEN |Voltage Glitch Positive Detection Event Interrupt Enable Bit 125 * | | |0 = LDO_CAP positive glitch event interrupt Disabled. 126 * | | |1 = LDO_CAP positive glitch event interrupt Enabled. 127 * |[10] |VGNIEN |Voltage Glitch Negative Detection Event Interrupt Enable Bit 128 * | | |0 = LDO_CAP negative glitch event interrupt Disabled. 129 * | | |1 = LDO_CAP negative glitch event interrupt Enabled. 130 * |[11] |ACTSIEN |Active Shield Event Interrupt Enable Bit 131 * | | |0 = Active shield event interrupt Disabled. 132 * | | |1 = Active shield event interrupt Enabled. 133 * |[16] |RTCLVRIEN |RTC Low Voltage Detection Event Interrupt Enable Bit 134 * | | |0 = VBAT low voltage detection event interrupt Disabled. 135 * | | |1 = VBAT low voltage detection event interrupt Enabled. 136 * |[17] |RTCIOIEN |RTC Tamper I/O Event Interrupt Enable Bit 137 * | | |0 = RTC tamper I/O detection event interrupt Disabled. 138 * | | |1 = RTC tamper I/O detection event interrupt Enabled. 139 * |[18] |RTCLKIEN |RTC Clock Monitor Detection Event Interrupt Enable Bit 140 * | | |0 = RTC clock monitor event interrupt Disabled. 141 * | | |1 = RTC clock monitor event interrupt Enabled. 142 * |[22] |BODIEN |BOD Event Interrupt Enable Bit 143 * | | |0 = Brown-out event interrupt Disabled. 144 * | | |1 = Brown-out event interrupt Enabled. 145 * @var TAMPER_T::INTSTS 146 * Offset: 0x10 Tamper Interrupt Status Register 147 * --------------------------------------------------------------------------------------------------- 148 * |Bits |Field |Descriptions 149 * | :----: | :----: | :---- | 150 * |[0] |TAMP0IF |Tamper 0 Event Interrupt Flag 151 * | | |0 = No Tamper 0 event interrupt flag is generated. 152 * | | |1 = Tamper 0 event interrupt flag is generated. 153 * | | |Note: Write 1 to clear this bit. 154 * |[1] |TAMP1IF |Tamper 1 Event Interrupt Flag 155 * | | |0 = No Tamper 1 event interrupt flag is generated. 156 * | | |1 = Tamper 1 event interrupt flag is generated. 157 * | | |Note: Write 1 to clear this bit. 158 * |[2] |TAMP2IF |Tamper 2 Event Interrupt Flag 159 * | | |0 = No Tamper 2 event interrupt flag is generated. 160 * | | |1 = Tamper 2 event interrupt flag is generated. 161 * | | |Note: Write 1 to clear this bit. 162 * |[3] |TAMP3IF |Tamper 3 Event Interrupt Flag 163 * | | |0 = No Tamper 3 event interrupt flag is generated. 164 * | | |1 = Tamper 3 event interrupt flag is generated. 165 * | | |Note: Write 1 to clear this bit. 166 * |[4] |TAMP4IF |Tamper 4 Event Interrupt Flag 167 * | | |0 = No Tamper 4 event interrupt flag is generated. 168 * | | |1 = Tamper 4 event interrupt flag is generated. 169 * | | |Note: Write 1 to clear this bit. 170 * |[5] |TAMP5IF |Tamper 5 Event Interrupt Flag 171 * | | |0 = No Tamper 5 event interrupt flag is generated. 172 * | | |1 = Tamper 5 event interrupt flag is generated. 173 * | | |Note: Write 1 to clear this bit. 174 * |[6] |CLKFAILIF |LXT Clock Frequency Monitor Fail Event Interrupt Flag 175 * | | |0 = LXT frequency is normal. 176 * | | |1 = LXT frequency is abnormal. 177 * | | |Note 1: Write 1 to clear this bit to 0. 178 * | | |Note 2: LXT detector will be automatically disabled when Fail/Stop flag rises, and resumes after Fail/Stop flag is cleared. 179 * |[7] |CLKSTOPIF |LXT Clock Frequency Monitor Stop Event Interrupt Flag 180 * | | |0 = LXT frequency is normal. 181 * | | |1 = LXT frequency is almost stopped. 182 * | | |Note 1: Write 1 to clear this bit to 0. 183 * | | |Note 2: LXT detector will be automatically disabled when Fail/Stop flag rises, and resumes after Fail/Stop flag is cleared. 184 * |[8] |OVPOUTIF |VDD Over Voltage Event Interrupt Flag 185 * | | |0 = VDD no over voltage is detected. 186 * | | |1 = VDD over voltage is detected. 187 * | | |Note: Write 1 to clear this bit. 188 * |[9] |VGPEVIF |Voltage Glitch Positive Detection Interrupt Flag 189 * | | |0 = LDO_CAP positive glitch is not detected. 190 * | | |1 = LDO_CAP positive glitch is detected. 191 * | | |Note: It can be written 1 to clear only (No clear by TCORERST) 192 * |[10] |VGNEVIF |Voltage Glitch Negative Detection Interrupt Flag 193 * | | |0 = LDO_CAP negative glitch is not detected. 194 * | | |1 = LDO_CAP negative glitch is detected. 195 * | | |Note: It can be written 1 to clear only (No clear by TCORERST) 196 * |[11] |ACTSEIF |Active Shield Event Detection Interrupt Flag 197 * | | |0 = Active shield event interrupt flag is not detected. 198 * | | |1 = Active shield event interrupt flag is detected including the voltage of voltage regulator and GND attack. 199 * | | |Note: Write 1 to clear this bit after all of ACTSTxIF bits have been cleaned. 200 * |[13] |ACTST5IF |Active Shield Tamper 5 Event Interrupt Flag 201 * | | |0 = No Active shield Tamper 5 event interrupt flag is generated. 202 * | | |1 = Active shield Tamper 5 event interrupt flag is generated. 203 * | | |Note: Write 1 to clear this bit. 204 * |[15] |ACTST25IF |Active Shield Tamper 5 Event Interrupt Flag 205 * | | |0 = No Active shield Tamper 5 event interrupt flag is generated. 206 * | | |1 = 2th Active shield Tamper 5 event interrupt flag is generated. 207 * | | |Note: Write 1 to clear this bit. 208 * |[16] |RTCLVRIF |RTC Low Voltage Detection Event Interrupt Flag 209 * | | |0 = VBAT low voltage detection event interrupt flag is not detected. 210 * | | |1 = VBAT low voltage detection event interrupt flag is detected. 211 * |[17] |RIOTRIGIF |RTC Tamper I/O Event Interrupt Flag 212 * | | |0 = There is no RTC tamper I/O detection event interrupt flag. 213 * | | |1 = There is RTC tamper I/O detection event interrupt flag. 214 * |[18] |RCLKTRIGIF|RTC Clock Monitor Detection Event Interrupt Flag 215 * | | |0 = There is no RTC clock monitor detection event interrupt flag. 216 * | | |1 = There is RTC clock monitor detection event interrupt flag. 217 * |[22] |BODIF |BOD Event Interrupt Flag 218 * | | |0 = Brown-out event interrupt flag is no detected. 219 * | | |1 = Brown-out interrupt flag is detected. 220 * | | |Note: It is used to detect the LDO_CAP. Write 1 to clear this bit. 221 * |[25] |ACTST1IF |Active Shield Tamper 1 Event Interrupt Flag 222 * | | |0 = No Active shield Tamper 1 event interrupt flag is generated. 223 * | | |1 = Active shield Tamper 1 event interrupt flag is generated. 224 * | | |Note: Write 1 to clear this bit. 225 * |[27] |ACTST3IF |Active Shield Tamper 3 Event Interrupt Flag 226 * | | |0 = No Active shield Tamper 3 event interrupt flag is generated. 227 * | | |1 = Active shield Tamper 3 event interrupt flag is generated. 228 * | | |Note: Write 1 to clear this bit. 229 * |[29] |ACTST21IF |2th Active Shield Tamper 1 Event Interrupt Flag 230 * | | |0 = No Active shield Tamper 1 event interrupt flag is generated. 231 * | | |1 = 2th Active shield Tamper 1 event interrupt flag is generated. 232 * | | |Note: Write 1 to clear this bit. 233 * |[31] |ACTST23IF |2th Active Shield Tamper 3 Event Interrupt Flag 234 * | | |0 = No Active shield Tamper 3 event interrupt flag is generated. 235 * | | |1 = 2th Active shield Tamper 3 event interrupt flag is generated. 236 * | | |Note: Write 1 to clear this bit. 237 * @var TAMPER_T::LIRCTL 238 * Offset: 0x14 Tamper LIRC Control Register 239 * --------------------------------------------------------------------------------------------------- 240 * |Bits |Field |Descriptions 241 * | :----: | :----: | :---- | 242 * |[8:0] |TLRCTRIM |Tamper TLIRC32K Trim Value 243 * | | |TLIRC32K trim value setting 244 * |[10:9] |TRIMMOS |Tamper TLIRC32K Trim MOS Value 245 * | | |TLIRC32K trim MOS value setting 246 * @var TAMPER_T::TIOCTL 247 * Offset: 0x18 Tamper I/O Function Control Register 248 * --------------------------------------------------------------------------------------------------- 249 * |Bits |Field |Descriptions 250 * | :----: | :----: | :---- | 251 * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select 252 * | | |This bit determines Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. 253 * | | |0 = Tamper input is from Tamper 2. 254 * | | |1 = Tamper input is from Tamper 0. 255 * | | |Note: This bit is effective only when DYNPR1EN (TAMPER_TIOCTL[23]) and DYNPR0EN (TAMPER_TIOCTL[15]) are set. 256 * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select 257 * | | |This bit determines Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. 258 * | | |0 = Tamper input is from Tamper 4. 259 * | | |1 = Tamper input is from Tamper 0. 260 * | | |Note: This bit has effect only when DYNPR2EN (TAMPER_TIOCTL[31]) and DYNPR0EN (TAMPER_TIOCTL[15]) are set. 261 * |[3] |DYNSRC |Dynamic Reference Pattern 262 * | | |This field determines the new reference pattern when current pattern run out in dynamic pair mode. 263 * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. 264 * | | |1 = The new reference pattern is repeated from SEED (TAMPER_SEED[31:0]) when the reference pattern run out. 265 * | | |Note: After this bit is modified, the SEEDRLD (TAMPER_TIOCTL[4]) should be set. 266 * |[4] |SEEDRLD |Reload New Seed for PRNG Engine 267 * | | |Setting this bit, the tamper configuration will be reloaded. 268 * | | |0 = Generating key based on the current seed. 269 * | | |1 = Reload new seed. 270 * | | |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. 271 * | | |Note 2: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. 272 * |[7:5] |DYNRATE |Dynamic Change Rate 273 * | | |This item is choice the dynamic tamper output change rate. 274 * | | |000 = 26 * RTC_CLK. 275 * | | |001 = 27 * RTC_CLK. 276 * | | |010 = 28 * RTC_CLK. 277 * | | |011 = 29 * RTC_CLK. 278 * | | |100 = 210 * RTC_CLK. 279 * | | |101 = 211 * RTC_CLK. 280 * | | |110 = 212 * RTC_CLK. 281 * | | |111 = 213 * RTC_CLK. 282 * | | |Note: After revising this field, setting SEEDRLD (TAMPER_TIOCTL[4]) can reload change rate immediately. 283 * |[8] |TAMP0EN |Tamper0 Detect Enable Bit 284 * | | |0 = Tamper 0 detect Disabled. 285 * | | |1 = Tamper 0 detect Enabled. 286 * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. 287 * |[9] |TAMP0LV |Tamper 0 Level 288 * | | |This bit depends on level attribute of tamper pin for static tamper detection. 289 * | | |0 = Detect voltage level is low. 290 * | | |1 = Detect voltage level is high. 291 * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit 292 * | | |0 = Tamper 0 de-bounce Disabled. 293 * | | |1 = Tamper 0 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. 294 * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit 295 * | | |0 = Tamper 1 detect Disabled. 296 * | | |1 = Tamper 1 detect Enabled. 297 * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. 298 * |[13] |TAMP1LV |Tamper 1 Level 299 * | | |This bit depends on level attribute of tamper pin for static tamper detection. 300 * | | |0 = Detect voltage level is low. 301 * | | |1 = Detect voltage level is high. 302 * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit 303 * | | |0 = Tamper 1 de-bounce Disabled. 304 * | | |1 = Tamper 1 de-bounce Enabled, tamper detection pin will sync 1 RTC clock. 305 * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit 306 * | | |0 = Static detect. 307 * | | |1 = Dynamic detect. 308 * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit 309 * | | |0 = Tamper 2 detect Disabled. 310 * | | |1 = Tamper 2 detect Enabled. 311 * | | |Note: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock. 312 * |[17] |TAMP2LV |Tamper 2 Level 313 * | | |This bit depends on level attribute of tamper pin for static tamper detection. 314 * | | |0 = Detect voltage level is low. 315 * | | |1 = Detect voltage level is high. 316 * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit 317 * | | |0 = Tamper 2 de-bounce Disabled. 318 * | | |1 = Tamper 2 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. 319 * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit 320 * | | |0 = Tamper 3 detect Disabled. 321 * | | |1 = Tamper 3 detect Enabled. 322 * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. 323 * |[21] |TAMP3LV |Tamper 3 Level 324 * | | |This bit depends on level attribute of tamper pin for static tamper detection. 325 * | | |0 = Detect voltage level is low. 326 * | | |1 = Detect voltage level is high. 327 * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit 328 * | | |0 = Tamper 3 de-bounce Disabled. 329 * | | |1 = Tamper 3 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. 330 * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit 331 * | | |0 = Static detect. 332 * | | |1 = Dynamic detect. 333 * |[24] |TAMP4EN |Tamper4 Detect Enable Bit 334 * | | |0 = Tamper 4 detect Disabled. 335 * | | |1 = Tamper 4 detect Enabled. 336 * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. 337 * |[25] |TAMP4LV |Tamper 4 Level 338 * | | |This bit depends on level attribute of tamper pin for static tamper detection. 339 * | | |0 = Detect voltage level is low. 340 * | | |1 = Detect voltage level is high. 341 * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit 342 * | | |0 = Tamper 4 de-bounce Disabled. 343 * | | |1 = Tamper 4 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. 344 * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit 345 * | | |0 = Tamper 5 detect Disabled. 346 * | | |1 = Tamper 5 detect Enabled. 347 * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. 348 * |[29] |TAMP5LV |Tamper 5 Level 349 * | | |This bit depends on level attribute of tamper pin for static tamper detection. 350 * | | |0 = Detect voltage level is low. 351 * | | |1 = Detect voltage level is high. 352 * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit 353 * | | |0 = Tamper 5 de-bounce Disabled. 354 * | | |1 = Tamper 5 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. 355 * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit 356 * | | |0 = Static detect. 357 * | | |1 = Dynamic detect. 358 * @var TAMPER_T::SEED 359 * Offset: 0x1C Tamper Seed Value Control Register 360 * --------------------------------------------------------------------------------------------------- 361 * |Bits |Field |Descriptions 362 * | :----: | :----: | :---- | 363 * |[31:0] |SEED |Seed value. 364 * @var TAMPER_T::SEED2 365 * Offset: 0x20 Tamper 2nd Seed Value Control Register 366 * --------------------------------------------------------------------------------------------------- 367 * |Bits |Field |Descriptions 368 * | :----: | :----: | :---- | 369 * |[31:0] |SEED2 |Seed value. These seed value are used for 2nd active shield I/O. 370 * @var TAMPER_T::ACTSTIOCTL1 371 * Offset: 0x24 Tamper Active Shield Tamper I/O Function Control Register 1 372 * --------------------------------------------------------------------------------------------------- 373 * |Bits |Field |Descriptions 374 * | :----: | :----: | :---- | 375 * |[0] |ADYN1ISS |Active Shied Dynamic Pair 1 Input Source Select 376 * | | |This bit determines Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. 377 * | | |0 = Tamper input is from Tamper 2. 378 * | | |1 = Tamper input is from Tamper 0. 379 * | | |Note: This bit is effective only when ADYNPR1EN (TAMPER_ACTSTIOCTL1[23]) and ADYNPR0EN (TAMPER_ACTSTIOCTL1[15]) are set. 380 * |[3] |ADYNSRC |Active Shied Dynamic Reference Pattern 381 * | | |This field determines the new reference pattern when current pattern run out in dynamic pair mode. 382 * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. 383 * | | |1 = The new reference pattern is repeated from SEED (TAMPER_SEED[31:0]) when the reference pattern run out. 384 * | | |Note: After this bit is modified, the SEEDRLD (TAMPER_TIOCTL[4]) should be set. 385 * |[7:5] |ADYNRATE |Active Shied Dynamic Change Rate 386 * | | |Use the bits to choose the dynamic tamper output change rate. 387 * | | |000 = 210 * TLIRC32K. 388 * | | |001 = 211 * TLIRC32K. 389 * | | |010 = 212 * TLIRC32K. 390 * | | |011 = 213 * TLIRC32K. 391 * | | |100 = 214 * TLIRC32K. 392 * | | |101 = 215 * TLIRC32K. 393 * | | |110 = 216 * TLIRC32K. 394 * | | |111 = 217 * TLIRC32K. 395 * | | |Note: After this field is modified, setting SEEDRLD (TAMPER_TIOCTL[4]) can reload the change rate immediately. 396 * |[8] |ATAMP0EN |Active Shied Tamper0 Detect Enable Bit 397 * | | |0 = Tamper 0 detect Disabled. 398 * | | |1 = Tamper 0 detect Enabled. 399 * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. 400 * |[12] |ATAMP1EN |Active Shied Tamper 1 Detect Enable Bit 401 * | | |0 = Tamper 1 detect Disabled. 402 * | | |1 = Tamper 1 detect Enabled. 403 * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. 404 * |[15] |ADYNPR0EN |Active Shied Dynamic Pair 0 Enable Bit 405 * | | |0 = Static detect (Not supported). 406 * | | |1 = Dynamic detect. 407 * |[16] |ATAMP2EN |Active Shied Tamper 2 Detect Enable Bit 408 * | | |0 = Tamper 2 detect Disabled. 409 * | | |1 = Tamper 2 detect Enabled. 410 * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. 411 * |[20] |ATAMP3EN |Active Shied Tamper 3 Detect Enable Bit 412 * | | |0 = Tamper 3 detect Disabled. 413 * | | |1 = Tamper 3 detect Enabled. 414 * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. 415 * |[23] |ADYNPR1EN |Active Shied Dynamic Pair 1 Enable Bit 416 * | | |0 = Static detect (Not supported). 417 * | | |1 = Dynamic detect. 418 * |[24] |ATAMP4EN |Active Tamper4 Detect Enable Bit 419 * | | |0 = Tamper 4 detect Disabled. 420 * | | |1 = Tamper 4 detect Enabled. 421 * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. 422 * |[28] |ATAMP5EN |Active Tamper 5 Detect Enable Bit 423 * | | |0 = Tamper 5 detect Disabled. 424 * | | |1 = Tamper 5 detect Enabled. 425 * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. 426 * |[31] |ADYNPR2EN |Active Shied Dynamic Pair 2 Enable Bit 427 * | | |0 = Static detect (Not supported). 428 * | | |1 = Dynamic detect. 429 * @var TAMPER_T::ACTSTIOCTL2 430 * Offset: 0x28 Tamper Active Shield Tamper I/O Function Control Register 2 431 * --------------------------------------------------------------------------------------------------- 432 * |Bits |Field |Descriptions 433 * | :----: | :----: | :---- | 434 * |[0] |ADYN1ISS2 |Active Shied Dynamic Pair 1 Input Source Select 2 435 * | | |This bit determines if Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. 436 * | | |0 = Tamper input is from Tamper 2. 437 * | | |1 = Tamper input is from Tamper 0. 438 * | | |Note: This bit is effective only when ADYNPR1EN2 (TAMPER_ACTSTIOCTL2[23]) and ADYNPR0EN2 (TAMPER_ACTSTIOCTL2[15]) are set. 439 * |[3] |ADYNSRC2 |Active Shied Dynamic Reference Pattern 2 440 * | | |This field determines the new reference pattern when current pattern run out in dynamic pair mode. 441 * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. 442 * | | |1 = The new reference pattern is repeated from SEED2 (TAMPER_SEED2[31:0]) when the reference pattern run out. 443 * | | |Note: After this bit is modified, the SEEDRLD2 (TAMPER_ACTSTIOCTL2[4]) should be set. 444 * |[4] |SEEDRLD2 |Reload New Seed for PRNG Engine 2 445 * | | |Setting this bit, the tamper configuration will be reloaded. 446 * | | |0 = Generating key based on the current seed. 447 * | | |1 = Reload new seed. 448 * | | |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. 449 * | | |Note 2: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. 450 * |[7:5] |ADYNRATE2 |Active Shied Dynamic Change Rate 2 451 * | | |Use the bits to choose the dynamic tamper output change rate. 452 * | | |000 = 210 * TLIRC32K. 453 * | | |001 = 211 * TLIRC32K. 454 * | | |010 = 212 * TLIRC32K. 455 * | | |011 = 213 * TLIRC32K. 456 * | | |100 = 214 * TLIRC32K. 457 * | | |101 = 215 * TLIRC32K. 458 * | | |110 = 216 * TLIRC32K. 459 * | | |111 = 217 * TLIRC32K. 460 * | | |Note: After this field is modified, setting SEEDRLD2 (TAMPER_ACTSTIOCTL2[4]) can reload change rate immediately. 461 * |[8] |ATAMP0EN2 |Active Shied Tamper0 Detect Enable Bit 2 462 * | | |0 = Tamper 0 detect Disabled. 463 * | | |1 = Tamper 0 detect Enabled. 464 * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. 465 * |[12] |ATAMP1EN2 |Active Shied Tamper 1 Detect Enable Bit 2 466 * | | |0 = Tamper 1 detect Disabled. 467 * | | |1 = Tamper 1 detect Enabled. 468 * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. 469 * |[15] |ADYNPR0EN2|Active Shied Dynamic Pair 0 Enable Bit 2 470 * | | |0 = Static detect (Not supported). 471 * | | |1 = Dynamic detect. 472 * |[16] |ATAMP2EN2 |Active Shied Tamper 2 Detect Enable Bit 2 473 * | | |0 = Tamper 2 detect Disabled. 474 * | | |1 = Tamper 2 detect Enabled. 475 * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. 476 * |[20] |ATAMP3EN2 |Active Shied Tamper 3 Detect Enable Bit 2 477 * | | |0 = Tamper 3 detect Disabled. 478 * | | |1 = Tamper 3 detect Enabled. 479 * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. 480 * |[23] |ADYNPR1EN2|Active Shied Dynamic Pair 1 Enable Bit 2 481 * | | |0 = Static detect (Not supported). 482 * | | |1 = Dynamic detect. 483 * |[24] |ATAMP4EN2 |Active Shied Tamper4 Detect Enable Bit 2 484 * | | |0 = Tamper 4 detect Disabled. 485 * | | |1 = Tamper 4 detect Enabled. 486 * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. 487 * |[28] |ATAMP5EN2 |Active Tamper 5 Detect Enable Bit 2 488 * | | |0 = Tamper 5 detect Disabled. 489 * | | |1 = Tamper 5 detect Enabled. 490 * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. 491 * |[31] |ADYNPR2EN2|Active Shied Dynamic Pair 2 Enable Bit 2 492 * | | |0 = Static detect (Not supported). 493 * | | |1 = Dynamic detect. 494 * @var TAMPER_T::CDBR 495 * Offset: 0x2C Tamper Clock Frequency Detector Boundary Register 496 * --------------------------------------------------------------------------------------------------- 497 * |Bits |Field |Descriptions 498 * | :----: | :----: | :---- | 499 * |[7:0] |STOPBD |LXT Clock Frequency Detector Stop Boundary 500 * | | |The bits define the stop value of frequency monitor window. 501 * | | |When LXT frequency monitor counter lower than Clock Frequency Detector Stop Boundary, the LXT frequency detect stop interrupt flag will set to 1. 502 * | | |Note: The boundary is defined as the maximum value of LXT among 256 Tamper clock time. 503 * |[23:16] |FAILBD |LXT Clock Frequency Detector Fail Boundary 504 * | | |The bits define the fail value of frequency monitor window. 505 * | | |When LXT frequency monitor counter lower than Clock Frequency Detector Fail Boundary, the LXT frequency detect fail interrupt flag will set to 1. 506 * | | |Note: The boundary is defined as the minimum value of LXT among 256 Tamper clock time. 507 * @var TAMPER_T::VG 508 * Offset: 0x30 Tamper Voltage Glitch Control Register 509 * --------------------------------------------------------------------------------------------------- 510 * |Bits |Field |Descriptions 511 * | :----: | :----: | :---- | 512 * |[3:0] |PCLKSEL0 |PL0 Positive Clock Trim Range 513 * | | |The setting value of the positive clock tolerance. 514 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 515 * | | |Note: PL0 means the power level is 1.26V 516 * | | |The power level is controlled in system manager 517 * |[7:4] |NCLKSEL0 |PL0 Negative Clock Trim Range 518 * | | |The setting value of the negative clock tolerance. 519 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 520 * |[11:8] |PDATSEL0 |PL0 Positive Data Trim Range 521 * | | |The setting value of the positive data tolerance. 522 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 523 * |[15:12] |NDATSEL0 |PL0 Negative Data Trim Range 524 * | | |The setting value of the negative data tolerance. 525 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 526 * |[19:16] |PCLKSEL1 |PL1 Positive Clock Trim Range 527 * | | |The setting value of the positive clock tolerance. 528 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 529 * | | |Note: PL1 means the power level is 1.2V 530 * |[23:20] |NCLKSEL1 |PL1 Negative Clock Trim Range 531 * | | |The setting value of the negative clock tolerance. 532 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 533 * |[27:24] |PDATSEL1 |PL1 Positive Data Trim Range 534 * | | |The setting value of the positive data tolerance. 535 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 536 * |[31:28] |NDATSEL1 |PL1 Negative Data Trim Range 537 * | | |The setting value of the negative data tolerance. 538 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 539 * @var TAMPER_T::VGEV 540 * Offset: 0x34 Tamper Voltage Glitch Event Tolerance Control Register 541 * --------------------------------------------------------------------------------------------------- 542 * |Bits |Field |Descriptions 543 * | :----: | :----: | :---- | 544 * |[7:0] |VGECNTP |Positive Voltage Glitch Error Tolerance 545 * | | |The value indicates the tolerance count for positive voltage glitch event. 546 * |[15:8] |VGECNTN |Negative Voltage Glitch Error Tolerance 547 * | | |The value indicates the tolerance count for negative voltage glitch event. 548 * @var TAMPER_T::LDOTRIM 549 * Offset: 0x38 Tamper LDO Trim Value Control Register 550 * --------------------------------------------------------------------------------------------------- 551 * |Bits |Field |Descriptions 552 * | :----: | :----: | :---- | 553 * |[3:0] |TLDOTRIM |Voltage Regulator Output Voltage Trim 554 * | | |The value indicates the trim value of the voltage regulator output voltage. 555 * |[9:8] |TLDOIQSEL |Voltage Regulator Qu Current Selection 556 * | | |Indicates the Qu current selection of voltage regulator. 557 * @var TAMPER_T::LBSTRIM 558 * Offset: 0x3C Tamper LDO BIAS Trim Value Control Register 559 * --------------------------------------------------------------------------------------------------- 560 * |Bits |Field |Descriptions 561 * | :----: | :----: | :---- | 562 * |[2:0] |TLVDSEL |Under-shoot Detect Level Trim Bits 563 * | | |The value indicates the trim value of the under-shoot detection level 564 * |[4] |TOVDSEL |Over-shoot Detect Level Trim Bits 565 * | | |The value indicates the trim value of the over-shoot detection level 566 * |[9:8] |BSCMPLV |Under-shoot Detect Comparator Current Trim Bits 567 * | | |The value indicates the trim value of the under-shoot detection comparator current trim level 568 * |[11:10] |BSCMPOV |Over-shoot Detect Comparator Current Trim Bits 569 * | | |The value indicates the trim value of the over-shoot detection comparator current trim level 570 * |[13:12] |HYSCMPLV |Under-shoot Detect Comparator Hysteresis Trim Bits 571 * | | |The value indicates the trim value of the under-shoot detection comparator of hysteresis trim level 572 * |[15:14] |HYSCMPOV |Over-shoot Detect Comparator Hysteresis Trim Bits 573 * | | |The value indicates the trim value of the over-shoot detection comparator of hysteresis trim level 574 * @var TAMPER_T::VG2 575 * Offset: 0x40 Tamper Voltage Glitch Control Register 2 576 * --------------------------------------------------------------------------------------------------- 577 * |Bits |Field |Descriptions 578 * | :----: | :----: | :---- | 579 * |[3:0] |PCLKSEL2 |PL2 Positive Clock Trim Range 580 * | | |The setting value of the positive clock tolerance. 581 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 582 * | | |Note: PL2 means the power level is 1.1V 583 * | | |The power level is controlled in system manager. 584 * |[7:4] |NCLKSEL2 |PL2 Negative Clock Trim Range 585 * | | |The setting value of the negative clock tolerance. 586 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 587 * |[11:8] |PDATSEL2 |PL2 Positive Data Trim Range 588 * | | |The setting value of the positive data tolerance. 589 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 590 * |[15:12] |NDATSEL2 |PL2 Negative Data Trim Range 591 * | | |The setting value of the negative data tolerance. 592 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 593 * |[19:16] |PCLKSEL3 |PL3 Positive Clock Trim Range 594 * | | |The setting value of the positive clock tolerance. 595 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 596 * | | |Note: PL3 means the power level is 0.9V 597 * |[23:20] |NCLKSEL3 |PL3 Negative Clock Trim Range 598 * | | |The setting value of the negative clock tolerance. 599 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 600 * |[27:24] |PDATSEL3 |PL3 Positive Data Trim Range 601 * | | |The setting value of the positive data tolerance. 602 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 603 * |[31:28] |NDATSEL3 |PL3 Negative Data Trim Range 604 * | | |The setting value of the negative data tolerance. 605 * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. 606 */ 607 __IO uint32_t INIT; /*!< [0x0000] Tamper Function Initiation Register */ 608 __IO uint32_t FUNEN; /*!< [0x0004] Tamper Block Function Enable Register */ 609 __IO uint32_t TRIEN; /*!< [0x0008] Tamper Trigger Enable Register */ 610 __IO uint32_t INTEN; /*!< [0x000c] Tamper Event Interrupt Enable Register */ 611 __IO uint32_t INTSTS; /*!< [0x0010] Tamper Interrupt Status Register */ 612 __IO uint32_t LIRCTL; /*!< [0x0014] Tamper LIRC Control Register */ 613 __IO uint32_t TIOCTL; /*!< [0x0018] Tamper I/O Function Control Register */ 614 __IO uint32_t SEED; /*!< [0x001c] Tamper Seed Value Control Register */ 615 __IO uint32_t SEED2; /*!< [0x0020] Tamper 2nd Seed Value Control Register */ 616 __IO uint32_t ACTSTIOCTL1; /*!< [0x0024] Tamper Active Shield Tamper I/O Function Control Register 1 */ 617 __IO uint32_t ACTSTIOCTL2; /*!< [0x0028] Tamper Active Shield Tamper I/O Function Control Register 2 */ 618 __IO uint32_t CDBR; /*!< [0x002c] Tamper Clock Frequency Detector Boundary Register */ 619 __IO uint32_t VG; /*!< [0x0030] Tamper Voltage Glitch Control Register */ 620 __IO uint32_t VGEV; /*!< [0x0034] Tamper Voltage Glitch Event Tolerance Control Register */ 621 __IO uint32_t LDOTRIM; /*!< [0x0038] Tamper LDO Trim Value Control Register */ 622 __IO uint32_t LBSTRIM; /*!< [0x003c] Tamper LDO BIAS Trim Value Control Register */ 623 __IO uint32_t VG2; /*!< [0x0040] Tamper Voltage Glitch Control Register 2 */ 624 625 } TAMPER_T; 626 627 /** 628 @addtogroup TAMPER_CONST Tamper Bit Field Definition 629 Constant Definitions for Tamper Controller 630 @{ 631 */ 632 633 #define TAMPER_INIT_TCORERST_Pos (0) /*!< TAMPER_T::INIT: TCORERST Position */ 634 #define TAMPER_INIT_TCORERST_Msk (0x1ul << TAMPER_INIT_TCORERST_Pos) /*!< TAMPER_T::INIT: TCORERST Mask */ 635 636 #define TAMPER_INIT_TLDORDY_Pos (31) /*!< TAMPER_T::INIT: TLDORDY Position */ 637 #define TAMPER_INIT_TLDORDY_Msk (0x1ul << TAMPER_INIT_TLDORDY_Pos) /*!< TAMPER_T::INIT: TLDORDY Mask */ 638 639 #define TAMPER_FUNEN_LXTDETEN_Pos (0) /*!< TAMPER_T::FUNEN: LXTDETEN Position */ 640 #define TAMPER_FUNEN_LXTDETEN_Msk (0x1ul << TAMPER_FUNEN_LXTDETEN_Pos) /*!< TAMPER_T::FUNEN: LXTDETEN Mask */ 641 642 #define TAMPER_FUNEN_TMPIOSEL_Pos (8) /*!< TAMPER_T::FUNEN: TMPIOSEL Position */ 643 #define TAMPER_FUNEN_TMPIOSEL_Msk (0x3ful << TAMPER_FUNEN_TMPIOSEL_Pos) /*!< TAMPER_T::FUNEN: TMPIOSEL Mask */ 644 645 #define TAMPER_FUNEN_HIRC48MEN_Pos (16) /*!< TAMPER_T::FUNEN: HIRC48MEN Position */ 646 #define TAMPER_FUNEN_HIRC48MEN_Msk (0xfful << TAMPER_FUNEN_HIRC48MEN_Pos) /*!< TAMPER_T::FUNEN: HIRC48MEN Mask */ 647 648 #define TAMPER_FUNEN_VGCHEN0_Pos (24) /*!< TAMPER_T::FUNEN: VGCHEN0 Position */ 649 #define TAMPER_FUNEN_VGCHEN0_Msk (0x1ul << TAMPER_FUNEN_VGCHEN0_Pos) /*!< TAMPER_T::FUNEN: VGCHEN0 Mask */ 650 651 #define TAMPER_FUNEN_VGCHEN1_Pos (25) /*!< TAMPER_T::FUNEN: VGCHEN1 Position */ 652 #define TAMPER_FUNEN_VGCHEN1_Msk (0x1ul << TAMPER_FUNEN_VGCHEN1_Pos) /*!< TAMPER_T::FUNEN: VGCHEN1 Mask */ 653 654 #define TAMPER_FUNEN_VGCHEN2_Pos (26) /*!< TAMPER_T::FUNEN: VGCHEN2 Position */ 655 #define TAMPER_FUNEN_VGCHEN2_Msk (0x1ul << TAMPER_FUNEN_VGCHEN2_Pos) /*!< TAMPER_T::FUNEN: VGCHEN2 Mask */ 656 657 #define TAMPER_FUNEN_VGCHEN3_Pos (27) /*!< TAMPER_T::FUNEN: VGCHEN3 Position */ 658 #define TAMPER_FUNEN_VGCHEN3_Msk (0x1ul << TAMPER_FUNEN_VGCHEN3_Pos) /*!< TAMPER_T::FUNEN: VGCHEN3 Mask */ 659 660 #define TAMPER_TRIEN_KSTRIGEN_Pos (1) /*!< TAMPER_T::TRIEN: KSTRIGEN Position */ 661 #define TAMPER_TRIEN_KSTRIGEN_Msk (0x1ul << TAMPER_TRIEN_KSTRIGEN_Pos) /*!< TAMPER_T::TRIEN: KSTRIGEN Mask */ 662 663 #define TAMPER_TRIEN_WAKEUPEN_Pos (2) /*!< TAMPER_T::TRIEN: WAKEUPEN Position */ 664 #define TAMPER_TRIEN_WAKEUPEN_Msk (0x1ul << TAMPER_TRIEN_WAKEUPEN_Pos) /*!< TAMPER_T::TRIEN: WAKEUPEN Mask */ 665 666 #define TAMPER_TRIEN_CRYPTOEN_Pos (3) /*!< TAMPER_T::TRIEN: CRYPTOEN Position */ 667 #define TAMPER_TRIEN_CRYPTOEN_Msk (0x1ul << TAMPER_TRIEN_CRYPTOEN_Pos) /*!< TAMPER_T::TRIEN: CRYPTOEN Mask */ 668 669 #define TAMPER_TRIEN_CHIPRSTEN_Pos (4) /*!< TAMPER_T::TRIEN: CHIPRSTEN Position */ 670 #define TAMPER_TRIEN_CHIPRSTEN_Msk (0x1ul << TAMPER_TRIEN_CHIPRSTEN_Pos) /*!< TAMPER_T::TRIEN: CHIPRSTEN Mask */ 671 672 #define TAMPER_TRIEN_RTCSPCLREN_Pos (5) /*!< TAMPER_T::TRIEN: RTCSPCLREN Position */ 673 #define TAMPER_TRIEN_RTCSPCLREN_Msk (0x1ul << TAMPER_TRIEN_RTCSPCLREN_Pos) /*!< TAMPER_T::TRIEN: RTCSPCLREN Mask */ 674 675 #define TAMPER_INTEN_TAMP0IEN_Pos (0) /*!< TAMPER_T::INTEN: TAMP0IEN Position */ 676 #define TAMPER_INTEN_TAMP0IEN_Msk (0x1ul << TAMPER_INTEN_TAMP0IEN_Pos) /*!< TAMPER_T::INTEN: TAMP0IEN Mask */ 677 678 #define TAMPER_INTEN_TAMP1IEN_Pos (1) /*!< TAMPER_T::INTEN: TAMP1IEN Position */ 679 #define TAMPER_INTEN_TAMP1IEN_Msk (0x1ul << TAMPER_INTEN_TAMP1IEN_Pos) /*!< TAMPER_T::INTEN: TAMP1IEN Mask */ 680 681 #define TAMPER_INTEN_TAMP2IEN_Pos (2) /*!< TAMPER_T::INTEN: TAMP2IEN Position */ 682 #define TAMPER_INTEN_TAMP2IEN_Msk (0x1ul << TAMPER_INTEN_TAMP2IEN_Pos) /*!< TAMPER_T::INTEN: TAMP2IEN Mask */ 683 684 #define TAMPER_INTEN_TAMP3IEN_Pos (3) /*!< TAMPER_T::INTEN: TAMP3IEN Position */ 685 #define TAMPER_INTEN_TAMP3IEN_Msk (0x1ul << TAMPER_INTEN_TAMP3IEN_Pos) /*!< TAMPER_T::INTEN: TAMP3IEN Mask */ 686 687 #define TAMPER_INTEN_TAMP4IEN_Pos (4) /*!< TAMPER_T::INTEN: TAMP4IEN Position */ 688 #define TAMPER_INTEN_TAMP4IEN_Msk (0x1ul << TAMPER_INTEN_TAMP4IEN_Pos) /*!< TAMPER_T::INTEN: TAMP4IEN Mask */ 689 690 #define TAMPER_INTEN_TAMP5IEN_Pos (5) /*!< TAMPER_T::INTEN: TAMP5IEN Position */ 691 #define TAMPER_INTEN_TAMP5IEN_Msk (0x1ul << TAMPER_INTEN_TAMP5IEN_Pos) /*!< TAMPER_T::INTEN: TAMP5IEN Mask */ 692 693 #define TAMPER_INTEN_CLKFIEN_Pos (6) /*!< TAMPER_T::INTEN: CLKFIEN Position */ 694 #define TAMPER_INTEN_CLKFIEN_Msk (0x1ul << TAMPER_INTEN_CLKFIEN_Pos) /*!< TAMPER_T::INTEN: CLKFIEN Mask */ 695 696 #define TAMPER_INTEN_CLKSTOPIEN_Pos (7) /*!< TAMPER_T::INTEN: CLKSTOPIEN Position */ 697 #define TAMPER_INTEN_CLKSTOPIEN_Msk (0x1ul << TAMPER_INTEN_CLKSTOPIEN_Pos) /*!< TAMPER_T::INTEN: CLKSTOPIEN Mask */ 698 699 #define TAMPER_INTEN_OVPIEN_Pos (8) /*!< TAMPER_T::INTEN: OVPIEN Position */ 700 #define TAMPER_INTEN_OVPIEN_Msk (0x1ul << TAMPER_INTEN_OVPIEN_Pos) /*!< TAMPER_T::INTEN: OVPIEN Mask */ 701 702 #define TAMPER_INTEN_VGPIEN_Pos (9) /*!< TAMPER_T::INTEN: VGPIEN Position */ 703 #define TAMPER_INTEN_VGPIEN_Msk (0x1ul << TAMPER_INTEN_VGPIEN_Pos) /*!< TAMPER_T::INTEN: VGPIEN Mask */ 704 705 #define TAMPER_INTEN_VGNIEN_Pos (10) /*!< TAMPER_T::INTEN: VGNIEN Position */ 706 #define TAMPER_INTEN_VGNIEN_Msk (0x1ul << TAMPER_INTEN_VGNIEN_Pos) /*!< TAMPER_T::INTEN: VGNIEN Mask */ 707 708 #define TAMPER_INTEN_ACTSIEN_Pos (11) /*!< TAMPER_T::INTEN: ACTSIEN Position */ 709 #define TAMPER_INTEN_ACTSIEN_Msk (0x1ul << TAMPER_INTEN_ACTSIEN_Pos) /*!< TAMPER_T::INTEN: ACTSIEN Mask */ 710 711 #define TAMPER_INTEN_RTCLVRIEN_Pos (16) /*!< TAMPER_T::INTEN: RTCLVRIEN Position */ 712 #define TAMPER_INTEN_RTCLVRIEN_Msk (0x1ul << TAMPER_INTEN_RTCLVRIEN_Pos) /*!< TAMPER_T::INTEN: RTCLVRIEN Mask */ 713 714 #define TAMPER_INTEN_RTCIOIEN_Pos (17) /*!< TAMPER_T::INTEN: RTCIOIEN Position */ 715 #define TAMPER_INTEN_RTCIOIEN_Msk (0x1ul << TAMPER_INTEN_RTCIOIEN_Pos) /*!< TAMPER_T::INTEN: RTCIOIEN Mask */ 716 717 #define TAMPER_INTEN_RTCLKIEN_Pos (18) /*!< TAMPER_T::INTEN: RTCLKIEN Position */ 718 #define TAMPER_INTEN_RTCLKIEN_Msk (0x1ul << TAMPER_INTEN_RTCLKIEN_Pos) /*!< TAMPER_T::INTEN: RTCLKIEN Mask */ 719 720 #define TAMPER_INTEN_BODIEN_Pos (22) /*!< TAMPER_T::INTEN: BODIEN Position */ 721 #define TAMPER_INTEN_BODIEN_Msk (0x1ul << TAMPER_INTEN_BODIEN_Pos) /*!< TAMPER_T::INTEN: BODIEN Mask */ 722 723 #define TAMPER_INTSTS_TAMP0IF_Pos (0) /*!< TAMPER_T::INTSTS: TAMP0IF Position */ 724 #define TAMPER_INTSTS_TAMP0IF_Msk (0x1ul << TAMPER_INTSTS_TAMP0IF_Pos) /*!< TAMPER_T::INTSTS: TAMP0IF Mask */ 725 726 #define TAMPER_INTSTS_TAMP1IF_Pos (1) /*!< TAMPER_T::INTSTS: TAMP1IF Position */ 727 #define TAMPER_INTSTS_TAMP1IF_Msk (0x1ul << TAMPER_INTSTS_TAMP1IF_Pos) /*!< TAMPER_T::INTSTS: TAMP1IF Mask */ 728 729 #define TAMPER_INTSTS_TAMP2IF_Pos (2) /*!< TAMPER_T::INTSTS: TAMP2IF Position */ 730 #define TAMPER_INTSTS_TAMP2IF_Msk (0x1ul << TAMPER_INTSTS_TAMP2IF_Pos) /*!< TAMPER_T::INTSTS: TAMP2IF Mask */ 731 732 #define TAMPER_INTSTS_TAMP3IF_Pos (3) /*!< TAMPER_T::INTSTS: TAMP3IF Position */ 733 #define TAMPER_INTSTS_TAMP3IF_Msk (0x1ul << TAMPER_INTSTS_TAMP3IF_Pos) /*!< TAMPER_T::INTSTS: TAMP3IF Mask */ 734 735 #define TAMPER_INTSTS_TAMP4IF_Pos (4) /*!< TAMPER_T::INTSTS: TAMP4IF Position */ 736 #define TAMPER_INTSTS_TAMP4IF_Msk (0x1ul << TAMPER_INTSTS_TAMP4IF_Pos) /*!< TAMPER_T::INTSTS: TAMP4IF Mask */ 737 738 #define TAMPER_INTSTS_TAMP5IF_Pos (5) /*!< TAMPER_T::INTSTS: TAMP5IF Position */ 739 #define TAMPER_INTSTS_TAMP5IF_Msk (0x1ul << TAMPER_INTSTS_TAMP5IF_Pos) /*!< TAMPER_T::INTSTS: TAMP5IF Mask */ 740 741 #define TAMPER_INTSTS_CLKFAILIF_Pos (6) /*!< TAMPER_T::INTSTS: CLKFAILIF Position */ 742 #define TAMPER_INTSTS_CLKFAILIF_Msk (0x1ul << TAMPER_INTSTS_CLKFAILIF_Pos) /*!< TAMPER_T::INTSTS: CLKFAILIF Mask */ 743 744 #define TAMPER_INTSTS_CLKSTOPIF_Pos (7) /*!< TAMPER_T::INTSTS: CLKSTOPIF Position */ 745 #define TAMPER_INTSTS_CLKSTOPIF_Msk (0x1ul << TAMPER_INTSTS_CLKSTOPIF_Pos) /*!< TAMPER_T::INTSTS: CLKSTOPIF Mask */ 746 747 #define TAMPER_INTSTS_OVPOUTIF_Pos (8) /*!< TAMPER_T::INTSTS: OVPOUTIF Position */ 748 #define TAMPER_INTSTS_OVPOUTIF_Msk (0x1ul << TAMPER_INTSTS_OVPOUTIF_Pos) /*!< TAMPER_T::INTSTS: OVPOUTIF Mask */ 749 750 #define TAMPER_INTSTS_VGPEVIF_Pos (9) /*!< TAMPER_T::INTSTS: VGPEVIF Position */ 751 #define TAMPER_INTSTS_VGPEVIF_Msk (0x1ul << TAMPER_INTSTS_VGPEVIF_Pos) /*!< TAMPER_T::INTSTS: VGPEVIF Mask */ 752 753 #define TAMPER_INTSTS_VGNEVIF_Pos (10) /*!< TAMPER_T::INTSTS: VGNEVIF Position */ 754 #define TAMPER_INTSTS_VGNEVIF_Msk (0x1ul << TAMPER_INTSTS_VGNEVIF_Pos) /*!< TAMPER_T::INTSTS: VGNEVIF Mask */ 755 756 #define TAMPER_INTSTS_ACTSEIF_Pos (11) /*!< TAMPER_T::INTSTS: ACTSEIF Position */ 757 #define TAMPER_INTSTS_ACTSEIF_Msk (0x1ul << TAMPER_INTSTS_ACTSEIF_Pos) /*!< TAMPER_T::INTSTS: ACTSEIF Mask */ 758 759 #define TAMPER_INTSTS_ACTST5IF_Pos (13) /*!< TAMPER_T::INTSTS: ACTST5IF Position */ 760 #define TAMPER_INTSTS_ACTST5IF_Msk (0x1ul << TAMPER_INTSTS_ACTST5IF_Pos) /*!< TAMPER_T::INTSTS: ACTST5IF Mask */ 761 762 #define TAMPER_INTSTS_ACTST25IF_Pos (15) /*!< TAMPER_T::INTSTS: ACTST25IF Position */ 763 #define TAMPER_INTSTS_ACTST25IF_Msk (0x1ul << TAMPER_INTSTS_ACTST25IF_Pos) /*!< TAMPER_T::INTSTS: ACTST25IF Mask */ 764 765 #define TAMPER_INTSTS_RTCLVRIF_Pos (16) /*!< TAMPER_T::INTSTS: RTCLVRIF Position */ 766 #define TAMPER_INTSTS_RTCLVRIF_Msk (0x1ul << TAMPER_INTSTS_RTCLVRIF_Pos) /*!< TAMPER_T::INTSTS: RTCLVRIF Mask */ 767 768 #define TAMPER_INTSTS_RIOTRIGIF_Pos (17) /*!< TAMPER_T::INTSTS: RIOTRIGIF Position */ 769 #define TAMPER_INTSTS_RIOTRIGIF_Msk (0x1ul << TAMPER_INTSTS_RIOTRIGIF_Pos) /*!< TAMPER_T::INTSTS: RIOTRIGIF Mask */ 770 771 #define TAMPER_INTSTS_RCLKTRIGIF_Pos (18) /*!< TAMPER_T::INTSTS: RCLKTRIGIF Position */ 772 #define TAMPER_INTSTS_RCLKTRIGIF_Msk (0x1ul << TAMPER_INTSTS_RCLKTRIGIF_Pos) /*!< TAMPER_T::INTSTS: RCLKTRIGIF Mask */ 773 774 #define TAMPER_INTSTS_BODIF_Pos (22) /*!< TAMPER_T::INTSTS: BODIF Position */ 775 #define TAMPER_INTSTS_BODIF_Msk (0x1ul << TAMPER_INTSTS_BODIF_Pos) /*!< TAMPER_T::INTSTS: BODIF Mask */ 776 777 #define TAMPER_INTSTS_ACTST1IF_Pos (25) /*!< TAMPER_T::INTSTS: ACTST1IF Position */ 778 #define TAMPER_INTSTS_ACTST1IF_Msk (0x1ul << TAMPER_INTSTS_ACTST1IF_Pos) /*!< TAMPER_T::INTSTS: ACTST1IF Mask */ 779 780 #define TAMPER_INTSTS_ACTST3IF_Pos (27) /*!< TAMPER_T::INTSTS: ACTST3IF Position */ 781 #define TAMPER_INTSTS_ACTST3IF_Msk (0x1ul << TAMPER_INTSTS_ACTST3IF_Pos) /*!< TAMPER_T::INTSTS: ACTST3IF Mask */ 782 783 #define TAMPER_INTSTS_ACTST21IF_Pos (29) /*!< TAMPER_T::INTSTS: ACTST21IF Position */ 784 #define TAMPER_INTSTS_ACTST21IF_Msk (0x1ul << TAMPER_INTSTS_ACTST21IF_Pos) /*!< TAMPER_T::INTSTS: ACTST21IF Mask */ 785 786 #define TAMPER_INTSTS_ACTST23IF_Pos (31) /*!< TAMPER_T::INTSTS: ACTST23IF Position */ 787 #define TAMPER_INTSTS_ACTST23IF_Msk (0x1ul << TAMPER_INTSTS_ACTST23IF_Pos) /*!< TAMPER_T::INTSTS: ACTST23IF Mask */ 788 789 #define TAMPER_LIRCTL_TLRCTRIM_Pos (0) /*!< TAMPER_T::LIRCTL: TLRCTRIM Position */ 790 #define TAMPER_LIRCTL_TLRCTRIM_Msk (0x1fful << TAMPER_LIRCTL_TLRCTRIM_Pos) /*!< TAMPER_T::LIRCTL: TLRCTRIM Mask */ 791 792 #define TAMPER_LIRCTL_TRIMMOS_Pos (9) /*!< TAMPER_T::LIRCTL: TRIMMOS Position */ 793 #define TAMPER_LIRCTL_TRIMMOS_Msk (0x3ul << TAMPER_LIRCTL_TRIMMOS_Pos) /*!< TAMPER_T::LIRCTL: TRIMMOS Mask */ 794 795 #define TAMPER_TIOCTL_DYN1ISS_Pos (0) /*!< TAMPER_T::TIOCTL: DYN1ISS Position */ 796 #define TAMPER_TIOCTL_DYN1ISS_Msk (0x1ul << TAMPER_TIOCTL_DYN1ISS_Pos) /*!< TAMPER_T::TIOCTL: DYN1ISS Mask */ 797 798 #define TAMPER_TIOCTL_DYN2ISS_Pos (1) /*!< TAMPER_T::TIOCTL: DYN2ISS Position */ 799 #define TAMPER_TIOCTL_DYN2ISS_Msk (0x1ul << TAMPER_TIOCTL_DYN2ISS_Pos) /*!< TAMPER_T::TIOCTL: DYN2ISS Mask */ 800 801 #define TAMPER_TIOCTL_DYNSRC_Pos (3) /*!< TAMPER_T::TIOCTL: DYNSRC Position */ 802 #define TAMPER_TIOCTL_DYNSRC_Msk (0x1ul << TAMPER_TIOCTL_DYNSRC_Pos) /*!< TAMPER_T::TIOCTL: DYNSRC Mask */ 803 804 #define TAMPER_TIOCTL_SEEDRLD_Pos (4) /*!< TAMPER_T::TIOCTL: SEEDRLD Position */ 805 #define TAMPER_TIOCTL_SEEDRLD_Msk (0x1ul << TAMPER_TIOCTL_SEEDRLD_Pos) /*!< TAMPER_T::TIOCTL: SEEDRLD Mask */ 806 807 #define TAMPER_TIOCTL_DYNRATE_Pos (5) /*!< TAMPER_T::TIOCTL: DYNRATE Position */ 808 #define TAMPER_TIOCTL_DYNRATE_Msk (0x7ul << TAMPER_TIOCTL_DYNRATE_Pos) /*!< TAMPER_T::TIOCTL: DYNRATE Mask */ 809 810 #define TAMPER_TIOCTL_TAMP0EN_Pos (8) /*!< TAMPER_T::TIOCTL: TAMP0EN Position */ 811 #define TAMPER_TIOCTL_TAMP0EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP0EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP0EN Mask */ 812 813 #define TAMPER_TIOCTL_TAMP0LV_Pos (9) /*!< TAMPER_T::TIOCTL: TAMP0LV Position */ 814 #define TAMPER_TIOCTL_TAMP0LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP0LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP0LV Mask */ 815 816 #define TAMPER_TIOCTL_TAMP0DBEN_Pos (10) /*!< TAMPER_T::TIOCTL: TAMP0DBEN Position */ 817 #define TAMPER_TIOCTL_TAMP0DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP0DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP0DBEN Mask */ 818 819 #define TAMPER_TIOCTL_TAMP1EN_Pos (12) /*!< TAMPER_T::TIOCTL: TAMP1EN Position */ 820 #define TAMPER_TIOCTL_TAMP1EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP1EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP1EN Mask */ 821 822 #define TAMPER_TIOCTL_TAMP1LV_Pos (13) /*!< TAMPER_T::TIOCTL: TAMP1LV Position */ 823 #define TAMPER_TIOCTL_TAMP1LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP1LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP1LV Mask */ 824 825 #define TAMPER_TIOCTL_TAMP1DBEN_Pos (14) /*!< TAMPER_T::TIOCTL: TAMP1DBEN Position */ 826 #define TAMPER_TIOCTL_TAMP1DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP1DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP1DBEN Mask */ 827 828 #define TAMPER_TIOCTL_DYNPR0EN_Pos (15) /*!< TAMPER_T::TIOCTL: DYNPR0EN Position */ 829 #define TAMPER_TIOCTL_DYNPR0EN_Msk (0x1ul << TAMPER_TIOCTL_DYNPR0EN_Pos) /*!< TAMPER_T::TIOCTL: DYNPR0EN Mask */ 830 831 #define TAMPER_TIOCTL_TAMP2EN_Pos (16) /*!< TAMPER_T::TIOCTL: TAMP2EN Position */ 832 #define TAMPER_TIOCTL_TAMP2EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP2EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP2EN Mask */ 833 834 #define TAMPER_TIOCTL_TAMP2LV_Pos (17) /*!< TAMPER_T::TIOCTL: TAMP2LV Position */ 835 #define TAMPER_TIOCTL_TAMP2LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP2LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP2LV Mask */ 836 837 #define TAMPER_TIOCTL_TAMP2DBEN_Pos (18) /*!< TAMPER_T::TIOCTL: TAMP2DBEN Position */ 838 #define TAMPER_TIOCTL_TAMP2DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP2DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP2DBEN Mask */ 839 840 #define TAMPER_TIOCTL_TAMP3EN_Pos (20) /*!< TAMPER_T::TIOCTL: TAMP3EN Position */ 841 #define TAMPER_TIOCTL_TAMP3EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP3EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP3EN Mask */ 842 843 #define TAMPER_TIOCTL_TAMP3LV_Pos (21) /*!< TAMPER_T::TIOCTL: TAMP3LV Position */ 844 #define TAMPER_TIOCTL_TAMP3LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP3LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP3LV Mask */ 845 846 #define TAMPER_TIOCTL_TAMP3DBEN_Pos (22) /*!< TAMPER_T::TIOCTL: TAMP3DBEN Position */ 847 #define TAMPER_TIOCTL_TAMP3DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP3DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP3DBEN Mask */ 848 849 #define TAMPER_TIOCTL_DYNPR1EN_Pos (23) /*!< TAMPER_T::TIOCTL: DYNPR1EN Position */ 850 #define TAMPER_TIOCTL_DYNPR1EN_Msk (0x1ul << TAMPER_TIOCTL_DYNPR1EN_Pos) /*!< TAMPER_T::TIOCTL: DYNPR1EN Mask */ 851 852 #define TAMPER_TIOCTL_TAMP4EN_Pos (24) /*!< TAMPER_T::TIOCTL: TAMP4EN Position */ 853 #define TAMPER_TIOCTL_TAMP4EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP4EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP4EN Mask */ 854 855 #define TAMPER_TIOCTL_TAMP4LV_Pos (25) /*!< TAMPER_T::TIOCTL: TAMP4LV Position */ 856 #define TAMPER_TIOCTL_TAMP4LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP4LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP4LV Mask */ 857 858 #define TAMPER_TIOCTL_TAMP4DBEN_Pos (26) /*!< TAMPER_T::TIOCTL: TAMP4DBEN Position */ 859 #define TAMPER_TIOCTL_TAMP4DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP4DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP4DBEN Mask */ 860 861 #define TAMPER_TIOCTL_TAMP5EN_Pos (28) /*!< TAMPER_T::TIOCTL: TAMP5EN Position */ 862 #define TAMPER_TIOCTL_TAMP5EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP5EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP5EN Mask */ 863 864 #define TAMPER_TIOCTL_TAMP5LV_Pos (29) /*!< TAMPER_T::TIOCTL: TAMP5LV Position */ 865 #define TAMPER_TIOCTL_TAMP5LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP5LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP5LV Mask */ 866 867 #define TAMPER_TIOCTL_TAMP5DBEN_Pos (30) /*!< TAMPER_T::TIOCTL: TAMP5DBEN Position */ 868 #define TAMPER_TIOCTL_TAMP5DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP5DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP5DBEN Mask */ 869 870 #define TAMPER_TIOCTL_DYNPR2EN_Pos (31) /*!< TAMPER_T::TIOCTL: DYNPR2EN Position */ 871 #define TAMPER_TIOCTL_DYNPR2EN_Msk (0x1ul << TAMPER_TIOCTL_DYNPR2EN_Pos) /*!< TAMPER_T::TIOCTL: DYNPR2EN Mask */ 872 873 #define TAMPER_SEED_SEED_Pos (0) /*!< TAMPER_T::SEED: SEED Position */ 874 #define TAMPER_SEED_SEED_Msk (0xfffffffful << TAMPER_SEED_SEED_Pos) /*!< TAMPER_T::SEED: SEED Mask */ 875 876 #define TAMPER_SEED2_SEED2_Pos (0) /*!< TAMPER_T::SEED2: SEED2 Position */ 877 #define TAMPER_SEED2_SEED2_Msk (0xfffffffful << TAMPER_SEED2_SEED2_Pos) /*!< TAMPER_T::SEED2: SEED2 Mask */ 878 879 #define TAMPER_ACTSTIOCTL1_ADYN1ISS_Pos (0) /*!< TAMPER_T::ACTSTIOCTL1: ADYN1ISS Position*/ 880 #define TAMPER_ACTSTIOCTL1_ADYN1ISS_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYN1ISS_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYN1ISS Mask */ 881 882 #define TAMPER_ACTSTIOCTL1_ADYNSRC_Pos (3) /*!< TAMPER_T::ACTSTIOCTL1: ADYNSRC Position*/ 883 #define TAMPER_ACTSTIOCTL1_ADYNSRC_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNSRC_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNSRC Mask */ 884 885 #define TAMPER_ACTSTIOCTL1_ADYNRATE_Pos (5) /*!< TAMPER_T::ACTSTIOCTL1: ADYNRATE Position*/ 886 #define TAMPER_ACTSTIOCTL1_ADYNRATE_Msk (0x7ul << TAMPER_ACTSTIOCTL1_ADYNRATE_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNRATE Mask */ 887 888 #define TAMPER_ACTSTIOCTL1_ATAMP0EN_Pos (8) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP0EN Position*/ 889 #define TAMPER_ACTSTIOCTL1_ATAMP0EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP0EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP0EN Mask */ 890 891 #define TAMPER_ACTSTIOCTL1_ATAMP1EN_Pos (12) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP1EN Position*/ 892 #define TAMPER_ACTSTIOCTL1_ATAMP1EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP1EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP1EN Mask */ 893 894 #define TAMPER_ACTSTIOCTL1_ADYNPR0EN_Pos (15) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR0EN Position*/ 895 #define TAMPER_ACTSTIOCTL1_ADYNPR0EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNPR0EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR0EN Mask */ 896 897 #define TAMPER_ACTSTIOCTL1_ATAMP2EN_Pos (16) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP2EN Position*/ 898 #define TAMPER_ACTSTIOCTL1_ATAMP2EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP2EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP2EN Mask */ 899 900 #define TAMPER_ACTSTIOCTL1_ATAMP3EN_Pos (20) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP3EN Position*/ 901 #define TAMPER_ACTSTIOCTL1_ATAMP3EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP3EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP3EN Mask */ 902 903 #define TAMPER_ACTSTIOCTL1_ADYNPR1EN_Pos (23) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR1EN Position*/ 904 #define TAMPER_ACTSTIOCTL1_ADYNPR1EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNPR1EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR1EN Mask */ 905 906 #define TAMPER_ACTSTIOCTL1_ATAMP4EN_Pos (24) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP4EN Position*/ 907 #define TAMPER_ACTSTIOCTL1_ATAMP4EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP4EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP4EN Mask */ 908 909 #define TAMPER_ACTSTIOCTL1_ATAMP5EN_Pos (28) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP5EN Position*/ 910 #define TAMPER_ACTSTIOCTL1_ATAMP5EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP5EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP5EN Mask */ 911 912 #define TAMPER_ACTSTIOCTL1_ADYNPR2EN_Pos (31) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR2EN Position*/ 913 #define TAMPER_ACTSTIOCTL1_ADYNPR2EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNPR2EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR2EN Mask */ 914 915 #define TAMPER_ACTSTIOCTL2_ADYN1ISS2_Pos (0) /*!< TAMPER_T::ACTSTIOCTL2: ADYN1ISS2 Position*/ 916 #define TAMPER_ACTSTIOCTL2_ADYN1ISS2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYN1ISS2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYN1ISS2 Mask */ 917 918 #define TAMPER_ACTSTIOCTL2_ADYNSRC2_Pos (3) /*!< TAMPER_T::ACTSTIOCTL2: ADYNSRC2 Position*/ 919 #define TAMPER_ACTSTIOCTL2_ADYNSRC2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNSRC2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNSRC2 Mask */ 920 921 #define TAMPER_ACTSTIOCTL2_SEEDRLD2_Pos (4) /*!< TAMPER_T::ACTSTIOCTL2: SEEDRLD2 Position*/ 922 #define TAMPER_ACTSTIOCTL2_SEEDRLD2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_SEEDRLD2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: SEEDRLD2 Mask */ 923 924 #define TAMPER_ACTSTIOCTL2_ADYNRATE2_Pos (5) /*!< TAMPER_T::ACTSTIOCTL2: ADYNRATE2 Position*/ 925 #define TAMPER_ACTSTIOCTL2_ADYNRATE2_Msk (0x7ul << TAMPER_ACTSTIOCTL2_ADYNRATE2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNRATE2 Mask */ 926 927 #define TAMPER_ACTSTIOCTL2_ATAMP0EN2_Pos (8) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP0EN2 Position*/ 928 #define TAMPER_ACTSTIOCTL2_ATAMP0EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP0EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP0EN2 Mask */ 929 930 #define TAMPER_ACTSTIOCTL2_ATAMP1EN2_Pos (12) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP1EN2 Position*/ 931 #define TAMPER_ACTSTIOCTL2_ATAMP1EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP1EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP1EN2 Mask */ 932 933 #define TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Pos (15) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR0EN2 Position*/ 934 #define TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR0EN2 Mask */ 935 936 #define TAMPER_ACTSTIOCTL2_ATAMP2EN2_Pos (16) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP2EN2 Position*/ 937 #define TAMPER_ACTSTIOCTL2_ATAMP2EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP2EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP2EN2 Mask */ 938 939 #define TAMPER_ACTSTIOCTL2_ATAMP3EN2_Pos (20) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP3EN2 Position*/ 940 #define TAMPER_ACTSTIOCTL2_ATAMP3EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP3EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP3EN2 Mask */ 941 942 #define TAMPER_ACTSTIOCTL2_ADYNPR1EN2_Pos (23) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR1EN2 Position*/ 943 #define TAMPER_ACTSTIOCTL2_ADYNPR1EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNPR1EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR1EN2 Mask */ 944 945 #define TAMPER_ACTSTIOCTL2_ATAMP4EN2_Pos (24) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP4EN2 Position*/ 946 #define TAMPER_ACTSTIOCTL2_ATAMP4EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP4EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP4EN2 Mask */ 947 948 #define TAMPER_ACTSTIOCTL2_ATAMP5EN2_Pos (28) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP5EN2 Position*/ 949 #define TAMPER_ACTSTIOCTL2_ATAMP5EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP5EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP5EN2 Mask */ 950 951 #define TAMPER_ACTSTIOCTL2_ADYNPR2EN2_Pos (31) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR2EN2 Position*/ 952 #define TAMPER_ACTSTIOCTL2_ADYNPR2EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNPR2EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR2EN2 Mask */ 953 954 #define TAMPER_CDBR_STOPBD_Pos (0) /*!< TAMPER_T::CDBR: STOPBD Position */ 955 #define TAMPER_CDBR_STOPBD_Msk (0xfful << TAMPER_CDBR_STOPBD_Pos) /*!< TAMPER_T::CDBR: STOPBD Mask */ 956 957 #define TAMPER_CDBR_FAILBD_Pos (16) /*!< TAMPER_T::CDBR: FAILBD Position */ 958 #define TAMPER_CDBR_FAILBD_Msk (0xfful << TAMPER_CDBR_FAILBD_Pos) /*!< TAMPER_T::CDBR: FAILBD Mask */ 959 960 #define TAMPER_VG_PCLKSEL0_Pos (0) /*!< TAMPER_T::VG: PCLKSEL0 Position */ 961 #define TAMPER_VG_PCLKSEL0_Msk (0xful << TAMPER_VG_PCLKSEL0_Pos) /*!< TAMPER_T::VG: PCLKSEL0 Mask */ 962 963 #define TAMPER_VG_NCLKSEL0_Pos (4) /*!< TAMPER_T::VG: NCLKSEL0 Position */ 964 #define TAMPER_VG_NCLKSEL0_Msk (0xful << TAMPER_VG_NCLKSEL0_Pos) /*!< TAMPER_T::VG: NCLKSEL0 Mask */ 965 966 #define TAMPER_VG_PDATSEL0_Pos (8) /*!< TAMPER_T::VG: PDATSEL0 Position */ 967 #define TAMPER_VG_PDATSEL0_Msk (0xful << TAMPER_VG_PDATSEL0_Pos) /*!< TAMPER_T::VG: PDATSEL0 Mask */ 968 969 #define TAMPER_VG_NDATSEL0_Pos (12) /*!< TAMPER_T::VG: NDATSEL0 Position */ 970 #define TAMPER_VG_NDATSEL0_Msk (0xful << TAMPER_VG_NDATSEL0_Pos) /*!< TAMPER_T::VG: NDATSEL0 Mask */ 971 972 #define TAMPER_VG_PCLKSEL1_Pos (16) /*!< TAMPER_T::VG: PCLKSEL1 Position */ 973 #define TAMPER_VG_PCLKSEL1_Msk (0xful << TAMPER_VG_PCLKSEL1_Pos) /*!< TAMPER_T::VG: PCLKSEL1 Mask */ 974 975 #define TAMPER_VG_NCLKSEL1_Pos (20) /*!< TAMPER_T::VG: NCLKSEL1 Position */ 976 #define TAMPER_VG_NCLKSEL1_Msk (0xful << TAMPER_VG_NCLKSEL1_Pos) /*!< TAMPER_T::VG: NCLKSEL1 Mask */ 977 978 #define TAMPER_VG_PDATSEL1_Pos (24) /*!< TAMPER_T::VG: PDATSEL1 Position */ 979 #define TAMPER_VG_PDATSEL1_Msk (0xful << TAMPER_VG_PDATSEL1_Pos) /*!< TAMPER_T::VG: PDATSEL1 Mask */ 980 981 #define TAMPER_VG_NDATSEL1_Pos (28) /*!< TAMPER_T::VG: NDATSEL1 Position */ 982 #define TAMPER_VG_NDATSEL1_Msk (0xful << TAMPER_VG_NDATSEL1_Pos) /*!< TAMPER_T::VG: NDATSEL1 Mask */ 983 984 #define TAMPER_VGEV_VGECNTP_Pos (0) /*!< TAMPER_T::VGEV: VGECNTP Position */ 985 #define TAMPER_VGEV_VGECNTP_Msk (0xfful << TAMPER_VGEV_VGECNTP_Pos) /*!< TAMPER_T::VGEV: VGECNTP Mask */ 986 987 #define TAMPER_VGEV_VGECNTN_Pos (8) /*!< TAMPER_T::VGEV: VGECNTN Position */ 988 #define TAMPER_VGEV_VGECNTN_Msk (0xfful << TAMPER_VGEV_VGECNTN_Pos) /*!< TAMPER_T::VGEV: VGECNTN Mask */ 989 990 #define TAMPER_LDOTRIM_TLDOTRIM_Pos (0) /*!< TAMPER_T::LDOTRIM: TLDOTRIM Position */ 991 #define TAMPER_LDOTRIM_TLDOTRIM_Msk (0xful << TAMPER_LDOTRIM_TLDOTRIM_Pos) /*!< TAMPER_T::LDOTRIM: TLDOTRIM Mask */ 992 993 #define TAMPER_LDOTRIM_TLDOIQSEL_Pos (8) /*!< TAMPER_T::LDOTRIM: TLDOIQSEL Position */ 994 #define TAMPER_LDOTRIM_TLDOIQSEL_Msk (0x3ul << TAMPER_LDOTRIM_TLDOIQSEL_Pos) /*!< TAMPER_T::LDOTRIM: TLDOIQSEL Mask */ 995 996 #define TAMPER_LBSTRIM_TLVDSEL_Pos (0) /*!< TAMPER_T::LBSTRIM: TLVDSEL Position */ 997 #define TAMPER_LBSTRIM_TLVDSEL_Msk (0x7ul << TAMPER_LBSTRIM_TLVDSEL_Pos) /*!< TAMPER_T::LBSTRIM: TLVDSEL Mask */ 998 999 #define TAMPER_LBSTRIM_TOVDSEL_Pos (4) /*!< TAMPER_T::LBSTRIM: TOVDSEL Position */ 1000 #define TAMPER_LBSTRIM_TOVDSEL_Msk (0x1ul << TAMPER_LBSTRIM_TOVDSEL_Pos) /*!< TAMPER_T::LBSTRIM: TOVDSEL Mask */ 1001 1002 #define TAMPER_LBSTRIM_BSCMPLV_Pos (8) /*!< TAMPER_T::LBSTRIM: BSCMPLV Position */ 1003 #define TAMPER_LBSTRIM_BSCMPLV_Msk (0x3ul << TAMPER_LBSTRIM_BSCMPLV_Pos) /*!< TAMPER_T::LBSTRIM: BSCMPLV Mask */ 1004 1005 #define TAMPER_LBSTRIM_BSCMPOV_Pos (10) /*!< TAMPER_T::LBSTRIM: BSCMPOV Position */ 1006 #define TAMPER_LBSTRIM_BSCMPOV_Msk (0x3ul << TAMPER_LBSTRIM_BSCMPOV_Pos) /*!< TAMPER_T::LBSTRIM: BSCMPOV Mask */ 1007 1008 #define TAMPER_LBSTRIM_HYSCMPLV_Pos (12) /*!< TAMPER_T::LBSTRIM: HYSCMPLV Position */ 1009 #define TAMPER_LBSTRIM_HYSCMPLV_Msk (0x3ul << TAMPER_LBSTRIM_HYSCMPLV_Pos) /*!< TAMPER_T::LBSTRIM: HYSCMPLV Mask */ 1010 1011 #define TAMPER_LBSTRIM_HYSCMPOV_Pos (14) /*!< TAMPER_T::LBSTRIM: HYSCMPOV Position */ 1012 #define TAMPER_LBSTRIM_HYSCMPOV_Msk (0x3ul << TAMPER_LBSTRIM_HYSCMPOV_Pos) /*!< TAMPER_T::LBSTRIM: HYSCMPOV Mask */ 1013 1014 #define TAMPER_VG2_PCLKSEL2_Pos (0) /*!< TAMPER_T::VG2: PCLKSEL2 Position */ 1015 #define TAMPER_VG2_PCLKSEL2_Msk (0xful << TAMPER_VG2_PCLKSEL2_Pos) /*!< TAMPER_T::VG2: PCLKSEL2 Mask */ 1016 1017 #define TAMPER_VG2_NCLKSEL2_Pos (4) /*!< TAMPER_T::VG2: NCLKSEL2 Position */ 1018 #define TAMPER_VG2_NCLKSEL2_Msk (0xful << TAMPER_VG2_NCLKSEL2_Pos) /*!< TAMPER_T::VG2: NCLKSEL2 Mask */ 1019 1020 #define TAMPER_VG2_PDATSEL2_Pos (8) /*!< TAMPER_T::VG2: PDATSEL2 Position */ 1021 #define TAMPER_VG2_PDATSEL2_Msk (0xful << TAMPER_VG2_PDATSEL2_Pos) /*!< TAMPER_T::VG2: PDATSEL2 Mask */ 1022 1023 #define TAMPER_VG2_NDATSEL2_Pos (12) /*!< TAMPER_T::VG2: NDATSEL2 Position */ 1024 #define TAMPER_VG2_NDATSEL2_Msk (0xful << TAMPER_VG2_NDATSEL2_Pos) /*!< TAMPER_T::VG2: NDATSEL2 Mask */ 1025 1026 #define TAMPER_VG2_PCLKSEL3_Pos (16) /*!< TAMPER_T::VG2: PCLKSEL3 Position */ 1027 #define TAMPER_VG2_PCLKSEL3_Msk (0xful << TAMPER_VG2_PCLKSEL3_Pos) /*!< TAMPER_T::VG2: PCLKSEL3 Mask */ 1028 1029 #define TAMPER_VG2_NCLKSEL3_Pos (20) /*!< TAMPER_T::VG2: NCLKSEL3 Position */ 1030 #define TAMPER_VG2_NCLKSEL3_Msk (0xful << TAMPER_VG2_NCLKSEL3_Pos) /*!< TAMPER_T::VG2: NCLKSEL3 Mask */ 1031 1032 #define TAMPER_VG2_PDATSEL3_Pos (24) /*!< TAMPER_T::VG2: PDATSEL3 Position */ 1033 #define TAMPER_VG2_PDATSEL3_Msk (0xful << TAMPER_VG2_PDATSEL3_Pos) /*!< TAMPER_T::VG2: PDATSEL3 Mask */ 1034 1035 #define TAMPER_VG2_NDATSEL3_Pos (28) /*!< TAMPER_T::VG2: NDATSEL3 Position */ 1036 #define TAMPER_VG2_NDATSEL3_Msk (0xful << TAMPER_VG2_NDATSEL3_Pos) /*!< TAMPER_T::VG2: NDATSEL3 Mask */ 1037 1038 /**@}*/ /* TAMPER_CONST */ 1039 /**@}*/ /* end of TAMPER register group */ 1040 /**@}*/ /* end of REGISTER group */ 1041 1042 #endif /* __TAMPER_REG_H__ */ 1043
