1 /***************************************************************************//**
2 * \file system_cyw20829.c
3 * \version 1.3
4 *
5 * The device system-source file.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27
28 #if defined (CY_DEVICE_CYW20829)
29
30 #include <stdbool.h>
31 #include "system_cat1b.h"
32 #include "cy_syslib.h"
33 #include "cy_wdt.h"
34 #include "cy_sysclk.h"
35 #include "cy_syspm.h"
36
37 CY_MISRA_DEVIATE_BLOCK_START('ARRAY_VS_SINGLETON', 1, \
38 'Checked manually. Using pointer as an array will not corrupt or misinterpret adjacent memory locations.')
39 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 18.1', 1, \
40 'Checked manually. Dereferencing a pointer to one beyond the end of an array will not result in undefined behaviour.')
41 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 18.3', 1, \
42 'Checked manually. Attempting to make comparisons between pointers will not result in undefined behaviour.')
43 CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.6', 2, \
44 'Checked manually. The definition is a part of linker script or application.')
45
46 /*******************************************************************************
47 * SystemCoreClockUpdate()
48 *******************************************************************************/
49
50 /** Default HFClk frequency in Hz */
51 #define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (48000000UL)
52
53 /** Default PeriClk frequency in Hz */
54 #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (48000000UL)
55
56 /** Default system core frequency in Hz */
57 #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (48000000UL)
58
59 /** Holds the CLK_HF0 system core clock. */
60 uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
61
62 /** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
63 uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
64
65 /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
66 uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
67
68 /** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */
69 uint32_t cy_AhbFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
70
71 /*******************************************************************************
72 * SystemCoreClockUpdate (void)
73 *******************************************************************************/
74
75 /* Do not use these definitions directly in your application */
76 #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
77 #define CY_DELAY_1K_THRESHOLD (1000u)
78 #define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
79 #define CY_DELAY_1M_THRESHOLD (1000000u)
80 #define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
81 uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
82
83 uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
84 CY_DELAY_1K_THRESHOLD;
85
86 uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
87 CY_DELAY_1M_THRESHOLD);
88
89
90 #if defined (CY_PDL_FLASH_BOOT)
91
92 #if !defined (__ARMCC_VERSION)
bootstrapInit(void)93 void bootstrapInit(void)
94 {
95 typedef struct
96 {
97 uint32_t* dest;
98 uint32_t wlen;
99 } __bootstrap_zero_table_t;
100
101 extern const __bootstrap_zero_table_t __bootstrapzero_table_start__;
102 extern const __bootstrap_zero_table_t __bootstrapzero_table_end__;
103
104 /* Initialize .cy_l1bss section to zero */
105 for (__bootstrap_zero_table_t const* pTable = &__bootstrapzero_table_start__; pTable < &__bootstrapzero_table_end__; ++pTable)
106 {
107 for(uint32_t i=0u; i<pTable->wlen; ++i)
108 {
109 pTable->dest[i] = 0u;
110 }
111 }
112 }
113 #endif
114 #endif /* CY_PDL_FLASH_BOOT */
115
SystemInit_CAT1B_CM33(void)116 void SystemInit_CAT1B_CM33(void)
117 {
118 /* Release reset for all groups IP except group 0 and group 3 */
119 (void)Cy_SysClk_PeriGroupSetSlaveCtl(1, CY_SYSCLK_PERI_GROUP_SL_CTL2, 0x0U); /* typecast void to suppress a compiler warning about unused return value */
120 (void)Cy_SysClk_PeriGroupSetSlaveCtl(2, CY_SYSCLK_PERI_GROUP_SL_CTL2, 0x0U); /* typecast void to suppress a compiler warning about unused return value */
121 (void)Cy_SysClk_PeriGroupSetSlaveCtl(3, CY_SYSCLK_PERI_GROUP_SL_CTL2, 0x1U); /* typecast void to suppress a compiler warning about unused return value */
122
123 (void)Cy_SysClk_PeriGroupSetSlaveCtl(1, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFFFFFU); /* typecast void to suppress a compiler warning about unused return value */
124 (void)Cy_SysClk_PeriGroupSetSlaveCtl(2, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFFFFFU); /* typecast void to suppress a compiler warning about unused return value */
125 (void)Cy_SysClk_PeriGroupSetSlaveCtl(3, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFFFFFU); /* typecast void to suppress a compiler warning about unused return value */
126
127 Cy_PDL_Init(CY_DEVICE_CFG);
128 (void)Cy_SystemInit(); /* typecast void to suppress a compiler warning about unused return value */
129
130 /* Unlock and disable WDT */
131 Cy_WDT_Unlock();
132 Cy_WDT_Disable();
133
134 SystemCoreClockUpdate();
135 }
136
137 CY_SECTION_RAMFUNC_BEGIN
138 /*******************************************************************************
139 * Function Name: SystemInit_Warmboot_CAT1B_CM33
140 ****************************************************************************//**
141 *
142 * Prepares the system to work after warmboot:
143 * - Intializes Vector Table
144 * - Enables all the IP's through Slave Control Registers
145 * - Unfreezes the IO's
146 *
147 *******************************************************************************/
SystemInit_Warmboot_CAT1B_CM33()148 void SystemInit_Warmboot_CAT1B_CM33()
149 {
150 SCB->VTOR = (uint32_t)__ns_vector_table_rw;
151 (void)Cy_SysClk_PeriGroupSetSlaveCtl(1, CY_SYSCLK_PERI_GROUP_SL_CTL2, 0x0U);
152 (void)Cy_SysClk_PeriGroupSetSlaveCtl(2, CY_SYSCLK_PERI_GROUP_SL_CTL2, 0x0U);
153 (void)Cy_SysClk_PeriGroupSetSlaveCtl(1, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFFFFFU);
154 (void)Cy_SysClk_PeriGroupSetSlaveCtl(2, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFFFFFU);
155 (void)Cy_SysClk_PeriGroupSetSlaveCtl(3, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFFFFFU);
156
157 if (Cy_SysPm_DeepSleepIoIsFrozen())
158 {
159 Cy_SysPm_DeepSleepIoUnfreeze();
160 }
161
162 cy_WakeupFromWarmBootStatus = true;
163 }
164 CY_SECTION_RAMFUNC_END
165
166 #define CY_NVIC_REG_COUNT 3U
167 #define CY_NVIC_IPR_REG_COUNT 69U
168
169 uint32_t nvicStoreRestore[CY_NVIC_REG_COUNT];
170 uint32_t nvicIPRStoreRestore[CY_NVIC_IPR_REG_COUNT];
171 uint32_t scbSHPR3StoreRestore;
172 #define SCB_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
173
174 /*******************************************************************************
175 * Function Name: System_Store_NVIC_Reg
176 ****************************************************************************//**
177 *
178 * Stores the NVIC register before Deepsleep RAM:
179 *
180 *******************************************************************************/
181 CY_SECTION_RAMFUNC_BEGIN
System_Store_NVIC_Reg(void)182 void System_Store_NVIC_Reg(void)
183 {
184 for (uint32_t idx = 0; idx < CY_NVIC_REG_COUNT; idx++)
185 {
186 nvicStoreRestore[idx] = NVIC->ISER[idx];
187 }
188
189 for (uint32_t idx = 0; idx < CY_NVIC_IPR_REG_COUNT; idx++)
190 {
191 nvicIPRStoreRestore[idx] = NVIC->IPR[idx];
192 }
193
194 scbSHPR3StoreRestore = SCB_SHPR3_REG;
195 }
196 CY_SECTION_RAMFUNC_END
197
198
199 /*******************************************************************************
200 * Function Name: System_Restore_NVIC_Reg
201 ****************************************************************************//**
202 *
203 * Restores the NVIC register After Deepsleep RAM Wakeup i.e. Warmboot:
204 *
205 *******************************************************************************/
206 CY_SECTION_RAMFUNC_BEGIN
System_Restore_NVIC_Reg(void)207 void System_Restore_NVIC_Reg(void)
208 {
209 for (uint32_t idx = 0; idx < CY_NVIC_REG_COUNT; idx++)
210 {
211 NVIC->ISER[idx] = nvicStoreRestore[idx];
212 }
213
214 for (uint32_t idx = 0; idx < CY_NVIC_IPR_REG_COUNT; idx++)
215 {
216 NVIC->IPR[idx] = nvicIPRStoreRestore[idx];
217 }
218
219 SCB_SHPR3_REG = scbSHPR3StoreRestore;
220 }
221 CY_SECTION_RAMFUNC_END
222
SystemInit(void)223 void SystemInit(void)
224 {
225
226 #ifdef CY_PDL_FLASH_BOOT
227 #if !defined (__ARMCC_VERSION)
228 bootstrapInit();
229 #endif
230 #endif
231
232 SystemInit_CAT1B_CM33();
233 };
234
235 /*******************************************************************************
236 * Function Name: Cy_SystemInit
237 ****************************************************************************//**
238 *
239 * The function is called during device startup.
240 *
241 *******************************************************************************/
Cy_SystemInit(void)242 __WEAK void Cy_SystemInit(void)
243 {
244 /* Empty weak function.
245 */
246 __NOP(); /* No operation */
247 }
248
249 /*******************************************************************************
250 * Function Name: SystemCoreClockUpdate
251 ****************************************************************************//**
252 *
253 * The function is called during device startup.
254 *
255 *******************************************************************************/
SystemCoreClockUpdate(void)256 void SystemCoreClockUpdate (void)
257 {
258 uint32_t pathFreqHz;
259 uint32_t clkHfPath;
260
261 /* Get frequency for the high-frequency clock # 0 */
262 clkHfPath = CY_SYSCLK_CLK_CORE_HF_PATH_NUM;
263
264 pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
265
266 SystemCoreClock = pathFreqHz;
267
268 cy_Hfclk0FreqHz = SystemCoreClock;
269
270 /* Get frequency for the high-frequency clock # 2 , whcih is used for PERI PCLK*/
271 clkHfPath = CY_SYSCLK_CLK_PERI_HF_PATH_NUM;
272
273 pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
274
275 cy_PeriClkFreqHz = pathFreqHz;
276
277 /* Sets clock frequency for Delay API */
278 cy_delayFreqHz = SystemCoreClock;
279 cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
280 cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
281
282 /* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
283 cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
284 }
285
286 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6')
287 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 18.3')
288 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 18.1')
289 CY_MISRA_BLOCK_END('ARRAY_VS_SINGLETON')
290
291 #endif /* defined (CY_DEVICE_CYW20829) */
292 /* [] END OF FILE */
293
294
