1 /**************************************************************************//**
2 * @file system_M480.c
3 * @version V1.000
4 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M480
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9
10 #include "NuMicro.h"
11
12
13 /*----------------------------------------------------------------------------
14 DEFINES
15 *----------------------------------------------------------------------------*/
16
17
18 /*----------------------------------------------------------------------------
19 Clock Variable definitions
20 *----------------------------------------------------------------------------*/
21 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
22 uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */
23 uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
24 uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC};
25
26 /*----------------------------------------------------------------------------
27 Clock functions
28 *----------------------------------------------------------------------------*/
SystemCoreClockUpdate(void)29 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
30 {
31 uint32_t u32Freq, u32ClkSrc;
32 uint32_t u32HclkDiv;
33
34 /* Update PLL Clock */
35 PllClock = CLK_GetPLLClockFreq();
36
37 u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
38
39 if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
40 {
41 /* Use PLL clock */
42 u32Freq = PllClock;
43 }
44 else
45 {
46 /* Use the clock sources directly */
47 u32Freq = gau32ClkSrcTbl[u32ClkSrc];
48 }
49
50 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
51
52 /* Update System Core Clock */
53 SystemCoreClock = u32Freq / u32HclkDiv;
54
55
56 //if(SystemCoreClock == 0)
57 // __BKPT(0);
58
59 CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
60 }
61
62 /**
63 * @brief Set PF.2 and PF.3 to input mode
64 * @param None
65 * @return None
66 * @details GPIO default state could be configured as input or quasi through user config.
67 * To use HXT, PF.2 and PF.3 must not set as quasi mode. This function changes
68 * PF.2 and PF.3 to input mode no matter which mode they are working at.
69 */
HXTInit(void)70 static __INLINE void HXTInit(void)
71 {
72 PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
73
74 }
75
76 /**
77 * @brief Initialize the System
78 *
79 * @param none
80 * @return none
81 */
SystemInit(void)82 void SystemInit (void)
83 {
84 /* Add your system initialize code here.
85 Do not use global variables because this function is called before
86 reaching pre-main. RW section maybe overwritten afterwards. */
87
88
89 /* FPU settings ------------------------------------------------------------*/
90 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
91 SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
92 (3UL << 11*2) ); /* set CP11 Full Access */
93 #endif
94
95 /* Set access cycle for CPU @ 192MHz */
96 FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (8 << FMC_CYCCTL_CYCLE_Pos);
97 /* Configure power down bias, must set 1 before entering power down mode.
98 So set it at the very beginning */
99 CLK->LDOCTL |= CLK_LDOCTL_PDBIASEN_Msk;
100 /* Hand over the control of PF.4~11 I/O function from RTC module to GPIO module */
101 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
102 RTC->GPIOCTL0 &= ~(RTC_GPIOCTL0_CTLSEL0_Msk | RTC_GPIOCTL0_CTLSEL1_Msk |
103 RTC_GPIOCTL0_CTLSEL2_Msk | RTC_GPIOCTL0_CTLSEL3_Msk);
104 RTC->GPIOCTL1 &= ~(RTC_GPIOCTL1_CTLSEL4_Msk | RTC_GPIOCTL1_CTLSEL5_Msk |
105 RTC_GPIOCTL1_CTLSEL6_Msk | RTC_GPIOCTL1_CTLSEL7_Msk);
106 CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
107 HXTInit();
108
109 }
110 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
111
