1 /**************************************************************************//** 2 * @file <Device>.h 3 * @brief CMSIS-Core(A) Device Header File for Device <Device> 4 * 5 * @version V1.0.1 6 * @date 18. July 2023 7 ******************************************************************************/ 8 /* 9 * Copyright (c) 2009-2023 Arm Limited. All rights reserved. 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 26 #ifndef <Device>_H /* ToDo: replace '<Device>' with your device name */ 27 #define <Device>_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 34 /* ========================================================================= */ 35 /* ============ Interrupt Number Definition ============ */ 36 /* ========================================================================= */ 37 38 typedef enum IRQn 39 { 40 /* ================ Cortex-A Specific Interrupt Numbers =============== */ 41 42 /* Software Generated Interrupts */ 43 SGI0_IRQn = 0, /* Software Generated Interrupt 0 */ 44 SGI1_IRQn = 1, /* Software Generated Interrupt 1 */ 45 SGI2_IRQn = 2, /* Software Generated Interrupt 2 */ 46 SGI3_IRQn = 3, /* Software Generated Interrupt 3 */ 47 SGI4_IRQn = 4, /* Software Generated Interrupt 4 */ 48 SGI5_IRQn = 5, /* Software Generated Interrupt 5 */ 49 SGI6_IRQn = 6, /* Software Generated Interrupt 6 */ 50 SGI7_IRQn = 7, /* Software Generated Interrupt 7 */ 51 SGI8_IRQn = 8, /* Software Generated Interrupt 8 */ 52 SGI9_IRQn = 9, /* Software Generated Interrupt 9 */ 53 SGI10_IRQn = 10, /* Software Generated Interrupt 10 */ 54 SGI11_IRQn = 11, /* Software Generated Interrupt 11 */ 55 SGI12_IRQn = 12, /* Software Generated Interrupt 12 */ 56 SGI13_IRQn = 13, /* Software Generated Interrupt 13 */ 57 SGI14_IRQn = 14, /* Software Generated Interrupt 14 */ 58 SGI15_IRQn = 15, /* Software Generated Interrupt 15 */ 59 60 /* Private Peripheral Interrupts */ 61 VirtualMaintenanceInterrupt_IRQn = 25, /* Virtual Maintenance Interrupt */ 62 HypervisorTimer_IRQn = 26, /* Hypervisor Timer Interrupt */ 63 VirtualTimer_IRQn = 27, /* Virtual Timer Interrupt */ 64 Legacy_nFIQ_IRQn = 28, /* Legacy nFIQ Interrupt */ 65 SecurePhyTimer_IRQn = 29, /* Secure Physical Timer Interrupt */ 66 NonSecurePhyTimer_IRQn = 30, /* Non-Secure Physical Timer Interrupt */ 67 Legacy_nIRQ_IRQn = 31, /* Legacy nIRQ Interrupt */ 68 69 /* Shared Peripheral Interrupts */ 70 /* ToDo: add here your device specific external interrupt numbers */ 71 <DeviceInterrupt>_IRQn = 0, /* Device Interrupt */ 72 } IRQn_Type; 73 74 75 /* ========================================================================= */ 76 /* ============ Processor and Core Peripheral Section ============ */ 77 /* ========================================================================= */ 78 79 /* ================ Start of section using anonymous unions ================ */ 80 #if defined (__CC_ARM) 81 #pragma push 82 #pragma anon_unions 83 #elif defined (__ICCARM__) 84 #pragma language=extended 85 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 86 #pragma clang diagnostic push 87 #pragma clang diagnostic ignored "-Wc11-extensions" 88 #pragma clang diagnostic ignored "-Wreserved-id-macro" 89 #elif defined (__GNUC__) 90 /* anonymous unions are enabled by default */ 91 #elif defined (__TMS470__) 92 /* anonymous unions are enabled by default */ 93 #elif defined (__TASKING__) 94 #pragma warning 586 95 #elif defined (__CSMC__) 96 /* anonymous unions are enabled by default */ 97 #else 98 #warning Not supported compiler type 99 #endif 100 101 102 /* -------- Configuration of Core Peripherals ----------------------------------- */ 103 /* ToDo: set the defines according your Device */ 104 /* ToDo: define the correct core revision 105 5U if your device is a CORTEX-A5 device 106 7U if your device is a CORTEX-A7 device 107 9U if your device is a CORTEX-A9 device */ 108 #define __CORTEX_A #U /* Cortex-A# Core */ 109 #define __CA_REV 0x0000U /* Core revision r0p0 */ 110 /* ToDo: define the correct core features for the <Device> */ 111 #define __FPU_PRESENT 1U /* Set to 1 if FPU is present */ 112 #define __GIC_PRESENT 1U /* Set to 1 if GIC is present */ 113 #define __TIM_PRESENT 1U /* Set to 1 if TIM is present */ 114 #define __L2C_PRESENT 1U /* Set to 1 if L2C is present */ 115 116 /* ToDo: include the correct core_ca#.h file 117 core_ca5.h if your device is a CORTEX-A5 device 118 core_ca7.h if your device is a CORTEX-A7 device 119 core_ca9.h if your device is a CORTEX-A9 device */ 120 #include <core_ca#.h> /* Processor and core peripherals */ 121 /* ToDo: include your system_<Device>.h file 122 replace '<Device>' with your device name */ 123 #include "system_<Device>.h" /* System Header */ 124 125 126 127 /* ========================================================================= */ 128 /* ============ Device Specific Peripheral Section ============ */ 129 /* ========================================================================= */ 130 131 132 /* ToDo: add here your device specific peripheral access structure typedefs 133 following is an example for a timer */ 134 135 /* ========================================================================= */ 136 /* ============ TMR ============ */ 137 /* ========================================================================= */ 138 139 typedef struct 140 { 141 __IOM uint32_t TimerLoad; /* Offset: 0x004 (R/W) Load Register */ 142 __IM uint32_t TimerValue; /* Offset: 0x008 (R/ ) Counter Current Value Register */ 143 __IOM uint32_t TimerControl; /* Offset: 0x00C (R/W) Control Register */ 144 __OM uint32_t TimerIntClr; /* Offset: 0x010 ( /W) Interrupt Clear Register */ 145 __IM uint32_t TimerRIS; /* Offset: 0x014 (R/ ) Raw Interrupt Status Register */ 146 __IM uint32_t TimerMIS; /* Offset: 0x018 (R/ ) Masked Interrupt Status Register */ 147 __IM uint32_t RESERVED[1]; 148 __IOM uint32_t TimerBGLoad; /* Offset: 0x020 (R/W) Background Load Register */ 149 } <DeviceAbbreviation>_TMR_TypeDef; 150 151 152 153 /* -------- End of section using anonymous unions and disabling warnings -------- */ 154 #if defined (__CC_ARM) 155 #pragma pop 156 #elif defined (__ICCARM__) 157 /* leave anonymous unions enabled */ 158 #elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) 159 #pragma clang diagnostic pop 160 #elif defined (__GNUC__) 161 /* anonymous unions are enabled by default */ 162 #elif defined (__TMS470__) 163 /* anonymous unions are enabled by default */ 164 #elif defined (__TASKING__) 165 #pragma warning restore 166 #elif defined (__CSMC__) 167 /* anonymous unions are enabled by default */ 168 #else 169 #warning Not supported compiler type 170 #endif 171 172 173 /* ========================================================================= */ 174 /* ============ Device Specific Peripheral Address Map ============ */ 175 /* ========================================================================= */ 176 177 178 /* ToDo: add here your device peripherals base addresses 179 following is an example for timer */ 180 181 /* Peripheral and SRAM base address */ 182 #define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /* (FLASH ) Base Address */ 183 #define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /* (SRAM ) Base Address */ 184 #define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /* (Peripheral) Base Address */ 185 186 /* Peripheral memory map */ 187 #define <DeviceAbbreviation>TIM0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /* (Timer0 ) Base Address */ 188 #define <DeviceAbbreviation>TIM1_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /* (Timer1 ) Base Address */ 189 #define <DeviceAbbreviation>TIM2_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /* (Timer2 ) Base Address */ 190 191 192 /* ========================================================================= */ 193 /* ============ Peripheral declaration ============ */ 194 /* ========================================================================= */ 195 196 197 /* ToDo: Add here your device peripherals pointer definitions 198 following is an example for timer */ 199 200 #define <DeviceAbbreviation>_TIM0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) 201 #define <DeviceAbbreviation>_TIM1 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) 202 #define <DeviceAbbreviation>_TIM2 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) 203 204 #ifdef __cplusplus 205 } 206 #endif 207 208 #endif /* <Device>_H */ 209
