1 /*
2 * Copyright 2021-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Uart.c
9 * @version 1.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Uart.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_UART_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_UART_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_UART_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_UART_SW_MAJOR_VERSION_C 1
44 #define SCHM_UART_SW_MINOR_VERSION_C 0
45 #define SCHM_UART_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_00) static volatile uint32 msr_UART_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_01) static volatile uint32 msr_UART_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_02) static volatile uint32 msr_UART_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_03) static volatile uint32 msr_UART_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_04) static volatile uint32 msr_UART_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_05) static volatile uint32 msr_UART_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_06) static volatile uint32 msr_UART_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_07) static volatile uint32 msr_UART_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_08) static volatile uint32 msr_UART_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_09) static volatile uint32 msr_UART_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_10) static volatile uint32 msr_UART_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_11) static volatile uint32 msr_UART_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_12) static volatile uint32 msr_UART_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_13) static volatile uint32 msr_UART_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_14) static volatile uint32 msr_UART_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_15) static volatile uint32 msr_UART_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_16) static volatile uint32 msr_UART_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_17) static volatile uint32 msr_UART_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_18) static volatile uint32 msr_UART_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_19) static volatile uint32 msr_UART_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_19) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_20) static volatile uint32 msr_UART_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_20) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
144 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_21) static volatile uint32 msr_UART_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
145 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_21) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
146
147 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
148 #include "Rte_MemMap.h"
149 /*==================================================================================================
150 * GLOBAL CONSTANTS
151 ==================================================================================================*/
152
153
154 /*==================================================================================================
155 * GLOBAL VARIABLES
156 ==================================================================================================*/
157
158 /*==================================================================================================
159 * LOCAL FUNCTION PROTOTYPES
160 ==================================================================================================*/
161
162 #ifndef _COSMIC_C_S32ZE_
163 /*================================================================================================*/
164 /**
165 * @brief This function returns the MSR register value (32 bits).
166 * @details This function returns the MSR register value (32 bits).
167 *
168 * @param[in] void No input parameters
169 * @return uint32 msr This function returns the MSR register value (32 bits).
170 *
171 * @pre None
172 * @post None
173 *
174 */
175 uint32 Uart_schm_read_msr(void);
176 #endif /*ifndef _COSMIC_C_S32ZE_*/
177 /*==================================================================================================
178 * LOCAL FUNCTIONS
179 ==================================================================================================*/
180 #define RTE_START_SEC_CODE
181 #include "Rte_MemMap.h"
182
183 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
184 /*================================================================================================*/
185 /**
186 * @brief This macro returns the MSR register value (32 bits).
187 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
188 *
189 * @pre None
190 * @post None
191 *
192 */
193 #ifdef MCAL_PLATFORM_ARM
194 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Uart_schm_read_msr(void)195 ASM_KEYWORD uint32 Uart_schm_read_msr(void)
196 {
197 mrs x0, S3_3_c4_c2_1
198 }
199 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Uart_schm_read_msr(void)200 ASM_KEYWORD uint32 Uart_schm_read_msr(void)
201 {
202 mrs r0, CPSR
203 }
204 #else
Uart_schm_read_msr(void)205 ASM_KEYWORD uint32 Uart_schm_read_msr(void)
206 {
207 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
208 mrs r0, BASEPRI
209 #else
210 mrs r0, PRIMASK
211 #endif
212 }
213 #endif
214 #else
215 #ifdef MCAL_PLATFORM_S12
Uart_schm_read_msr(void)216 ASM_KEYWORD uint32 Uart_schm_read_msr(void)
217 {
218 tfr ccr, d6
219 }
220 #else
Uart_schm_read_msr(void)221 ASM_KEYWORD uint32 Uart_schm_read_msr(void)
222 {
223 mfmsr r3
224 }
225 #endif
226 #endif
227 #endif /*#ifdef GHS||CW*/
228
229 #ifdef _DIABDATA_C_S32ZE_
230 /**
231 * @brief This function returns the MSR register value (32 bits).
232 * @details This function returns the MSR register value (32 bits).
233 *
234 * @param[in] void No input parameters
235 * @return uint32 msr This function returns the MSR register value (32 bits).
236 *
237 * @pre None
238 * @post None
239 *
240 */
241 #ifdef MCAL_PLATFORM_ARM
Uart_schm_read_msr(void)242 uint32 Uart_schm_read_msr(void)
243 {
244 register uint32 reg_tmp;
245 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
246 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
247 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
248 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
249 #else
250 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
251 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
252 #else
253 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
254 #endif
255 #endif
256 return (uint32)reg_tmp;
257 }
258 #else
Uart_schm_read_msr(void)259 ASM_KEYWORD uint32 Uart_schm_read_msr(void)
260 {
261 mfmsr r3
262 }
263 #endif /* MCAL_PLATFORM_ARM */
264
265 #endif /* _DIABDATA_C_S32ZE_*/
266
267 #ifdef _COSMIC_C_S32ZE_
268 /*================================================================================================*/
269 /**
270 * @brief This function returns the MSR register value (32 bits).
271 * @details This function returns the MSR register value (32 bits).
272 *
273 * @param[in] void No input parameters
274 * @return uint32 msr This function returns the MSR register value (32 bits).
275 *
276 * @pre None
277 * @post None
278 *
279 */
280
281 #ifdef MCAL_PLATFORM_S12
282 #define Uart_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
283 #else
284 #define Uart_schm_read_msr() ASM_KEYWORD("mfmsr r3")
285 #endif
286
287 #endif /*Cosmic compiler only*/
288
289
290 #ifdef _HITECH_C_S32ZE_
291 /*================================================================================================*/
292 /**
293 * @brief This function returns the MSR register value (32 bits).
294 * @details This function returns the MSR register value (32 bits).
295 *
296 * @param[in] void No input parameters
297 * @return uint32 msr This function returns the MSR register value (32 bits).
298 *
299 * @pre None
300 * @post None
301 *
302 */
Uart_schm_read_msr(void)303 uint32 Uart_schm_read_msr(void)
304 {
305 uint32 result;
306 __asm volatile("mfmsr %0" : "=r" (result) :);
307 return result;
308 }
309
310 #endif /*HighTec compiler only*/
311 /*================================================================================================*/
312 #ifdef _LINARO_C_S32ZE_
313 /**
314 * @brief This function returns the MSR register value (32 bits).
315 * @details This function returns the MSR register value (32 bits).
316 *
317 * @param[in] void No input parameters
318 * @return uint32 msr This function returns the MSR register value (32 bits).
319 *
320 * @pre None
321 * @post None
322 *
323 */
Uart_schm_read_msr(void)324 uint32 Uart_schm_read_msr(void)
325 {
326 register uint32 reg_tmp;
327 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
328 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
329 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
330 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
331 #else
332 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
333 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
334 #else
335 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
336 #endif
337 #endif
338 return (uint32)reg_tmp;
339 }
340 #endif /* _LINARO_C_S32ZE_*/
341 /*================================================================================================*/
342
343 #ifdef _ARM_DS5_C_S32ZE_
344 /**
345 * @brief This function returns the MSR register value (32 bits).
346 * @details This function returns the MSR register value (32 bits).
347 *
348 * @param[in] void No input parameters
349 * @return uint32 msr This function returns the MSR register value (32 bits).
350 *
351 * @pre None
352 * @post None
353 *
354 */
Uart_schm_read_msr(void)355 uint32 Uart_schm_read_msr(void)
356 {
357 register uint32 reg_tmp;
358 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
359 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
360 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
361 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
362 #else
363 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
364 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
365 #else
366 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
367 #endif
368 #endif
369 return (uint32)reg_tmp;
370 }
371 #endif /* _ARM_DS5_C_S32ZE_ */
372
373 #ifdef _IAR_C_S32ZE_
374 /**
375 * @brief This function returns the MSR register value (32 bits).
376 * @details This function returns the MSR register value (32 bits).
377 *
378 * @param[in] void No input parameters
379 * @return uint32 msr This function returns the MSR register value (32 bits).
380 *
381 * @pre None
382 * @post None
383 *
384 */
Uart_schm_read_msr(void)385 uint32 Uart_schm_read_msr(void)
386 {
387 register uint32 reg_tmp;
388
389 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
390 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
391 #else
392 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
393 #endif
394
395 return (uint32)reg_tmp;
396 }
397 #endif /* _IAR_C_S32ZE_ */
398
399 #define RTE_STOP_SEC_CODE
400 #include "Rte_MemMap.h"
401
402 /*==================================================================================================
403 * GLOBAL FUNCTIONS
404 ==================================================================================================*/
405 #define RTE_START_SEC_CODE
406 #include "Rte_MemMap.h"
407
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_00(void)408 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_00(void)
409 {
410 uint32 msr;
411 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
412
413 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_00[u32CoreId])
414 {
415 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
416 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
417 #else
418 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
419 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
420 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
421 {
422 OsIf_SuspendAllInterrupts();
423 #ifdef _ARM_DS5_C_S32ZE_
424 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
425 #endif
426 }
427 msr_UART_EXCLUSIVE_AREA_00[u32CoreId] = msr;
428 }
429 reentry_guard_UART_EXCLUSIVE_AREA_00[u32CoreId]++;
430 }
431
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_00(void)432 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_00(void)
433 {
434 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
435
436 reentry_guard_UART_EXCLUSIVE_AREA_00[u32CoreId]--;
437 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
438 {
439 OsIf_ResumeAllInterrupts();
440 #ifdef _ARM_DS5_C_S32ZE_
441 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
442 #endif
443 }
444 }
445
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_01(void)446 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_01(void)
447 {
448 uint32 msr;
449 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
450
451 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_01[u32CoreId])
452 {
453 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
454 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
455 #else
456 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
457 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
458 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
459 {
460 OsIf_SuspendAllInterrupts();
461 #ifdef _ARM_DS5_C_S32ZE_
462 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
463 #endif
464 }
465 msr_UART_EXCLUSIVE_AREA_01[u32CoreId] = msr;
466 }
467 reentry_guard_UART_EXCLUSIVE_AREA_01[u32CoreId]++;
468 }
469
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_01(void)470 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_01(void)
471 {
472 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
473
474 reentry_guard_UART_EXCLUSIVE_AREA_01[u32CoreId]--;
475 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
476 {
477 OsIf_ResumeAllInterrupts();
478 #ifdef _ARM_DS5_C_S32ZE_
479 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
480 #endif
481 }
482 }
483
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_02(void)484 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_02(void)
485 {
486 uint32 msr;
487 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
488
489 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_02[u32CoreId])
490 {
491 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
492 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
493 #else
494 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
495 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
496 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
497 {
498 OsIf_SuspendAllInterrupts();
499 #ifdef _ARM_DS5_C_S32ZE_
500 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
501 #endif
502 }
503 msr_UART_EXCLUSIVE_AREA_02[u32CoreId] = msr;
504 }
505 reentry_guard_UART_EXCLUSIVE_AREA_02[u32CoreId]++;
506 }
507
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_02(void)508 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_02(void)
509 {
510 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
511
512 reentry_guard_UART_EXCLUSIVE_AREA_02[u32CoreId]--;
513 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
514 {
515 OsIf_ResumeAllInterrupts();
516 #ifdef _ARM_DS5_C_S32ZE_
517 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
518 #endif
519 }
520 }
521
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_03(void)522 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_03(void)
523 {
524 uint32 msr;
525 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
526
527 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_03[u32CoreId])
528 {
529 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
530 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
531 #else
532 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
533 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
534 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
535 {
536 OsIf_SuspendAllInterrupts();
537 #ifdef _ARM_DS5_C_S32ZE_
538 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
539 #endif
540 }
541 msr_UART_EXCLUSIVE_AREA_03[u32CoreId] = msr;
542 }
543 reentry_guard_UART_EXCLUSIVE_AREA_03[u32CoreId]++;
544 }
545
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_03(void)546 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_03(void)
547 {
548 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
549
550 reentry_guard_UART_EXCLUSIVE_AREA_03[u32CoreId]--;
551 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
552 {
553 OsIf_ResumeAllInterrupts();
554 #ifdef _ARM_DS5_C_S32ZE_
555 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
556 #endif
557 }
558 }
559
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_04(void)560 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_04(void)
561 {
562 uint32 msr;
563 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
564
565 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_04[u32CoreId])
566 {
567 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
568 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
569 #else
570 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
571 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
572 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
573 {
574 OsIf_SuspendAllInterrupts();
575 #ifdef _ARM_DS5_C_S32ZE_
576 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
577 #endif
578 }
579 msr_UART_EXCLUSIVE_AREA_04[u32CoreId] = msr;
580 }
581 reentry_guard_UART_EXCLUSIVE_AREA_04[u32CoreId]++;
582 }
583
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_04(void)584 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_04(void)
585 {
586 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
587
588 reentry_guard_UART_EXCLUSIVE_AREA_04[u32CoreId]--;
589 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
590 {
591 OsIf_ResumeAllInterrupts();
592 #ifdef _ARM_DS5_C_S32ZE_
593 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
594 #endif
595 }
596 }
597
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_05(void)598 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_05(void)
599 {
600 uint32 msr;
601 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
602
603 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_05[u32CoreId])
604 {
605 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
606 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
607 #else
608 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
609 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
610 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
611 {
612 OsIf_SuspendAllInterrupts();
613 #ifdef _ARM_DS5_C_S32ZE_
614 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
615 #endif
616 }
617 msr_UART_EXCLUSIVE_AREA_05[u32CoreId] = msr;
618 }
619 reentry_guard_UART_EXCLUSIVE_AREA_05[u32CoreId]++;
620 }
621
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_05(void)622 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_05(void)
623 {
624 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
625
626 reentry_guard_UART_EXCLUSIVE_AREA_05[u32CoreId]--;
627 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
628 {
629 OsIf_ResumeAllInterrupts();
630 #ifdef _ARM_DS5_C_S32ZE_
631 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
632 #endif
633 }
634 }
635
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_06(void)636 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_06(void)
637 {
638 uint32 msr;
639 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
640
641 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_06[u32CoreId])
642 {
643 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
644 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
645 #else
646 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
647 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
648 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
649 {
650 OsIf_SuspendAllInterrupts();
651 #ifdef _ARM_DS5_C_S32ZE_
652 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
653 #endif
654 }
655 msr_UART_EXCLUSIVE_AREA_06[u32CoreId] = msr;
656 }
657 reentry_guard_UART_EXCLUSIVE_AREA_06[u32CoreId]++;
658 }
659
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_06(void)660 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_06(void)
661 {
662 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
663
664 reentry_guard_UART_EXCLUSIVE_AREA_06[u32CoreId]--;
665 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
666 {
667 OsIf_ResumeAllInterrupts();
668 #ifdef _ARM_DS5_C_S32ZE_
669 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
670 #endif
671 }
672 }
673
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_07(void)674 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_07(void)
675 {
676 uint32 msr;
677 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
678
679 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_07[u32CoreId])
680 {
681 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
682 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
683 #else
684 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
685 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
686 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
687 {
688 OsIf_SuspendAllInterrupts();
689 #ifdef _ARM_DS5_C_S32ZE_
690 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
691 #endif
692 }
693 msr_UART_EXCLUSIVE_AREA_07[u32CoreId] = msr;
694 }
695 reentry_guard_UART_EXCLUSIVE_AREA_07[u32CoreId]++;
696 }
697
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_07(void)698 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_07(void)
699 {
700 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
701
702 reentry_guard_UART_EXCLUSIVE_AREA_07[u32CoreId]--;
703 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
704 {
705 OsIf_ResumeAllInterrupts();
706 #ifdef _ARM_DS5_C_S32ZE_
707 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
708 #endif
709 }
710 }
711
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_08(void)712 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_08(void)
713 {
714 uint32 msr;
715 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
716
717 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_08[u32CoreId])
718 {
719 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
720 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
721 #else
722 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
723 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
724 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
725 {
726 OsIf_SuspendAllInterrupts();
727 #ifdef _ARM_DS5_C_S32ZE_
728 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
729 #endif
730 }
731 msr_UART_EXCLUSIVE_AREA_08[u32CoreId] = msr;
732 }
733 reentry_guard_UART_EXCLUSIVE_AREA_08[u32CoreId]++;
734 }
735
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_08(void)736 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_08(void)
737 {
738 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
739
740 reentry_guard_UART_EXCLUSIVE_AREA_08[u32CoreId]--;
741 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
742 {
743 OsIf_ResumeAllInterrupts();
744 #ifdef _ARM_DS5_C_S32ZE_
745 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
746 #endif
747 }
748 }
749
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_09(void)750 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_09(void)
751 {
752 uint32 msr;
753 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
754
755 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_09[u32CoreId])
756 {
757 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
758 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
759 #else
760 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
761 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
762 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
763 {
764 OsIf_SuspendAllInterrupts();
765 #ifdef _ARM_DS5_C_S32ZE_
766 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
767 #endif
768 }
769 msr_UART_EXCLUSIVE_AREA_09[u32CoreId] = msr;
770 }
771 reentry_guard_UART_EXCLUSIVE_AREA_09[u32CoreId]++;
772 }
773
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_09(void)774 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_09(void)
775 {
776 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
777
778 reentry_guard_UART_EXCLUSIVE_AREA_09[u32CoreId]--;
779 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
780 {
781 OsIf_ResumeAllInterrupts();
782 #ifdef _ARM_DS5_C_S32ZE_
783 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
784 #endif
785 }
786 }
787
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_10(void)788 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_10(void)
789 {
790 uint32 msr;
791 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
792
793 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_10[u32CoreId])
794 {
795 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
796 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
797 #else
798 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
799 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
800 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
801 {
802 OsIf_SuspendAllInterrupts();
803 #ifdef _ARM_DS5_C_S32ZE_
804 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
805 #endif
806 }
807 msr_UART_EXCLUSIVE_AREA_10[u32CoreId] = msr;
808 }
809 reentry_guard_UART_EXCLUSIVE_AREA_10[u32CoreId]++;
810 }
811
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_10(void)812 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_10(void)
813 {
814 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
815
816 reentry_guard_UART_EXCLUSIVE_AREA_10[u32CoreId]--;
817 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
818 {
819 OsIf_ResumeAllInterrupts();
820 #ifdef _ARM_DS5_C_S32ZE_
821 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
822 #endif
823 }
824 }
825
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_11(void)826 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_11(void)
827 {
828 uint32 msr;
829 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
830
831 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_11[u32CoreId])
832 {
833 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
834 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
835 #else
836 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
837 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
838 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
839 {
840 OsIf_SuspendAllInterrupts();
841 #ifdef _ARM_DS5_C_S32ZE_
842 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
843 #endif
844 }
845 msr_UART_EXCLUSIVE_AREA_11[u32CoreId] = msr;
846 }
847 reentry_guard_UART_EXCLUSIVE_AREA_11[u32CoreId]++;
848 }
849
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_11(void)850 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_11(void)
851 {
852 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
853
854 reentry_guard_UART_EXCLUSIVE_AREA_11[u32CoreId]--;
855 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
856 {
857 OsIf_ResumeAllInterrupts();
858 #ifdef _ARM_DS5_C_S32ZE_
859 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
860 #endif
861 }
862 }
863
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_12(void)864 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_12(void)
865 {
866 uint32 msr;
867 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
868
869 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_12[u32CoreId])
870 {
871 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
872 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
873 #else
874 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
875 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
876 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
877 {
878 OsIf_SuspendAllInterrupts();
879 #ifdef _ARM_DS5_C_S32ZE_
880 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
881 #endif
882 }
883 msr_UART_EXCLUSIVE_AREA_12[u32CoreId] = msr;
884 }
885 reentry_guard_UART_EXCLUSIVE_AREA_12[u32CoreId]++;
886 }
887
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_12(void)888 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_12(void)
889 {
890 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
891
892 reentry_guard_UART_EXCLUSIVE_AREA_12[u32CoreId]--;
893 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
894 {
895 OsIf_ResumeAllInterrupts();
896 #ifdef _ARM_DS5_C_S32ZE_
897 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
898 #endif
899 }
900 }
901
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_13(void)902 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_13(void)
903 {
904 uint32 msr;
905 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
906
907 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_13[u32CoreId])
908 {
909 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
910 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
911 #else
912 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
913 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
914 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
915 {
916 OsIf_SuspendAllInterrupts();
917 #ifdef _ARM_DS5_C_S32ZE_
918 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
919 #endif
920 }
921 msr_UART_EXCLUSIVE_AREA_13[u32CoreId] = msr;
922 }
923 reentry_guard_UART_EXCLUSIVE_AREA_13[u32CoreId]++;
924 }
925
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_13(void)926 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_13(void)
927 {
928 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
929
930 reentry_guard_UART_EXCLUSIVE_AREA_13[u32CoreId]--;
931 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
932 {
933 OsIf_ResumeAllInterrupts();
934 #ifdef _ARM_DS5_C_S32ZE_
935 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
936 #endif
937 }
938 }
939
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_14(void)940 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_14(void)
941 {
942 uint32 msr;
943 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
944
945 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_14[u32CoreId])
946 {
947 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
948 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
949 #else
950 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
951 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
952 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
953 {
954 OsIf_SuspendAllInterrupts();
955 #ifdef _ARM_DS5_C_S32ZE_
956 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
957 #endif
958 }
959 msr_UART_EXCLUSIVE_AREA_14[u32CoreId] = msr;
960 }
961 reentry_guard_UART_EXCLUSIVE_AREA_14[u32CoreId]++;
962 }
963
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_14(void)964 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_14(void)
965 {
966 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
967
968 reentry_guard_UART_EXCLUSIVE_AREA_14[u32CoreId]--;
969 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
970 {
971 OsIf_ResumeAllInterrupts();
972 #ifdef _ARM_DS5_C_S32ZE_
973 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
974 #endif
975 }
976 }
977
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_15(void)978 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_15(void)
979 {
980 uint32 msr;
981 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
982
983 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_15[u32CoreId])
984 {
985 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
986 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
987 #else
988 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
989 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
990 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
991 {
992 OsIf_SuspendAllInterrupts();
993 #ifdef _ARM_DS5_C_S32ZE_
994 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
995 #endif
996 }
997 msr_UART_EXCLUSIVE_AREA_15[u32CoreId] = msr;
998 }
999 reentry_guard_UART_EXCLUSIVE_AREA_15[u32CoreId]++;
1000 }
1001
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_15(void)1002 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_15(void)
1003 {
1004 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1005
1006 reentry_guard_UART_EXCLUSIVE_AREA_15[u32CoreId]--;
1007 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
1008 {
1009 OsIf_ResumeAllInterrupts();
1010 #ifdef _ARM_DS5_C_S32ZE_
1011 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1012 #endif
1013 }
1014 }
1015
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_16(void)1016 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_16(void)
1017 {
1018 uint32 msr;
1019 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1020
1021 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_16[u32CoreId])
1022 {
1023 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1024 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
1025 #else
1026 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
1027 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1028 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1029 {
1030 OsIf_SuspendAllInterrupts();
1031 #ifdef _ARM_DS5_C_S32ZE_
1032 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1033 #endif
1034 }
1035 msr_UART_EXCLUSIVE_AREA_16[u32CoreId] = msr;
1036 }
1037 reentry_guard_UART_EXCLUSIVE_AREA_16[u32CoreId]++;
1038 }
1039
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_16(void)1040 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_16(void)
1041 {
1042 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1043
1044 reentry_guard_UART_EXCLUSIVE_AREA_16[u32CoreId]--;
1045 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
1046 {
1047 OsIf_ResumeAllInterrupts();
1048 #ifdef _ARM_DS5_C_S32ZE_
1049 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1050 #endif
1051 }
1052 }
1053
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_17(void)1054 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_17(void)
1055 {
1056 uint32 msr;
1057 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1058
1059 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_17[u32CoreId])
1060 {
1061 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1062 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
1063 #else
1064 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
1065 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1066 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1067 {
1068 OsIf_SuspendAllInterrupts();
1069 #ifdef _ARM_DS5_C_S32ZE_
1070 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1071 #endif
1072 }
1073 msr_UART_EXCLUSIVE_AREA_17[u32CoreId] = msr;
1074 }
1075 reentry_guard_UART_EXCLUSIVE_AREA_17[u32CoreId]++;
1076 }
1077
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_17(void)1078 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_17(void)
1079 {
1080 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1081
1082 reentry_guard_UART_EXCLUSIVE_AREA_17[u32CoreId]--;
1083 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
1084 {
1085 OsIf_ResumeAllInterrupts();
1086 #ifdef _ARM_DS5_C_S32ZE_
1087 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1088 #endif
1089 }
1090 }
1091
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_18(void)1092 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_18(void)
1093 {
1094 uint32 msr;
1095 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1096
1097 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_18[u32CoreId])
1098 {
1099 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1100 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
1101 #else
1102 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
1103 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1104 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1105 {
1106 OsIf_SuspendAllInterrupts();
1107 #ifdef _ARM_DS5_C_S32ZE_
1108 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1109 #endif
1110 }
1111 msr_UART_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1112 }
1113 reentry_guard_UART_EXCLUSIVE_AREA_18[u32CoreId]++;
1114 }
1115
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_18(void)1116 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_18(void)
1117 {
1118 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1119
1120 reentry_guard_UART_EXCLUSIVE_AREA_18[u32CoreId]--;
1121 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1122 {
1123 OsIf_ResumeAllInterrupts();
1124 #ifdef _ARM_DS5_C_S32ZE_
1125 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1126 #endif
1127 }
1128 }
1129
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_19(void)1130 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_19(void)
1131 {
1132 uint32 msr;
1133 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1134
1135 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_19[u32CoreId])
1136 {
1137 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1138 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
1139 #else
1140 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
1141 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1142 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1143 {
1144 OsIf_SuspendAllInterrupts();
1145 #ifdef _ARM_DS5_C_S32ZE_
1146 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1147 #endif
1148 }
1149 msr_UART_EXCLUSIVE_AREA_19[u32CoreId] = msr;
1150 }
1151 reentry_guard_UART_EXCLUSIVE_AREA_19[u32CoreId]++;
1152 }
1153
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_19(void)1154 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_19(void)
1155 {
1156 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1157
1158 reentry_guard_UART_EXCLUSIVE_AREA_19[u32CoreId]--;
1159 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_19[u32CoreId])) /*if interrupts were enabled*/
1160 {
1161 OsIf_ResumeAllInterrupts();
1162 #ifdef _ARM_DS5_C_S32ZE_
1163 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1164 #endif
1165 }
1166 }
1167
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_20(void)1168 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_20(void)
1169 {
1170 uint32 msr;
1171 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1172
1173 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_20[u32CoreId])
1174 {
1175 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1176 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
1177 #else
1178 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
1179 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1180 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1181 {
1182 OsIf_SuspendAllInterrupts();
1183 #ifdef _ARM_DS5_C_S32ZE_
1184 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1185 #endif
1186 }
1187 msr_UART_EXCLUSIVE_AREA_20[u32CoreId] = msr;
1188 }
1189 reentry_guard_UART_EXCLUSIVE_AREA_20[u32CoreId]++;
1190 }
1191
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_20(void)1192 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_20(void)
1193 {
1194 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1195
1196 reentry_guard_UART_EXCLUSIVE_AREA_20[u32CoreId]--;
1197 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
1198 {
1199 OsIf_ResumeAllInterrupts();
1200 #ifdef _ARM_DS5_C_S32ZE_
1201 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1202 #endif
1203 }
1204 }
1205
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_21(void)1206 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_21(void)
1207 {
1208 uint32 msr;
1209 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1210
1211 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_21[u32CoreId])
1212 {
1213 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1214 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
1215 #else
1216 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
1217 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1218 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1219 {
1220 OsIf_SuspendAllInterrupts();
1221 #ifdef _ARM_DS5_C_S32ZE_
1222 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1223 #endif
1224 }
1225 msr_UART_EXCLUSIVE_AREA_21[u32CoreId] = msr;
1226 }
1227 reentry_guard_UART_EXCLUSIVE_AREA_21[u32CoreId]++;
1228 }
1229
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_21(void)1230 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_21(void)
1231 {
1232 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1233
1234 reentry_guard_UART_EXCLUSIVE_AREA_21[u32CoreId]--;
1235 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
1236 {
1237 OsIf_ResumeAllInterrupts();
1238 #ifdef _ARM_DS5_C_S32ZE_
1239 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1240 #endif
1241 }
1242 }
1243
1244 #ifdef MCAL_TESTING_ENVIRONMENT
1245 /**
1246 @brief This function checks that all entered exclusive areas were also exited.
1247 @details This function checks that all entered exclusive areas were also exited. The check
1248 is done by verifying that all reentry_guard_* static variables are back to the
1249 zero value.
1250
1251 @param[in] void No input parameters
1252 @return void This function does not return a value. Test asserts are used instead.
1253
1254 @pre None
1255 @post None
1256
1257 @remarks Covers
1258 @remarks Implements
1259 */
SchM_Check_uart(void)1260 void SchM_Check_uart(void)
1261 {
1262 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1263
1264 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_00[u32CoreId]);
1265 reentry_guard_UART_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_00 for the next test in the suite*/
1266
1267 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_01[u32CoreId]);
1268 reentry_guard_UART_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_01 for the next test in the suite*/
1269
1270 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_02[u32CoreId]);
1271 reentry_guard_UART_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_02 for the next test in the suite*/
1272
1273 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_03[u32CoreId]);
1274 reentry_guard_UART_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_03 for the next test in the suite*/
1275
1276 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_04[u32CoreId]);
1277 reentry_guard_UART_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_04 for the next test in the suite*/
1278
1279 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_05[u32CoreId]);
1280 reentry_guard_UART_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_05 for the next test in the suite*/
1281
1282 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_06[u32CoreId]);
1283 reentry_guard_UART_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_06 for the next test in the suite*/
1284
1285 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_07[u32CoreId]);
1286 reentry_guard_UART_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_07 for the next test in the suite*/
1287
1288 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_08[u32CoreId]);
1289 reentry_guard_UART_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_08 for the next test in the suite*/
1290
1291 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_09[u32CoreId]);
1292 reentry_guard_UART_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_09 for the next test in the suite*/
1293
1294 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_10[u32CoreId]);
1295 reentry_guard_UART_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_10 for the next test in the suite*/
1296
1297 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_11[u32CoreId]);
1298 reentry_guard_UART_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_11 for the next test in the suite*/
1299
1300 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_12[u32CoreId]);
1301 reentry_guard_UART_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_12 for the next test in the suite*/
1302
1303 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_13[u32CoreId]);
1304 reentry_guard_UART_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_13 for the next test in the suite*/
1305
1306 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_14[u32CoreId]);
1307 reentry_guard_UART_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_14 for the next test in the suite*/
1308
1309 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_15[u32CoreId]);
1310 reentry_guard_UART_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_15 for the next test in the suite*/
1311
1312 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_16[u32CoreId]);
1313 reentry_guard_UART_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_16 for the next test in the suite*/
1314
1315 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_17[u32CoreId]);
1316 reentry_guard_UART_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_17 for the next test in the suite*/
1317
1318 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_18[u32CoreId]);
1319 reentry_guard_UART_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_18 for the next test in the suite*/
1320
1321 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_19[u32CoreId]);
1322 reentry_guard_UART_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_19 for the next test in the suite*/
1323
1324 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_20[u32CoreId]);
1325 reentry_guard_UART_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_20 for the next test in the suite*/
1326
1327 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_21[u32CoreId]);
1328 reentry_guard_UART_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_21 for the next test in the suite*/
1329
1330 }
1331 #endif /*MCAL_TESTING_ENVIRONMENT*/
1332
1333 #define RTE_STOP_SEC_CODE
1334 #include "Rte_MemMap.h"
1335
1336 #ifdef __cplusplus
1337 }
1338 #endif
1339
1340 /** @} */
1341
