1 /*
2 * Copyright 2021-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup RTE_MODULE
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Std_Types.h"
25 #include "Mcal.h"
26 #include "OsIf.h"
27 #include "SchM_Uart.h"
28 #ifdef MCAL_TESTING_ENVIRONMENT
29 #include "EUnit.h" /* EUnit Test Suite */
30 #endif
31
32 /*==================================================================================================
33 * SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define SCHM_UART_AR_RELEASE_MAJOR_VERSION_C 4
36 #define SCHM_UART_AR_RELEASE_MINOR_VERSION_C 7
37 #define SCHM_UART_AR_RELEASE_REVISION_VERSION_C 0
38 #define SCHM_UART_SW_MAJOR_VERSION_C 0
39 #define SCHM_UART_SW_MINOR_VERSION_C 9
40 #define SCHM_UART_SW_PATCH_VERSION_C 0
41
42 /*==================================================================================================
43 * LOCAL CONSTANTS
44 ==================================================================================================*/
45 #ifdef MCAL_PLATFORM_ARM
46 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
47 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
48 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
49 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
50 #else
51 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
52 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
53 #else
54 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
55 #endif
56 #endif
57 #else
58 #ifdef MCAL_PLATFORM_S12
59 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
60 #else
61 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
62 #endif
63 #endif
64 /*==================================================================================================
65 * LOCAL MACROS
66 ==================================================================================================*/
67 #ifdef MCAL_PLATFORM_ARM
68 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
69 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
70 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
71 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
72 #else
73 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
74 #endif
75 #else
76 #ifdef MCAL_PLATFORM_S12
77 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
78 #else
79 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
80 #endif
81 #endif
82
83 /*==================================================================================================
84 * FILE VERSION CHECKS
85 ==================================================================================================*/
86
87 /*==================================================================================================
88 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
89 ==================================================================================================*/
90
91
92 /*==================================================================================================
93 * LOCAL VARIABLES
94 ==================================================================================================*/
95 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
96 #include "Rte_MemMap.h"
97 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_00) static volatile uint32 msr_UART_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
98 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
99 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_01) static volatile uint32 msr_UART_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
100 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
101 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_02) static volatile uint32 msr_UART_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
102 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_03) static volatile uint32 msr_UART_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_04) static volatile uint32 msr_UART_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_05) static volatile uint32 msr_UART_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_06) static volatile uint32 msr_UART_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_07) static volatile uint32 msr_UART_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(msr_UART_EXCLUSIVE_AREA_08) static volatile uint32 msr_UART_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(reentry_guard_UART_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
115
116 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
117 #include "Rte_MemMap.h"
118 /*==================================================================================================
119 * GLOBAL CONSTANTS
120 ==================================================================================================*/
121
122
123 /*==================================================================================================
124 * GLOBAL VARIABLES
125 ==================================================================================================*/
126
127 /*==================================================================================================
128 * LOCAL FUNCTION PROTOTYPES
129 ==================================================================================================*/
130
131 #ifndef _COSMIC_C_S32ZE_
132 /*================================================================================================*/
133 /**
134 * @brief This function returns the MSR register value (32 bits).
135 * @details This function returns the MSR register value (32 bits).
136 *
137 * @param[in] void No input parameters
138 * @return uint32 msr This function returns the MSR register value (32 bits).
139 *
140 * @pre None
141 * @post None
142 *
143 */
144 uint32 Uart_schm_read_msr(void);
145 #endif /*ifndef _COSMIC_C_S32ZE_*/
146 /*==================================================================================================
147 * LOCAL FUNCTIONS
148 ==================================================================================================*/
149 #define RTE_START_SEC_CODE
150 #include "Rte_MemMap.h"
151
152 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
153 /*================================================================================================*/
154 /**
155 * @brief This macro returns the MSR register value (32 bits).
156 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
157 *
158 * @pre None
159 * @post None
160 *
161 */
162 #ifdef MCAL_PLATFORM_ARM
163 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Uart_schm_read_msr(void)164 ASM_KEYWORD uint32 Uart_schm_read_msr(void)
165 {
166 mrs x0, S3_3_c4_c2_1
167 }
168 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Uart_schm_read_msr(void)169 ASM_KEYWORD uint32 Uart_schm_read_msr(void)
170 {
171 mrs r0, CPSR
172 }
173 #else
Uart_schm_read_msr(void)174 ASM_KEYWORD uint32 Uart_schm_read_msr(void)
175 {
176 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
177 mrs r0, BASEPRI
178 #else
179 mrs r0, PRIMASK
180 #endif
181 }
182 #endif
183 #else
184 #ifdef MCAL_PLATFORM_S12
Uart_schm_read_msr(void)185 ASM_KEYWORD uint32 Uart_schm_read_msr(void)
186 {
187 tfr ccr, d6
188 }
189 #else
Uart_schm_read_msr(void)190 ASM_KEYWORD uint32 Uart_schm_read_msr(void)
191 {
192 mfmsr r3
193 }
194 #endif
195 #endif
196 #endif /*#ifdef GHS||CW*/
197
198 #ifdef _DIABDATA_C_S32ZE_
199 /**
200 * @brief This function returns the MSR register value (32 bits).
201 * @details This function returns the MSR register value (32 bits).
202 *
203 * @param[in] void No input parameters
204 * @return uint32 msr This function returns the MSR register value (32 bits).
205 *
206 * @pre None
207 * @post None
208 *
209 */
210 #ifdef MCAL_PLATFORM_ARM
Uart_schm_read_msr(void)211 uint32 Uart_schm_read_msr(void)
212 {
213 register uint32 reg_tmp;
214 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
215 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
216 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
217 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
218 #else
219 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
220 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
221 #else
222 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
223 #endif
224 #endif
225 return (uint32)reg_tmp;
226 }
227 #else
Uart_schm_read_msr(void)228 ASM_KEYWORD uint32 Uart_schm_read_msr(void)
229 {
230 mfmsr r3
231 }
232 #endif /* MCAL_PLATFORM_ARM */
233
234 #endif /* _DIABDATA_C_S32ZE_*/
235
236 #ifdef _COSMIC_C_S32ZE_
237 /*================================================================================================*/
238 /**
239 * @brief This function returns the MSR register value (32 bits).
240 * @details This function returns the MSR register value (32 bits).
241 *
242 * @param[in] void No input parameters
243 * @return uint32 msr This function returns the MSR register value (32 bits).
244 *
245 * @pre None
246 * @post None
247 *
248 */
249
250 #ifdef MCAL_PLATFORM_S12
251 #define Uart_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
252 #else
253 #define Uart_schm_read_msr() ASM_KEYWORD("mfmsr r3")
254 #endif
255
256 #endif /*Cosmic compiler only*/
257
258
259 #ifdef _HITECH_C_S32ZE_
260 /*================================================================================================*/
261 /**
262 * @brief This function returns the MSR register value (32 bits).
263 * @details This function returns the MSR register value (32 bits).
264 *
265 * @param[in] void No input parameters
266 * @return uint32 msr This function returns the MSR register value (32 bits).
267 *
268 * @pre None
269 * @post None
270 *
271 */
Uart_schm_read_msr(void)272 uint32 Uart_schm_read_msr(void)
273 {
274 uint32 result;
275 __asm volatile("mfmsr %0" : "=r" (result) :);
276 return result;
277 }
278
279 #endif /*HighTec compiler only*/
280 /*================================================================================================*/
281 #ifdef _LINARO_C_S32ZE_
282 /**
283 * @brief This function returns the MSR register value (32 bits).
284 * @details This function returns the MSR register value (32 bits).
285 *
286 * @param[in] void No input parameters
287 * @return uint32 msr This function returns the MSR register value (32 bits).
288 *
289 * @pre None
290 * @post None
291 *
292 */
Uart_schm_read_msr(void)293 uint32 Uart_schm_read_msr(void)
294 {
295 register uint32 reg_tmp;
296 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
297 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
298 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
299 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
300 #else
301 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
302 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
303 #else
304 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
305 #endif
306 #endif
307 return (uint32)reg_tmp;
308 }
309 #endif /* _LINARO_C_S32ZE_*/
310 /*================================================================================================*/
311
312 #ifdef _ARM_DS5_C_S32ZE_
313 /**
314 * @brief This function returns the MSR register value (32 bits).
315 * @details This function returns the MSR register value (32 bits).
316 *
317 * @param[in] void No input parameters
318 * @return uint32 msr This function returns the MSR register value (32 bits).
319 *
320 * @pre None
321 * @post None
322 *
323 */
Uart_schm_read_msr(void)324 uint32 Uart_schm_read_msr(void)
325 {
326 register uint32 reg_tmp;
327 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
328 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
329 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
330 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
331 #else
332 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
333 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
334 #else
335 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
336 #endif
337 #endif
338 return (uint32)reg_tmp;
339 }
340 #endif /* _ARM_DS5_C_S32ZE_ */
341
342 #ifdef _IAR_C_S32ZE_
343 /**
344 * @brief This function returns the MSR register value (32 bits).
345 * @details This function returns the MSR register value (32 bits).
346 *
347 * @param[in] void No input parameters
348 * @return uint32 msr This function returns the MSR register value (32 bits).
349 *
350 * @pre None
351 * @post None
352 *
353 */
Uart_schm_read_msr(void)354 uint32 Uart_schm_read_msr(void)
355 {
356 register uint32 reg_tmp;
357
358 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
359 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
360 #else
361 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
362 #endif
363
364 return (uint32)reg_tmp;
365 }
366 #endif /* _IAR_C_S32ZE_ */
367
368 #define RTE_STOP_SEC_CODE
369 #include "Rte_MemMap.h"
370
371 /*==================================================================================================
372 * GLOBAL FUNCTIONS
373 ==================================================================================================*/
374 #define RTE_START_SEC_CODE
375 #include "Rte_MemMap.h"
376
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_00(void)377 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_00(void)
378 {
379 uint32 msr;
380 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
381
382 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_00[u32CoreId])
383 {
384 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
385 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
386 #else
387 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
388 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
389 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
390 {
391 OsIf_SuspendAllInterrupts();
392 #ifdef _ARM_DS5_C_S32ZE_
393 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
394 #endif
395 }
396 msr_UART_EXCLUSIVE_AREA_00[u32CoreId] = msr;
397 }
398 reentry_guard_UART_EXCLUSIVE_AREA_00[u32CoreId]++;
399 }
400
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_00(void)401 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_00(void)
402 {
403 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
404
405 reentry_guard_UART_EXCLUSIVE_AREA_00[u32CoreId]--;
406 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
407 {
408 OsIf_ResumeAllInterrupts();
409 #ifdef _ARM_DS5_C_S32ZE_
410 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
411 #endif
412 }
413 }
414
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_01(void)415 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_01(void)
416 {
417 uint32 msr;
418 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
419
420 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_01[u32CoreId])
421 {
422 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
423 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
424 #else
425 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
426 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
427 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
428 {
429 OsIf_SuspendAllInterrupts();
430 #ifdef _ARM_DS5_C_S32ZE_
431 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
432 #endif
433 }
434 msr_UART_EXCLUSIVE_AREA_01[u32CoreId] = msr;
435 }
436 reentry_guard_UART_EXCLUSIVE_AREA_01[u32CoreId]++;
437 }
438
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_01(void)439 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_01(void)
440 {
441 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
442
443 reentry_guard_UART_EXCLUSIVE_AREA_01[u32CoreId]--;
444 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
445 {
446 OsIf_ResumeAllInterrupts();
447 #ifdef _ARM_DS5_C_S32ZE_
448 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
449 #endif
450 }
451 }
452
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_02(void)453 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_02(void)
454 {
455 uint32 msr;
456 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
457
458 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_02[u32CoreId])
459 {
460 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
461 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
462 #else
463 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
464 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
465 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
466 {
467 OsIf_SuspendAllInterrupts();
468 #ifdef _ARM_DS5_C_S32ZE_
469 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
470 #endif
471 }
472 msr_UART_EXCLUSIVE_AREA_02[u32CoreId] = msr;
473 }
474 reentry_guard_UART_EXCLUSIVE_AREA_02[u32CoreId]++;
475 }
476
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_02(void)477 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_02(void)
478 {
479 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
480
481 reentry_guard_UART_EXCLUSIVE_AREA_02[u32CoreId]--;
482 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
483 {
484 OsIf_ResumeAllInterrupts();
485 #ifdef _ARM_DS5_C_S32ZE_
486 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
487 #endif
488 }
489 }
490
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_03(void)491 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_03(void)
492 {
493 uint32 msr;
494 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
495
496 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_03[u32CoreId])
497 {
498 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
499 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
500 #else
501 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
502 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
503 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
504 {
505 OsIf_SuspendAllInterrupts();
506 #ifdef _ARM_DS5_C_S32ZE_
507 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
508 #endif
509 }
510 msr_UART_EXCLUSIVE_AREA_03[u32CoreId] = msr;
511 }
512 reentry_guard_UART_EXCLUSIVE_AREA_03[u32CoreId]++;
513 }
514
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_03(void)515 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_03(void)
516 {
517 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
518
519 reentry_guard_UART_EXCLUSIVE_AREA_03[u32CoreId]--;
520 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
521 {
522 OsIf_ResumeAllInterrupts();
523 #ifdef _ARM_DS5_C_S32ZE_
524 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
525 #endif
526 }
527 }
528
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_04(void)529 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_04(void)
530 {
531 uint32 msr;
532 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
533
534 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_04[u32CoreId])
535 {
536 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
537 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
538 #else
539 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
540 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
541 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
542 {
543 OsIf_SuspendAllInterrupts();
544 #ifdef _ARM_DS5_C_S32ZE_
545 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
546 #endif
547 }
548 msr_UART_EXCLUSIVE_AREA_04[u32CoreId] = msr;
549 }
550 reentry_guard_UART_EXCLUSIVE_AREA_04[u32CoreId]++;
551 }
552
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_04(void)553 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_04(void)
554 {
555 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
556
557 reentry_guard_UART_EXCLUSIVE_AREA_04[u32CoreId]--;
558 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
559 {
560 OsIf_ResumeAllInterrupts();
561 #ifdef _ARM_DS5_C_S32ZE_
562 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
563 #endif
564 }
565 }
566
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_05(void)567 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_05(void)
568 {
569 uint32 msr;
570 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
571
572 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_05[u32CoreId])
573 {
574 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
575 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
576 #else
577 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
578 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
579 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
580 {
581 OsIf_SuspendAllInterrupts();
582 #ifdef _ARM_DS5_C_S32ZE_
583 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
584 #endif
585 }
586 msr_UART_EXCLUSIVE_AREA_05[u32CoreId] = msr;
587 }
588 reentry_guard_UART_EXCLUSIVE_AREA_05[u32CoreId]++;
589 }
590
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_05(void)591 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_05(void)
592 {
593 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
594
595 reentry_guard_UART_EXCLUSIVE_AREA_05[u32CoreId]--;
596 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
597 {
598 OsIf_ResumeAllInterrupts();
599 #ifdef _ARM_DS5_C_S32ZE_
600 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
601 #endif
602 }
603 }
604
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_06(void)605 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_06(void)
606 {
607 uint32 msr;
608 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
609
610 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_06[u32CoreId])
611 {
612 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
613 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
614 #else
615 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
616 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
617 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
618 {
619 OsIf_SuspendAllInterrupts();
620 #ifdef _ARM_DS5_C_S32ZE_
621 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
622 #endif
623 }
624 msr_UART_EXCLUSIVE_AREA_06[u32CoreId] = msr;
625 }
626 reentry_guard_UART_EXCLUSIVE_AREA_06[u32CoreId]++;
627 }
628
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_06(void)629 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_06(void)
630 {
631 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
632
633 reentry_guard_UART_EXCLUSIVE_AREA_06[u32CoreId]--;
634 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
635 {
636 OsIf_ResumeAllInterrupts();
637 #ifdef _ARM_DS5_C_S32ZE_
638 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
639 #endif
640 }
641 }
642
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_07(void)643 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_07(void)
644 {
645 uint32 msr;
646 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
647
648 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_07[u32CoreId])
649 {
650 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
651 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
652 #else
653 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
654 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
655 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
656 {
657 OsIf_SuspendAllInterrupts();
658 #ifdef _ARM_DS5_C_S32ZE_
659 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
660 #endif
661 }
662 msr_UART_EXCLUSIVE_AREA_07[u32CoreId] = msr;
663 }
664 reentry_guard_UART_EXCLUSIVE_AREA_07[u32CoreId]++;
665 }
666
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_07(void)667 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_07(void)
668 {
669 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
670
671 reentry_guard_UART_EXCLUSIVE_AREA_07[u32CoreId]--;
672 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
673 {
674 OsIf_ResumeAllInterrupts();
675 #ifdef _ARM_DS5_C_S32ZE_
676 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
677 #endif
678 }
679 }
680
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_08(void)681 void SchM_Enter_Uart_UART_EXCLUSIVE_AREA_08(void)
682 {
683 uint32 msr;
684 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
685
686 if(0UL == reentry_guard_UART_EXCLUSIVE_AREA_08[u32CoreId])
687 {
688 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
689 msr = OsIf_Trusted_Call_Return(Uart_schm_read_msr);
690 #else
691 msr = Uart_schm_read_msr(); /*read MSR (to store interrupts state)*/
692 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
693 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
694 {
695 OsIf_SuspendAllInterrupts();
696 #ifdef _ARM_DS5_C_S32ZE_
697 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
698 #endif
699 }
700 msr_UART_EXCLUSIVE_AREA_08[u32CoreId] = msr;
701 }
702 reentry_guard_UART_EXCLUSIVE_AREA_08[u32CoreId]++;
703 }
704
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_08(void)705 void SchM_Exit_Uart_UART_EXCLUSIVE_AREA_08(void)
706 {
707 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
708
709 reentry_guard_UART_EXCLUSIVE_AREA_08[u32CoreId]--;
710 if ((ISR_ON(msr_UART_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_UART_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
711 {
712 OsIf_ResumeAllInterrupts();
713 #ifdef _ARM_DS5_C_S32ZE_
714 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
715 #endif
716 }
717 }
718
719
720 #ifdef MCAL_TESTING_ENVIRONMENT
721 /**
722 @brief This function checks that all entered exclusive areas were also exited.
723 @details This function checks that all entered exclusive areas were also exited. The check
724 is done by verifying that all reentry_guard_* static variables are back to the
725 zero value.
726
727 @param[in] void No input parameters
728 @return void This function does not return a value. Test asserts are used instead.
729
730 @pre None
731 @post None
732
733 @remarks Covers
734 @remarks Implements
735 */
SchM_Check_uart(void)736 void SchM_Check_uart(void)
737 {
738 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
739
740 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_00[u32CoreId]);
741 reentry_guard_UART_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_00 for the next test in the suite*/
742
743 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_01[u32CoreId]);
744 reentry_guard_UART_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_01 for the next test in the suite*/
745
746 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_02[u32CoreId]);
747 reentry_guard_UART_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_02 for the next test in the suite*/
748
749 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_03[u32CoreId]);
750 reentry_guard_UART_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_03 for the next test in the suite*/
751
752 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_04[u32CoreId]);
753 reentry_guard_UART_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_04 for the next test in the suite*/
754
755 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_05[u32CoreId]);
756 reentry_guard_UART_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_05 for the next test in the suite*/
757
758 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_06[u32CoreId]);
759 reentry_guard_UART_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_06 for the next test in the suite*/
760
761 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_07[u32CoreId]);
762 reentry_guard_UART_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_07 for the next test in the suite*/
763
764 EU_ASSERT(0UL == reentry_guard_UART_EXCLUSIVE_AREA_08[u32CoreId]);
765 reentry_guard_UART_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_UART_EXCLUSIVE_AREA_08 for the next test in the suite*/
766
767
768 }
769 #endif /*MCAL_TESTING_ENVIRONMENT*/
770
771 #define RTE_STOP_SEC_CODE
772 #include "Rte_MemMap.h"
773
774 #ifdef __cplusplus
775 }
776 #endif
777
778 /** @} */
779
