1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Pwm.c
9 * @version 3.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Pwm.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_PWM_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_PWM_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_PWM_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_PWM_SW_MAJOR_VERSION_C 3
44 #define SCHM_PWM_SW_MINOR_VERSION_C 0
45 #define SCHM_PWM_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_00) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_01) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_02) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_03) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_04) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_05) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_06) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_07) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_08) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_09) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_10) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_11) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_12) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_13) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_14) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_15) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_16) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_17) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_18) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_19) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_19) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_20) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_20) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
144 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_21) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
145 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_21) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
146 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_22) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
147 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_22) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
148 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_23) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
149 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_23) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
150 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_24) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
151 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_24) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
152 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_25) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
153 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_25) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
154 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_26) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
155 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_26) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
156 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_27) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
157 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_27) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
158 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_28) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
159 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_28) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
160 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_29) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
161 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_29) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
162 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_30) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
163 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_30) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
164 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_31) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
165 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_31) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
166 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_32) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
167 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_32) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
168 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_33) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
169 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_33) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
170 VAR_SEC_NOCACHE(msr_PWM_EXCLUSIVE_AREA_34) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_34[NUMBER_OF_CORES];
171 VAR_SEC_NOCACHE(reentry_guard_PWM_EXCLUSIVE_AREA_34) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_34[NUMBER_OF_CORES];
172
173 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
174 #include "Rte_MemMap.h"
175 /*==================================================================================================
176 * GLOBAL CONSTANTS
177 ==================================================================================================*/
178
179
180 /*==================================================================================================
181 * GLOBAL VARIABLES
182 ==================================================================================================*/
183
184 /*==================================================================================================
185 * LOCAL FUNCTION PROTOTYPES
186 ==================================================================================================*/
187
188 #ifndef _COSMIC_C_S32K3XX_
189 /*================================================================================================*/
190 /**
191 * @brief This function returns the MSR register value (32 bits).
192 * @details This function returns the MSR register value (32 bits).
193 *
194 * @param[in] void No input parameters
195 * @return uint32 msr This function returns the MSR register value (32 bits).
196 *
197 * @pre None
198 * @post None
199 *
200 */
201 uint32 Pwm_schm_read_msr(void);
202 #endif /*ifndef _COSMIC_C_S32K3XX_*/
203 /*==================================================================================================
204 * LOCAL FUNCTIONS
205 ==================================================================================================*/
206 #define RTE_START_SEC_CODE
207 #include "Rte_MemMap.h"
208
209 #if (defined(_GREENHILLS_C_S32K3XX_) || defined(_CODEWARRIOR_C_S32K3XX_))
210 /*================================================================================================*/
211 /**
212 * @brief This macro returns the MSR register value (32 bits).
213 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
214 *
215 * @pre None
216 * @post None
217 *
218 */
219 #ifdef MCAL_PLATFORM_ARM
220 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Pwm_schm_read_msr(void)221 ASM_KEYWORD uint32 Pwm_schm_read_msr(void)
222 {
223 mrs x0, S3_3_c4_c2_1
224 }
225 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Pwm_schm_read_msr(void)226 ASM_KEYWORD uint32 Pwm_schm_read_msr(void)
227 {
228 mrs r0, CPSR
229 }
230 #else
Pwm_schm_read_msr(void)231 ASM_KEYWORD uint32 Pwm_schm_read_msr(void)
232 {
233 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
234 mrs r0, BASEPRI
235 #else
236 mrs r0, PRIMASK
237 #endif
238 }
239 #endif
240 #else
241 #ifdef MCAL_PLATFORM_S12
Pwm_schm_read_msr(void)242 ASM_KEYWORD uint32 Pwm_schm_read_msr(void)
243 {
244 tfr ccr, d6
245 }
246 #else
Pwm_schm_read_msr(void)247 ASM_KEYWORD uint32 Pwm_schm_read_msr(void)
248 {
249 mfmsr r3
250 }
251 #endif
252 #endif
253 #endif /*#ifdef GHS||CW*/
254
255 #ifdef _DIABDATA_C_S32K3XX_
256 /**
257 * @brief This function returns the MSR register value (32 bits).
258 * @details This function returns the MSR register value (32 bits).
259 *
260 * @param[in] void No input parameters
261 * @return uint32 msr This function returns the MSR register value (32 bits).
262 *
263 * @pre None
264 * @post None
265 *
266 */
267 #ifdef MCAL_PLATFORM_ARM
Pwm_schm_read_msr(void)268 uint32 Pwm_schm_read_msr(void)
269 {
270 register uint32 reg_tmp;
271 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
272 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
273 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
274 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
275 #else
276 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
277 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
278 #else
279 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
280 #endif
281 #endif
282 return (uint32)reg_tmp;
283 }
284 #else
Pwm_schm_read_msr(void)285 ASM_KEYWORD uint32 Pwm_schm_read_msr(void)
286 {
287 mfmsr r3
288 }
289 #endif /* MCAL_PLATFORM_ARM */
290
291 #endif /* _DIABDATA_C_S32K3XX_*/
292
293 #ifdef _COSMIC_C_S32K3XX_
294 /*================================================================================================*/
295 /**
296 * @brief This function returns the MSR register value (32 bits).
297 * @details This function returns the MSR register value (32 bits).
298 *
299 * @param[in] void No input parameters
300 * @return uint32 msr This function returns the MSR register value (32 bits).
301 *
302 * @pre None
303 * @post None
304 *
305 */
306
307 #ifdef MCAL_PLATFORM_S12
308 #define Pwm_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
309 #else
310 #define Pwm_schm_read_msr() ASM_KEYWORD("mfmsr r3")
311 #endif
312
313 #endif /*Cosmic compiler only*/
314
315
316 #ifdef _HITECH_C_S32K3XX_
317 /*================================================================================================*/
318 /**
319 * @brief This function returns the MSR register value (32 bits).
320 * @details This function returns the MSR register value (32 bits).
321 *
322 * @param[in] void No input parameters
323 * @return uint32 msr This function returns the MSR register value (32 bits).
324 *
325 * @pre None
326 * @post None
327 *
328 */
Pwm_schm_read_msr(void)329 uint32 Pwm_schm_read_msr(void)
330 {
331 uint32 result;
332 __asm volatile("mfmsr %0" : "=r" (result) :);
333 return result;
334 }
335
336 #endif /*HighTec compiler only*/
337 /*================================================================================================*/
338 #ifdef _LINARO_C_S32K3XX_
339 /**
340 * @brief This function returns the MSR register value (32 bits).
341 * @details This function returns the MSR register value (32 bits).
342 *
343 * @param[in] void No input parameters
344 * @return uint32 msr This function returns the MSR register value (32 bits).
345 *
346 * @pre None
347 * @post None
348 *
349 */
Pwm_schm_read_msr(void)350 uint32 Pwm_schm_read_msr(void)
351 {
352 register uint32 reg_tmp;
353 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
354 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
355 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
356 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
357 #else
358 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
359 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
360 #else
361 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
362 #endif
363 #endif
364 return (uint32)reg_tmp;
365 }
366 #endif /* _LINARO_C_S32K3XX_*/
367 /*================================================================================================*/
368
369 #ifdef _ARM_DS5_C_S32K3XX_
370 /**
371 * @brief This function returns the MSR register value (32 bits).
372 * @details This function returns the MSR register value (32 bits).
373 *
374 * @param[in] void No input parameters
375 * @return uint32 msr This function returns the MSR register value (32 bits).
376 *
377 * @pre None
378 * @post None
379 *
380 */
Pwm_schm_read_msr(void)381 uint32 Pwm_schm_read_msr(void)
382 {
383 register uint32 reg_tmp;
384 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
385 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
386 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
387 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
388 #else
389 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
390 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
391 #else
392 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
393 #endif
394 #endif
395 return (uint32)reg_tmp;
396 }
397 #endif /* _ARM_DS5_C_S32K3XX_ */
398
399 #ifdef _IAR_C_S32K3XX_
400 /**
401 * @brief This function returns the MSR register value (32 bits).
402 * @details This function returns the MSR register value (32 bits).
403 *
404 * @param[in] void No input parameters
405 * @return uint32 msr This function returns the MSR register value (32 bits).
406 *
407 * @pre None
408 * @post None
409 *
410 */
Pwm_schm_read_msr(void)411 uint32 Pwm_schm_read_msr(void)
412 {
413 register uint32 reg_tmp;
414
415 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
416 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
417 #else
418 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
419 #endif
420
421 return (uint32)reg_tmp;
422 }
423 #endif /* _IAR_C_S32K3XX_ */
424
425 #define RTE_STOP_SEC_CODE
426 #include "Rte_MemMap.h"
427
428 /*==================================================================================================
429 * GLOBAL FUNCTIONS
430 ==================================================================================================*/
431 #define RTE_START_SEC_CODE
432 #include "Rte_MemMap.h"
433
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_00(void)434 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_00(void)
435 {
436 uint32 msr;
437 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
438
439 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_00[u32CoreId])
440 {
441 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
442 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
443 #else
444 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
445 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
446 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
447 {
448 OsIf_SuspendAllInterrupts();
449 #ifdef _ARM_DS5_C_S32K3XX_
450 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
451 #endif
452 }
453 msr_PWM_EXCLUSIVE_AREA_00[u32CoreId] = msr;
454 }
455 reentry_guard_PWM_EXCLUSIVE_AREA_00[u32CoreId]++;
456 }
457
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_00(void)458 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_00(void)
459 {
460 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
461
462 reentry_guard_PWM_EXCLUSIVE_AREA_00[u32CoreId]--;
463 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
464 {
465 OsIf_ResumeAllInterrupts();
466 #ifdef _ARM_DS5_C_S32K3XX_
467 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
468 #endif
469 }
470 }
471
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_01(void)472 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_01(void)
473 {
474 uint32 msr;
475 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
476
477 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_01[u32CoreId])
478 {
479 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
480 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
481 #else
482 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
483 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
484 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
485 {
486 OsIf_SuspendAllInterrupts();
487 #ifdef _ARM_DS5_C_S32K3XX_
488 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
489 #endif
490 }
491 msr_PWM_EXCLUSIVE_AREA_01[u32CoreId] = msr;
492 }
493 reentry_guard_PWM_EXCLUSIVE_AREA_01[u32CoreId]++;
494 }
495
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_01(void)496 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_01(void)
497 {
498 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
499
500 reentry_guard_PWM_EXCLUSIVE_AREA_01[u32CoreId]--;
501 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
502 {
503 OsIf_ResumeAllInterrupts();
504 #ifdef _ARM_DS5_C_S32K3XX_
505 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
506 #endif
507 }
508 }
509
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_02(void)510 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_02(void)
511 {
512 uint32 msr;
513 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
514
515 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_02[u32CoreId])
516 {
517 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
518 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
519 #else
520 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
521 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
522 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
523 {
524 OsIf_SuspendAllInterrupts();
525 #ifdef _ARM_DS5_C_S32K3XX_
526 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
527 #endif
528 }
529 msr_PWM_EXCLUSIVE_AREA_02[u32CoreId] = msr;
530 }
531 reentry_guard_PWM_EXCLUSIVE_AREA_02[u32CoreId]++;
532 }
533
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_02(void)534 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_02(void)
535 {
536 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
537
538 reentry_guard_PWM_EXCLUSIVE_AREA_02[u32CoreId]--;
539 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
540 {
541 OsIf_ResumeAllInterrupts();
542 #ifdef _ARM_DS5_C_S32K3XX_
543 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
544 #endif
545 }
546 }
547
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_03(void)548 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_03(void)
549 {
550 uint32 msr;
551 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
552
553 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_03[u32CoreId])
554 {
555 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
556 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
557 #else
558 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
559 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
560 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
561 {
562 OsIf_SuspendAllInterrupts();
563 #ifdef _ARM_DS5_C_S32K3XX_
564 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
565 #endif
566 }
567 msr_PWM_EXCLUSIVE_AREA_03[u32CoreId] = msr;
568 }
569 reentry_guard_PWM_EXCLUSIVE_AREA_03[u32CoreId]++;
570 }
571
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_03(void)572 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_03(void)
573 {
574 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
575
576 reentry_guard_PWM_EXCLUSIVE_AREA_03[u32CoreId]--;
577 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
578 {
579 OsIf_ResumeAllInterrupts();
580 #ifdef _ARM_DS5_C_S32K3XX_
581 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
582 #endif
583 }
584 }
585
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_04(void)586 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_04(void)
587 {
588 uint32 msr;
589 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
590
591 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_04[u32CoreId])
592 {
593 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
594 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
595 #else
596 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
597 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
598 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
599 {
600 OsIf_SuspendAllInterrupts();
601 #ifdef _ARM_DS5_C_S32K3XX_
602 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
603 #endif
604 }
605 msr_PWM_EXCLUSIVE_AREA_04[u32CoreId] = msr;
606 }
607 reentry_guard_PWM_EXCLUSIVE_AREA_04[u32CoreId]++;
608 }
609
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_04(void)610 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_04(void)
611 {
612 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
613
614 reentry_guard_PWM_EXCLUSIVE_AREA_04[u32CoreId]--;
615 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
616 {
617 OsIf_ResumeAllInterrupts();
618 #ifdef _ARM_DS5_C_S32K3XX_
619 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
620 #endif
621 }
622 }
623
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_05(void)624 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_05(void)
625 {
626 uint32 msr;
627 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
628
629 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_05[u32CoreId])
630 {
631 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
632 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
633 #else
634 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
635 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
636 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
637 {
638 OsIf_SuspendAllInterrupts();
639 #ifdef _ARM_DS5_C_S32K3XX_
640 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
641 #endif
642 }
643 msr_PWM_EXCLUSIVE_AREA_05[u32CoreId] = msr;
644 }
645 reentry_guard_PWM_EXCLUSIVE_AREA_05[u32CoreId]++;
646 }
647
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_05(void)648 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_05(void)
649 {
650 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
651
652 reentry_guard_PWM_EXCLUSIVE_AREA_05[u32CoreId]--;
653 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
654 {
655 OsIf_ResumeAllInterrupts();
656 #ifdef _ARM_DS5_C_S32K3XX_
657 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
658 #endif
659 }
660 }
661
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_06(void)662 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_06(void)
663 {
664 uint32 msr;
665 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
666
667 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_06[u32CoreId])
668 {
669 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
670 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
671 #else
672 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
673 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
674 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
675 {
676 OsIf_SuspendAllInterrupts();
677 #ifdef _ARM_DS5_C_S32K3XX_
678 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
679 #endif
680 }
681 msr_PWM_EXCLUSIVE_AREA_06[u32CoreId] = msr;
682 }
683 reentry_guard_PWM_EXCLUSIVE_AREA_06[u32CoreId]++;
684 }
685
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_06(void)686 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_06(void)
687 {
688 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
689
690 reentry_guard_PWM_EXCLUSIVE_AREA_06[u32CoreId]--;
691 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
692 {
693 OsIf_ResumeAllInterrupts();
694 #ifdef _ARM_DS5_C_S32K3XX_
695 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
696 #endif
697 }
698 }
699
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_07(void)700 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_07(void)
701 {
702 uint32 msr;
703 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
704
705 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_07[u32CoreId])
706 {
707 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
708 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
709 #else
710 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
711 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
712 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
713 {
714 OsIf_SuspendAllInterrupts();
715 #ifdef _ARM_DS5_C_S32K3XX_
716 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
717 #endif
718 }
719 msr_PWM_EXCLUSIVE_AREA_07[u32CoreId] = msr;
720 }
721 reentry_guard_PWM_EXCLUSIVE_AREA_07[u32CoreId]++;
722 }
723
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_07(void)724 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_07(void)
725 {
726 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
727
728 reentry_guard_PWM_EXCLUSIVE_AREA_07[u32CoreId]--;
729 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
730 {
731 OsIf_ResumeAllInterrupts();
732 #ifdef _ARM_DS5_C_S32K3XX_
733 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
734 #endif
735 }
736 }
737
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_08(void)738 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_08(void)
739 {
740 uint32 msr;
741 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
742
743 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_08[u32CoreId])
744 {
745 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
746 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
747 #else
748 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
749 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
750 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
751 {
752 OsIf_SuspendAllInterrupts();
753 #ifdef _ARM_DS5_C_S32K3XX_
754 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
755 #endif
756 }
757 msr_PWM_EXCLUSIVE_AREA_08[u32CoreId] = msr;
758 }
759 reentry_guard_PWM_EXCLUSIVE_AREA_08[u32CoreId]++;
760 }
761
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_08(void)762 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_08(void)
763 {
764 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
765
766 reentry_guard_PWM_EXCLUSIVE_AREA_08[u32CoreId]--;
767 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
768 {
769 OsIf_ResumeAllInterrupts();
770 #ifdef _ARM_DS5_C_S32K3XX_
771 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
772 #endif
773 }
774 }
775
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_09(void)776 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_09(void)
777 {
778 uint32 msr;
779 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
780
781 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_09[u32CoreId])
782 {
783 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
784 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
785 #else
786 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
787 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
788 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
789 {
790 OsIf_SuspendAllInterrupts();
791 #ifdef _ARM_DS5_C_S32K3XX_
792 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
793 #endif
794 }
795 msr_PWM_EXCLUSIVE_AREA_09[u32CoreId] = msr;
796 }
797 reentry_guard_PWM_EXCLUSIVE_AREA_09[u32CoreId]++;
798 }
799
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_09(void)800 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_09(void)
801 {
802 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
803
804 reentry_guard_PWM_EXCLUSIVE_AREA_09[u32CoreId]--;
805 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
806 {
807 OsIf_ResumeAllInterrupts();
808 #ifdef _ARM_DS5_C_S32K3XX_
809 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
810 #endif
811 }
812 }
813
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_10(void)814 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_10(void)
815 {
816 uint32 msr;
817 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
818
819 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_10[u32CoreId])
820 {
821 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
822 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
823 #else
824 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
825 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
826 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
827 {
828 OsIf_SuspendAllInterrupts();
829 #ifdef _ARM_DS5_C_S32K3XX_
830 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
831 #endif
832 }
833 msr_PWM_EXCLUSIVE_AREA_10[u32CoreId] = msr;
834 }
835 reentry_guard_PWM_EXCLUSIVE_AREA_10[u32CoreId]++;
836 }
837
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_10(void)838 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_10(void)
839 {
840 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
841
842 reentry_guard_PWM_EXCLUSIVE_AREA_10[u32CoreId]--;
843 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
844 {
845 OsIf_ResumeAllInterrupts();
846 #ifdef _ARM_DS5_C_S32K3XX_
847 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
848 #endif
849 }
850 }
851
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_11(void)852 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_11(void)
853 {
854 uint32 msr;
855 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
856
857 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_11[u32CoreId])
858 {
859 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
860 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
861 #else
862 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
863 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
864 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
865 {
866 OsIf_SuspendAllInterrupts();
867 #ifdef _ARM_DS5_C_S32K3XX_
868 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
869 #endif
870 }
871 msr_PWM_EXCLUSIVE_AREA_11[u32CoreId] = msr;
872 }
873 reentry_guard_PWM_EXCLUSIVE_AREA_11[u32CoreId]++;
874 }
875
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_11(void)876 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_11(void)
877 {
878 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
879
880 reentry_guard_PWM_EXCLUSIVE_AREA_11[u32CoreId]--;
881 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
882 {
883 OsIf_ResumeAllInterrupts();
884 #ifdef _ARM_DS5_C_S32K3XX_
885 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
886 #endif
887 }
888 }
889
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_12(void)890 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_12(void)
891 {
892 uint32 msr;
893 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
894
895 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_12[u32CoreId])
896 {
897 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
898 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
899 #else
900 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
901 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
902 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
903 {
904 OsIf_SuspendAllInterrupts();
905 #ifdef _ARM_DS5_C_S32K3XX_
906 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
907 #endif
908 }
909 msr_PWM_EXCLUSIVE_AREA_12[u32CoreId] = msr;
910 }
911 reentry_guard_PWM_EXCLUSIVE_AREA_12[u32CoreId]++;
912 }
913
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_12(void)914 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_12(void)
915 {
916 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
917
918 reentry_guard_PWM_EXCLUSIVE_AREA_12[u32CoreId]--;
919 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
920 {
921 OsIf_ResumeAllInterrupts();
922 #ifdef _ARM_DS5_C_S32K3XX_
923 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
924 #endif
925 }
926 }
927
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_13(void)928 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_13(void)
929 {
930 uint32 msr;
931 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
932
933 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_13[u32CoreId])
934 {
935 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
936 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
937 #else
938 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
939 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
940 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
941 {
942 OsIf_SuspendAllInterrupts();
943 #ifdef _ARM_DS5_C_S32K3XX_
944 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
945 #endif
946 }
947 msr_PWM_EXCLUSIVE_AREA_13[u32CoreId] = msr;
948 }
949 reentry_guard_PWM_EXCLUSIVE_AREA_13[u32CoreId]++;
950 }
951
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_13(void)952 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_13(void)
953 {
954 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
955
956 reentry_guard_PWM_EXCLUSIVE_AREA_13[u32CoreId]--;
957 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
958 {
959 OsIf_ResumeAllInterrupts();
960 #ifdef _ARM_DS5_C_S32K3XX_
961 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
962 #endif
963 }
964 }
965
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_14(void)966 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_14(void)
967 {
968 uint32 msr;
969 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
970
971 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_14[u32CoreId])
972 {
973 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
974 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
975 #else
976 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
977 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
978 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
979 {
980 OsIf_SuspendAllInterrupts();
981 #ifdef _ARM_DS5_C_S32K3XX_
982 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
983 #endif
984 }
985 msr_PWM_EXCLUSIVE_AREA_14[u32CoreId] = msr;
986 }
987 reentry_guard_PWM_EXCLUSIVE_AREA_14[u32CoreId]++;
988 }
989
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_14(void)990 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_14(void)
991 {
992 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
993
994 reentry_guard_PWM_EXCLUSIVE_AREA_14[u32CoreId]--;
995 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
996 {
997 OsIf_ResumeAllInterrupts();
998 #ifdef _ARM_DS5_C_S32K3XX_
999 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1000 #endif
1001 }
1002 }
1003
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_15(void)1004 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_15(void)
1005 {
1006 uint32 msr;
1007 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1008
1009 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_15[u32CoreId])
1010 {
1011 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1012 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1013 #else
1014 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1015 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1016 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1017 {
1018 OsIf_SuspendAllInterrupts();
1019 #ifdef _ARM_DS5_C_S32K3XX_
1020 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1021 #endif
1022 }
1023 msr_PWM_EXCLUSIVE_AREA_15[u32CoreId] = msr;
1024 }
1025 reentry_guard_PWM_EXCLUSIVE_AREA_15[u32CoreId]++;
1026 }
1027
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_15(void)1028 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_15(void)
1029 {
1030 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1031
1032 reentry_guard_PWM_EXCLUSIVE_AREA_15[u32CoreId]--;
1033 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
1034 {
1035 OsIf_ResumeAllInterrupts();
1036 #ifdef _ARM_DS5_C_S32K3XX_
1037 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1038 #endif
1039 }
1040 }
1041
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_16(void)1042 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_16(void)
1043 {
1044 uint32 msr;
1045 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1046
1047 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_16[u32CoreId])
1048 {
1049 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1050 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1051 #else
1052 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1053 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1054 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1055 {
1056 OsIf_SuspendAllInterrupts();
1057 #ifdef _ARM_DS5_C_S32K3XX_
1058 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1059 #endif
1060 }
1061 msr_PWM_EXCLUSIVE_AREA_16[u32CoreId] = msr;
1062 }
1063 reentry_guard_PWM_EXCLUSIVE_AREA_16[u32CoreId]++;
1064 }
1065
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_16(void)1066 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_16(void)
1067 {
1068 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1069
1070 reentry_guard_PWM_EXCLUSIVE_AREA_16[u32CoreId]--;
1071 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
1072 {
1073 OsIf_ResumeAllInterrupts();
1074 #ifdef _ARM_DS5_C_S32K3XX_
1075 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1076 #endif
1077 }
1078 }
1079
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_17(void)1080 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_17(void)
1081 {
1082 uint32 msr;
1083 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1084
1085 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_17[u32CoreId])
1086 {
1087 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1088 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1089 #else
1090 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1091 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1092 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1093 {
1094 OsIf_SuspendAllInterrupts();
1095 #ifdef _ARM_DS5_C_S32K3XX_
1096 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1097 #endif
1098 }
1099 msr_PWM_EXCLUSIVE_AREA_17[u32CoreId] = msr;
1100 }
1101 reentry_guard_PWM_EXCLUSIVE_AREA_17[u32CoreId]++;
1102 }
1103
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_17(void)1104 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_17(void)
1105 {
1106 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1107
1108 reentry_guard_PWM_EXCLUSIVE_AREA_17[u32CoreId]--;
1109 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
1110 {
1111 OsIf_ResumeAllInterrupts();
1112 #ifdef _ARM_DS5_C_S32K3XX_
1113 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1114 #endif
1115 }
1116 }
1117
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_18(void)1118 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_18(void)
1119 {
1120 uint32 msr;
1121 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1122
1123 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_18[u32CoreId])
1124 {
1125 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1126 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1127 #else
1128 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1129 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1130 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1131 {
1132 OsIf_SuspendAllInterrupts();
1133 #ifdef _ARM_DS5_C_S32K3XX_
1134 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1135 #endif
1136 }
1137 msr_PWM_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1138 }
1139 reentry_guard_PWM_EXCLUSIVE_AREA_18[u32CoreId]++;
1140 }
1141
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_18(void)1142 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_18(void)
1143 {
1144 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1145
1146 reentry_guard_PWM_EXCLUSIVE_AREA_18[u32CoreId]--;
1147 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1148 {
1149 OsIf_ResumeAllInterrupts();
1150 #ifdef _ARM_DS5_C_S32K3XX_
1151 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1152 #endif
1153 }
1154 }
1155
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_19(void)1156 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_19(void)
1157 {
1158 uint32 msr;
1159 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1160
1161 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_19[u32CoreId])
1162 {
1163 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1164 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1165 #else
1166 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1167 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1168 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1169 {
1170 OsIf_SuspendAllInterrupts();
1171 #ifdef _ARM_DS5_C_S32K3XX_
1172 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1173 #endif
1174 }
1175 msr_PWM_EXCLUSIVE_AREA_19[u32CoreId] = msr;
1176 }
1177 reentry_guard_PWM_EXCLUSIVE_AREA_19[u32CoreId]++;
1178 }
1179
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_19(void)1180 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_19(void)
1181 {
1182 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1183
1184 reentry_guard_PWM_EXCLUSIVE_AREA_19[u32CoreId]--;
1185 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_19[u32CoreId])) /*if interrupts were enabled*/
1186 {
1187 OsIf_ResumeAllInterrupts();
1188 #ifdef _ARM_DS5_C_S32K3XX_
1189 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1190 #endif
1191 }
1192 }
1193
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_20(void)1194 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_20(void)
1195 {
1196 uint32 msr;
1197 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1198
1199 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_20[u32CoreId])
1200 {
1201 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1202 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1203 #else
1204 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1205 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1206 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1207 {
1208 OsIf_SuspendAllInterrupts();
1209 #ifdef _ARM_DS5_C_S32K3XX_
1210 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1211 #endif
1212 }
1213 msr_PWM_EXCLUSIVE_AREA_20[u32CoreId] = msr;
1214 }
1215 reentry_guard_PWM_EXCLUSIVE_AREA_20[u32CoreId]++;
1216 }
1217
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_20(void)1218 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_20(void)
1219 {
1220 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1221
1222 reentry_guard_PWM_EXCLUSIVE_AREA_20[u32CoreId]--;
1223 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
1224 {
1225 OsIf_ResumeAllInterrupts();
1226 #ifdef _ARM_DS5_C_S32K3XX_
1227 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1228 #endif
1229 }
1230 }
1231
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_21(void)1232 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_21(void)
1233 {
1234 uint32 msr;
1235 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1236
1237 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_21[u32CoreId])
1238 {
1239 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1240 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1241 #else
1242 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1243 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1244 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1245 {
1246 OsIf_SuspendAllInterrupts();
1247 #ifdef _ARM_DS5_C_S32K3XX_
1248 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1249 #endif
1250 }
1251 msr_PWM_EXCLUSIVE_AREA_21[u32CoreId] = msr;
1252 }
1253 reentry_guard_PWM_EXCLUSIVE_AREA_21[u32CoreId]++;
1254 }
1255
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_21(void)1256 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_21(void)
1257 {
1258 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1259
1260 reentry_guard_PWM_EXCLUSIVE_AREA_21[u32CoreId]--;
1261 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
1262 {
1263 OsIf_ResumeAllInterrupts();
1264 #ifdef _ARM_DS5_C_S32K3XX_
1265 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1266 #endif
1267 }
1268 }
1269
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_22(void)1270 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_22(void)
1271 {
1272 uint32 msr;
1273 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1274
1275 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_22[u32CoreId])
1276 {
1277 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1278 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1279 #else
1280 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1281 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1282 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1283 {
1284 OsIf_SuspendAllInterrupts();
1285 #ifdef _ARM_DS5_C_S32K3XX_
1286 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1287 #endif
1288 }
1289 msr_PWM_EXCLUSIVE_AREA_22[u32CoreId] = msr;
1290 }
1291 reentry_guard_PWM_EXCLUSIVE_AREA_22[u32CoreId]++;
1292 }
1293
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_22(void)1294 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_22(void)
1295 {
1296 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1297
1298 reentry_guard_PWM_EXCLUSIVE_AREA_22[u32CoreId]--;
1299 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_22[u32CoreId])) /*if interrupts were enabled*/
1300 {
1301 OsIf_ResumeAllInterrupts();
1302 #ifdef _ARM_DS5_C_S32K3XX_
1303 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1304 #endif
1305 }
1306 }
1307
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_23(void)1308 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_23(void)
1309 {
1310 uint32 msr;
1311 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1312
1313 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_23[u32CoreId])
1314 {
1315 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1316 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1317 #else
1318 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1319 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1320 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1321 {
1322 OsIf_SuspendAllInterrupts();
1323 #ifdef _ARM_DS5_C_S32K3XX_
1324 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1325 #endif
1326 }
1327 msr_PWM_EXCLUSIVE_AREA_23[u32CoreId] = msr;
1328 }
1329 reentry_guard_PWM_EXCLUSIVE_AREA_23[u32CoreId]++;
1330 }
1331
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_23(void)1332 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_23(void)
1333 {
1334 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1335
1336 reentry_guard_PWM_EXCLUSIVE_AREA_23[u32CoreId]--;
1337 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_23[u32CoreId])) /*if interrupts were enabled*/
1338 {
1339 OsIf_ResumeAllInterrupts();
1340 #ifdef _ARM_DS5_C_S32K3XX_
1341 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1342 #endif
1343 }
1344 }
1345
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_24(void)1346 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_24(void)
1347 {
1348 uint32 msr;
1349 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1350
1351 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_24[u32CoreId])
1352 {
1353 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1354 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1355 #else
1356 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1357 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1358 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1359 {
1360 OsIf_SuspendAllInterrupts();
1361 #ifdef _ARM_DS5_C_S32K3XX_
1362 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1363 #endif
1364 }
1365 msr_PWM_EXCLUSIVE_AREA_24[u32CoreId] = msr;
1366 }
1367 reentry_guard_PWM_EXCLUSIVE_AREA_24[u32CoreId]++;
1368 }
1369
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_24(void)1370 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_24(void)
1371 {
1372 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1373
1374 reentry_guard_PWM_EXCLUSIVE_AREA_24[u32CoreId]--;
1375 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_24[u32CoreId])) /*if interrupts were enabled*/
1376 {
1377 OsIf_ResumeAllInterrupts();
1378 #ifdef _ARM_DS5_C_S32K3XX_
1379 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1380 #endif
1381 }
1382 }
1383
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_25(void)1384 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_25(void)
1385 {
1386 uint32 msr;
1387 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1388
1389 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_25[u32CoreId])
1390 {
1391 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1392 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1393 #else
1394 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1395 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1396 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1397 {
1398 OsIf_SuspendAllInterrupts();
1399 #ifdef _ARM_DS5_C_S32K3XX_
1400 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1401 #endif
1402 }
1403 msr_PWM_EXCLUSIVE_AREA_25[u32CoreId] = msr;
1404 }
1405 reentry_guard_PWM_EXCLUSIVE_AREA_25[u32CoreId]++;
1406 }
1407
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_25(void)1408 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_25(void)
1409 {
1410 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1411
1412 reentry_guard_PWM_EXCLUSIVE_AREA_25[u32CoreId]--;
1413 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_25[u32CoreId])) /*if interrupts were enabled*/
1414 {
1415 OsIf_ResumeAllInterrupts();
1416 #ifdef _ARM_DS5_C_S32K3XX_
1417 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1418 #endif
1419 }
1420 }
1421
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_26(void)1422 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_26(void)
1423 {
1424 uint32 msr;
1425 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1426
1427 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_26[u32CoreId])
1428 {
1429 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1430 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1431 #else
1432 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1433 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1434 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1435 {
1436 OsIf_SuspendAllInterrupts();
1437 #ifdef _ARM_DS5_C_S32K3XX_
1438 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1439 #endif
1440 }
1441 msr_PWM_EXCLUSIVE_AREA_26[u32CoreId] = msr;
1442 }
1443 reentry_guard_PWM_EXCLUSIVE_AREA_26[u32CoreId]++;
1444 }
1445
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_26(void)1446 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_26(void)
1447 {
1448 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1449
1450 reentry_guard_PWM_EXCLUSIVE_AREA_26[u32CoreId]--;
1451 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_26[u32CoreId])) /*if interrupts were enabled*/
1452 {
1453 OsIf_ResumeAllInterrupts();
1454 #ifdef _ARM_DS5_C_S32K3XX_
1455 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1456 #endif
1457 }
1458 }
1459
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_27(void)1460 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_27(void)
1461 {
1462 uint32 msr;
1463 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1464
1465 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_27[u32CoreId])
1466 {
1467 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1468 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1469 #else
1470 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1471 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1472 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1473 {
1474 OsIf_SuspendAllInterrupts();
1475 #ifdef _ARM_DS5_C_S32K3XX_
1476 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1477 #endif
1478 }
1479 msr_PWM_EXCLUSIVE_AREA_27[u32CoreId] = msr;
1480 }
1481 reentry_guard_PWM_EXCLUSIVE_AREA_27[u32CoreId]++;
1482 }
1483
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_27(void)1484 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_27(void)
1485 {
1486 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1487
1488 reentry_guard_PWM_EXCLUSIVE_AREA_27[u32CoreId]--;
1489 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_27[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_27[u32CoreId])) /*if interrupts were enabled*/
1490 {
1491 OsIf_ResumeAllInterrupts();
1492 #ifdef _ARM_DS5_C_S32K3XX_
1493 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1494 #endif
1495 }
1496 }
1497
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_28(void)1498 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_28(void)
1499 {
1500 uint32 msr;
1501 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1502
1503 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_28[u32CoreId])
1504 {
1505 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1506 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1507 #else
1508 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1509 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1510 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1511 {
1512 OsIf_SuspendAllInterrupts();
1513 #ifdef _ARM_DS5_C_S32K3XX_
1514 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1515 #endif
1516 }
1517 msr_PWM_EXCLUSIVE_AREA_28[u32CoreId] = msr;
1518 }
1519 reentry_guard_PWM_EXCLUSIVE_AREA_28[u32CoreId]++;
1520 }
1521
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_28(void)1522 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_28(void)
1523 {
1524 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1525
1526 reentry_guard_PWM_EXCLUSIVE_AREA_28[u32CoreId]--;
1527 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_28[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_28[u32CoreId])) /*if interrupts were enabled*/
1528 {
1529 OsIf_ResumeAllInterrupts();
1530 #ifdef _ARM_DS5_C_S32K3XX_
1531 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1532 #endif
1533 }
1534 }
1535
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_29(void)1536 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_29(void)
1537 {
1538 uint32 msr;
1539 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1540
1541 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_29[u32CoreId])
1542 {
1543 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1544 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1545 #else
1546 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1547 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1548 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1549 {
1550 OsIf_SuspendAllInterrupts();
1551 #ifdef _ARM_DS5_C_S32K3XX_
1552 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1553 #endif
1554 }
1555 msr_PWM_EXCLUSIVE_AREA_29[u32CoreId] = msr;
1556 }
1557 reentry_guard_PWM_EXCLUSIVE_AREA_29[u32CoreId]++;
1558 }
1559
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_29(void)1560 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_29(void)
1561 {
1562 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1563
1564 reentry_guard_PWM_EXCLUSIVE_AREA_29[u32CoreId]--;
1565 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_29[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_29[u32CoreId])) /*if interrupts were enabled*/
1566 {
1567 OsIf_ResumeAllInterrupts();
1568 #ifdef _ARM_DS5_C_S32K3XX_
1569 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1570 #endif
1571 }
1572 }
1573
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_30(void)1574 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_30(void)
1575 {
1576 uint32 msr;
1577 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1578
1579 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_30[u32CoreId])
1580 {
1581 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1582 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1583 #else
1584 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1585 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1586 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1587 {
1588 OsIf_SuspendAllInterrupts();
1589 #ifdef _ARM_DS5_C_S32K3XX_
1590 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1591 #endif
1592 }
1593 msr_PWM_EXCLUSIVE_AREA_30[u32CoreId] = msr;
1594 }
1595 reentry_guard_PWM_EXCLUSIVE_AREA_30[u32CoreId]++;
1596 }
1597
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_30(void)1598 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_30(void)
1599 {
1600 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1601
1602 reentry_guard_PWM_EXCLUSIVE_AREA_30[u32CoreId]--;
1603 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_30[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_30[u32CoreId])) /*if interrupts were enabled*/
1604 {
1605 OsIf_ResumeAllInterrupts();
1606 #ifdef _ARM_DS5_C_S32K3XX_
1607 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1608 #endif
1609 }
1610 }
1611
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_31(void)1612 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_31(void)
1613 {
1614 uint32 msr;
1615 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1616
1617 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_31[u32CoreId])
1618 {
1619 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1620 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1621 #else
1622 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1623 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1624 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1625 {
1626 OsIf_SuspendAllInterrupts();
1627 #ifdef _ARM_DS5_C_S32K3XX_
1628 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1629 #endif
1630 }
1631 msr_PWM_EXCLUSIVE_AREA_31[u32CoreId] = msr;
1632 }
1633 reentry_guard_PWM_EXCLUSIVE_AREA_31[u32CoreId]++;
1634 }
1635
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_31(void)1636 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_31(void)
1637 {
1638 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1639
1640 reentry_guard_PWM_EXCLUSIVE_AREA_31[u32CoreId]--;
1641 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_31[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_31[u32CoreId])) /*if interrupts were enabled*/
1642 {
1643 OsIf_ResumeAllInterrupts();
1644 #ifdef _ARM_DS5_C_S32K3XX_
1645 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1646 #endif
1647 }
1648 }
1649
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_32(void)1650 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_32(void)
1651 {
1652 uint32 msr;
1653 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1654
1655 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_32[u32CoreId])
1656 {
1657 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1658 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1659 #else
1660 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1661 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1662 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1663 {
1664 OsIf_SuspendAllInterrupts();
1665 #ifdef _ARM_DS5_C_S32K3XX_
1666 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1667 #endif
1668 }
1669 msr_PWM_EXCLUSIVE_AREA_32[u32CoreId] = msr;
1670 }
1671 reentry_guard_PWM_EXCLUSIVE_AREA_32[u32CoreId]++;
1672 }
1673
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_32(void)1674 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_32(void)
1675 {
1676 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1677
1678 reentry_guard_PWM_EXCLUSIVE_AREA_32[u32CoreId]--;
1679 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_32[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_32[u32CoreId])) /*if interrupts were enabled*/
1680 {
1681 OsIf_ResumeAllInterrupts();
1682 #ifdef _ARM_DS5_C_S32K3XX_
1683 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1684 #endif
1685 }
1686 }
1687
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_33(void)1688 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_33(void)
1689 {
1690 uint32 msr;
1691 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1692
1693 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_33[u32CoreId])
1694 {
1695 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1696 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1697 #else
1698 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1699 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1700 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1701 {
1702 OsIf_SuspendAllInterrupts();
1703 #ifdef _ARM_DS5_C_S32K3XX_
1704 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1705 #endif
1706 }
1707 msr_PWM_EXCLUSIVE_AREA_33[u32CoreId] = msr;
1708 }
1709 reentry_guard_PWM_EXCLUSIVE_AREA_33[u32CoreId]++;
1710 }
1711
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_33(void)1712 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_33(void)
1713 {
1714 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1715
1716 reentry_guard_PWM_EXCLUSIVE_AREA_33[u32CoreId]--;
1717 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_33[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_33[u32CoreId])) /*if interrupts were enabled*/
1718 {
1719 OsIf_ResumeAllInterrupts();
1720 #ifdef _ARM_DS5_C_S32K3XX_
1721 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1722 #endif
1723 }
1724 }
1725
SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_34(void)1726 void SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_34(void)
1727 {
1728 uint32 msr;
1729 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1730
1731 if(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_34[u32CoreId])
1732 {
1733 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1734 msr = OsIf_Trusted_Call_Return(Pwm_schm_read_msr);
1735 #else
1736 msr = Pwm_schm_read_msr(); /*read MSR (to store interrupts state)*/
1737 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1738 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1739 {
1740 OsIf_SuspendAllInterrupts();
1741 #ifdef _ARM_DS5_C_S32K3XX_
1742 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1743 #endif
1744 }
1745 msr_PWM_EXCLUSIVE_AREA_34[u32CoreId] = msr;
1746 }
1747 reentry_guard_PWM_EXCLUSIVE_AREA_34[u32CoreId]++;
1748 }
1749
SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_34(void)1750 void SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_34(void)
1751 {
1752 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1753
1754 reentry_guard_PWM_EXCLUSIVE_AREA_34[u32CoreId]--;
1755 if ((ISR_ON(msr_PWM_EXCLUSIVE_AREA_34[u32CoreId]))&&(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_34[u32CoreId])) /*if interrupts were enabled*/
1756 {
1757 OsIf_ResumeAllInterrupts();
1758 #ifdef _ARM_DS5_C_S32K3XX_
1759 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1760 #endif
1761 }
1762 }
1763
1764
1765 #ifdef MCAL_TESTING_ENVIRONMENT
1766 /**
1767 @brief This function checks that all entered exclusive areas were also exited.
1768 @details This function checks that all entered exclusive areas were also exited. The check
1769 is done by verifying that all reentry_guard_* static variables are back to the
1770 zero value.
1771
1772 @param[in] void No input parameters
1773 @return void This function does not return a value. Test asserts are used instead.
1774
1775 @pre None
1776 @post None
1777
1778 @remarks Covers
1779 @remarks Implements
1780 */
SchM_Check_pwm(void)1781 void SchM_Check_pwm(void)
1782 {
1783 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1784
1785 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_00[u32CoreId]);
1786 reentry_guard_PWM_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_00 for the next test in the suite*/
1787
1788 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_01[u32CoreId]);
1789 reentry_guard_PWM_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_01 for the next test in the suite*/
1790
1791 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_02[u32CoreId]);
1792 reentry_guard_PWM_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_02 for the next test in the suite*/
1793
1794 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_03[u32CoreId]);
1795 reentry_guard_PWM_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_03 for the next test in the suite*/
1796
1797 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_04[u32CoreId]);
1798 reentry_guard_PWM_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_04 for the next test in the suite*/
1799
1800 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_05[u32CoreId]);
1801 reentry_guard_PWM_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_05 for the next test in the suite*/
1802
1803 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_06[u32CoreId]);
1804 reentry_guard_PWM_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_06 for the next test in the suite*/
1805
1806 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_07[u32CoreId]);
1807 reentry_guard_PWM_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_07 for the next test in the suite*/
1808
1809 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_08[u32CoreId]);
1810 reentry_guard_PWM_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_08 for the next test in the suite*/
1811
1812 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_09[u32CoreId]);
1813 reentry_guard_PWM_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_09 for the next test in the suite*/
1814
1815 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_10[u32CoreId]);
1816 reentry_guard_PWM_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_10 for the next test in the suite*/
1817
1818 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_11[u32CoreId]);
1819 reentry_guard_PWM_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_11 for the next test in the suite*/
1820
1821 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_12[u32CoreId]);
1822 reentry_guard_PWM_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_12 for the next test in the suite*/
1823
1824 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_13[u32CoreId]);
1825 reentry_guard_PWM_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_13 for the next test in the suite*/
1826
1827 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_14[u32CoreId]);
1828 reentry_guard_PWM_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_14 for the next test in the suite*/
1829
1830 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_15[u32CoreId]);
1831 reentry_guard_PWM_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_15 for the next test in the suite*/
1832
1833 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_16[u32CoreId]);
1834 reentry_guard_PWM_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_16 for the next test in the suite*/
1835
1836 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_17[u32CoreId]);
1837 reentry_guard_PWM_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_17 for the next test in the suite*/
1838
1839 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_18[u32CoreId]);
1840 reentry_guard_PWM_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_18 for the next test in the suite*/
1841
1842 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_19[u32CoreId]);
1843 reentry_guard_PWM_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_19 for the next test in the suite*/
1844
1845 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_20[u32CoreId]);
1846 reentry_guard_PWM_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_20 for the next test in the suite*/
1847
1848 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_21[u32CoreId]);
1849 reentry_guard_PWM_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_21 for the next test in the suite*/
1850
1851 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_22[u32CoreId]);
1852 reentry_guard_PWM_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_22 for the next test in the suite*/
1853
1854 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_23[u32CoreId]);
1855 reentry_guard_PWM_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_23 for the next test in the suite*/
1856
1857 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_24[u32CoreId]);
1858 reentry_guard_PWM_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_24 for the next test in the suite*/
1859
1860 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_25[u32CoreId]);
1861 reentry_guard_PWM_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_25 for the next test in the suite*/
1862
1863 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_26[u32CoreId]);
1864 reentry_guard_PWM_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_26 for the next test in the suite*/
1865
1866 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_27[u32CoreId]);
1867 reentry_guard_PWM_EXCLUSIVE_AREA_27[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_27 for the next test in the suite*/
1868
1869 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_28[u32CoreId]);
1870 reentry_guard_PWM_EXCLUSIVE_AREA_28[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_28 for the next test in the suite*/
1871
1872 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_29[u32CoreId]);
1873 reentry_guard_PWM_EXCLUSIVE_AREA_29[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_29 for the next test in the suite*/
1874
1875 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_30[u32CoreId]);
1876 reentry_guard_PWM_EXCLUSIVE_AREA_30[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_30 for the next test in the suite*/
1877
1878 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_31[u32CoreId]);
1879 reentry_guard_PWM_EXCLUSIVE_AREA_31[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_31 for the next test in the suite*/
1880
1881 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_32[u32CoreId]);
1882 reentry_guard_PWM_EXCLUSIVE_AREA_32[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_32 for the next test in the suite*/
1883
1884 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_33[u32CoreId]);
1885 reentry_guard_PWM_EXCLUSIVE_AREA_33[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_33 for the next test in the suite*/
1886
1887 EU_ASSERT(0UL == reentry_guard_PWM_EXCLUSIVE_AREA_34[u32CoreId]);
1888 reentry_guard_PWM_EXCLUSIVE_AREA_34[u32CoreId] = 0UL; /*reset reentry_guard_PWM_EXCLUSIVE_AREA_34 for the next test in the suite*/
1889
1890
1891 }
1892 #endif /*MCAL_TESTING_ENVIRONMENT*/
1893
1894 #define RTE_STOP_SEC_CODE
1895 #include "Rte_MemMap.h"
1896
1897 #ifdef __cplusplus
1898 }
1899 #endif
1900
1901 /** @} */
1902
