1 /*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Platform.c
9 * @version 2.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Platform.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_PLATFORM_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_PLATFORM_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_PLATFORM_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_PLATFORM_SW_MAJOR_VERSION_C 2
44 #define SCHM_PLATFORM_SW_MINOR_VERSION_C 0
45 #define SCHM_PLATFORM_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_00) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_01) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_02) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_03) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_04) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_05) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_06) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_07) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_08) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_09) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_10) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_11) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_PLATFORM_EXCLUSIVE_AREA_12) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_PLATFORM_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
128
129 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
130 #include "Rte_MemMap.h"
131 /*==================================================================================================
132 * GLOBAL CONSTANTS
133 ==================================================================================================*/
134
135
136 /*==================================================================================================
137 * GLOBAL VARIABLES
138 ==================================================================================================*/
139
140 /*==================================================================================================
141 * LOCAL FUNCTION PROTOTYPES
142 ==================================================================================================*/
143
144 #ifndef _COSMIC_C_S32ZE_
145 /*================================================================================================*/
146 /**
147 * @brief This function returns the MSR register value (32 bits).
148 * @details This function returns the MSR register value (32 bits).
149 *
150 * @param[in] void No input parameters
151 * @return uint32 msr This function returns the MSR register value (32 bits).
152 *
153 * @pre None
154 * @post None
155 *
156 */
157 uint32 Platform_schm_read_msr(void);
158 #endif /*ifndef _COSMIC_C_S32ZE_*/
159 /*==================================================================================================
160 * LOCAL FUNCTIONS
161 ==================================================================================================*/
162 #define RTE_START_SEC_CODE
163 #include "Rte_MemMap.h"
164
165 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
166 /*================================================================================================*/
167 /**
168 * @brief This macro returns the MSR register value (32 bits).
169 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
170 *
171 * @pre None
172 * @post None
173 *
174 */
175 #ifdef MCAL_PLATFORM_ARM
176 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Platform_schm_read_msr(void)177 ASM_KEYWORD uint32 Platform_schm_read_msr(void)
178 {
179 mrs x0, S3_3_c4_c2_1
180 }
181 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Platform_schm_read_msr(void)182 ASM_KEYWORD uint32 Platform_schm_read_msr(void)
183 {
184 mrs r0, CPSR
185 }
186 #else
Platform_schm_read_msr(void)187 ASM_KEYWORD uint32 Platform_schm_read_msr(void)
188 {
189 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
190 mrs r0, BASEPRI
191 #else
192 mrs r0, PRIMASK
193 #endif
194 }
195 #endif
196 #else
197 #ifdef MCAL_PLATFORM_S12
Platform_schm_read_msr(void)198 ASM_KEYWORD uint32 Platform_schm_read_msr(void)
199 {
200 tfr ccr, d6
201 }
202 #else
Platform_schm_read_msr(void)203 ASM_KEYWORD uint32 Platform_schm_read_msr(void)
204 {
205 mfmsr r3
206 }
207 #endif
208 #endif
209 #endif /*#ifdef GHS||CW*/
210
211 #ifdef _DIABDATA_C_S32ZE_
212 /**
213 * @brief This function returns the MSR register value (32 bits).
214 * @details This function returns the MSR register value (32 bits).
215 *
216 * @param[in] void No input parameters
217 * @return uint32 msr This function returns the MSR register value (32 bits).
218 *
219 * @pre None
220 * @post None
221 *
222 */
223 #ifdef MCAL_PLATFORM_ARM
Platform_schm_read_msr(void)224 uint32 Platform_schm_read_msr(void)
225 {
226 register uint32 reg_tmp;
227 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
228 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
229 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
230 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
231 #else
232 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
233 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
234 #else
235 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
236 #endif
237 #endif
238 return (uint32)reg_tmp;
239 }
240 #else
Platform_schm_read_msr(void)241 ASM_KEYWORD uint32 Platform_schm_read_msr(void)
242 {
243 mfmsr r3
244 }
245 #endif /* MCAL_PLATFORM_ARM */
246
247 #endif /* _DIABDATA_C_S32ZE_*/
248
249 #ifdef _COSMIC_C_S32ZE_
250 /*================================================================================================*/
251 /**
252 * @brief This function returns the MSR register value (32 bits).
253 * @details This function returns the MSR register value (32 bits).
254 *
255 * @param[in] void No input parameters
256 * @return uint32 msr This function returns the MSR register value (32 bits).
257 *
258 * @pre None
259 * @post None
260 *
261 */
262
263 #ifdef MCAL_PLATFORM_S12
264 #define Platform_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
265 #else
266 #define Platform_schm_read_msr() ASM_KEYWORD("mfmsr r3")
267 #endif
268
269 #endif /*Cosmic compiler only*/
270
271
272 #ifdef _HITECH_C_S32ZE_
273 /*================================================================================================*/
274 /**
275 * @brief This function returns the MSR register value (32 bits).
276 * @details This function returns the MSR register value (32 bits).
277 *
278 * @param[in] void No input parameters
279 * @return uint32 msr This function returns the MSR register value (32 bits).
280 *
281 * @pre None
282 * @post None
283 *
284 */
Platform_schm_read_msr(void)285 uint32 Platform_schm_read_msr(void)
286 {
287 uint32 result;
288 __asm volatile("mfmsr %0" : "=r" (result) :);
289 return result;
290 }
291
292 #endif /*HighTec compiler only*/
293 /*================================================================================================*/
294 #ifdef _GCC_C_S32ZE_
295 /**
296 * @brief This function returns the MSR register value (32 bits).
297 * @details This function returns the MSR register value (32 bits).
298 *
299 * @param[in] void No input parameters
300 * @return uint32 msr This function returns the MSR register value (32 bits).
301 *
302 * @pre None
303 * @post None
304 *
305 */
Platform_schm_read_msr(void)306 uint32 Platform_schm_read_msr(void)
307 {
308 register uint32 reg_tmp;
309 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
310 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
311 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
312 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
313 #else
314 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
315 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
316 #else
317 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
318 #endif
319 #endif
320 return (uint32)reg_tmp;
321 }
322 #endif /* _GCC_C_S32ZE_*/
323 /*================================================================================================*/
324
325 #ifdef _ARM_DS5_C_S32ZE_
326 /**
327 * @brief This function returns the MSR register value (32 bits).
328 * @details This function returns the MSR register value (32 bits).
329 *
330 * @param[in] void No input parameters
331 * @return uint32 msr This function returns the MSR register value (32 bits).
332 *
333 * @pre None
334 * @post None
335 *
336 */
Platform_schm_read_msr(void)337 uint32 Platform_schm_read_msr(void)
338 {
339 register uint32 reg_tmp;
340 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
341 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
342 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
343 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
344 #else
345 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
346 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
347 #else
348 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
349 #endif
350 #endif
351 return (uint32)reg_tmp;
352 }
353 #endif /* _ARM_DS5_C_S32ZE_ */
354
355 #ifdef _IAR_C_S32ZE_
356 /**
357 * @brief This function returns the MSR register value (32 bits).
358 * @details This function returns the MSR register value (32 bits).
359 *
360 * @param[in] void No input parameters
361 * @return uint32 msr This function returns the MSR register value (32 bits).
362 *
363 * @pre None
364 * @post None
365 *
366 */
Platform_schm_read_msr(void)367 uint32 Platform_schm_read_msr(void)
368 {
369 register uint32 reg_tmp;
370
371 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
372 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
373 #else
374 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
375 #endif
376
377 return (uint32)reg_tmp;
378 }
379 #endif /* _IAR_C_S32ZE_ */
380
381 #define RTE_STOP_SEC_CODE
382 #include "Rte_MemMap.h"
383
384 /*==================================================================================================
385 * GLOBAL FUNCTIONS
386 ==================================================================================================*/
387 #define RTE_START_SEC_CODE
388 #include "Rte_MemMap.h"
389
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_00(void)390 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_00(void)
391 {
392 uint32 msr;
393 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
394
395 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_00[u32CoreId])
396 {
397 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
398 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
399 #else
400 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
401 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
402 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
403 {
404 OsIf_SuspendAllInterrupts();
405 #ifdef _ARM_DS5_C_S32ZE_
406 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
407 #endif
408 }
409 msr_PLATFORM_EXCLUSIVE_AREA_00[u32CoreId] = msr;
410 }
411 reentry_guard_PLATFORM_EXCLUSIVE_AREA_00[u32CoreId]++;
412 }
413
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_00(void)414 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_00(void)
415 {
416 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
417
418 reentry_guard_PLATFORM_EXCLUSIVE_AREA_00[u32CoreId]--;
419 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
420 {
421 OsIf_ResumeAllInterrupts();
422 #ifdef _ARM_DS5_C_S32ZE_
423 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
424 #endif
425 }
426 }
427
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_01(void)428 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_01(void)
429 {
430 uint32 msr;
431 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
432
433 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_01[u32CoreId])
434 {
435 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
436 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
437 #else
438 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
439 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
440 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
441 {
442 OsIf_SuspendAllInterrupts();
443 #ifdef _ARM_DS5_C_S32ZE_
444 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
445 #endif
446 }
447 msr_PLATFORM_EXCLUSIVE_AREA_01[u32CoreId] = msr;
448 }
449 reentry_guard_PLATFORM_EXCLUSIVE_AREA_01[u32CoreId]++;
450 }
451
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_01(void)452 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_01(void)
453 {
454 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
455
456 reentry_guard_PLATFORM_EXCLUSIVE_AREA_01[u32CoreId]--;
457 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
458 {
459 OsIf_ResumeAllInterrupts();
460 #ifdef _ARM_DS5_C_S32ZE_
461 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
462 #endif
463 }
464 }
465
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_02(void)466 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_02(void)
467 {
468 uint32 msr;
469 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
470
471 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_02[u32CoreId])
472 {
473 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
474 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
475 #else
476 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
477 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
478 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
479 {
480 OsIf_SuspendAllInterrupts();
481 #ifdef _ARM_DS5_C_S32ZE_
482 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
483 #endif
484 }
485 msr_PLATFORM_EXCLUSIVE_AREA_02[u32CoreId] = msr;
486 }
487 reentry_guard_PLATFORM_EXCLUSIVE_AREA_02[u32CoreId]++;
488 }
489
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_02(void)490 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_02(void)
491 {
492 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
493
494 reentry_guard_PLATFORM_EXCLUSIVE_AREA_02[u32CoreId]--;
495 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
496 {
497 OsIf_ResumeAllInterrupts();
498 #ifdef _ARM_DS5_C_S32ZE_
499 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
500 #endif
501 }
502 }
503
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_03(void)504 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_03(void)
505 {
506 uint32 msr;
507 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
508
509 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_03[u32CoreId])
510 {
511 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
512 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
513 #else
514 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
515 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
516 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
517 {
518 OsIf_SuspendAllInterrupts();
519 #ifdef _ARM_DS5_C_S32ZE_
520 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
521 #endif
522 }
523 msr_PLATFORM_EXCLUSIVE_AREA_03[u32CoreId] = msr;
524 }
525 reentry_guard_PLATFORM_EXCLUSIVE_AREA_03[u32CoreId]++;
526 }
527
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_03(void)528 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_03(void)
529 {
530 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
531
532 reentry_guard_PLATFORM_EXCLUSIVE_AREA_03[u32CoreId]--;
533 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
534 {
535 OsIf_ResumeAllInterrupts();
536 #ifdef _ARM_DS5_C_S32ZE_
537 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
538 #endif
539 }
540 }
541
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_04(void)542 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_04(void)
543 {
544 uint32 msr;
545 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
546
547 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_04[u32CoreId])
548 {
549 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
550 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
551 #else
552 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
553 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
554 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
555 {
556 OsIf_SuspendAllInterrupts();
557 #ifdef _ARM_DS5_C_S32ZE_
558 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
559 #endif
560 }
561 msr_PLATFORM_EXCLUSIVE_AREA_04[u32CoreId] = msr;
562 }
563 reentry_guard_PLATFORM_EXCLUSIVE_AREA_04[u32CoreId]++;
564 }
565
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_04(void)566 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_04(void)
567 {
568 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
569
570 reentry_guard_PLATFORM_EXCLUSIVE_AREA_04[u32CoreId]--;
571 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
572 {
573 OsIf_ResumeAllInterrupts();
574 #ifdef _ARM_DS5_C_S32ZE_
575 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
576 #endif
577 }
578 }
579
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_05(void)580 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_05(void)
581 {
582 uint32 msr;
583 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
584
585 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_05[u32CoreId])
586 {
587 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
588 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
589 #else
590 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
591 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
592 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
593 {
594 OsIf_SuspendAllInterrupts();
595 #ifdef _ARM_DS5_C_S32ZE_
596 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
597 #endif
598 }
599 msr_PLATFORM_EXCLUSIVE_AREA_05[u32CoreId] = msr;
600 }
601 reentry_guard_PLATFORM_EXCLUSIVE_AREA_05[u32CoreId]++;
602 }
603
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_05(void)604 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_05(void)
605 {
606 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
607
608 reentry_guard_PLATFORM_EXCLUSIVE_AREA_05[u32CoreId]--;
609 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
610 {
611 OsIf_ResumeAllInterrupts();
612 #ifdef _ARM_DS5_C_S32ZE_
613 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
614 #endif
615 }
616 }
617
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_06(void)618 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_06(void)
619 {
620 uint32 msr;
621 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
622
623 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_06[u32CoreId])
624 {
625 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
626 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
627 #else
628 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
629 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
630 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
631 {
632 OsIf_SuspendAllInterrupts();
633 #ifdef _ARM_DS5_C_S32ZE_
634 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
635 #endif
636 }
637 msr_PLATFORM_EXCLUSIVE_AREA_06[u32CoreId] = msr;
638 }
639 reentry_guard_PLATFORM_EXCLUSIVE_AREA_06[u32CoreId]++;
640 }
641
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_06(void)642 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_06(void)
643 {
644 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
645
646 reentry_guard_PLATFORM_EXCLUSIVE_AREA_06[u32CoreId]--;
647 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
648 {
649 OsIf_ResumeAllInterrupts();
650 #ifdef _ARM_DS5_C_S32ZE_
651 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
652 #endif
653 }
654 }
655
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_07(void)656 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_07(void)
657 {
658 uint32 msr;
659 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
660
661 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_07[u32CoreId])
662 {
663 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
664 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
665 #else
666 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
667 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
668 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
669 {
670 OsIf_SuspendAllInterrupts();
671 #ifdef _ARM_DS5_C_S32ZE_
672 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
673 #endif
674 }
675 msr_PLATFORM_EXCLUSIVE_AREA_07[u32CoreId] = msr;
676 }
677 reentry_guard_PLATFORM_EXCLUSIVE_AREA_07[u32CoreId]++;
678 }
679
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_07(void)680 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_07(void)
681 {
682 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
683
684 reentry_guard_PLATFORM_EXCLUSIVE_AREA_07[u32CoreId]--;
685 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
686 {
687 OsIf_ResumeAllInterrupts();
688 #ifdef _ARM_DS5_C_S32ZE_
689 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
690 #endif
691 }
692 }
693
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_08(void)694 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_08(void)
695 {
696 uint32 msr;
697 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
698
699 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_08[u32CoreId])
700 {
701 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
702 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
703 #else
704 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
705 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
706 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
707 {
708 OsIf_SuspendAllInterrupts();
709 #ifdef _ARM_DS5_C_S32ZE_
710 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
711 #endif
712 }
713 msr_PLATFORM_EXCLUSIVE_AREA_08[u32CoreId] = msr;
714 }
715 reentry_guard_PLATFORM_EXCLUSIVE_AREA_08[u32CoreId]++;
716 }
717
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_08(void)718 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_08(void)
719 {
720 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
721
722 reentry_guard_PLATFORM_EXCLUSIVE_AREA_08[u32CoreId]--;
723 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
724 {
725 OsIf_ResumeAllInterrupts();
726 #ifdef _ARM_DS5_C_S32ZE_
727 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
728 #endif
729 }
730 }
731
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_09(void)732 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_09(void)
733 {
734 uint32 msr;
735 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
736
737 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_09[u32CoreId])
738 {
739 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
740 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
741 #else
742 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
743 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
744 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
745 {
746 OsIf_SuspendAllInterrupts();
747 #ifdef _ARM_DS5_C_S32ZE_
748 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
749 #endif
750 }
751 msr_PLATFORM_EXCLUSIVE_AREA_09[u32CoreId] = msr;
752 }
753 reentry_guard_PLATFORM_EXCLUSIVE_AREA_09[u32CoreId]++;
754 }
755
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_09(void)756 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_09(void)
757 {
758 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
759
760 reentry_guard_PLATFORM_EXCLUSIVE_AREA_09[u32CoreId]--;
761 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
762 {
763 OsIf_ResumeAllInterrupts();
764 #ifdef _ARM_DS5_C_S32ZE_
765 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
766 #endif
767 }
768 }
769
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_10(void)770 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_10(void)
771 {
772 uint32 msr;
773 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
774
775 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_10[u32CoreId])
776 {
777 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
778 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
779 #else
780 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
781 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
782 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
783 {
784 OsIf_SuspendAllInterrupts();
785 #ifdef _ARM_DS5_C_S32ZE_
786 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
787 #endif
788 }
789 msr_PLATFORM_EXCLUSIVE_AREA_10[u32CoreId] = msr;
790 }
791 reentry_guard_PLATFORM_EXCLUSIVE_AREA_10[u32CoreId]++;
792 }
793
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_10(void)794 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_10(void)
795 {
796 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
797
798 reentry_guard_PLATFORM_EXCLUSIVE_AREA_10[u32CoreId]--;
799 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
800 {
801 OsIf_ResumeAllInterrupts();
802 #ifdef _ARM_DS5_C_S32ZE_
803 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
804 #endif
805 }
806 }
807
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_11(void)808 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_11(void)
809 {
810 uint32 msr;
811 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
812
813 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_11[u32CoreId])
814 {
815 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
816 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
817 #else
818 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
819 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
820 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
821 {
822 OsIf_SuspendAllInterrupts();
823 #ifdef _ARM_DS5_C_S32ZE_
824 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
825 #endif
826 }
827 msr_PLATFORM_EXCLUSIVE_AREA_11[u32CoreId] = msr;
828 }
829 reentry_guard_PLATFORM_EXCLUSIVE_AREA_11[u32CoreId]++;
830 }
831
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_11(void)832 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_11(void)
833 {
834 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
835
836 reentry_guard_PLATFORM_EXCLUSIVE_AREA_11[u32CoreId]--;
837 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
838 {
839 OsIf_ResumeAllInterrupts();
840 #ifdef _ARM_DS5_C_S32ZE_
841 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
842 #endif
843 }
844 }
845
SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_12(void)846 void SchM_Enter_Platform_PLATFORM_EXCLUSIVE_AREA_12(void)
847 {
848 uint32 msr;
849 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
850
851 if(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_12[u32CoreId])
852 {
853 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
854 msr = OsIf_Trusted_Call_Return(Platform_schm_read_msr);
855 #else
856 msr = Platform_schm_read_msr(); /*read MSR (to store interrupts state)*/
857 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
858 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
859 {
860 OsIf_SuspendAllInterrupts();
861 #ifdef _ARM_DS5_C_S32ZE_
862 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
863 #endif
864 }
865 msr_PLATFORM_EXCLUSIVE_AREA_12[u32CoreId] = msr;
866 }
867 reentry_guard_PLATFORM_EXCLUSIVE_AREA_12[u32CoreId]++;
868 }
869
SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_12(void)870 void SchM_Exit_Platform_PLATFORM_EXCLUSIVE_AREA_12(void)
871 {
872 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
873
874 reentry_guard_PLATFORM_EXCLUSIVE_AREA_12[u32CoreId]--;
875 if ((ISR_ON(msr_PLATFORM_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
876 {
877 OsIf_ResumeAllInterrupts();
878 #ifdef _ARM_DS5_C_S32ZE_
879 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
880 #endif
881 }
882 }
883
884
885 #ifdef MCAL_TESTING_ENVIRONMENT
886 /**
887 @brief This function checks that all entered exclusive areas were also exited.
888 @details This function checks that all entered exclusive areas were also exited. The check
889 is done by verifying that all reentry_guard_* static variables are back to the
890 zero value.
891
892 @param[in] void No input parameters
893 @return void This function does not return a value. Test asserts are used instead.
894
895 @pre None
896 @post None
897
898 @remarks Covers
899 @remarks Implements
900 */
SchM_Check_platform(void)901 void SchM_Check_platform(void)
902 {
903 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
904
905 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_00[u32CoreId]);
906 reentry_guard_PLATFORM_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_00 for the next test in the suite*/
907
908 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_01[u32CoreId]);
909 reentry_guard_PLATFORM_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_01 for the next test in the suite*/
910
911 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_02[u32CoreId]);
912 reentry_guard_PLATFORM_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_02 for the next test in the suite*/
913
914 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_03[u32CoreId]);
915 reentry_guard_PLATFORM_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_03 for the next test in the suite*/
916
917 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_04[u32CoreId]);
918 reentry_guard_PLATFORM_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_04 for the next test in the suite*/
919
920 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_05[u32CoreId]);
921 reentry_guard_PLATFORM_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_05 for the next test in the suite*/
922
923 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_06[u32CoreId]);
924 reentry_guard_PLATFORM_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_06 for the next test in the suite*/
925
926 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_07[u32CoreId]);
927 reentry_guard_PLATFORM_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_07 for the next test in the suite*/
928
929 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_08[u32CoreId]);
930 reentry_guard_PLATFORM_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_08 for the next test in the suite*/
931
932 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_09[u32CoreId]);
933 reentry_guard_PLATFORM_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_09 for the next test in the suite*/
934
935 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_10[u32CoreId]);
936 reentry_guard_PLATFORM_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_10 for the next test in the suite*/
937
938 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_11[u32CoreId]);
939 reentry_guard_PLATFORM_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_11 for the next test in the suite*/
940
941 EU_ASSERT(0UL == reentry_guard_PLATFORM_EXCLUSIVE_AREA_12[u32CoreId]);
942 reentry_guard_PLATFORM_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_PLATFORM_EXCLUSIVE_AREA_12 for the next test in the suite*/
943
944
945 }
946 #endif /*MCAL_TESTING_ENVIRONMENT*/
947
948 #define RTE_STOP_SEC_CODE
949 #include "Rte_MemMap.h"
950
951 #ifdef __cplusplus
952 }
953 #endif
954
955 /** @} */
956
