1 /*
2 * Copyright 2021-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Gpt.c
9 * @version 1.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Gpt.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_GPT_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_GPT_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_GPT_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_GPT_SW_MAJOR_VERSION_C 1
44 #define SCHM_GPT_SW_MINOR_VERSION_C 0
45 #define SCHM_GPT_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_00) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_01) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_02) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_03) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_04) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_05) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_06) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_07) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_10) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_11) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_17) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_21) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_21) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_22) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_22) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_23) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_23) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_24) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_24) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_25) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_25) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_26) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_26) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_29) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_29) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_30) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_30) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_31) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_31) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_35) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_35[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_35) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_35[NUMBER_OF_CORES];
144 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_36) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_36[NUMBER_OF_CORES];
145 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_36) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_36[NUMBER_OF_CORES];
146 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_38) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_38[NUMBER_OF_CORES];
147 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_38) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_38[NUMBER_OF_CORES];
148 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_39) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_39[NUMBER_OF_CORES];
149 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_39) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_39[NUMBER_OF_CORES];
150 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_40) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_40[NUMBER_OF_CORES];
151 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_40) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_40[NUMBER_OF_CORES];
152 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_41) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_41[NUMBER_OF_CORES];
153 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_41) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_41[NUMBER_OF_CORES];
154 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_42) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_42[NUMBER_OF_CORES];
155 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_42) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_42[NUMBER_OF_CORES];
156 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_43) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_43[NUMBER_OF_CORES];
157 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_43) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_43[NUMBER_OF_CORES];
158 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_44) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
159 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_44) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
160 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_45) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
161 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_45) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
162 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_46) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
163 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_46) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
164 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_50) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
165 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_50) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
166 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_51) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_51[NUMBER_OF_CORES];
167 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_51) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_51[NUMBER_OF_CORES];
168 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_52) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_52[NUMBER_OF_CORES];
169 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_52) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_52[NUMBER_OF_CORES];
170 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_53) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_53[NUMBER_OF_CORES];
171 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_53) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_53[NUMBER_OF_CORES];
172 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_54) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_54[NUMBER_OF_CORES];
173 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_54) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_54[NUMBER_OF_CORES];
174 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_55) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_55[NUMBER_OF_CORES];
175 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_55) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_55[NUMBER_OF_CORES];
176 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_56) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_56[NUMBER_OF_CORES];
177 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_56) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_56[NUMBER_OF_CORES];
178 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_60) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_60[NUMBER_OF_CORES];
179 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_60) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_60[NUMBER_OF_CORES];
180 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_61) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_61[NUMBER_OF_CORES];
181 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_61) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_61[NUMBER_OF_CORES];
182 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_62) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_62[NUMBER_OF_CORES];
183 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_62) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_62[NUMBER_OF_CORES];
184 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_63) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_63[NUMBER_OF_CORES];
185 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_63) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_63[NUMBER_OF_CORES];
186 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_64) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_64[NUMBER_OF_CORES];
187 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_64) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_64[NUMBER_OF_CORES];
188 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_65) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_65[NUMBER_OF_CORES];
189 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_65) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_65[NUMBER_OF_CORES];
190 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_66) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_66[NUMBER_OF_CORES];
191 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_66) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_66[NUMBER_OF_CORES];
192 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_67) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_67[NUMBER_OF_CORES];
193 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_67) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_67[NUMBER_OF_CORES];
194 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_68) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_68[NUMBER_OF_CORES];
195 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_68) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_68[NUMBER_OF_CORES];
196 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_69) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_69[NUMBER_OF_CORES];
197 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_69) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_69[NUMBER_OF_CORES];
198 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_70) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_70[NUMBER_OF_CORES];
199 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_70) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_70[NUMBER_OF_CORES];
200 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_71) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_71[NUMBER_OF_CORES];
201 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_71) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_71[NUMBER_OF_CORES];
202 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_72) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_72[NUMBER_OF_CORES];
203 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_72) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_72[NUMBER_OF_CORES];
204 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_73) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_73[NUMBER_OF_CORES];
205 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_73) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_73[NUMBER_OF_CORES];
206
207 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
208 #include "Rte_MemMap.h"
209 /*==================================================================================================
210 * GLOBAL CONSTANTS
211 ==================================================================================================*/
212
213
214 /*==================================================================================================
215 * GLOBAL VARIABLES
216 ==================================================================================================*/
217
218 /*==================================================================================================
219 * LOCAL FUNCTION PROTOTYPES
220 ==================================================================================================*/
221
222 #ifndef _COSMIC_C_S32ZE_
223 /*================================================================================================*/
224 /**
225 * @brief This function returns the MSR register value (32 bits).
226 * @details This function returns the MSR register value (32 bits).
227 *
228 * @param[in] void No input parameters
229 * @return uint32 msr This function returns the MSR register value (32 bits).
230 *
231 * @pre None
232 * @post None
233 *
234 */
235 uint32 Gpt_schm_read_msr(void);
236 #endif /*ifndef _COSMIC_C_S32ZE_*/
237 /*==================================================================================================
238 * LOCAL FUNCTIONS
239 ==================================================================================================*/
240 #define RTE_START_SEC_CODE
241 #include "Rte_MemMap.h"
242
243 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
244 /*================================================================================================*/
245 /**
246 * @brief This macro returns the MSR register value (32 bits).
247 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
248 *
249 * @pre None
250 * @post None
251 *
252 */
253 #ifdef MCAL_PLATFORM_ARM
254 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Gpt_schm_read_msr(void)255 ASM_KEYWORD uint32 Gpt_schm_read_msr(void)
256 {
257 mrs x0, S3_3_c4_c2_1
258 }
259 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Gpt_schm_read_msr(void)260 ASM_KEYWORD uint32 Gpt_schm_read_msr(void)
261 {
262 mrs r0, CPSR
263 }
264 #else
Gpt_schm_read_msr(void)265 ASM_KEYWORD uint32 Gpt_schm_read_msr(void)
266 {
267 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
268 mrs r0, BASEPRI
269 #else
270 mrs r0, PRIMASK
271 #endif
272 }
273 #endif
274 #else
275 #ifdef MCAL_PLATFORM_S12
Gpt_schm_read_msr(void)276 ASM_KEYWORD uint32 Gpt_schm_read_msr(void)
277 {
278 tfr ccr, d6
279 }
280 #else
Gpt_schm_read_msr(void)281 ASM_KEYWORD uint32 Gpt_schm_read_msr(void)
282 {
283 mfmsr r3
284 }
285 #endif
286 #endif
287 #endif /*#ifdef GHS||CW*/
288
289 #ifdef _DIABDATA_C_S32ZE_
290 /**
291 * @brief This function returns the MSR register value (32 bits).
292 * @details This function returns the MSR register value (32 bits).
293 *
294 * @param[in] void No input parameters
295 * @return uint32 msr This function returns the MSR register value (32 bits).
296 *
297 * @pre None
298 * @post None
299 *
300 */
301 #ifdef MCAL_PLATFORM_ARM
Gpt_schm_read_msr(void)302 uint32 Gpt_schm_read_msr(void)
303 {
304 register uint32 reg_tmp;
305 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
306 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
307 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
308 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
309 #else
310 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
311 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
312 #else
313 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
314 #endif
315 #endif
316 return (uint32)reg_tmp;
317 }
318 #else
Gpt_schm_read_msr(void)319 ASM_KEYWORD uint32 Gpt_schm_read_msr(void)
320 {
321 mfmsr r3
322 }
323 #endif /* MCAL_PLATFORM_ARM */
324
325 #endif /* _DIABDATA_C_S32ZE_*/
326
327 #ifdef _COSMIC_C_S32ZE_
328 /*================================================================================================*/
329 /**
330 * @brief This function returns the MSR register value (32 bits).
331 * @details This function returns the MSR register value (32 bits).
332 *
333 * @param[in] void No input parameters
334 * @return uint32 msr This function returns the MSR register value (32 bits).
335 *
336 * @pre None
337 * @post None
338 *
339 */
340
341 #ifdef MCAL_PLATFORM_S12
342 #define Gpt_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
343 #else
344 #define Gpt_schm_read_msr() ASM_KEYWORD("mfmsr r3")
345 #endif
346
347 #endif /*Cosmic compiler only*/
348
349
350 #ifdef _HITECH_C_S32ZE_
351 /*================================================================================================*/
352 /**
353 * @brief This function returns the MSR register value (32 bits).
354 * @details This function returns the MSR register value (32 bits).
355 *
356 * @param[in] void No input parameters
357 * @return uint32 msr This function returns the MSR register value (32 bits).
358 *
359 * @pre None
360 * @post None
361 *
362 */
Gpt_schm_read_msr(void)363 uint32 Gpt_schm_read_msr(void)
364 {
365 uint32 result;
366 __asm volatile("mfmsr %0" : "=r" (result) :);
367 return result;
368 }
369
370 #endif /*HighTec compiler only*/
371 /*================================================================================================*/
372 #ifdef _LINARO_C_S32ZE_
373 /**
374 * @brief This function returns the MSR register value (32 bits).
375 * @details This function returns the MSR register value (32 bits).
376 *
377 * @param[in] void No input parameters
378 * @return uint32 msr This function returns the MSR register value (32 bits).
379 *
380 * @pre None
381 * @post None
382 *
383 */
Gpt_schm_read_msr(void)384 uint32 Gpt_schm_read_msr(void)
385 {
386 register uint32 reg_tmp;
387 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
388 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
389 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
390 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
391 #else
392 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
393 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
394 #else
395 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
396 #endif
397 #endif
398 return (uint32)reg_tmp;
399 }
400 #endif /* _LINARO_C_S32ZE_*/
401 /*================================================================================================*/
402
403 #ifdef _ARM_DS5_C_S32ZE_
404 /**
405 * @brief This function returns the MSR register value (32 bits).
406 * @details This function returns the MSR register value (32 bits).
407 *
408 * @param[in] void No input parameters
409 * @return uint32 msr This function returns the MSR register value (32 bits).
410 *
411 * @pre None
412 * @post None
413 *
414 */
Gpt_schm_read_msr(void)415 uint32 Gpt_schm_read_msr(void)
416 {
417 register uint32 reg_tmp;
418 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
419 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
420 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
421 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
422 #else
423 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
424 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
425 #else
426 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
427 #endif
428 #endif
429 return (uint32)reg_tmp;
430 }
431 #endif /* _ARM_DS5_C_S32ZE_ */
432
433 #ifdef _IAR_C_S32ZE_
434 /**
435 * @brief This function returns the MSR register value (32 bits).
436 * @details This function returns the MSR register value (32 bits).
437 *
438 * @param[in] void No input parameters
439 * @return uint32 msr This function returns the MSR register value (32 bits).
440 *
441 * @pre None
442 * @post None
443 *
444 */
Gpt_schm_read_msr(void)445 uint32 Gpt_schm_read_msr(void)
446 {
447 register uint32 reg_tmp;
448
449 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
450 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
451 #else
452 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
453 #endif
454
455 return (uint32)reg_tmp;
456 }
457 #endif /* _IAR_C_S32ZE_ */
458
459 #define RTE_STOP_SEC_CODE
460 #include "Rte_MemMap.h"
461
462 /*==================================================================================================
463 * GLOBAL FUNCTIONS
464 ==================================================================================================*/
465 #define RTE_START_SEC_CODE
466 #include "Rte_MemMap.h"
467
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_00(void)468 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_00(void)
469 {
470 uint32 msr;
471 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
472
473 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_00[u32CoreId])
474 {
475 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
476 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
477 #else
478 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
479 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
480 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
481 {
482 OsIf_SuspendAllInterrupts();
483 #ifdef _ARM_DS5_C_S32ZE_
484 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
485 #endif
486 }
487 msr_GPT_EXCLUSIVE_AREA_00[u32CoreId] = msr;
488 }
489 reentry_guard_GPT_EXCLUSIVE_AREA_00[u32CoreId]++;
490 }
491
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_00(void)492 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_00(void)
493 {
494 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
495
496 reentry_guard_GPT_EXCLUSIVE_AREA_00[u32CoreId]--;
497 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
498 {
499 OsIf_ResumeAllInterrupts();
500 #ifdef _ARM_DS5_C_S32ZE_
501 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
502 #endif
503 }
504 }
505
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_01(void)506 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_01(void)
507 {
508 uint32 msr;
509 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
510
511 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_01[u32CoreId])
512 {
513 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
514 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
515 #else
516 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
517 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
518 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
519 {
520 OsIf_SuspendAllInterrupts();
521 #ifdef _ARM_DS5_C_S32ZE_
522 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
523 #endif
524 }
525 msr_GPT_EXCLUSIVE_AREA_01[u32CoreId] = msr;
526 }
527 reentry_guard_GPT_EXCLUSIVE_AREA_01[u32CoreId]++;
528 }
529
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_01(void)530 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_01(void)
531 {
532 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
533
534 reentry_guard_GPT_EXCLUSIVE_AREA_01[u32CoreId]--;
535 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
536 {
537 OsIf_ResumeAllInterrupts();
538 #ifdef _ARM_DS5_C_S32ZE_
539 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
540 #endif
541 }
542 }
543
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_02(void)544 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_02(void)
545 {
546 uint32 msr;
547 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
548
549 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_02[u32CoreId])
550 {
551 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
552 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
553 #else
554 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
555 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
556 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
557 {
558 OsIf_SuspendAllInterrupts();
559 #ifdef _ARM_DS5_C_S32ZE_
560 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
561 #endif
562 }
563 msr_GPT_EXCLUSIVE_AREA_02[u32CoreId] = msr;
564 }
565 reentry_guard_GPT_EXCLUSIVE_AREA_02[u32CoreId]++;
566 }
567
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_02(void)568 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_02(void)
569 {
570 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
571
572 reentry_guard_GPT_EXCLUSIVE_AREA_02[u32CoreId]--;
573 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
574 {
575 OsIf_ResumeAllInterrupts();
576 #ifdef _ARM_DS5_C_S32ZE_
577 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
578 #endif
579 }
580 }
581
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_03(void)582 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_03(void)
583 {
584 uint32 msr;
585 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
586
587 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_03[u32CoreId])
588 {
589 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
590 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
591 #else
592 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
593 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
594 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
595 {
596 OsIf_SuspendAllInterrupts();
597 #ifdef _ARM_DS5_C_S32ZE_
598 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
599 #endif
600 }
601 msr_GPT_EXCLUSIVE_AREA_03[u32CoreId] = msr;
602 }
603 reentry_guard_GPT_EXCLUSIVE_AREA_03[u32CoreId]++;
604 }
605
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_03(void)606 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_03(void)
607 {
608 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
609
610 reentry_guard_GPT_EXCLUSIVE_AREA_03[u32CoreId]--;
611 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
612 {
613 OsIf_ResumeAllInterrupts();
614 #ifdef _ARM_DS5_C_S32ZE_
615 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
616 #endif
617 }
618 }
619
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_04(void)620 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_04(void)
621 {
622 uint32 msr;
623 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
624
625 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_04[u32CoreId])
626 {
627 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
628 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
629 #else
630 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
631 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
632 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
633 {
634 OsIf_SuspendAllInterrupts();
635 #ifdef _ARM_DS5_C_S32ZE_
636 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
637 #endif
638 }
639 msr_GPT_EXCLUSIVE_AREA_04[u32CoreId] = msr;
640 }
641 reentry_guard_GPT_EXCLUSIVE_AREA_04[u32CoreId]++;
642 }
643
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_04(void)644 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_04(void)
645 {
646 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
647
648 reentry_guard_GPT_EXCLUSIVE_AREA_04[u32CoreId]--;
649 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
650 {
651 OsIf_ResumeAllInterrupts();
652 #ifdef _ARM_DS5_C_S32ZE_
653 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
654 #endif
655 }
656 }
657
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_05(void)658 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_05(void)
659 {
660 uint32 msr;
661 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
662
663 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_05[u32CoreId])
664 {
665 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
666 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
667 #else
668 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
669 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
670 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
671 {
672 OsIf_SuspendAllInterrupts();
673 #ifdef _ARM_DS5_C_S32ZE_
674 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
675 #endif
676 }
677 msr_GPT_EXCLUSIVE_AREA_05[u32CoreId] = msr;
678 }
679 reentry_guard_GPT_EXCLUSIVE_AREA_05[u32CoreId]++;
680 }
681
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_05(void)682 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_05(void)
683 {
684 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
685
686 reentry_guard_GPT_EXCLUSIVE_AREA_05[u32CoreId]--;
687 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
688 {
689 OsIf_ResumeAllInterrupts();
690 #ifdef _ARM_DS5_C_S32ZE_
691 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
692 #endif
693 }
694 }
695
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_06(void)696 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_06(void)
697 {
698 uint32 msr;
699 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
700
701 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_06[u32CoreId])
702 {
703 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
704 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
705 #else
706 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
707 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
708 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
709 {
710 OsIf_SuspendAllInterrupts();
711 #ifdef _ARM_DS5_C_S32ZE_
712 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
713 #endif
714 }
715 msr_GPT_EXCLUSIVE_AREA_06[u32CoreId] = msr;
716 }
717 reentry_guard_GPT_EXCLUSIVE_AREA_06[u32CoreId]++;
718 }
719
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_06(void)720 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_06(void)
721 {
722 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
723
724 reentry_guard_GPT_EXCLUSIVE_AREA_06[u32CoreId]--;
725 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
726 {
727 OsIf_ResumeAllInterrupts();
728 #ifdef _ARM_DS5_C_S32ZE_
729 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
730 #endif
731 }
732 }
733
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_07(void)734 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_07(void)
735 {
736 uint32 msr;
737 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
738
739 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_07[u32CoreId])
740 {
741 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
742 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
743 #else
744 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
745 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
746 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
747 {
748 OsIf_SuspendAllInterrupts();
749 #ifdef _ARM_DS5_C_S32ZE_
750 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
751 #endif
752 }
753 msr_GPT_EXCLUSIVE_AREA_07[u32CoreId] = msr;
754 }
755 reentry_guard_GPT_EXCLUSIVE_AREA_07[u32CoreId]++;
756 }
757
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_07(void)758 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_07(void)
759 {
760 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
761
762 reentry_guard_GPT_EXCLUSIVE_AREA_07[u32CoreId]--;
763 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
764 {
765 OsIf_ResumeAllInterrupts();
766 #ifdef _ARM_DS5_C_S32ZE_
767 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
768 #endif
769 }
770 }
771
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_10(void)772 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_10(void)
773 {
774 uint32 msr;
775 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
776
777 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_10[u32CoreId])
778 {
779 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
780 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
781 #else
782 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
783 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
784 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
785 {
786 OsIf_SuspendAllInterrupts();
787 #ifdef _ARM_DS5_C_S32ZE_
788 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
789 #endif
790 }
791 msr_GPT_EXCLUSIVE_AREA_10[u32CoreId] = msr;
792 }
793 reentry_guard_GPT_EXCLUSIVE_AREA_10[u32CoreId]++;
794 }
795
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_10(void)796 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_10(void)
797 {
798 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
799
800 reentry_guard_GPT_EXCLUSIVE_AREA_10[u32CoreId]--;
801 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
802 {
803 OsIf_ResumeAllInterrupts();
804 #ifdef _ARM_DS5_C_S32ZE_
805 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
806 #endif
807 }
808 }
809
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_11(void)810 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_11(void)
811 {
812 uint32 msr;
813 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
814
815 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_11[u32CoreId])
816 {
817 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
818 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
819 #else
820 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
821 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
822 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
823 {
824 OsIf_SuspendAllInterrupts();
825 #ifdef _ARM_DS5_C_S32ZE_
826 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
827 #endif
828 }
829 msr_GPT_EXCLUSIVE_AREA_11[u32CoreId] = msr;
830 }
831 reentry_guard_GPT_EXCLUSIVE_AREA_11[u32CoreId]++;
832 }
833
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_11(void)834 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_11(void)
835 {
836 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
837
838 reentry_guard_GPT_EXCLUSIVE_AREA_11[u32CoreId]--;
839 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
840 {
841 OsIf_ResumeAllInterrupts();
842 #ifdef _ARM_DS5_C_S32ZE_
843 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
844 #endif
845 }
846 }
847
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_17(void)848 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_17(void)
849 {
850 uint32 msr;
851 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
852
853 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_17[u32CoreId])
854 {
855 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
856 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
857 #else
858 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
859 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
860 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
861 {
862 OsIf_SuspendAllInterrupts();
863 #ifdef _ARM_DS5_C_S32ZE_
864 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
865 #endif
866 }
867 msr_GPT_EXCLUSIVE_AREA_17[u32CoreId] = msr;
868 }
869 reentry_guard_GPT_EXCLUSIVE_AREA_17[u32CoreId]++;
870 }
871
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_17(void)872 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_17(void)
873 {
874 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
875
876 reentry_guard_GPT_EXCLUSIVE_AREA_17[u32CoreId]--;
877 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
878 {
879 OsIf_ResumeAllInterrupts();
880 #ifdef _ARM_DS5_C_S32ZE_
881 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
882 #endif
883 }
884 }
885
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_21(void)886 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_21(void)
887 {
888 uint32 msr;
889 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
890
891 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_21[u32CoreId])
892 {
893 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
894 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
895 #else
896 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
897 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
898 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
899 {
900 OsIf_SuspendAllInterrupts();
901 #ifdef _ARM_DS5_C_S32ZE_
902 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
903 #endif
904 }
905 msr_GPT_EXCLUSIVE_AREA_21[u32CoreId] = msr;
906 }
907 reentry_guard_GPT_EXCLUSIVE_AREA_21[u32CoreId]++;
908 }
909
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_21(void)910 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_21(void)
911 {
912 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
913
914 reentry_guard_GPT_EXCLUSIVE_AREA_21[u32CoreId]--;
915 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
916 {
917 OsIf_ResumeAllInterrupts();
918 #ifdef _ARM_DS5_C_S32ZE_
919 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
920 #endif
921 }
922 }
923
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_22(void)924 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_22(void)
925 {
926 uint32 msr;
927 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
928
929 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_22[u32CoreId])
930 {
931 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
932 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
933 #else
934 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
935 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
936 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
937 {
938 OsIf_SuspendAllInterrupts();
939 #ifdef _ARM_DS5_C_S32ZE_
940 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
941 #endif
942 }
943 msr_GPT_EXCLUSIVE_AREA_22[u32CoreId] = msr;
944 }
945 reentry_guard_GPT_EXCLUSIVE_AREA_22[u32CoreId]++;
946 }
947
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_22(void)948 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_22(void)
949 {
950 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
951
952 reentry_guard_GPT_EXCLUSIVE_AREA_22[u32CoreId]--;
953 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_22[u32CoreId])) /*if interrupts were enabled*/
954 {
955 OsIf_ResumeAllInterrupts();
956 #ifdef _ARM_DS5_C_S32ZE_
957 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
958 #endif
959 }
960 }
961
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_23(void)962 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_23(void)
963 {
964 uint32 msr;
965 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
966
967 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_23[u32CoreId])
968 {
969 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
970 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
971 #else
972 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
973 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
974 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
975 {
976 OsIf_SuspendAllInterrupts();
977 #ifdef _ARM_DS5_C_S32ZE_
978 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
979 #endif
980 }
981 msr_GPT_EXCLUSIVE_AREA_23[u32CoreId] = msr;
982 }
983 reentry_guard_GPT_EXCLUSIVE_AREA_23[u32CoreId]++;
984 }
985
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_23(void)986 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_23(void)
987 {
988 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
989
990 reentry_guard_GPT_EXCLUSIVE_AREA_23[u32CoreId]--;
991 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_23[u32CoreId])) /*if interrupts were enabled*/
992 {
993 OsIf_ResumeAllInterrupts();
994 #ifdef _ARM_DS5_C_S32ZE_
995 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
996 #endif
997 }
998 }
999
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_24(void)1000 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_24(void)
1001 {
1002 uint32 msr;
1003 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1004
1005 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_24[u32CoreId])
1006 {
1007 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1008 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1009 #else
1010 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1011 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1012 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1013 {
1014 OsIf_SuspendAllInterrupts();
1015 #ifdef _ARM_DS5_C_S32ZE_
1016 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1017 #endif
1018 }
1019 msr_GPT_EXCLUSIVE_AREA_24[u32CoreId] = msr;
1020 }
1021 reentry_guard_GPT_EXCLUSIVE_AREA_24[u32CoreId]++;
1022 }
1023
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_24(void)1024 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_24(void)
1025 {
1026 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1027
1028 reentry_guard_GPT_EXCLUSIVE_AREA_24[u32CoreId]--;
1029 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_24[u32CoreId])) /*if interrupts were enabled*/
1030 {
1031 OsIf_ResumeAllInterrupts();
1032 #ifdef _ARM_DS5_C_S32ZE_
1033 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1034 #endif
1035 }
1036 }
1037
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_25(void)1038 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_25(void)
1039 {
1040 uint32 msr;
1041 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1042
1043 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_25[u32CoreId])
1044 {
1045 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1046 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1047 #else
1048 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1049 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1050 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1051 {
1052 OsIf_SuspendAllInterrupts();
1053 #ifdef _ARM_DS5_C_S32ZE_
1054 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1055 #endif
1056 }
1057 msr_GPT_EXCLUSIVE_AREA_25[u32CoreId] = msr;
1058 }
1059 reentry_guard_GPT_EXCLUSIVE_AREA_25[u32CoreId]++;
1060 }
1061
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_25(void)1062 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_25(void)
1063 {
1064 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1065
1066 reentry_guard_GPT_EXCLUSIVE_AREA_25[u32CoreId]--;
1067 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_25[u32CoreId])) /*if interrupts were enabled*/
1068 {
1069 OsIf_ResumeAllInterrupts();
1070 #ifdef _ARM_DS5_C_S32ZE_
1071 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1072 #endif
1073 }
1074 }
1075
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_26(void)1076 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_26(void)
1077 {
1078 uint32 msr;
1079 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1080
1081 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_26[u32CoreId])
1082 {
1083 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1084 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1085 #else
1086 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1087 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1088 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1089 {
1090 OsIf_SuspendAllInterrupts();
1091 #ifdef _ARM_DS5_C_S32ZE_
1092 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1093 #endif
1094 }
1095 msr_GPT_EXCLUSIVE_AREA_26[u32CoreId] = msr;
1096 }
1097 reentry_guard_GPT_EXCLUSIVE_AREA_26[u32CoreId]++;
1098 }
1099
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_26(void)1100 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_26(void)
1101 {
1102 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1103
1104 reentry_guard_GPT_EXCLUSIVE_AREA_26[u32CoreId]--;
1105 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_26[u32CoreId])) /*if interrupts were enabled*/
1106 {
1107 OsIf_ResumeAllInterrupts();
1108 #ifdef _ARM_DS5_C_S32ZE_
1109 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1110 #endif
1111 }
1112 }
1113
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_29(void)1114 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_29(void)
1115 {
1116 uint32 msr;
1117 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1118
1119 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_29[u32CoreId])
1120 {
1121 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1122 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1123 #else
1124 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1125 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1126 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1127 {
1128 OsIf_SuspendAllInterrupts();
1129 #ifdef _ARM_DS5_C_S32ZE_
1130 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1131 #endif
1132 }
1133 msr_GPT_EXCLUSIVE_AREA_29[u32CoreId] = msr;
1134 }
1135 reentry_guard_GPT_EXCLUSIVE_AREA_29[u32CoreId]++;
1136 }
1137
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_29(void)1138 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_29(void)
1139 {
1140 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1141
1142 reentry_guard_GPT_EXCLUSIVE_AREA_29[u32CoreId]--;
1143 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_29[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_29[u32CoreId])) /*if interrupts were enabled*/
1144 {
1145 OsIf_ResumeAllInterrupts();
1146 #ifdef _ARM_DS5_C_S32ZE_
1147 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1148 #endif
1149 }
1150 }
1151
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_30(void)1152 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_30(void)
1153 {
1154 uint32 msr;
1155 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1156
1157 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_30[u32CoreId])
1158 {
1159 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1160 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1161 #else
1162 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1163 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1164 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1165 {
1166 OsIf_SuspendAllInterrupts();
1167 #ifdef _ARM_DS5_C_S32ZE_
1168 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1169 #endif
1170 }
1171 msr_GPT_EXCLUSIVE_AREA_30[u32CoreId] = msr;
1172 }
1173 reentry_guard_GPT_EXCLUSIVE_AREA_30[u32CoreId]++;
1174 }
1175
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_30(void)1176 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_30(void)
1177 {
1178 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1179
1180 reentry_guard_GPT_EXCLUSIVE_AREA_30[u32CoreId]--;
1181 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_30[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_30[u32CoreId])) /*if interrupts were enabled*/
1182 {
1183 OsIf_ResumeAllInterrupts();
1184 #ifdef _ARM_DS5_C_S32ZE_
1185 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1186 #endif
1187 }
1188 }
1189
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_31(void)1190 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_31(void)
1191 {
1192 uint32 msr;
1193 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1194
1195 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_31[u32CoreId])
1196 {
1197 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1198 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1199 #else
1200 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1201 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1202 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1203 {
1204 OsIf_SuspendAllInterrupts();
1205 #ifdef _ARM_DS5_C_S32ZE_
1206 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1207 #endif
1208 }
1209 msr_GPT_EXCLUSIVE_AREA_31[u32CoreId] = msr;
1210 }
1211 reentry_guard_GPT_EXCLUSIVE_AREA_31[u32CoreId]++;
1212 }
1213
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_31(void)1214 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_31(void)
1215 {
1216 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1217
1218 reentry_guard_GPT_EXCLUSIVE_AREA_31[u32CoreId]--;
1219 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_31[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_31[u32CoreId])) /*if interrupts were enabled*/
1220 {
1221 OsIf_ResumeAllInterrupts();
1222 #ifdef _ARM_DS5_C_S32ZE_
1223 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1224 #endif
1225 }
1226 }
1227
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_35(void)1228 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_35(void)
1229 {
1230 uint32 msr;
1231 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1232
1233 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_35[u32CoreId])
1234 {
1235 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1236 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1237 #else
1238 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1239 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1240 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1241 {
1242 OsIf_SuspendAllInterrupts();
1243 #ifdef _ARM_DS5_C_S32ZE_
1244 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1245 #endif
1246 }
1247 msr_GPT_EXCLUSIVE_AREA_35[u32CoreId] = msr;
1248 }
1249 reentry_guard_GPT_EXCLUSIVE_AREA_35[u32CoreId]++;
1250 }
1251
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_35(void)1252 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_35(void)
1253 {
1254 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1255
1256 reentry_guard_GPT_EXCLUSIVE_AREA_35[u32CoreId]--;
1257 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_35[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_35[u32CoreId])) /*if interrupts were enabled*/
1258 {
1259 OsIf_ResumeAllInterrupts();
1260 #ifdef _ARM_DS5_C_S32ZE_
1261 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1262 #endif
1263 }
1264 }
1265
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_36(void)1266 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_36(void)
1267 {
1268 uint32 msr;
1269 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1270
1271 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_36[u32CoreId])
1272 {
1273 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1274 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1275 #else
1276 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1277 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1278 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1279 {
1280 OsIf_SuspendAllInterrupts();
1281 #ifdef _ARM_DS5_C_S32ZE_
1282 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1283 #endif
1284 }
1285 msr_GPT_EXCLUSIVE_AREA_36[u32CoreId] = msr;
1286 }
1287 reentry_guard_GPT_EXCLUSIVE_AREA_36[u32CoreId]++;
1288 }
1289
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_36(void)1290 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_36(void)
1291 {
1292 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1293
1294 reentry_guard_GPT_EXCLUSIVE_AREA_36[u32CoreId]--;
1295 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_36[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_36[u32CoreId])) /*if interrupts were enabled*/
1296 {
1297 OsIf_ResumeAllInterrupts();
1298 #ifdef _ARM_DS5_C_S32ZE_
1299 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1300 #endif
1301 }
1302 }
1303
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_38(void)1304 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_38(void)
1305 {
1306 uint32 msr;
1307 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1308
1309 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_38[u32CoreId])
1310 {
1311 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1312 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1313 #else
1314 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1315 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1316 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1317 {
1318 OsIf_SuspendAllInterrupts();
1319 #ifdef _ARM_DS5_C_S32ZE_
1320 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1321 #endif
1322 }
1323 msr_GPT_EXCLUSIVE_AREA_38[u32CoreId] = msr;
1324 }
1325 reentry_guard_GPT_EXCLUSIVE_AREA_38[u32CoreId]++;
1326 }
1327
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_38(void)1328 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_38(void)
1329 {
1330 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1331
1332 reentry_guard_GPT_EXCLUSIVE_AREA_38[u32CoreId]--;
1333 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_38[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_38[u32CoreId])) /*if interrupts were enabled*/
1334 {
1335 OsIf_ResumeAllInterrupts();
1336 #ifdef _ARM_DS5_C_S32ZE_
1337 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1338 #endif
1339 }
1340 }
1341
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_39(void)1342 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_39(void)
1343 {
1344 uint32 msr;
1345 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1346
1347 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_39[u32CoreId])
1348 {
1349 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1350 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1351 #else
1352 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1353 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1354 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1355 {
1356 OsIf_SuspendAllInterrupts();
1357 #ifdef _ARM_DS5_C_S32ZE_
1358 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1359 #endif
1360 }
1361 msr_GPT_EXCLUSIVE_AREA_39[u32CoreId] = msr;
1362 }
1363 reentry_guard_GPT_EXCLUSIVE_AREA_39[u32CoreId]++;
1364 }
1365
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_39(void)1366 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_39(void)
1367 {
1368 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1369
1370 reentry_guard_GPT_EXCLUSIVE_AREA_39[u32CoreId]--;
1371 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_39[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_39[u32CoreId])) /*if interrupts were enabled*/
1372 {
1373 OsIf_ResumeAllInterrupts();
1374 #ifdef _ARM_DS5_C_S32ZE_
1375 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1376 #endif
1377 }
1378 }
1379
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_40(void)1380 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_40(void)
1381 {
1382 uint32 msr;
1383 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1384
1385 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_40[u32CoreId])
1386 {
1387 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1388 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1389 #else
1390 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1391 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1392 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1393 {
1394 OsIf_SuspendAllInterrupts();
1395 #ifdef _ARM_DS5_C_S32ZE_
1396 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1397 #endif
1398 }
1399 msr_GPT_EXCLUSIVE_AREA_40[u32CoreId] = msr;
1400 }
1401 reentry_guard_GPT_EXCLUSIVE_AREA_40[u32CoreId]++;
1402 }
1403
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_40(void)1404 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_40(void)
1405 {
1406 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1407
1408 reentry_guard_GPT_EXCLUSIVE_AREA_40[u32CoreId]--;
1409 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_40[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_40[u32CoreId])) /*if interrupts were enabled*/
1410 {
1411 OsIf_ResumeAllInterrupts();
1412 #ifdef _ARM_DS5_C_S32ZE_
1413 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1414 #endif
1415 }
1416 }
1417
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_41(void)1418 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_41(void)
1419 {
1420 uint32 msr;
1421 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1422
1423 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_41[u32CoreId])
1424 {
1425 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1426 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1427 #else
1428 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1429 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1430 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1431 {
1432 OsIf_SuspendAllInterrupts();
1433 #ifdef _ARM_DS5_C_S32ZE_
1434 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1435 #endif
1436 }
1437 msr_GPT_EXCLUSIVE_AREA_41[u32CoreId] = msr;
1438 }
1439 reentry_guard_GPT_EXCLUSIVE_AREA_41[u32CoreId]++;
1440 }
1441
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_41(void)1442 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_41(void)
1443 {
1444 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1445
1446 reentry_guard_GPT_EXCLUSIVE_AREA_41[u32CoreId]--;
1447 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_41[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_41[u32CoreId])) /*if interrupts were enabled*/
1448 {
1449 OsIf_ResumeAllInterrupts();
1450 #ifdef _ARM_DS5_C_S32ZE_
1451 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1452 #endif
1453 }
1454 }
1455
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_42(void)1456 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_42(void)
1457 {
1458 uint32 msr;
1459 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1460
1461 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_42[u32CoreId])
1462 {
1463 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1464 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1465 #else
1466 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1467 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1468 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1469 {
1470 OsIf_SuspendAllInterrupts();
1471 #ifdef _ARM_DS5_C_S32ZE_
1472 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1473 #endif
1474 }
1475 msr_GPT_EXCLUSIVE_AREA_42[u32CoreId] = msr;
1476 }
1477 reentry_guard_GPT_EXCLUSIVE_AREA_42[u32CoreId]++;
1478 }
1479
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_42(void)1480 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_42(void)
1481 {
1482 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1483
1484 reentry_guard_GPT_EXCLUSIVE_AREA_42[u32CoreId]--;
1485 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_42[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_42[u32CoreId])) /*if interrupts were enabled*/
1486 {
1487 OsIf_ResumeAllInterrupts();
1488 #ifdef _ARM_DS5_C_S32ZE_
1489 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1490 #endif
1491 }
1492 }
1493
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_43(void)1494 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_43(void)
1495 {
1496 uint32 msr;
1497 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1498
1499 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_43[u32CoreId])
1500 {
1501 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1502 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1503 #else
1504 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1505 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1506 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1507 {
1508 OsIf_SuspendAllInterrupts();
1509 #ifdef _ARM_DS5_C_S32ZE_
1510 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1511 #endif
1512 }
1513 msr_GPT_EXCLUSIVE_AREA_43[u32CoreId] = msr;
1514 }
1515 reentry_guard_GPT_EXCLUSIVE_AREA_43[u32CoreId]++;
1516 }
1517
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_43(void)1518 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_43(void)
1519 {
1520 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1521
1522 reentry_guard_GPT_EXCLUSIVE_AREA_43[u32CoreId]--;
1523 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_43[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_43[u32CoreId])) /*if interrupts were enabled*/
1524 {
1525 OsIf_ResumeAllInterrupts();
1526 #ifdef _ARM_DS5_C_S32ZE_
1527 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1528 #endif
1529 }
1530 }
1531
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_44(void)1532 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_44(void)
1533 {
1534 uint32 msr;
1535 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1536
1537 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_44[u32CoreId])
1538 {
1539 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1540 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1541 #else
1542 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1543 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1544 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1545 {
1546 OsIf_SuspendAllInterrupts();
1547 #ifdef _ARM_DS5_C_S32ZE_
1548 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1549 #endif
1550 }
1551 msr_GPT_EXCLUSIVE_AREA_44[u32CoreId] = msr;
1552 }
1553 reentry_guard_GPT_EXCLUSIVE_AREA_44[u32CoreId]++;
1554 }
1555
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_44(void)1556 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_44(void)
1557 {
1558 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1559
1560 reentry_guard_GPT_EXCLUSIVE_AREA_44[u32CoreId]--;
1561 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_44[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_44[u32CoreId])) /*if interrupts were enabled*/
1562 {
1563 OsIf_ResumeAllInterrupts();
1564 #ifdef _ARM_DS5_C_S32ZE_
1565 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1566 #endif
1567 }
1568 }
1569
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_45(void)1570 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_45(void)
1571 {
1572 uint32 msr;
1573 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1574
1575 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_45[u32CoreId])
1576 {
1577 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1578 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1579 #else
1580 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1581 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1582 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1583 {
1584 OsIf_SuspendAllInterrupts();
1585 #ifdef _ARM_DS5_C_S32ZE_
1586 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1587 #endif
1588 }
1589 msr_GPT_EXCLUSIVE_AREA_45[u32CoreId] = msr;
1590 }
1591 reentry_guard_GPT_EXCLUSIVE_AREA_45[u32CoreId]++;
1592 }
1593
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_45(void)1594 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_45(void)
1595 {
1596 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1597
1598 reentry_guard_GPT_EXCLUSIVE_AREA_45[u32CoreId]--;
1599 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_45[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_45[u32CoreId])) /*if interrupts were enabled*/
1600 {
1601 OsIf_ResumeAllInterrupts();
1602 #ifdef _ARM_DS5_C_S32ZE_
1603 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1604 #endif
1605 }
1606 }
1607
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_46(void)1608 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_46(void)
1609 {
1610 uint32 msr;
1611 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1612
1613 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_46[u32CoreId])
1614 {
1615 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1616 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1617 #else
1618 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1619 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1620 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1621 {
1622 OsIf_SuspendAllInterrupts();
1623 #ifdef _ARM_DS5_C_S32ZE_
1624 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1625 #endif
1626 }
1627 msr_GPT_EXCLUSIVE_AREA_46[u32CoreId] = msr;
1628 }
1629 reentry_guard_GPT_EXCLUSIVE_AREA_46[u32CoreId]++;
1630 }
1631
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_46(void)1632 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_46(void)
1633 {
1634 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1635
1636 reentry_guard_GPT_EXCLUSIVE_AREA_46[u32CoreId]--;
1637 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_46[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_46[u32CoreId])) /*if interrupts were enabled*/
1638 {
1639 OsIf_ResumeAllInterrupts();
1640 #ifdef _ARM_DS5_C_S32ZE_
1641 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1642 #endif
1643 }
1644 }
1645
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_50(void)1646 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_50(void)
1647 {
1648 uint32 msr;
1649 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1650
1651 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_50[u32CoreId])
1652 {
1653 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1654 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1655 #else
1656 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1657 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1658 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1659 {
1660 OsIf_SuspendAllInterrupts();
1661 #ifdef _ARM_DS5_C_S32ZE_
1662 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1663 #endif
1664 }
1665 msr_GPT_EXCLUSIVE_AREA_50[u32CoreId] = msr;
1666 }
1667 reentry_guard_GPT_EXCLUSIVE_AREA_50[u32CoreId]++;
1668 }
1669
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_50(void)1670 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_50(void)
1671 {
1672 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1673
1674 reentry_guard_GPT_EXCLUSIVE_AREA_50[u32CoreId]--;
1675 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_50[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_50[u32CoreId])) /*if interrupts were enabled*/
1676 {
1677 OsIf_ResumeAllInterrupts();
1678 #ifdef _ARM_DS5_C_S32ZE_
1679 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1680 #endif
1681 }
1682 }
1683
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_51(void)1684 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_51(void)
1685 {
1686 uint32 msr;
1687 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1688
1689 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_51[u32CoreId])
1690 {
1691 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1692 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1693 #else
1694 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1695 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1696 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1697 {
1698 OsIf_SuspendAllInterrupts();
1699 #ifdef _ARM_DS5_C_S32ZE_
1700 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1701 #endif
1702 }
1703 msr_GPT_EXCLUSIVE_AREA_51[u32CoreId] = msr;
1704 }
1705 reentry_guard_GPT_EXCLUSIVE_AREA_51[u32CoreId]++;
1706 }
1707
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_51(void)1708 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_51(void)
1709 {
1710 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1711
1712 reentry_guard_GPT_EXCLUSIVE_AREA_51[u32CoreId]--;
1713 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_51[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_51[u32CoreId])) /*if interrupts were enabled*/
1714 {
1715 OsIf_ResumeAllInterrupts();
1716 #ifdef _ARM_DS5_C_S32ZE_
1717 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1718 #endif
1719 }
1720 }
1721
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_52(void)1722 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_52(void)
1723 {
1724 uint32 msr;
1725 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1726
1727 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_52[u32CoreId])
1728 {
1729 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1730 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1731 #else
1732 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1733 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1734 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1735 {
1736 OsIf_SuspendAllInterrupts();
1737 #ifdef _ARM_DS5_C_S32ZE_
1738 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1739 #endif
1740 }
1741 msr_GPT_EXCLUSIVE_AREA_52[u32CoreId] = msr;
1742 }
1743 reentry_guard_GPT_EXCLUSIVE_AREA_52[u32CoreId]++;
1744 }
1745
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_52(void)1746 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_52(void)
1747 {
1748 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1749
1750 reentry_guard_GPT_EXCLUSIVE_AREA_52[u32CoreId]--;
1751 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_52[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_52[u32CoreId])) /*if interrupts were enabled*/
1752 {
1753 OsIf_ResumeAllInterrupts();
1754 #ifdef _ARM_DS5_C_S32ZE_
1755 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1756 #endif
1757 }
1758 }
1759
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_53(void)1760 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_53(void)
1761 {
1762 uint32 msr;
1763 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1764
1765 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_53[u32CoreId])
1766 {
1767 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1768 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1769 #else
1770 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1771 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1772 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1773 {
1774 OsIf_SuspendAllInterrupts();
1775 #ifdef _ARM_DS5_C_S32ZE_
1776 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1777 #endif
1778 }
1779 msr_GPT_EXCLUSIVE_AREA_53[u32CoreId] = msr;
1780 }
1781 reentry_guard_GPT_EXCLUSIVE_AREA_53[u32CoreId]++;
1782 }
1783
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_53(void)1784 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_53(void)
1785 {
1786 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1787
1788 reentry_guard_GPT_EXCLUSIVE_AREA_53[u32CoreId]--;
1789 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_53[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_53[u32CoreId])) /*if interrupts were enabled*/
1790 {
1791 OsIf_ResumeAllInterrupts();
1792 #ifdef _ARM_DS5_C_S32ZE_
1793 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1794 #endif
1795 }
1796 }
1797
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_54(void)1798 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_54(void)
1799 {
1800 uint32 msr;
1801 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1802
1803 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_54[u32CoreId])
1804 {
1805 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1806 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1807 #else
1808 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1809 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1810 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1811 {
1812 OsIf_SuspendAllInterrupts();
1813 #ifdef _ARM_DS5_C_S32ZE_
1814 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1815 #endif
1816 }
1817 msr_GPT_EXCLUSIVE_AREA_54[u32CoreId] = msr;
1818 }
1819 reentry_guard_GPT_EXCLUSIVE_AREA_54[u32CoreId]++;
1820 }
1821
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_54(void)1822 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_54(void)
1823 {
1824 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1825
1826 reentry_guard_GPT_EXCLUSIVE_AREA_54[u32CoreId]--;
1827 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_54[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_54[u32CoreId])) /*if interrupts were enabled*/
1828 {
1829 OsIf_ResumeAllInterrupts();
1830 #ifdef _ARM_DS5_C_S32ZE_
1831 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1832 #endif
1833 }
1834 }
1835
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_55(void)1836 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_55(void)
1837 {
1838 uint32 msr;
1839 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1840
1841 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_55[u32CoreId])
1842 {
1843 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1844 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1845 #else
1846 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1847 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1848 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1849 {
1850 OsIf_SuspendAllInterrupts();
1851 #ifdef _ARM_DS5_C_S32ZE_
1852 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1853 #endif
1854 }
1855 msr_GPT_EXCLUSIVE_AREA_55[u32CoreId] = msr;
1856 }
1857 reentry_guard_GPT_EXCLUSIVE_AREA_55[u32CoreId]++;
1858 }
1859
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_55(void)1860 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_55(void)
1861 {
1862 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1863
1864 reentry_guard_GPT_EXCLUSIVE_AREA_55[u32CoreId]--;
1865 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_55[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_55[u32CoreId])) /*if interrupts were enabled*/
1866 {
1867 OsIf_ResumeAllInterrupts();
1868 #ifdef _ARM_DS5_C_S32ZE_
1869 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1870 #endif
1871 }
1872 }
1873
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_56(void)1874 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_56(void)
1875 {
1876 uint32 msr;
1877 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1878
1879 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_56[u32CoreId])
1880 {
1881 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1882 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1883 #else
1884 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1885 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1886 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1887 {
1888 OsIf_SuspendAllInterrupts();
1889 #ifdef _ARM_DS5_C_S32ZE_
1890 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1891 #endif
1892 }
1893 msr_GPT_EXCLUSIVE_AREA_56[u32CoreId] = msr;
1894 }
1895 reentry_guard_GPT_EXCLUSIVE_AREA_56[u32CoreId]++;
1896 }
1897
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_56(void)1898 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_56(void)
1899 {
1900 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1901
1902 reentry_guard_GPT_EXCLUSIVE_AREA_56[u32CoreId]--;
1903 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_56[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_56[u32CoreId])) /*if interrupts were enabled*/
1904 {
1905 OsIf_ResumeAllInterrupts();
1906 #ifdef _ARM_DS5_C_S32ZE_
1907 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1908 #endif
1909 }
1910 }
1911
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_60(void)1912 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_60(void)
1913 {
1914 uint32 msr;
1915 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1916
1917 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_60[u32CoreId])
1918 {
1919 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1920 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1921 #else
1922 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1923 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1924 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1925 {
1926 OsIf_SuspendAllInterrupts();
1927 #ifdef _ARM_DS5_C_S32ZE_
1928 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1929 #endif
1930 }
1931 msr_GPT_EXCLUSIVE_AREA_60[u32CoreId] = msr;
1932 }
1933 reentry_guard_GPT_EXCLUSIVE_AREA_60[u32CoreId]++;
1934 }
1935
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_60(void)1936 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_60(void)
1937 {
1938 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1939
1940 reentry_guard_GPT_EXCLUSIVE_AREA_60[u32CoreId]--;
1941 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_60[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_60[u32CoreId])) /*if interrupts were enabled*/
1942 {
1943 OsIf_ResumeAllInterrupts();
1944 #ifdef _ARM_DS5_C_S32ZE_
1945 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1946 #endif
1947 }
1948 }
1949
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_61(void)1950 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_61(void)
1951 {
1952 uint32 msr;
1953 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1954
1955 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_61[u32CoreId])
1956 {
1957 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1958 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1959 #else
1960 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1961 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1962 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1963 {
1964 OsIf_SuspendAllInterrupts();
1965 #ifdef _ARM_DS5_C_S32ZE_
1966 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1967 #endif
1968 }
1969 msr_GPT_EXCLUSIVE_AREA_61[u32CoreId] = msr;
1970 }
1971 reentry_guard_GPT_EXCLUSIVE_AREA_61[u32CoreId]++;
1972 }
1973
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_61(void)1974 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_61(void)
1975 {
1976 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1977
1978 reentry_guard_GPT_EXCLUSIVE_AREA_61[u32CoreId]--;
1979 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_61[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_61[u32CoreId])) /*if interrupts were enabled*/
1980 {
1981 OsIf_ResumeAllInterrupts();
1982 #ifdef _ARM_DS5_C_S32ZE_
1983 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1984 #endif
1985 }
1986 }
1987
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_62(void)1988 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_62(void)
1989 {
1990 uint32 msr;
1991 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1992
1993 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_62[u32CoreId])
1994 {
1995 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1996 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1997 #else
1998 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1999 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2000 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2001 {
2002 OsIf_SuspendAllInterrupts();
2003 #ifdef _ARM_DS5_C_S32ZE_
2004 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2005 #endif
2006 }
2007 msr_GPT_EXCLUSIVE_AREA_62[u32CoreId] = msr;
2008 }
2009 reentry_guard_GPT_EXCLUSIVE_AREA_62[u32CoreId]++;
2010 }
2011
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_62(void)2012 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_62(void)
2013 {
2014 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2015
2016 reentry_guard_GPT_EXCLUSIVE_AREA_62[u32CoreId]--;
2017 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_62[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_62[u32CoreId])) /*if interrupts were enabled*/
2018 {
2019 OsIf_ResumeAllInterrupts();
2020 #ifdef _ARM_DS5_C_S32ZE_
2021 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2022 #endif
2023 }
2024 }
2025
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_63(void)2026 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_63(void)
2027 {
2028 uint32 msr;
2029 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2030
2031 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_63[u32CoreId])
2032 {
2033 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2034 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2035 #else
2036 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2037 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2038 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2039 {
2040 OsIf_SuspendAllInterrupts();
2041 #ifdef _ARM_DS5_C_S32ZE_
2042 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2043 #endif
2044 }
2045 msr_GPT_EXCLUSIVE_AREA_63[u32CoreId] = msr;
2046 }
2047 reentry_guard_GPT_EXCLUSIVE_AREA_63[u32CoreId]++;
2048 }
2049
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_63(void)2050 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_63(void)
2051 {
2052 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2053
2054 reentry_guard_GPT_EXCLUSIVE_AREA_63[u32CoreId]--;
2055 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_63[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_63[u32CoreId])) /*if interrupts were enabled*/
2056 {
2057 OsIf_ResumeAllInterrupts();
2058 #ifdef _ARM_DS5_C_S32ZE_
2059 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2060 #endif
2061 }
2062 }
2063
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_64(void)2064 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_64(void)
2065 {
2066 uint32 msr;
2067 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2068
2069 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_64[u32CoreId])
2070 {
2071 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2072 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2073 #else
2074 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2075 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2076 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2077 {
2078 OsIf_SuspendAllInterrupts();
2079 #ifdef _ARM_DS5_C_S32ZE_
2080 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2081 #endif
2082 }
2083 msr_GPT_EXCLUSIVE_AREA_64[u32CoreId] = msr;
2084 }
2085 reentry_guard_GPT_EXCLUSIVE_AREA_64[u32CoreId]++;
2086 }
2087
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_64(void)2088 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_64(void)
2089 {
2090 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2091
2092 reentry_guard_GPT_EXCLUSIVE_AREA_64[u32CoreId]--;
2093 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_64[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_64[u32CoreId])) /*if interrupts were enabled*/
2094 {
2095 OsIf_ResumeAllInterrupts();
2096 #ifdef _ARM_DS5_C_S32ZE_
2097 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2098 #endif
2099 }
2100 }
2101
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_65(void)2102 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_65(void)
2103 {
2104 uint32 msr;
2105 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2106
2107 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_65[u32CoreId])
2108 {
2109 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2110 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2111 #else
2112 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2113 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2114 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2115 {
2116 OsIf_SuspendAllInterrupts();
2117 #ifdef _ARM_DS5_C_S32ZE_
2118 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2119 #endif
2120 }
2121 msr_GPT_EXCLUSIVE_AREA_65[u32CoreId] = msr;
2122 }
2123 reentry_guard_GPT_EXCLUSIVE_AREA_65[u32CoreId]++;
2124 }
2125
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_65(void)2126 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_65(void)
2127 {
2128 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2129
2130 reentry_guard_GPT_EXCLUSIVE_AREA_65[u32CoreId]--;
2131 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_65[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_65[u32CoreId])) /*if interrupts were enabled*/
2132 {
2133 OsIf_ResumeAllInterrupts();
2134 #ifdef _ARM_DS5_C_S32ZE_
2135 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2136 #endif
2137 }
2138 }
2139
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_66(void)2140 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_66(void)
2141 {
2142 uint32 msr;
2143 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2144
2145 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_66[u32CoreId])
2146 {
2147 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2148 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2149 #else
2150 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2151 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2152 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2153 {
2154 OsIf_SuspendAllInterrupts();
2155 #ifdef _ARM_DS5_C_S32ZE_
2156 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2157 #endif
2158 }
2159 msr_GPT_EXCLUSIVE_AREA_66[u32CoreId] = msr;
2160 }
2161 reentry_guard_GPT_EXCLUSIVE_AREA_66[u32CoreId]++;
2162 }
2163
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_66(void)2164 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_66(void)
2165 {
2166 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2167
2168 reentry_guard_GPT_EXCLUSIVE_AREA_66[u32CoreId]--;
2169 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_66[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_66[u32CoreId])) /*if interrupts were enabled*/
2170 {
2171 OsIf_ResumeAllInterrupts();
2172 #ifdef _ARM_DS5_C_S32ZE_
2173 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2174 #endif
2175 }
2176 }
2177
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_67(void)2178 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_67(void)
2179 {
2180 uint32 msr;
2181 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2182
2183 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_67[u32CoreId])
2184 {
2185 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2186 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2187 #else
2188 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2189 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2190 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2191 {
2192 OsIf_SuspendAllInterrupts();
2193 #ifdef _ARM_DS5_C_S32ZE_
2194 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2195 #endif
2196 }
2197 msr_GPT_EXCLUSIVE_AREA_67[u32CoreId] = msr;
2198 }
2199 reentry_guard_GPT_EXCLUSIVE_AREA_67[u32CoreId]++;
2200 }
2201
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_67(void)2202 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_67(void)
2203 {
2204 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2205
2206 reentry_guard_GPT_EXCLUSIVE_AREA_67[u32CoreId]--;
2207 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_67[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_67[u32CoreId])) /*if interrupts were enabled*/
2208 {
2209 OsIf_ResumeAllInterrupts();
2210 #ifdef _ARM_DS5_C_S32ZE_
2211 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2212 #endif
2213 }
2214 }
2215
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_68(void)2216 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_68(void)
2217 {
2218 uint32 msr;
2219 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2220
2221 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_68[u32CoreId])
2222 {
2223 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2224 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2225 #else
2226 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2227 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2228 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2229 {
2230 OsIf_SuspendAllInterrupts();
2231 #ifdef _ARM_DS5_C_S32ZE_
2232 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2233 #endif
2234 }
2235 msr_GPT_EXCLUSIVE_AREA_68[u32CoreId] = msr;
2236 }
2237 reentry_guard_GPT_EXCLUSIVE_AREA_68[u32CoreId]++;
2238 }
2239
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_68(void)2240 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_68(void)
2241 {
2242 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2243
2244 reentry_guard_GPT_EXCLUSIVE_AREA_68[u32CoreId]--;
2245 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_68[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_68[u32CoreId])) /*if interrupts were enabled*/
2246 {
2247 OsIf_ResumeAllInterrupts();
2248 #ifdef _ARM_DS5_C_S32ZE_
2249 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2250 #endif
2251 }
2252 }
2253
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_69(void)2254 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_69(void)
2255 {
2256 uint32 msr;
2257 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2258
2259 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_69[u32CoreId])
2260 {
2261 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2262 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2263 #else
2264 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2265 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2266 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2267 {
2268 OsIf_SuspendAllInterrupts();
2269 #ifdef _ARM_DS5_C_S32ZE_
2270 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2271 #endif
2272 }
2273 msr_GPT_EXCLUSIVE_AREA_69[u32CoreId] = msr;
2274 }
2275 reentry_guard_GPT_EXCLUSIVE_AREA_69[u32CoreId]++;
2276 }
2277
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_69(void)2278 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_69(void)
2279 {
2280 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2281
2282 reentry_guard_GPT_EXCLUSIVE_AREA_69[u32CoreId]--;
2283 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_69[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_69[u32CoreId])) /*if interrupts were enabled*/
2284 {
2285 OsIf_ResumeAllInterrupts();
2286 #ifdef _ARM_DS5_C_S32ZE_
2287 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2288 #endif
2289 }
2290 }
2291
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_70(void)2292 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_70(void)
2293 {
2294 uint32 msr;
2295 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2296
2297 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_70[u32CoreId])
2298 {
2299 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2300 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2301 #else
2302 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2303 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2304 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2305 {
2306 OsIf_SuspendAllInterrupts();
2307 #ifdef _ARM_DS5_C_S32ZE_
2308 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2309 #endif
2310 }
2311 msr_GPT_EXCLUSIVE_AREA_70[u32CoreId] = msr;
2312 }
2313 reentry_guard_GPT_EXCLUSIVE_AREA_70[u32CoreId]++;
2314 }
2315
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_70(void)2316 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_70(void)
2317 {
2318 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2319
2320 reentry_guard_GPT_EXCLUSIVE_AREA_70[u32CoreId]--;
2321 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_70[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_70[u32CoreId])) /*if interrupts were enabled*/
2322 {
2323 OsIf_ResumeAllInterrupts();
2324 #ifdef _ARM_DS5_C_S32ZE_
2325 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2326 #endif
2327 }
2328 }
2329
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_71(void)2330 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_71(void)
2331 {
2332 uint32 msr;
2333 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2334
2335 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_71[u32CoreId])
2336 {
2337 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2338 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2339 #else
2340 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2341 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2342 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2343 {
2344 OsIf_SuspendAllInterrupts();
2345 #ifdef _ARM_DS5_C_S32ZE_
2346 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2347 #endif
2348 }
2349 msr_GPT_EXCLUSIVE_AREA_71[u32CoreId] = msr;
2350 }
2351 reentry_guard_GPT_EXCLUSIVE_AREA_71[u32CoreId]++;
2352 }
2353
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_71(void)2354 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_71(void)
2355 {
2356 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2357
2358 reentry_guard_GPT_EXCLUSIVE_AREA_71[u32CoreId]--;
2359 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_71[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_71[u32CoreId])) /*if interrupts were enabled*/
2360 {
2361 OsIf_ResumeAllInterrupts();
2362 #ifdef _ARM_DS5_C_S32ZE_
2363 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2364 #endif
2365 }
2366 }
2367
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_72(void)2368 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_72(void)
2369 {
2370 uint32 msr;
2371 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2372
2373 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_72[u32CoreId])
2374 {
2375 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2376 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2377 #else
2378 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2379 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2380 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2381 {
2382 OsIf_SuspendAllInterrupts();
2383 #ifdef _ARM_DS5_C_S32ZE_
2384 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2385 #endif
2386 }
2387 msr_GPT_EXCLUSIVE_AREA_72[u32CoreId] = msr;
2388 }
2389 reentry_guard_GPT_EXCLUSIVE_AREA_72[u32CoreId]++;
2390 }
2391
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_72(void)2392 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_72(void)
2393 {
2394 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2395
2396 reentry_guard_GPT_EXCLUSIVE_AREA_72[u32CoreId]--;
2397 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_72[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_72[u32CoreId])) /*if interrupts were enabled*/
2398 {
2399 OsIf_ResumeAllInterrupts();
2400 #ifdef _ARM_DS5_C_S32ZE_
2401 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2402 #endif
2403 }
2404 }
2405
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_73(void)2406 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_73(void)
2407 {
2408 uint32 msr;
2409 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2410
2411 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_73[u32CoreId])
2412 {
2413 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2414 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2415 #else
2416 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2417 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2418 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2419 {
2420 OsIf_SuspendAllInterrupts();
2421 #ifdef _ARM_DS5_C_S32ZE_
2422 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2423 #endif
2424 }
2425 msr_GPT_EXCLUSIVE_AREA_73[u32CoreId] = msr;
2426 }
2427 reentry_guard_GPT_EXCLUSIVE_AREA_73[u32CoreId]++;
2428 }
2429
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_73(void)2430 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_73(void)
2431 {
2432 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2433
2434 reentry_guard_GPT_EXCLUSIVE_AREA_73[u32CoreId]--;
2435 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_73[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_73[u32CoreId])) /*if interrupts were enabled*/
2436 {
2437 OsIf_ResumeAllInterrupts();
2438 #ifdef _ARM_DS5_C_S32ZE_
2439 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2440 #endif
2441 }
2442 }
2443
2444
2445 #ifdef MCAL_TESTING_ENVIRONMENT
2446 /**
2447 @brief This function checks that all entered exclusive areas were also exited.
2448 @details This function checks that all entered exclusive areas were also exited. The check
2449 is done by verifying that all reentry_guard_* static variables are back to the
2450 zero value.
2451
2452 @param[in] void No input parameters
2453 @return void This function does not return a value. Test asserts are used instead.
2454
2455 @pre None
2456 @post None
2457
2458 @remarks Covers
2459 @remarks Implements
2460 */
SchM_Check_gpt(void)2461 void SchM_Check_gpt(void)
2462 {
2463 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2464
2465 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_00[u32CoreId]);
2466 reentry_guard_GPT_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_00 for the next test in the suite*/
2467
2468 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_01[u32CoreId]);
2469 reentry_guard_GPT_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_01 for the next test in the suite*/
2470
2471 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_02[u32CoreId]);
2472 reentry_guard_GPT_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_02 for the next test in the suite*/
2473
2474 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_03[u32CoreId]);
2475 reentry_guard_GPT_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_03 for the next test in the suite*/
2476
2477 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_04[u32CoreId]);
2478 reentry_guard_GPT_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_04 for the next test in the suite*/
2479
2480 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_05[u32CoreId]);
2481 reentry_guard_GPT_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_05 for the next test in the suite*/
2482
2483 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_06[u32CoreId]);
2484 reentry_guard_GPT_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_06 for the next test in the suite*/
2485
2486 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_07[u32CoreId]);
2487 reentry_guard_GPT_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_07 for the next test in the suite*/
2488
2489 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_10[u32CoreId]);
2490 reentry_guard_GPT_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_10 for the next test in the suite*/
2491
2492 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_11[u32CoreId]);
2493 reentry_guard_GPT_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_11 for the next test in the suite*/
2494
2495 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_17[u32CoreId]);
2496 reentry_guard_GPT_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_17 for the next test in the suite*/
2497
2498 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_21[u32CoreId]);
2499 reentry_guard_GPT_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_21 for the next test in the suite*/
2500
2501 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_22[u32CoreId]);
2502 reentry_guard_GPT_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_22 for the next test in the suite*/
2503
2504 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_23[u32CoreId]);
2505 reentry_guard_GPT_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_23 for the next test in the suite*/
2506
2507 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_24[u32CoreId]);
2508 reentry_guard_GPT_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_24 for the next test in the suite*/
2509
2510 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_25[u32CoreId]);
2511 reentry_guard_GPT_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_25 for the next test in the suite*/
2512
2513 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_26[u32CoreId]);
2514 reentry_guard_GPT_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_26 for the next test in the suite*/
2515
2516 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_29[u32CoreId]);
2517 reentry_guard_GPT_EXCLUSIVE_AREA_29[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_29 for the next test in the suite*/
2518
2519 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_30[u32CoreId]);
2520 reentry_guard_GPT_EXCLUSIVE_AREA_30[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_30 for the next test in the suite*/
2521
2522 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_31[u32CoreId]);
2523 reentry_guard_GPT_EXCLUSIVE_AREA_31[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_31 for the next test in the suite*/
2524
2525 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_35[u32CoreId]);
2526 reentry_guard_GPT_EXCLUSIVE_AREA_35[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_35 for the next test in the suite*/
2527
2528 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_36[u32CoreId]);
2529 reentry_guard_GPT_EXCLUSIVE_AREA_36[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_36 for the next test in the suite*/
2530
2531 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_38[u32CoreId]);
2532 reentry_guard_GPT_EXCLUSIVE_AREA_38[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_38 for the next test in the suite*/
2533
2534 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_39[u32CoreId]);
2535 reentry_guard_GPT_EXCLUSIVE_AREA_39[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_39 for the next test in the suite*/
2536
2537 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_40[u32CoreId]);
2538 reentry_guard_GPT_EXCLUSIVE_AREA_40[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_40 for the next test in the suite*/
2539
2540 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_41[u32CoreId]);
2541 reentry_guard_GPT_EXCLUSIVE_AREA_41[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_41 for the next test in the suite*/
2542
2543 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_42[u32CoreId]);
2544 reentry_guard_GPT_EXCLUSIVE_AREA_42[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_42 for the next test in the suite*/
2545
2546 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_43[u32CoreId]);
2547 reentry_guard_GPT_EXCLUSIVE_AREA_43[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_43 for the next test in the suite*/
2548
2549 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_44[u32CoreId]);
2550 reentry_guard_GPT_EXCLUSIVE_AREA_44[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_44 for the next test in the suite*/
2551
2552 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_45[u32CoreId]);
2553 reentry_guard_GPT_EXCLUSIVE_AREA_45[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_45 for the next test in the suite*/
2554
2555 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_46[u32CoreId]);
2556 reentry_guard_GPT_EXCLUSIVE_AREA_46[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_46 for the next test in the suite*/
2557
2558 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_50[u32CoreId]);
2559 reentry_guard_GPT_EXCLUSIVE_AREA_50[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_50 for the next test in the suite*/
2560
2561 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_51[u32CoreId]);
2562 reentry_guard_GPT_EXCLUSIVE_AREA_51[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_51 for the next test in the suite*/
2563
2564 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_52[u32CoreId]);
2565 reentry_guard_GPT_EXCLUSIVE_AREA_52[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_52 for the next test in the suite*/
2566
2567 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_53[u32CoreId]);
2568 reentry_guard_GPT_EXCLUSIVE_AREA_53[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_53 for the next test in the suite*/
2569
2570 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_54[u32CoreId]);
2571 reentry_guard_GPT_EXCLUSIVE_AREA_54[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_54 for the next test in the suite*/
2572
2573 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_55[u32CoreId]);
2574 reentry_guard_GPT_EXCLUSIVE_AREA_55[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_55 for the next test in the suite*/
2575
2576 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_56[u32CoreId]);
2577 reentry_guard_GPT_EXCLUSIVE_AREA_56[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_56 for the next test in the suite*/
2578
2579 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_60[u32CoreId]);
2580 reentry_guard_GPT_EXCLUSIVE_AREA_60[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_60 for the next test in the suite*/
2581
2582 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_61[u32CoreId]);
2583 reentry_guard_GPT_EXCLUSIVE_AREA_61[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_61 for the next test in the suite*/
2584
2585 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_62[u32CoreId]);
2586 reentry_guard_GPT_EXCLUSIVE_AREA_62[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_62 for the next test in the suite*/
2587
2588 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_63[u32CoreId]);
2589 reentry_guard_GPT_EXCLUSIVE_AREA_63[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_63 for the next test in the suite*/
2590
2591 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_64[u32CoreId]);
2592 reentry_guard_GPT_EXCLUSIVE_AREA_64[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_64 for the next test in the suite*/
2593
2594 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_65[u32CoreId]);
2595 reentry_guard_GPT_EXCLUSIVE_AREA_65[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_65 for the next test in the suite*/
2596
2597 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_66[u32CoreId]);
2598 reentry_guard_GPT_EXCLUSIVE_AREA_66[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_66 for the next test in the suite*/
2599
2600 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_67[u32CoreId]);
2601 reentry_guard_GPT_EXCLUSIVE_AREA_67[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_67 for the next test in the suite*/
2602
2603 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_68[u32CoreId]);
2604 reentry_guard_GPT_EXCLUSIVE_AREA_68[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_68 for the next test in the suite*/
2605
2606 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_69[u32CoreId]);
2607 reentry_guard_GPT_EXCLUSIVE_AREA_69[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_69 for the next test in the suite*/
2608
2609 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_70[u32CoreId]);
2610 reentry_guard_GPT_EXCLUSIVE_AREA_70[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_70 for the next test in the suite*/
2611
2612 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_71[u32CoreId]);
2613 reentry_guard_GPT_EXCLUSIVE_AREA_71[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_71 for the next test in the suite*/
2614
2615 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_72[u32CoreId]);
2616 reentry_guard_GPT_EXCLUSIVE_AREA_72[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_72 for the next test in the suite*/
2617
2618 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_73[u32CoreId]);
2619 reentry_guard_GPT_EXCLUSIVE_AREA_73[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_73 for the next test in the suite*/
2620
2621
2622 }
2623 #endif /*MCAL_TESTING_ENVIRONMENT*/
2624
2625 #define RTE_STOP_SEC_CODE
2626 #include "Rte_MemMap.h"
2627
2628 #ifdef __cplusplus
2629 }
2630 #endif
2631
2632 /** @} */
2633
