1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Adc.c
9 * @version 3.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Adc.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_ADC_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_ADC_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_ADC_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_ADC_SW_MAJOR_VERSION_C 3
44 #define SCHM_ADC_SW_MINOR_VERSION_C 0
45 #define SCHM_ADC_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_00) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_01) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_02) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_03) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_04) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_05) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_10) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_100) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_100[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_100) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_100[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_101) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_101[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_101) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_101[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_102) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_102[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_102) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_102[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_103) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_103[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_103) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_103[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_11) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_12) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_13) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_14) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_15) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_16) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_17) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_18) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_19) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_19) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_20) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_20) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
144 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_21) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
145 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_21) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
146 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_22) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
147 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_22) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
148 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_23) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
149 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_23) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
150 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_24) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
151 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_24) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
152 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_25) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
153 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_25) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
154 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_26) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
155 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_26) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
156 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_27) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
157 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_27) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
158 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_28) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
159 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_28) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
160 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_29) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
161 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_29) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
162 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_30) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
163 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_30) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
164 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_31) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
165 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_31) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
166 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_32) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
167 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_32) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
168 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_33) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
169 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_33) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
170 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_34) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_34[NUMBER_OF_CORES];
171 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_34) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_34[NUMBER_OF_CORES];
172 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_35) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_35[NUMBER_OF_CORES];
173 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_35) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_35[NUMBER_OF_CORES];
174 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_36) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_36[NUMBER_OF_CORES];
175 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_36) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_36[NUMBER_OF_CORES];
176 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_37) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_37[NUMBER_OF_CORES];
177 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_37) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_37[NUMBER_OF_CORES];
178 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_38) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_38[NUMBER_OF_CORES];
179 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_38) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_38[NUMBER_OF_CORES];
180 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_39) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_39[NUMBER_OF_CORES];
181 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_39) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_39[NUMBER_OF_CORES];
182 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_40) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_40[NUMBER_OF_CORES];
183 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_40) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_40[NUMBER_OF_CORES];
184 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_41) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_41[NUMBER_OF_CORES];
185 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_41) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_41[NUMBER_OF_CORES];
186 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_42) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_42[NUMBER_OF_CORES];
187 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_42) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_42[NUMBER_OF_CORES];
188 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_43) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_43[NUMBER_OF_CORES];
189 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_43) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_43[NUMBER_OF_CORES];
190 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_44) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
191 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_44) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
192 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_45) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
193 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_45) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
194 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_46) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
195 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_46) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
196 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_47) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_47[NUMBER_OF_CORES];
197 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_47) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_47[NUMBER_OF_CORES];
198 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_48) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_48[NUMBER_OF_CORES];
199 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_48) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_48[NUMBER_OF_CORES];
200 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_49) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_49[NUMBER_OF_CORES];
201 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_49) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_49[NUMBER_OF_CORES];
202 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_50) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
203 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_50) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
204 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_51) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_51[NUMBER_OF_CORES];
205 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_51) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_51[NUMBER_OF_CORES];
206 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_54) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_54[NUMBER_OF_CORES];
207 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_54) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_54[NUMBER_OF_CORES];
208 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_55) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_55[NUMBER_OF_CORES];
209 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_55) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_55[NUMBER_OF_CORES];
210 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_56) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_56[NUMBER_OF_CORES];
211 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_56) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_56[NUMBER_OF_CORES];
212 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_57) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_57[NUMBER_OF_CORES];
213 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_57) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_57[NUMBER_OF_CORES];
214 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_58) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_58[NUMBER_OF_CORES];
215 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_58) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_58[NUMBER_OF_CORES];
216 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_59) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_59[NUMBER_OF_CORES];
217 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_59) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_59[NUMBER_OF_CORES];
218 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_60) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_60[NUMBER_OF_CORES];
219 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_60) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_60[NUMBER_OF_CORES];
220 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_61) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_61[NUMBER_OF_CORES];
221 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_61) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_61[NUMBER_OF_CORES];
222 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_62) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_62[NUMBER_OF_CORES];
223 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_62) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_62[NUMBER_OF_CORES];
224 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_63) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_63[NUMBER_OF_CORES];
225 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_63) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_63[NUMBER_OF_CORES];
226 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_64) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_64[NUMBER_OF_CORES];
227 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_64) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_64[NUMBER_OF_CORES];
228 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_65) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_65[NUMBER_OF_CORES];
229 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_65) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_65[NUMBER_OF_CORES];
230 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_66) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_66[NUMBER_OF_CORES];
231 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_66) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_66[NUMBER_OF_CORES];
232 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_67) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_67[NUMBER_OF_CORES];
233 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_67) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_67[NUMBER_OF_CORES];
234 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_68) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_68[NUMBER_OF_CORES];
235 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_68) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_68[NUMBER_OF_CORES];
236 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_69) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_69[NUMBER_OF_CORES];
237 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_69) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_69[NUMBER_OF_CORES];
238 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_70) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_70[NUMBER_OF_CORES];
239 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_70) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_70[NUMBER_OF_CORES];
240 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_71) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_71[NUMBER_OF_CORES];
241 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_71) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_71[NUMBER_OF_CORES];
242 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_72) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_72[NUMBER_OF_CORES];
243 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_72) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_72[NUMBER_OF_CORES];
244 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_73) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_73[NUMBER_OF_CORES];
245 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_73) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_73[NUMBER_OF_CORES];
246 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_74) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_74[NUMBER_OF_CORES];
247 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_74) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_74[NUMBER_OF_CORES];
248 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_75) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_75[NUMBER_OF_CORES];
249 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_75) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_75[NUMBER_OF_CORES];
250 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_76) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_76[NUMBER_OF_CORES];
251 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_76) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_76[NUMBER_OF_CORES];
252 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_77) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_77[NUMBER_OF_CORES];
253 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_77) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_77[NUMBER_OF_CORES];
254 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_78) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_78[NUMBER_OF_CORES];
255 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_78) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_78[NUMBER_OF_CORES];
256 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_79) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_79[NUMBER_OF_CORES];
257 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_79) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_79[NUMBER_OF_CORES];
258 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_80) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_80[NUMBER_OF_CORES];
259 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_80) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_80[NUMBER_OF_CORES];
260 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_81) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_81[NUMBER_OF_CORES];
261 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_81) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_81[NUMBER_OF_CORES];
262 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_82) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_82[NUMBER_OF_CORES];
263 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_82) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_82[NUMBER_OF_CORES];
264 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_83) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_83[NUMBER_OF_CORES];
265 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_83) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_83[NUMBER_OF_CORES];
266 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_84) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_84[NUMBER_OF_CORES];
267 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_84) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_84[NUMBER_OF_CORES];
268 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_85) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_85[NUMBER_OF_CORES];
269 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_85) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_85[NUMBER_OF_CORES];
270 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_86) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_86[NUMBER_OF_CORES];
271 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_86) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_86[NUMBER_OF_CORES];
272 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_87) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_87[NUMBER_OF_CORES];
273 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_87) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_87[NUMBER_OF_CORES];
274 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_88) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_88[NUMBER_OF_CORES];
275 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_88) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_88[NUMBER_OF_CORES];
276 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_89) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_89[NUMBER_OF_CORES];
277 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_89) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_89[NUMBER_OF_CORES];
278 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_90) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_90[NUMBER_OF_CORES];
279 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_90) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_90[NUMBER_OF_CORES];
280 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_91) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_91[NUMBER_OF_CORES];
281 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_91) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_91[NUMBER_OF_CORES];
282 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_92) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_92[NUMBER_OF_CORES];
283 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_92) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_92[NUMBER_OF_CORES];
284 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_93) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_93[NUMBER_OF_CORES];
285 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_93) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_93[NUMBER_OF_CORES];
286 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_94) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_94[NUMBER_OF_CORES];
287 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_94) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_94[NUMBER_OF_CORES];
288 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_95) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_95[NUMBER_OF_CORES];
289 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_95) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_95[NUMBER_OF_CORES];
290 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_96) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_96[NUMBER_OF_CORES];
291 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_96) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_96[NUMBER_OF_CORES];
292 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_97) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_97[NUMBER_OF_CORES];
293 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_97) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_97[NUMBER_OF_CORES];
294 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_98) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_98[NUMBER_OF_CORES];
295 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_98) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_98[NUMBER_OF_CORES];
296 VAR_SEC_NOCACHE(msr_ADC_EXCLUSIVE_AREA_99) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_99[NUMBER_OF_CORES];
297 VAR_SEC_NOCACHE(reentry_guard_ADC_EXCLUSIVE_AREA_99) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_99[NUMBER_OF_CORES];
298
299 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
300 #include "Rte_MemMap.h"
301 /*==================================================================================================
302 * GLOBAL CONSTANTS
303 ==================================================================================================*/
304
305
306 /*==================================================================================================
307 * GLOBAL VARIABLES
308 ==================================================================================================*/
309
310 /*==================================================================================================
311 * LOCAL FUNCTION PROTOTYPES
312 ==================================================================================================*/
313
314 #ifndef _COSMIC_C_S32K3XX_
315 /*================================================================================================*/
316 /**
317 * @brief This function returns the MSR register value (32 bits).
318 * @details This function returns the MSR register value (32 bits).
319 *
320 * @param[in] void No input parameters
321 * @return uint32 msr This function returns the MSR register value (32 bits).
322 *
323 * @pre None
324 * @post None
325 *
326 */
327 uint32 Adc_schm_read_msr(void);
328 #endif /*ifndef _COSMIC_C_S32K3XX_*/
329 /*==================================================================================================
330 * LOCAL FUNCTIONS
331 ==================================================================================================*/
332 #define RTE_START_SEC_CODE
333 #include "Rte_MemMap.h"
334
335 #if (defined(_GREENHILLS_C_S32K3XX_) || defined(_CODEWARRIOR_C_S32K3XX_))
336 /*================================================================================================*/
337 /**
338 * @brief This macro returns the MSR register value (32 bits).
339 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
340 *
341 * @pre None
342 * @post None
343 *
344 */
345 #ifdef MCAL_PLATFORM_ARM
346 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Adc_schm_read_msr(void)347 ASM_KEYWORD uint32 Adc_schm_read_msr(void)
348 {
349 mrs x0, S3_3_c4_c2_1
350 }
351 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Adc_schm_read_msr(void)352 ASM_KEYWORD uint32 Adc_schm_read_msr(void)
353 {
354 mrs r0, CPSR
355 }
356 #else
Adc_schm_read_msr(void)357 ASM_KEYWORD uint32 Adc_schm_read_msr(void)
358 {
359 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
360 mrs r0, BASEPRI
361 #else
362 mrs r0, PRIMASK
363 #endif
364 }
365 #endif
366 #else
367 #ifdef MCAL_PLATFORM_S12
Adc_schm_read_msr(void)368 ASM_KEYWORD uint32 Adc_schm_read_msr(void)
369 {
370 tfr ccr, d6
371 }
372 #else
Adc_schm_read_msr(void)373 ASM_KEYWORD uint32 Adc_schm_read_msr(void)
374 {
375 mfmsr r3
376 }
377 #endif
378 #endif
379 #endif /*#ifdef GHS||CW*/
380
381 #ifdef _DIABDATA_C_S32K3XX_
382 /**
383 * @brief This function returns the MSR register value (32 bits).
384 * @details This function returns the MSR register value (32 bits).
385 *
386 * @param[in] void No input parameters
387 * @return uint32 msr This function returns the MSR register value (32 bits).
388 *
389 * @pre None
390 * @post None
391 *
392 */
393 #ifdef MCAL_PLATFORM_ARM
Adc_schm_read_msr(void)394 uint32 Adc_schm_read_msr(void)
395 {
396 register uint32 reg_tmp;
397 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
398 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
399 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
400 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
401 #else
402 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
403 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
404 #else
405 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
406 #endif
407 #endif
408 return (uint32)reg_tmp;
409 }
410 #else
Adc_schm_read_msr(void)411 ASM_KEYWORD uint32 Adc_schm_read_msr(void)
412 {
413 mfmsr r3
414 }
415 #endif /* MCAL_PLATFORM_ARM */
416
417 #endif /* _DIABDATA_C_S32K3XX_*/
418
419 #ifdef _COSMIC_C_S32K3XX_
420 /*================================================================================================*/
421 /**
422 * @brief This function returns the MSR register value (32 bits).
423 * @details This function returns the MSR register value (32 bits).
424 *
425 * @param[in] void No input parameters
426 * @return uint32 msr This function returns the MSR register value (32 bits).
427 *
428 * @pre None
429 * @post None
430 *
431 */
432
433 #ifdef MCAL_PLATFORM_S12
434 #define Adc_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
435 #else
436 #define Adc_schm_read_msr() ASM_KEYWORD("mfmsr r3")
437 #endif
438
439 #endif /*Cosmic compiler only*/
440
441
442 #ifdef _HITECH_C_S32K3XX_
443 /*================================================================================================*/
444 /**
445 * @brief This function returns the MSR register value (32 bits).
446 * @details This function returns the MSR register value (32 bits).
447 *
448 * @param[in] void No input parameters
449 * @return uint32 msr This function returns the MSR register value (32 bits).
450 *
451 * @pre None
452 * @post None
453 *
454 */
Adc_schm_read_msr(void)455 uint32 Adc_schm_read_msr(void)
456 {
457 uint32 result;
458 __asm volatile("mfmsr %0" : "=r" (result) :);
459 return result;
460 }
461
462 #endif /*HighTec compiler only*/
463 /*================================================================================================*/
464 #ifdef _LINARO_C_S32K3XX_
465 /**
466 * @brief This function returns the MSR register value (32 bits).
467 * @details This function returns the MSR register value (32 bits).
468 *
469 * @param[in] void No input parameters
470 * @return uint32 msr This function returns the MSR register value (32 bits).
471 *
472 * @pre None
473 * @post None
474 *
475 */
Adc_schm_read_msr(void)476 uint32 Adc_schm_read_msr(void)
477 {
478 register uint32 reg_tmp;
479 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
480 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
481 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
482 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
483 #else
484 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
485 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
486 #else
487 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
488 #endif
489 #endif
490 return (uint32)reg_tmp;
491 }
492 #endif /* _LINARO_C_S32K3XX_*/
493 /*================================================================================================*/
494
495 #ifdef _ARM_DS5_C_S32K3XX_
496 /**
497 * @brief This function returns the MSR register value (32 bits).
498 * @details This function returns the MSR register value (32 bits).
499 *
500 * @param[in] void No input parameters
501 * @return uint32 msr This function returns the MSR register value (32 bits).
502 *
503 * @pre None
504 * @post None
505 *
506 */
Adc_schm_read_msr(void)507 uint32 Adc_schm_read_msr(void)
508 {
509 register uint32 reg_tmp;
510 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
511 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
512 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
513 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
514 #else
515 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
516 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
517 #else
518 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
519 #endif
520 #endif
521 return (uint32)reg_tmp;
522 }
523 #endif /* _ARM_DS5_C_S32K3XX_ */
524
525 #ifdef _IAR_C_S32K3XX_
526 /**
527 * @brief This function returns the MSR register value (32 bits).
528 * @details This function returns the MSR register value (32 bits).
529 *
530 * @param[in] void No input parameters
531 * @return uint32 msr This function returns the MSR register value (32 bits).
532 *
533 * @pre None
534 * @post None
535 *
536 */
Adc_schm_read_msr(void)537 uint32 Adc_schm_read_msr(void)
538 {
539 register uint32 reg_tmp;
540
541 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
542 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
543 #else
544 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
545 #endif
546
547 return (uint32)reg_tmp;
548 }
549 #endif /* _IAR_C_S32K3XX_ */
550
551 #define RTE_STOP_SEC_CODE
552 #include "Rte_MemMap.h"
553
554 /*==================================================================================================
555 * GLOBAL FUNCTIONS
556 ==================================================================================================*/
557 #define RTE_START_SEC_CODE
558 #include "Rte_MemMap.h"
559
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_00(void)560 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_00(void)
561 {
562 uint32 msr;
563 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
564
565 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId])
566 {
567 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
568 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
569 #else
570 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
571 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
572 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
573 {
574 OsIf_SuspendAllInterrupts();
575 #ifdef _ARM_DS5_C_S32K3XX_
576 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
577 #endif
578 }
579 msr_ADC_EXCLUSIVE_AREA_00[u32CoreId] = msr;
580 }
581 reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId]++;
582 }
583
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_00(void)584 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_00(void)
585 {
586 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
587
588 reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId]--;
589 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
590 {
591 OsIf_ResumeAllInterrupts();
592 #ifdef _ARM_DS5_C_S32K3XX_
593 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
594 #endif
595 }
596 }
597
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_01(void)598 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_01(void)
599 {
600 uint32 msr;
601 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
602
603 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId])
604 {
605 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
606 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
607 #else
608 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
609 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
610 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
611 {
612 OsIf_SuspendAllInterrupts();
613 #ifdef _ARM_DS5_C_S32K3XX_
614 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
615 #endif
616 }
617 msr_ADC_EXCLUSIVE_AREA_01[u32CoreId] = msr;
618 }
619 reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId]++;
620 }
621
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_01(void)622 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_01(void)
623 {
624 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
625
626 reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId]--;
627 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
628 {
629 OsIf_ResumeAllInterrupts();
630 #ifdef _ARM_DS5_C_S32K3XX_
631 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
632 #endif
633 }
634 }
635
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_02(void)636 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_02(void)
637 {
638 uint32 msr;
639 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
640
641 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId])
642 {
643 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
644 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
645 #else
646 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
647 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
648 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
649 {
650 OsIf_SuspendAllInterrupts();
651 #ifdef _ARM_DS5_C_S32K3XX_
652 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
653 #endif
654 }
655 msr_ADC_EXCLUSIVE_AREA_02[u32CoreId] = msr;
656 }
657 reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId]++;
658 }
659
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_02(void)660 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_02(void)
661 {
662 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
663
664 reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId]--;
665 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
666 {
667 OsIf_ResumeAllInterrupts();
668 #ifdef _ARM_DS5_C_S32K3XX_
669 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
670 #endif
671 }
672 }
673
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_03(void)674 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_03(void)
675 {
676 uint32 msr;
677 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
678
679 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId])
680 {
681 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
682 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
683 #else
684 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
685 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
686 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
687 {
688 OsIf_SuspendAllInterrupts();
689 #ifdef _ARM_DS5_C_S32K3XX_
690 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
691 #endif
692 }
693 msr_ADC_EXCLUSIVE_AREA_03[u32CoreId] = msr;
694 }
695 reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId]++;
696 }
697
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_03(void)698 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_03(void)
699 {
700 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
701
702 reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId]--;
703 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
704 {
705 OsIf_ResumeAllInterrupts();
706 #ifdef _ARM_DS5_C_S32K3XX_
707 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
708 #endif
709 }
710 }
711
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_04(void)712 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_04(void)
713 {
714 uint32 msr;
715 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
716
717 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId])
718 {
719 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
720 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
721 #else
722 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
723 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
724 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
725 {
726 OsIf_SuspendAllInterrupts();
727 #ifdef _ARM_DS5_C_S32K3XX_
728 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
729 #endif
730 }
731 msr_ADC_EXCLUSIVE_AREA_04[u32CoreId] = msr;
732 }
733 reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId]++;
734 }
735
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_04(void)736 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_04(void)
737 {
738 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
739
740 reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId]--;
741 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
742 {
743 OsIf_ResumeAllInterrupts();
744 #ifdef _ARM_DS5_C_S32K3XX_
745 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
746 #endif
747 }
748 }
749
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_05(void)750 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_05(void)
751 {
752 uint32 msr;
753 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
754
755 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId])
756 {
757 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
758 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
759 #else
760 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
761 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
762 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
763 {
764 OsIf_SuspendAllInterrupts();
765 #ifdef _ARM_DS5_C_S32K3XX_
766 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
767 #endif
768 }
769 msr_ADC_EXCLUSIVE_AREA_05[u32CoreId] = msr;
770 }
771 reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId]++;
772 }
773
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_05(void)774 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_05(void)
775 {
776 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
777
778 reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId]--;
779 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
780 {
781 OsIf_ResumeAllInterrupts();
782 #ifdef _ARM_DS5_C_S32K3XX_
783 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
784 #endif
785 }
786 }
787
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_10(void)788 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_10(void)
789 {
790 uint32 msr;
791 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
792
793 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId])
794 {
795 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
796 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
797 #else
798 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
799 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
800 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
801 {
802 OsIf_SuspendAllInterrupts();
803 #ifdef _ARM_DS5_C_S32K3XX_
804 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
805 #endif
806 }
807 msr_ADC_EXCLUSIVE_AREA_10[u32CoreId] = msr;
808 }
809 reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId]++;
810 }
811
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_10(void)812 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_10(void)
813 {
814 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
815
816 reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId]--;
817 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
818 {
819 OsIf_ResumeAllInterrupts();
820 #ifdef _ARM_DS5_C_S32K3XX_
821 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
822 #endif
823 }
824 }
825
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_100(void)826 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_100(void)
827 {
828 uint32 msr;
829 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
830
831 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_100[u32CoreId])
832 {
833 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
834 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
835 #else
836 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
837 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
838 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
839 {
840 OsIf_SuspendAllInterrupts();
841 #ifdef _ARM_DS5_C_S32K3XX_
842 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
843 #endif
844 }
845 msr_ADC_EXCLUSIVE_AREA_100[u32CoreId] = msr;
846 }
847 reentry_guard_ADC_EXCLUSIVE_AREA_100[u32CoreId]++;
848 }
849
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_100(void)850 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_100(void)
851 {
852 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
853
854 reentry_guard_ADC_EXCLUSIVE_AREA_100[u32CoreId]--;
855 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_100[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_100[u32CoreId])) /*if interrupts were enabled*/
856 {
857 OsIf_ResumeAllInterrupts();
858 #ifdef _ARM_DS5_C_S32K3XX_
859 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
860 #endif
861 }
862 }
863
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_101(void)864 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_101(void)
865 {
866 uint32 msr;
867 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
868
869 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_101[u32CoreId])
870 {
871 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
872 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
873 #else
874 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
875 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
876 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
877 {
878 OsIf_SuspendAllInterrupts();
879 #ifdef _ARM_DS5_C_S32K3XX_
880 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
881 #endif
882 }
883 msr_ADC_EXCLUSIVE_AREA_101[u32CoreId] = msr;
884 }
885 reentry_guard_ADC_EXCLUSIVE_AREA_101[u32CoreId]++;
886 }
887
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_101(void)888 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_101(void)
889 {
890 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
891
892 reentry_guard_ADC_EXCLUSIVE_AREA_101[u32CoreId]--;
893 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_101[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_101[u32CoreId])) /*if interrupts were enabled*/
894 {
895 OsIf_ResumeAllInterrupts();
896 #ifdef _ARM_DS5_C_S32K3XX_
897 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
898 #endif
899 }
900 }
901
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_102(void)902 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_102(void)
903 {
904 uint32 msr;
905 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
906
907 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_102[u32CoreId])
908 {
909 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
910 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
911 #else
912 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
913 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
914 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
915 {
916 OsIf_SuspendAllInterrupts();
917 #ifdef _ARM_DS5_C_S32K3XX_
918 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
919 #endif
920 }
921 msr_ADC_EXCLUSIVE_AREA_102[u32CoreId] = msr;
922 }
923 reentry_guard_ADC_EXCLUSIVE_AREA_102[u32CoreId]++;
924 }
925
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_102(void)926 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_102(void)
927 {
928 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
929
930 reentry_guard_ADC_EXCLUSIVE_AREA_102[u32CoreId]--;
931 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_102[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_102[u32CoreId])) /*if interrupts were enabled*/
932 {
933 OsIf_ResumeAllInterrupts();
934 #ifdef _ARM_DS5_C_S32K3XX_
935 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
936 #endif
937 }
938 }
939
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_103(void)940 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_103(void)
941 {
942 uint32 msr;
943 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
944
945 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_103[u32CoreId])
946 {
947 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
948 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
949 #else
950 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
951 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
952 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
953 {
954 OsIf_SuspendAllInterrupts();
955 #ifdef _ARM_DS5_C_S32K3XX_
956 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
957 #endif
958 }
959 msr_ADC_EXCLUSIVE_AREA_103[u32CoreId] = msr;
960 }
961 reentry_guard_ADC_EXCLUSIVE_AREA_103[u32CoreId]++;
962 }
963
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_103(void)964 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_103(void)
965 {
966 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
967
968 reentry_guard_ADC_EXCLUSIVE_AREA_103[u32CoreId]--;
969 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_103[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_103[u32CoreId])) /*if interrupts were enabled*/
970 {
971 OsIf_ResumeAllInterrupts();
972 #ifdef _ARM_DS5_C_S32K3XX_
973 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
974 #endif
975 }
976 }
977
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11(void)978 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11(void)
979 {
980 uint32 msr;
981 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
982
983 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId])
984 {
985 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
986 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
987 #else
988 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
989 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
990 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
991 {
992 OsIf_SuspendAllInterrupts();
993 #ifdef _ARM_DS5_C_S32K3XX_
994 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
995 #endif
996 }
997 msr_ADC_EXCLUSIVE_AREA_11[u32CoreId] = msr;
998 }
999 reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId]++;
1000 }
1001
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11(void)1002 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11(void)
1003 {
1004 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1005
1006 reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId]--;
1007 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
1008 {
1009 OsIf_ResumeAllInterrupts();
1010 #ifdef _ARM_DS5_C_S32K3XX_
1011 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1012 #endif
1013 }
1014 }
1015
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_12(void)1016 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_12(void)
1017 {
1018 uint32 msr;
1019 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1020
1021 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId])
1022 {
1023 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1024 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1025 #else
1026 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1027 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1028 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1029 {
1030 OsIf_SuspendAllInterrupts();
1031 #ifdef _ARM_DS5_C_S32K3XX_
1032 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1033 #endif
1034 }
1035 msr_ADC_EXCLUSIVE_AREA_12[u32CoreId] = msr;
1036 }
1037 reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId]++;
1038 }
1039
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_12(void)1040 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_12(void)
1041 {
1042 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1043
1044 reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId]--;
1045 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
1046 {
1047 OsIf_ResumeAllInterrupts();
1048 #ifdef _ARM_DS5_C_S32K3XX_
1049 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1050 #endif
1051 }
1052 }
1053
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_13(void)1054 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_13(void)
1055 {
1056 uint32 msr;
1057 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1058
1059 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId])
1060 {
1061 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1062 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1063 #else
1064 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1065 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1066 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1067 {
1068 OsIf_SuspendAllInterrupts();
1069 #ifdef _ARM_DS5_C_S32K3XX_
1070 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1071 #endif
1072 }
1073 msr_ADC_EXCLUSIVE_AREA_13[u32CoreId] = msr;
1074 }
1075 reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId]++;
1076 }
1077
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_13(void)1078 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_13(void)
1079 {
1080 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1081
1082 reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId]--;
1083 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
1084 {
1085 OsIf_ResumeAllInterrupts();
1086 #ifdef _ARM_DS5_C_S32K3XX_
1087 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1088 #endif
1089 }
1090 }
1091
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_14(void)1092 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_14(void)
1093 {
1094 uint32 msr;
1095 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1096
1097 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId])
1098 {
1099 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1100 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1101 #else
1102 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1103 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1104 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1105 {
1106 OsIf_SuspendAllInterrupts();
1107 #ifdef _ARM_DS5_C_S32K3XX_
1108 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1109 #endif
1110 }
1111 msr_ADC_EXCLUSIVE_AREA_14[u32CoreId] = msr;
1112 }
1113 reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId]++;
1114 }
1115
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_14(void)1116 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_14(void)
1117 {
1118 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1119
1120 reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId]--;
1121 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
1122 {
1123 OsIf_ResumeAllInterrupts();
1124 #ifdef _ARM_DS5_C_S32K3XX_
1125 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1126 #endif
1127 }
1128 }
1129
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_15(void)1130 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_15(void)
1131 {
1132 uint32 msr;
1133 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1134
1135 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId])
1136 {
1137 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1138 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1139 #else
1140 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1141 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1142 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1143 {
1144 OsIf_SuspendAllInterrupts();
1145 #ifdef _ARM_DS5_C_S32K3XX_
1146 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1147 #endif
1148 }
1149 msr_ADC_EXCLUSIVE_AREA_15[u32CoreId] = msr;
1150 }
1151 reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId]++;
1152 }
1153
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_15(void)1154 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_15(void)
1155 {
1156 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1157
1158 reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId]--;
1159 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
1160 {
1161 OsIf_ResumeAllInterrupts();
1162 #ifdef _ARM_DS5_C_S32K3XX_
1163 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1164 #endif
1165 }
1166 }
1167
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_16(void)1168 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_16(void)
1169 {
1170 uint32 msr;
1171 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1172
1173 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId])
1174 {
1175 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1176 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1177 #else
1178 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1179 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1180 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1181 {
1182 OsIf_SuspendAllInterrupts();
1183 #ifdef _ARM_DS5_C_S32K3XX_
1184 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1185 #endif
1186 }
1187 msr_ADC_EXCLUSIVE_AREA_16[u32CoreId] = msr;
1188 }
1189 reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId]++;
1190 }
1191
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_16(void)1192 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_16(void)
1193 {
1194 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1195
1196 reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId]--;
1197 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
1198 {
1199 OsIf_ResumeAllInterrupts();
1200 #ifdef _ARM_DS5_C_S32K3XX_
1201 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1202 #endif
1203 }
1204 }
1205
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_17(void)1206 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_17(void)
1207 {
1208 uint32 msr;
1209 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1210
1211 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId])
1212 {
1213 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1214 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1215 #else
1216 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1217 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1218 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1219 {
1220 OsIf_SuspendAllInterrupts();
1221 #ifdef _ARM_DS5_C_S32K3XX_
1222 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1223 #endif
1224 }
1225 msr_ADC_EXCLUSIVE_AREA_17[u32CoreId] = msr;
1226 }
1227 reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId]++;
1228 }
1229
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_17(void)1230 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_17(void)
1231 {
1232 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1233
1234 reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId]--;
1235 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
1236 {
1237 OsIf_ResumeAllInterrupts();
1238 #ifdef _ARM_DS5_C_S32K3XX_
1239 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1240 #endif
1241 }
1242 }
1243
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_18(void)1244 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_18(void)
1245 {
1246 uint32 msr;
1247 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1248
1249 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId])
1250 {
1251 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1252 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1253 #else
1254 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1255 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1256 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1257 {
1258 OsIf_SuspendAllInterrupts();
1259 #ifdef _ARM_DS5_C_S32K3XX_
1260 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1261 #endif
1262 }
1263 msr_ADC_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1264 }
1265 reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId]++;
1266 }
1267
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_18(void)1268 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_18(void)
1269 {
1270 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1271
1272 reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId]--;
1273 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1274 {
1275 OsIf_ResumeAllInterrupts();
1276 #ifdef _ARM_DS5_C_S32K3XX_
1277 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1278 #endif
1279 }
1280 }
1281
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_19(void)1282 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_19(void)
1283 {
1284 uint32 msr;
1285 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1286
1287 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId])
1288 {
1289 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1290 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1291 #else
1292 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1293 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1294 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1295 {
1296 OsIf_SuspendAllInterrupts();
1297 #ifdef _ARM_DS5_C_S32K3XX_
1298 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1299 #endif
1300 }
1301 msr_ADC_EXCLUSIVE_AREA_19[u32CoreId] = msr;
1302 }
1303 reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId]++;
1304 }
1305
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_19(void)1306 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_19(void)
1307 {
1308 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1309
1310 reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId]--;
1311 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId])) /*if interrupts were enabled*/
1312 {
1313 OsIf_ResumeAllInterrupts();
1314 #ifdef _ARM_DS5_C_S32K3XX_
1315 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1316 #endif
1317 }
1318 }
1319
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_20(void)1320 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_20(void)
1321 {
1322 uint32 msr;
1323 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1324
1325 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId])
1326 {
1327 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1328 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1329 #else
1330 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1331 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1332 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1333 {
1334 OsIf_SuspendAllInterrupts();
1335 #ifdef _ARM_DS5_C_S32K3XX_
1336 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1337 #endif
1338 }
1339 msr_ADC_EXCLUSIVE_AREA_20[u32CoreId] = msr;
1340 }
1341 reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId]++;
1342 }
1343
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_20(void)1344 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_20(void)
1345 {
1346 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1347
1348 reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId]--;
1349 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
1350 {
1351 OsIf_ResumeAllInterrupts();
1352 #ifdef _ARM_DS5_C_S32K3XX_
1353 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1354 #endif
1355 }
1356 }
1357
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_21(void)1358 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_21(void)
1359 {
1360 uint32 msr;
1361 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1362
1363 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId])
1364 {
1365 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1366 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1367 #else
1368 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1369 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1370 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1371 {
1372 OsIf_SuspendAllInterrupts();
1373 #ifdef _ARM_DS5_C_S32K3XX_
1374 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1375 #endif
1376 }
1377 msr_ADC_EXCLUSIVE_AREA_21[u32CoreId] = msr;
1378 }
1379 reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId]++;
1380 }
1381
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_21(void)1382 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_21(void)
1383 {
1384 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1385
1386 reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId]--;
1387 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
1388 {
1389 OsIf_ResumeAllInterrupts();
1390 #ifdef _ARM_DS5_C_S32K3XX_
1391 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1392 #endif
1393 }
1394 }
1395
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_22(void)1396 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_22(void)
1397 {
1398 uint32 msr;
1399 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1400
1401 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId])
1402 {
1403 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1404 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1405 #else
1406 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1407 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1408 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1409 {
1410 OsIf_SuspendAllInterrupts();
1411 #ifdef _ARM_DS5_C_S32K3XX_
1412 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1413 #endif
1414 }
1415 msr_ADC_EXCLUSIVE_AREA_22[u32CoreId] = msr;
1416 }
1417 reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId]++;
1418 }
1419
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_22(void)1420 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_22(void)
1421 {
1422 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1423
1424 reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId]--;
1425 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId])) /*if interrupts were enabled*/
1426 {
1427 OsIf_ResumeAllInterrupts();
1428 #ifdef _ARM_DS5_C_S32K3XX_
1429 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1430 #endif
1431 }
1432 }
1433
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_23(void)1434 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_23(void)
1435 {
1436 uint32 msr;
1437 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1438
1439 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId])
1440 {
1441 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1442 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1443 #else
1444 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1445 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1446 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1447 {
1448 OsIf_SuspendAllInterrupts();
1449 #ifdef _ARM_DS5_C_S32K3XX_
1450 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1451 #endif
1452 }
1453 msr_ADC_EXCLUSIVE_AREA_23[u32CoreId] = msr;
1454 }
1455 reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId]++;
1456 }
1457
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_23(void)1458 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_23(void)
1459 {
1460 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1461
1462 reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId]--;
1463 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId])) /*if interrupts were enabled*/
1464 {
1465 OsIf_ResumeAllInterrupts();
1466 #ifdef _ARM_DS5_C_S32K3XX_
1467 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1468 #endif
1469 }
1470 }
1471
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_24(void)1472 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_24(void)
1473 {
1474 uint32 msr;
1475 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1476
1477 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId])
1478 {
1479 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1480 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1481 #else
1482 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1483 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1484 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1485 {
1486 OsIf_SuspendAllInterrupts();
1487 #ifdef _ARM_DS5_C_S32K3XX_
1488 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1489 #endif
1490 }
1491 msr_ADC_EXCLUSIVE_AREA_24[u32CoreId] = msr;
1492 }
1493 reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId]++;
1494 }
1495
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_24(void)1496 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_24(void)
1497 {
1498 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1499
1500 reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId]--;
1501 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId])) /*if interrupts were enabled*/
1502 {
1503 OsIf_ResumeAllInterrupts();
1504 #ifdef _ARM_DS5_C_S32K3XX_
1505 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1506 #endif
1507 }
1508 }
1509
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_25(void)1510 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_25(void)
1511 {
1512 uint32 msr;
1513 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1514
1515 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId])
1516 {
1517 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1518 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1519 #else
1520 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1521 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1522 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1523 {
1524 OsIf_SuspendAllInterrupts();
1525 #ifdef _ARM_DS5_C_S32K3XX_
1526 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1527 #endif
1528 }
1529 msr_ADC_EXCLUSIVE_AREA_25[u32CoreId] = msr;
1530 }
1531 reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId]++;
1532 }
1533
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_25(void)1534 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_25(void)
1535 {
1536 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1537
1538 reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId]--;
1539 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId])) /*if interrupts were enabled*/
1540 {
1541 OsIf_ResumeAllInterrupts();
1542 #ifdef _ARM_DS5_C_S32K3XX_
1543 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1544 #endif
1545 }
1546 }
1547
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_26(void)1548 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_26(void)
1549 {
1550 uint32 msr;
1551 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1552
1553 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId])
1554 {
1555 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1556 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1557 #else
1558 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1559 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1560 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1561 {
1562 OsIf_SuspendAllInterrupts();
1563 #ifdef _ARM_DS5_C_S32K3XX_
1564 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1565 #endif
1566 }
1567 msr_ADC_EXCLUSIVE_AREA_26[u32CoreId] = msr;
1568 }
1569 reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId]++;
1570 }
1571
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_26(void)1572 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_26(void)
1573 {
1574 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1575
1576 reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId]--;
1577 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId])) /*if interrupts were enabled*/
1578 {
1579 OsIf_ResumeAllInterrupts();
1580 #ifdef _ARM_DS5_C_S32K3XX_
1581 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1582 #endif
1583 }
1584 }
1585
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_27(void)1586 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_27(void)
1587 {
1588 uint32 msr;
1589 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1590
1591 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId])
1592 {
1593 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1594 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1595 #else
1596 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1597 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1598 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1599 {
1600 OsIf_SuspendAllInterrupts();
1601 #ifdef _ARM_DS5_C_S32K3XX_
1602 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1603 #endif
1604 }
1605 msr_ADC_EXCLUSIVE_AREA_27[u32CoreId] = msr;
1606 }
1607 reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId]++;
1608 }
1609
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_27(void)1610 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_27(void)
1611 {
1612 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1613
1614 reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId]--;
1615 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_27[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId])) /*if interrupts were enabled*/
1616 {
1617 OsIf_ResumeAllInterrupts();
1618 #ifdef _ARM_DS5_C_S32K3XX_
1619 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1620 #endif
1621 }
1622 }
1623
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_28(void)1624 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_28(void)
1625 {
1626 uint32 msr;
1627 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1628
1629 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId])
1630 {
1631 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1632 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1633 #else
1634 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1635 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1636 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1637 {
1638 OsIf_SuspendAllInterrupts();
1639 #ifdef _ARM_DS5_C_S32K3XX_
1640 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1641 #endif
1642 }
1643 msr_ADC_EXCLUSIVE_AREA_28[u32CoreId] = msr;
1644 }
1645 reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId]++;
1646 }
1647
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_28(void)1648 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_28(void)
1649 {
1650 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1651
1652 reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId]--;
1653 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_28[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId])) /*if interrupts were enabled*/
1654 {
1655 OsIf_ResumeAllInterrupts();
1656 #ifdef _ARM_DS5_C_S32K3XX_
1657 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1658 #endif
1659 }
1660 }
1661
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_29(void)1662 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_29(void)
1663 {
1664 uint32 msr;
1665 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1666
1667 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId])
1668 {
1669 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1670 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1671 #else
1672 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1673 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1674 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1675 {
1676 OsIf_SuspendAllInterrupts();
1677 #ifdef _ARM_DS5_C_S32K3XX_
1678 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1679 #endif
1680 }
1681 msr_ADC_EXCLUSIVE_AREA_29[u32CoreId] = msr;
1682 }
1683 reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId]++;
1684 }
1685
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_29(void)1686 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_29(void)
1687 {
1688 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1689
1690 reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId]--;
1691 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_29[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId])) /*if interrupts were enabled*/
1692 {
1693 OsIf_ResumeAllInterrupts();
1694 #ifdef _ARM_DS5_C_S32K3XX_
1695 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1696 #endif
1697 }
1698 }
1699
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_30(void)1700 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_30(void)
1701 {
1702 uint32 msr;
1703 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1704
1705 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId])
1706 {
1707 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1708 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1709 #else
1710 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1711 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1712 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1713 {
1714 OsIf_SuspendAllInterrupts();
1715 #ifdef _ARM_DS5_C_S32K3XX_
1716 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1717 #endif
1718 }
1719 msr_ADC_EXCLUSIVE_AREA_30[u32CoreId] = msr;
1720 }
1721 reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId]++;
1722 }
1723
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_30(void)1724 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_30(void)
1725 {
1726 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1727
1728 reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId]--;
1729 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_30[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId])) /*if interrupts were enabled*/
1730 {
1731 OsIf_ResumeAllInterrupts();
1732 #ifdef _ARM_DS5_C_S32K3XX_
1733 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1734 #endif
1735 }
1736 }
1737
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_31(void)1738 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_31(void)
1739 {
1740 uint32 msr;
1741 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1742
1743 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId])
1744 {
1745 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1746 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1747 #else
1748 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1749 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1750 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1751 {
1752 OsIf_SuspendAllInterrupts();
1753 #ifdef _ARM_DS5_C_S32K3XX_
1754 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1755 #endif
1756 }
1757 msr_ADC_EXCLUSIVE_AREA_31[u32CoreId] = msr;
1758 }
1759 reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId]++;
1760 }
1761
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_31(void)1762 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_31(void)
1763 {
1764 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1765
1766 reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId]--;
1767 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_31[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId])) /*if interrupts were enabled*/
1768 {
1769 OsIf_ResumeAllInterrupts();
1770 #ifdef _ARM_DS5_C_S32K3XX_
1771 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1772 #endif
1773 }
1774 }
1775
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_32(void)1776 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_32(void)
1777 {
1778 uint32 msr;
1779 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1780
1781 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId])
1782 {
1783 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1784 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1785 #else
1786 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1787 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1788 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1789 {
1790 OsIf_SuspendAllInterrupts();
1791 #ifdef _ARM_DS5_C_S32K3XX_
1792 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1793 #endif
1794 }
1795 msr_ADC_EXCLUSIVE_AREA_32[u32CoreId] = msr;
1796 }
1797 reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId]++;
1798 }
1799
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_32(void)1800 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_32(void)
1801 {
1802 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1803
1804 reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId]--;
1805 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_32[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId])) /*if interrupts were enabled*/
1806 {
1807 OsIf_ResumeAllInterrupts();
1808 #ifdef _ARM_DS5_C_S32K3XX_
1809 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1810 #endif
1811 }
1812 }
1813
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_33(void)1814 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_33(void)
1815 {
1816 uint32 msr;
1817 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1818
1819 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId])
1820 {
1821 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1822 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1823 #else
1824 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1825 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1826 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1827 {
1828 OsIf_SuspendAllInterrupts();
1829 #ifdef _ARM_DS5_C_S32K3XX_
1830 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1831 #endif
1832 }
1833 msr_ADC_EXCLUSIVE_AREA_33[u32CoreId] = msr;
1834 }
1835 reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId]++;
1836 }
1837
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_33(void)1838 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_33(void)
1839 {
1840 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1841
1842 reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId]--;
1843 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_33[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId])) /*if interrupts were enabled*/
1844 {
1845 OsIf_ResumeAllInterrupts();
1846 #ifdef _ARM_DS5_C_S32K3XX_
1847 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1848 #endif
1849 }
1850 }
1851
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_34(void)1852 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_34(void)
1853 {
1854 uint32 msr;
1855 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1856
1857 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId])
1858 {
1859 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1860 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1861 #else
1862 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1863 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1864 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1865 {
1866 OsIf_SuspendAllInterrupts();
1867 #ifdef _ARM_DS5_C_S32K3XX_
1868 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1869 #endif
1870 }
1871 msr_ADC_EXCLUSIVE_AREA_34[u32CoreId] = msr;
1872 }
1873 reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId]++;
1874 }
1875
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_34(void)1876 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_34(void)
1877 {
1878 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1879
1880 reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId]--;
1881 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_34[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId])) /*if interrupts were enabled*/
1882 {
1883 OsIf_ResumeAllInterrupts();
1884 #ifdef _ARM_DS5_C_S32K3XX_
1885 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1886 #endif
1887 }
1888 }
1889
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_35(void)1890 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_35(void)
1891 {
1892 uint32 msr;
1893 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1894
1895 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId])
1896 {
1897 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1898 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1899 #else
1900 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1901 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1902 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1903 {
1904 OsIf_SuspendAllInterrupts();
1905 #ifdef _ARM_DS5_C_S32K3XX_
1906 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1907 #endif
1908 }
1909 msr_ADC_EXCLUSIVE_AREA_35[u32CoreId] = msr;
1910 }
1911 reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId]++;
1912 }
1913
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_35(void)1914 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_35(void)
1915 {
1916 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1917
1918 reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId]--;
1919 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_35[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId])) /*if interrupts were enabled*/
1920 {
1921 OsIf_ResumeAllInterrupts();
1922 #ifdef _ARM_DS5_C_S32K3XX_
1923 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1924 #endif
1925 }
1926 }
1927
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_36(void)1928 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_36(void)
1929 {
1930 uint32 msr;
1931 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1932
1933 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId])
1934 {
1935 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1936 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1937 #else
1938 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1939 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1940 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1941 {
1942 OsIf_SuspendAllInterrupts();
1943 #ifdef _ARM_DS5_C_S32K3XX_
1944 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1945 #endif
1946 }
1947 msr_ADC_EXCLUSIVE_AREA_36[u32CoreId] = msr;
1948 }
1949 reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId]++;
1950 }
1951
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_36(void)1952 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_36(void)
1953 {
1954 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1955
1956 reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId]--;
1957 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_36[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId])) /*if interrupts were enabled*/
1958 {
1959 OsIf_ResumeAllInterrupts();
1960 #ifdef _ARM_DS5_C_S32K3XX_
1961 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1962 #endif
1963 }
1964 }
1965
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_37(void)1966 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_37(void)
1967 {
1968 uint32 msr;
1969 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1970
1971 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId])
1972 {
1973 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1974 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
1975 #else
1976 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
1977 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1978 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1979 {
1980 OsIf_SuspendAllInterrupts();
1981 #ifdef _ARM_DS5_C_S32K3XX_
1982 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1983 #endif
1984 }
1985 msr_ADC_EXCLUSIVE_AREA_37[u32CoreId] = msr;
1986 }
1987 reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId]++;
1988 }
1989
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_37(void)1990 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_37(void)
1991 {
1992 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1993
1994 reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId]--;
1995 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_37[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId])) /*if interrupts were enabled*/
1996 {
1997 OsIf_ResumeAllInterrupts();
1998 #ifdef _ARM_DS5_C_S32K3XX_
1999 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2000 #endif
2001 }
2002 }
2003
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_38(void)2004 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_38(void)
2005 {
2006 uint32 msr;
2007 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2008
2009 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId])
2010 {
2011 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2012 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2013 #else
2014 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2015 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2016 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2017 {
2018 OsIf_SuspendAllInterrupts();
2019 #ifdef _ARM_DS5_C_S32K3XX_
2020 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2021 #endif
2022 }
2023 msr_ADC_EXCLUSIVE_AREA_38[u32CoreId] = msr;
2024 }
2025 reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId]++;
2026 }
2027
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_38(void)2028 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_38(void)
2029 {
2030 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2031
2032 reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId]--;
2033 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_38[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId])) /*if interrupts were enabled*/
2034 {
2035 OsIf_ResumeAllInterrupts();
2036 #ifdef _ARM_DS5_C_S32K3XX_
2037 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2038 #endif
2039 }
2040 }
2041
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_39(void)2042 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_39(void)
2043 {
2044 uint32 msr;
2045 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2046
2047 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId])
2048 {
2049 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2050 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2051 #else
2052 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2053 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2054 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2055 {
2056 OsIf_SuspendAllInterrupts();
2057 #ifdef _ARM_DS5_C_S32K3XX_
2058 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2059 #endif
2060 }
2061 msr_ADC_EXCLUSIVE_AREA_39[u32CoreId] = msr;
2062 }
2063 reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId]++;
2064 }
2065
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_39(void)2066 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_39(void)
2067 {
2068 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2069
2070 reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId]--;
2071 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_39[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId])) /*if interrupts were enabled*/
2072 {
2073 OsIf_ResumeAllInterrupts();
2074 #ifdef _ARM_DS5_C_S32K3XX_
2075 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2076 #endif
2077 }
2078 }
2079
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_40(void)2080 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_40(void)
2081 {
2082 uint32 msr;
2083 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2084
2085 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId])
2086 {
2087 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2088 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2089 #else
2090 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2091 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2092 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2093 {
2094 OsIf_SuspendAllInterrupts();
2095 #ifdef _ARM_DS5_C_S32K3XX_
2096 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2097 #endif
2098 }
2099 msr_ADC_EXCLUSIVE_AREA_40[u32CoreId] = msr;
2100 }
2101 reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId]++;
2102 }
2103
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_40(void)2104 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_40(void)
2105 {
2106 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2107
2108 reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId]--;
2109 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_40[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId])) /*if interrupts were enabled*/
2110 {
2111 OsIf_ResumeAllInterrupts();
2112 #ifdef _ARM_DS5_C_S32K3XX_
2113 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2114 #endif
2115 }
2116 }
2117
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_41(void)2118 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_41(void)
2119 {
2120 uint32 msr;
2121 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2122
2123 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId])
2124 {
2125 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2126 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2127 #else
2128 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2129 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2130 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2131 {
2132 OsIf_SuspendAllInterrupts();
2133 #ifdef _ARM_DS5_C_S32K3XX_
2134 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2135 #endif
2136 }
2137 msr_ADC_EXCLUSIVE_AREA_41[u32CoreId] = msr;
2138 }
2139 reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId]++;
2140 }
2141
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_41(void)2142 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_41(void)
2143 {
2144 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2145
2146 reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId]--;
2147 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_41[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId])) /*if interrupts were enabled*/
2148 {
2149 OsIf_ResumeAllInterrupts();
2150 #ifdef _ARM_DS5_C_S32K3XX_
2151 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2152 #endif
2153 }
2154 }
2155
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_42(void)2156 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_42(void)
2157 {
2158 uint32 msr;
2159 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2160
2161 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId])
2162 {
2163 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2164 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2165 #else
2166 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2167 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2168 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2169 {
2170 OsIf_SuspendAllInterrupts();
2171 #ifdef _ARM_DS5_C_S32K3XX_
2172 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2173 #endif
2174 }
2175 msr_ADC_EXCLUSIVE_AREA_42[u32CoreId] = msr;
2176 }
2177 reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId]++;
2178 }
2179
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_42(void)2180 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_42(void)
2181 {
2182 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2183
2184 reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId]--;
2185 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_42[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId])) /*if interrupts were enabled*/
2186 {
2187 OsIf_ResumeAllInterrupts();
2188 #ifdef _ARM_DS5_C_S32K3XX_
2189 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2190 #endif
2191 }
2192 }
2193
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_43(void)2194 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_43(void)
2195 {
2196 uint32 msr;
2197 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2198
2199 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId])
2200 {
2201 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2202 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2203 #else
2204 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2205 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2206 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2207 {
2208 OsIf_SuspendAllInterrupts();
2209 #ifdef _ARM_DS5_C_S32K3XX_
2210 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2211 #endif
2212 }
2213 msr_ADC_EXCLUSIVE_AREA_43[u32CoreId] = msr;
2214 }
2215 reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId]++;
2216 }
2217
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_43(void)2218 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_43(void)
2219 {
2220 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2221
2222 reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId]--;
2223 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_43[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId])) /*if interrupts were enabled*/
2224 {
2225 OsIf_ResumeAllInterrupts();
2226 #ifdef _ARM_DS5_C_S32K3XX_
2227 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2228 #endif
2229 }
2230 }
2231
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_44(void)2232 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_44(void)
2233 {
2234 uint32 msr;
2235 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2236
2237 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId])
2238 {
2239 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2240 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2241 #else
2242 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2243 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2244 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2245 {
2246 OsIf_SuspendAllInterrupts();
2247 #ifdef _ARM_DS5_C_S32K3XX_
2248 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2249 #endif
2250 }
2251 msr_ADC_EXCLUSIVE_AREA_44[u32CoreId] = msr;
2252 }
2253 reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId]++;
2254 }
2255
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_44(void)2256 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_44(void)
2257 {
2258 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2259
2260 reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId]--;
2261 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_44[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId])) /*if interrupts were enabled*/
2262 {
2263 OsIf_ResumeAllInterrupts();
2264 #ifdef _ARM_DS5_C_S32K3XX_
2265 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2266 #endif
2267 }
2268 }
2269
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_45(void)2270 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_45(void)
2271 {
2272 uint32 msr;
2273 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2274
2275 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId])
2276 {
2277 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2278 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2279 #else
2280 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2281 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2282 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2283 {
2284 OsIf_SuspendAllInterrupts();
2285 #ifdef _ARM_DS5_C_S32K3XX_
2286 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2287 #endif
2288 }
2289 msr_ADC_EXCLUSIVE_AREA_45[u32CoreId] = msr;
2290 }
2291 reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId]++;
2292 }
2293
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_45(void)2294 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_45(void)
2295 {
2296 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2297
2298 reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId]--;
2299 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_45[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId])) /*if interrupts were enabled*/
2300 {
2301 OsIf_ResumeAllInterrupts();
2302 #ifdef _ARM_DS5_C_S32K3XX_
2303 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2304 #endif
2305 }
2306 }
2307
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_46(void)2308 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_46(void)
2309 {
2310 uint32 msr;
2311 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2312
2313 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId])
2314 {
2315 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2316 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2317 #else
2318 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2319 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2320 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2321 {
2322 OsIf_SuspendAllInterrupts();
2323 #ifdef _ARM_DS5_C_S32K3XX_
2324 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2325 #endif
2326 }
2327 msr_ADC_EXCLUSIVE_AREA_46[u32CoreId] = msr;
2328 }
2329 reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId]++;
2330 }
2331
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_46(void)2332 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_46(void)
2333 {
2334 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2335
2336 reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId]--;
2337 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_46[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId])) /*if interrupts were enabled*/
2338 {
2339 OsIf_ResumeAllInterrupts();
2340 #ifdef _ARM_DS5_C_S32K3XX_
2341 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2342 #endif
2343 }
2344 }
2345
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_47(void)2346 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_47(void)
2347 {
2348 uint32 msr;
2349 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2350
2351 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId])
2352 {
2353 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2354 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2355 #else
2356 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2357 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2358 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2359 {
2360 OsIf_SuspendAllInterrupts();
2361 #ifdef _ARM_DS5_C_S32K3XX_
2362 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2363 #endif
2364 }
2365 msr_ADC_EXCLUSIVE_AREA_47[u32CoreId] = msr;
2366 }
2367 reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId]++;
2368 }
2369
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_47(void)2370 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_47(void)
2371 {
2372 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2373
2374 reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId]--;
2375 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_47[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId])) /*if interrupts were enabled*/
2376 {
2377 OsIf_ResumeAllInterrupts();
2378 #ifdef _ARM_DS5_C_S32K3XX_
2379 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2380 #endif
2381 }
2382 }
2383
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_48(void)2384 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_48(void)
2385 {
2386 uint32 msr;
2387 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2388
2389 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId])
2390 {
2391 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2392 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2393 #else
2394 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2395 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2396 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2397 {
2398 OsIf_SuspendAllInterrupts();
2399 #ifdef _ARM_DS5_C_S32K3XX_
2400 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2401 #endif
2402 }
2403 msr_ADC_EXCLUSIVE_AREA_48[u32CoreId] = msr;
2404 }
2405 reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId]++;
2406 }
2407
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_48(void)2408 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_48(void)
2409 {
2410 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2411
2412 reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId]--;
2413 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_48[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId])) /*if interrupts were enabled*/
2414 {
2415 OsIf_ResumeAllInterrupts();
2416 #ifdef _ARM_DS5_C_S32K3XX_
2417 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2418 #endif
2419 }
2420 }
2421
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_49(void)2422 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_49(void)
2423 {
2424 uint32 msr;
2425 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2426
2427 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId])
2428 {
2429 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2430 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2431 #else
2432 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2433 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2434 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2435 {
2436 OsIf_SuspendAllInterrupts();
2437 #ifdef _ARM_DS5_C_S32K3XX_
2438 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2439 #endif
2440 }
2441 msr_ADC_EXCLUSIVE_AREA_49[u32CoreId] = msr;
2442 }
2443 reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId]++;
2444 }
2445
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_49(void)2446 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_49(void)
2447 {
2448 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2449
2450 reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId]--;
2451 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_49[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId])) /*if interrupts were enabled*/
2452 {
2453 OsIf_ResumeAllInterrupts();
2454 #ifdef _ARM_DS5_C_S32K3XX_
2455 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2456 #endif
2457 }
2458 }
2459
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_50(void)2460 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_50(void)
2461 {
2462 uint32 msr;
2463 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2464
2465 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId])
2466 {
2467 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2468 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2469 #else
2470 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2471 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2472 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2473 {
2474 OsIf_SuspendAllInterrupts();
2475 #ifdef _ARM_DS5_C_S32K3XX_
2476 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2477 #endif
2478 }
2479 msr_ADC_EXCLUSIVE_AREA_50[u32CoreId] = msr;
2480 }
2481 reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId]++;
2482 }
2483
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_50(void)2484 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_50(void)
2485 {
2486 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2487
2488 reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId]--;
2489 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_50[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId])) /*if interrupts were enabled*/
2490 {
2491 OsIf_ResumeAllInterrupts();
2492 #ifdef _ARM_DS5_C_S32K3XX_
2493 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2494 #endif
2495 }
2496 }
2497
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_51(void)2498 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_51(void)
2499 {
2500 uint32 msr;
2501 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2502
2503 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_51[u32CoreId])
2504 {
2505 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2506 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2507 #else
2508 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2509 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2510 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2511 {
2512 OsIf_SuspendAllInterrupts();
2513 #ifdef _ARM_DS5_C_S32K3XX_
2514 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2515 #endif
2516 }
2517 msr_ADC_EXCLUSIVE_AREA_51[u32CoreId] = msr;
2518 }
2519 reentry_guard_ADC_EXCLUSIVE_AREA_51[u32CoreId]++;
2520 }
2521
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_51(void)2522 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_51(void)
2523 {
2524 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2525
2526 reentry_guard_ADC_EXCLUSIVE_AREA_51[u32CoreId]--;
2527 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_51[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_51[u32CoreId])) /*if interrupts were enabled*/
2528 {
2529 OsIf_ResumeAllInterrupts();
2530 #ifdef _ARM_DS5_C_S32K3XX_
2531 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2532 #endif
2533 }
2534 }
2535
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_54(void)2536 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_54(void)
2537 {
2538 uint32 msr;
2539 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2540
2541 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId])
2542 {
2543 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2544 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2545 #else
2546 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2547 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2548 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2549 {
2550 OsIf_SuspendAllInterrupts();
2551 #ifdef _ARM_DS5_C_S32K3XX_
2552 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2553 #endif
2554 }
2555 msr_ADC_EXCLUSIVE_AREA_54[u32CoreId] = msr;
2556 }
2557 reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId]++;
2558 }
2559
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_54(void)2560 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_54(void)
2561 {
2562 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2563
2564 reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId]--;
2565 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_54[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId])) /*if interrupts were enabled*/
2566 {
2567 OsIf_ResumeAllInterrupts();
2568 #ifdef _ARM_DS5_C_S32K3XX_
2569 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2570 #endif
2571 }
2572 }
2573
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_55(void)2574 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_55(void)
2575 {
2576 uint32 msr;
2577 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2578
2579 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId])
2580 {
2581 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2582 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2583 #else
2584 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2585 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2586 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2587 {
2588 OsIf_SuspendAllInterrupts();
2589 #ifdef _ARM_DS5_C_S32K3XX_
2590 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2591 #endif
2592 }
2593 msr_ADC_EXCLUSIVE_AREA_55[u32CoreId] = msr;
2594 }
2595 reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId]++;
2596 }
2597
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_55(void)2598 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_55(void)
2599 {
2600 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2601
2602 reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId]--;
2603 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_55[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId])) /*if interrupts were enabled*/
2604 {
2605 OsIf_ResumeAllInterrupts();
2606 #ifdef _ARM_DS5_C_S32K3XX_
2607 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2608 #endif
2609 }
2610 }
2611
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_56(void)2612 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_56(void)
2613 {
2614 uint32 msr;
2615 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2616
2617 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId])
2618 {
2619 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2620 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2621 #else
2622 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2623 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2624 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2625 {
2626 OsIf_SuspendAllInterrupts();
2627 #ifdef _ARM_DS5_C_S32K3XX_
2628 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2629 #endif
2630 }
2631 msr_ADC_EXCLUSIVE_AREA_56[u32CoreId] = msr;
2632 }
2633 reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId]++;
2634 }
2635
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_56(void)2636 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_56(void)
2637 {
2638 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2639
2640 reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId]--;
2641 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_56[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId])) /*if interrupts were enabled*/
2642 {
2643 OsIf_ResumeAllInterrupts();
2644 #ifdef _ARM_DS5_C_S32K3XX_
2645 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2646 #endif
2647 }
2648 }
2649
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_57(void)2650 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_57(void)
2651 {
2652 uint32 msr;
2653 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2654
2655 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId])
2656 {
2657 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2658 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2659 #else
2660 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2661 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2662 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2663 {
2664 OsIf_SuspendAllInterrupts();
2665 #ifdef _ARM_DS5_C_S32K3XX_
2666 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2667 #endif
2668 }
2669 msr_ADC_EXCLUSIVE_AREA_57[u32CoreId] = msr;
2670 }
2671 reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId]++;
2672 }
2673
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_57(void)2674 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_57(void)
2675 {
2676 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2677
2678 reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId]--;
2679 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_57[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId])) /*if interrupts were enabled*/
2680 {
2681 OsIf_ResumeAllInterrupts();
2682 #ifdef _ARM_DS5_C_S32K3XX_
2683 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2684 #endif
2685 }
2686 }
2687
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_58(void)2688 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_58(void)
2689 {
2690 uint32 msr;
2691 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2692
2693 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId])
2694 {
2695 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2696 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2697 #else
2698 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2699 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2700 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2701 {
2702 OsIf_SuspendAllInterrupts();
2703 #ifdef _ARM_DS5_C_S32K3XX_
2704 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2705 #endif
2706 }
2707 msr_ADC_EXCLUSIVE_AREA_58[u32CoreId] = msr;
2708 }
2709 reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId]++;
2710 }
2711
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_58(void)2712 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_58(void)
2713 {
2714 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2715
2716 reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId]--;
2717 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_58[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId])) /*if interrupts were enabled*/
2718 {
2719 OsIf_ResumeAllInterrupts();
2720 #ifdef _ARM_DS5_C_S32K3XX_
2721 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2722 #endif
2723 }
2724 }
2725
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_59(void)2726 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_59(void)
2727 {
2728 uint32 msr;
2729 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2730
2731 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId])
2732 {
2733 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2734 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2735 #else
2736 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2737 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2738 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2739 {
2740 OsIf_SuspendAllInterrupts();
2741 #ifdef _ARM_DS5_C_S32K3XX_
2742 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2743 #endif
2744 }
2745 msr_ADC_EXCLUSIVE_AREA_59[u32CoreId] = msr;
2746 }
2747 reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId]++;
2748 }
2749
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_59(void)2750 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_59(void)
2751 {
2752 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2753
2754 reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId]--;
2755 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_59[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId])) /*if interrupts were enabled*/
2756 {
2757 OsIf_ResumeAllInterrupts();
2758 #ifdef _ARM_DS5_C_S32K3XX_
2759 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2760 #endif
2761 }
2762 }
2763
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_60(void)2764 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_60(void)
2765 {
2766 uint32 msr;
2767 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2768
2769 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId])
2770 {
2771 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2772 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2773 #else
2774 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2775 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2776 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2777 {
2778 OsIf_SuspendAllInterrupts();
2779 #ifdef _ARM_DS5_C_S32K3XX_
2780 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2781 #endif
2782 }
2783 msr_ADC_EXCLUSIVE_AREA_60[u32CoreId] = msr;
2784 }
2785 reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId]++;
2786 }
2787
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_60(void)2788 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_60(void)
2789 {
2790 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2791
2792 reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId]--;
2793 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_60[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId])) /*if interrupts were enabled*/
2794 {
2795 OsIf_ResumeAllInterrupts();
2796 #ifdef _ARM_DS5_C_S32K3XX_
2797 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2798 #endif
2799 }
2800 }
2801
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_61(void)2802 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_61(void)
2803 {
2804 uint32 msr;
2805 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2806
2807 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId])
2808 {
2809 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2810 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2811 #else
2812 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2813 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2814 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2815 {
2816 OsIf_SuspendAllInterrupts();
2817 #ifdef _ARM_DS5_C_S32K3XX_
2818 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2819 #endif
2820 }
2821 msr_ADC_EXCLUSIVE_AREA_61[u32CoreId] = msr;
2822 }
2823 reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId]++;
2824 }
2825
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_61(void)2826 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_61(void)
2827 {
2828 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2829
2830 reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId]--;
2831 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_61[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId])) /*if interrupts were enabled*/
2832 {
2833 OsIf_ResumeAllInterrupts();
2834 #ifdef _ARM_DS5_C_S32K3XX_
2835 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2836 #endif
2837 }
2838 }
2839
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_62(void)2840 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_62(void)
2841 {
2842 uint32 msr;
2843 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2844
2845 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId])
2846 {
2847 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2848 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2849 #else
2850 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2851 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2852 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2853 {
2854 OsIf_SuspendAllInterrupts();
2855 #ifdef _ARM_DS5_C_S32K3XX_
2856 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2857 #endif
2858 }
2859 msr_ADC_EXCLUSIVE_AREA_62[u32CoreId] = msr;
2860 }
2861 reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId]++;
2862 }
2863
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_62(void)2864 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_62(void)
2865 {
2866 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2867
2868 reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId]--;
2869 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_62[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId])) /*if interrupts were enabled*/
2870 {
2871 OsIf_ResumeAllInterrupts();
2872 #ifdef _ARM_DS5_C_S32K3XX_
2873 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2874 #endif
2875 }
2876 }
2877
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_63(void)2878 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_63(void)
2879 {
2880 uint32 msr;
2881 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2882
2883 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId])
2884 {
2885 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2886 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2887 #else
2888 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2889 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2890 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2891 {
2892 OsIf_SuspendAllInterrupts();
2893 #ifdef _ARM_DS5_C_S32K3XX_
2894 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2895 #endif
2896 }
2897 msr_ADC_EXCLUSIVE_AREA_63[u32CoreId] = msr;
2898 }
2899 reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId]++;
2900 }
2901
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_63(void)2902 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_63(void)
2903 {
2904 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2905
2906 reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId]--;
2907 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_63[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId])) /*if interrupts were enabled*/
2908 {
2909 OsIf_ResumeAllInterrupts();
2910 #ifdef _ARM_DS5_C_S32K3XX_
2911 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2912 #endif
2913 }
2914 }
2915
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_64(void)2916 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_64(void)
2917 {
2918 uint32 msr;
2919 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2920
2921 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId])
2922 {
2923 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2924 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2925 #else
2926 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2927 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2928 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2929 {
2930 OsIf_SuspendAllInterrupts();
2931 #ifdef _ARM_DS5_C_S32K3XX_
2932 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2933 #endif
2934 }
2935 msr_ADC_EXCLUSIVE_AREA_64[u32CoreId] = msr;
2936 }
2937 reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId]++;
2938 }
2939
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_64(void)2940 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_64(void)
2941 {
2942 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2943
2944 reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId]--;
2945 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_64[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId])) /*if interrupts were enabled*/
2946 {
2947 OsIf_ResumeAllInterrupts();
2948 #ifdef _ARM_DS5_C_S32K3XX_
2949 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2950 #endif
2951 }
2952 }
2953
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_65(void)2954 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_65(void)
2955 {
2956 uint32 msr;
2957 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2958
2959 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId])
2960 {
2961 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2962 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
2963 #else
2964 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
2965 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2966 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2967 {
2968 OsIf_SuspendAllInterrupts();
2969 #ifdef _ARM_DS5_C_S32K3XX_
2970 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2971 #endif
2972 }
2973 msr_ADC_EXCLUSIVE_AREA_65[u32CoreId] = msr;
2974 }
2975 reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId]++;
2976 }
2977
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_65(void)2978 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_65(void)
2979 {
2980 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2981
2982 reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId]--;
2983 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_65[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId])) /*if interrupts were enabled*/
2984 {
2985 OsIf_ResumeAllInterrupts();
2986 #ifdef _ARM_DS5_C_S32K3XX_
2987 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2988 #endif
2989 }
2990 }
2991
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_66(void)2992 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_66(void)
2993 {
2994 uint32 msr;
2995 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2996
2997 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId])
2998 {
2999 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3000 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3001 #else
3002 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3003 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3004 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3005 {
3006 OsIf_SuspendAllInterrupts();
3007 #ifdef _ARM_DS5_C_S32K3XX_
3008 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3009 #endif
3010 }
3011 msr_ADC_EXCLUSIVE_AREA_66[u32CoreId] = msr;
3012 }
3013 reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId]++;
3014 }
3015
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_66(void)3016 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_66(void)
3017 {
3018 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3019
3020 reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId]--;
3021 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_66[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId])) /*if interrupts were enabled*/
3022 {
3023 OsIf_ResumeAllInterrupts();
3024 #ifdef _ARM_DS5_C_S32K3XX_
3025 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3026 #endif
3027 }
3028 }
3029
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_67(void)3030 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_67(void)
3031 {
3032 uint32 msr;
3033 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3034
3035 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId])
3036 {
3037 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3038 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3039 #else
3040 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3041 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3042 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3043 {
3044 OsIf_SuspendAllInterrupts();
3045 #ifdef _ARM_DS5_C_S32K3XX_
3046 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3047 #endif
3048 }
3049 msr_ADC_EXCLUSIVE_AREA_67[u32CoreId] = msr;
3050 }
3051 reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId]++;
3052 }
3053
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_67(void)3054 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_67(void)
3055 {
3056 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3057
3058 reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId]--;
3059 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_67[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId])) /*if interrupts were enabled*/
3060 {
3061 OsIf_ResumeAllInterrupts();
3062 #ifdef _ARM_DS5_C_S32K3XX_
3063 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3064 #endif
3065 }
3066 }
3067
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_68(void)3068 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_68(void)
3069 {
3070 uint32 msr;
3071 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3072
3073 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId])
3074 {
3075 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3076 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3077 #else
3078 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3079 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3080 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3081 {
3082 OsIf_SuspendAllInterrupts();
3083 #ifdef _ARM_DS5_C_S32K3XX_
3084 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3085 #endif
3086 }
3087 msr_ADC_EXCLUSIVE_AREA_68[u32CoreId] = msr;
3088 }
3089 reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId]++;
3090 }
3091
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_68(void)3092 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_68(void)
3093 {
3094 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3095
3096 reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId]--;
3097 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_68[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId])) /*if interrupts were enabled*/
3098 {
3099 OsIf_ResumeAllInterrupts();
3100 #ifdef _ARM_DS5_C_S32K3XX_
3101 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3102 #endif
3103 }
3104 }
3105
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_69(void)3106 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_69(void)
3107 {
3108 uint32 msr;
3109 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3110
3111 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId])
3112 {
3113 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3114 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3115 #else
3116 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3117 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3118 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3119 {
3120 OsIf_SuspendAllInterrupts();
3121 #ifdef _ARM_DS5_C_S32K3XX_
3122 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3123 #endif
3124 }
3125 msr_ADC_EXCLUSIVE_AREA_69[u32CoreId] = msr;
3126 }
3127 reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId]++;
3128 }
3129
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_69(void)3130 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_69(void)
3131 {
3132 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3133
3134 reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId]--;
3135 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_69[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId])) /*if interrupts were enabled*/
3136 {
3137 OsIf_ResumeAllInterrupts();
3138 #ifdef _ARM_DS5_C_S32K3XX_
3139 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3140 #endif
3141 }
3142 }
3143
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_70(void)3144 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_70(void)
3145 {
3146 uint32 msr;
3147 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3148
3149 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId])
3150 {
3151 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3152 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3153 #else
3154 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3155 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3156 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3157 {
3158 OsIf_SuspendAllInterrupts();
3159 #ifdef _ARM_DS5_C_S32K3XX_
3160 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3161 #endif
3162 }
3163 msr_ADC_EXCLUSIVE_AREA_70[u32CoreId] = msr;
3164 }
3165 reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId]++;
3166 }
3167
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_70(void)3168 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_70(void)
3169 {
3170 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3171
3172 reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId]--;
3173 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_70[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId])) /*if interrupts were enabled*/
3174 {
3175 OsIf_ResumeAllInterrupts();
3176 #ifdef _ARM_DS5_C_S32K3XX_
3177 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3178 #endif
3179 }
3180 }
3181
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_71(void)3182 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_71(void)
3183 {
3184 uint32 msr;
3185 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3186
3187 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId])
3188 {
3189 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3190 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3191 #else
3192 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3193 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3194 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3195 {
3196 OsIf_SuspendAllInterrupts();
3197 #ifdef _ARM_DS5_C_S32K3XX_
3198 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3199 #endif
3200 }
3201 msr_ADC_EXCLUSIVE_AREA_71[u32CoreId] = msr;
3202 }
3203 reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId]++;
3204 }
3205
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_71(void)3206 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_71(void)
3207 {
3208 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3209
3210 reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId]--;
3211 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_71[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId])) /*if interrupts were enabled*/
3212 {
3213 OsIf_ResumeAllInterrupts();
3214 #ifdef _ARM_DS5_C_S32K3XX_
3215 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3216 #endif
3217 }
3218 }
3219
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_72(void)3220 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_72(void)
3221 {
3222 uint32 msr;
3223 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3224
3225 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId])
3226 {
3227 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3228 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3229 #else
3230 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3231 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3232 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3233 {
3234 OsIf_SuspendAllInterrupts();
3235 #ifdef _ARM_DS5_C_S32K3XX_
3236 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3237 #endif
3238 }
3239 msr_ADC_EXCLUSIVE_AREA_72[u32CoreId] = msr;
3240 }
3241 reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId]++;
3242 }
3243
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_72(void)3244 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_72(void)
3245 {
3246 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3247
3248 reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId]--;
3249 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_72[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId])) /*if interrupts were enabled*/
3250 {
3251 OsIf_ResumeAllInterrupts();
3252 #ifdef _ARM_DS5_C_S32K3XX_
3253 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3254 #endif
3255 }
3256 }
3257
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_73(void)3258 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_73(void)
3259 {
3260 uint32 msr;
3261 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3262
3263 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId])
3264 {
3265 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3266 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3267 #else
3268 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3269 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3270 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3271 {
3272 OsIf_SuspendAllInterrupts();
3273 #ifdef _ARM_DS5_C_S32K3XX_
3274 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3275 #endif
3276 }
3277 msr_ADC_EXCLUSIVE_AREA_73[u32CoreId] = msr;
3278 }
3279 reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId]++;
3280 }
3281
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_73(void)3282 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_73(void)
3283 {
3284 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3285
3286 reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId]--;
3287 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_73[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId])) /*if interrupts were enabled*/
3288 {
3289 OsIf_ResumeAllInterrupts();
3290 #ifdef _ARM_DS5_C_S32K3XX_
3291 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3292 #endif
3293 }
3294 }
3295
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_74(void)3296 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_74(void)
3297 {
3298 uint32 msr;
3299 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3300
3301 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_74[u32CoreId])
3302 {
3303 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3304 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3305 #else
3306 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3307 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3308 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3309 {
3310 OsIf_SuspendAllInterrupts();
3311 #ifdef _ARM_DS5_C_S32K3XX_
3312 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3313 #endif
3314 }
3315 msr_ADC_EXCLUSIVE_AREA_74[u32CoreId] = msr;
3316 }
3317 reentry_guard_ADC_EXCLUSIVE_AREA_74[u32CoreId]++;
3318 }
3319
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_74(void)3320 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_74(void)
3321 {
3322 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3323
3324 reentry_guard_ADC_EXCLUSIVE_AREA_74[u32CoreId]--;
3325 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_74[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_74[u32CoreId])) /*if interrupts were enabled*/
3326 {
3327 OsIf_ResumeAllInterrupts();
3328 #ifdef _ARM_DS5_C_S32K3XX_
3329 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3330 #endif
3331 }
3332 }
3333
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_75(void)3334 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_75(void)
3335 {
3336 uint32 msr;
3337 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3338
3339 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_75[u32CoreId])
3340 {
3341 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3342 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3343 #else
3344 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3345 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3346 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3347 {
3348 OsIf_SuspendAllInterrupts();
3349 #ifdef _ARM_DS5_C_S32K3XX_
3350 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3351 #endif
3352 }
3353 msr_ADC_EXCLUSIVE_AREA_75[u32CoreId] = msr;
3354 }
3355 reentry_guard_ADC_EXCLUSIVE_AREA_75[u32CoreId]++;
3356 }
3357
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_75(void)3358 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_75(void)
3359 {
3360 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3361
3362 reentry_guard_ADC_EXCLUSIVE_AREA_75[u32CoreId]--;
3363 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_75[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_75[u32CoreId])) /*if interrupts were enabled*/
3364 {
3365 OsIf_ResumeAllInterrupts();
3366 #ifdef _ARM_DS5_C_S32K3XX_
3367 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3368 #endif
3369 }
3370 }
3371
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_76(void)3372 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_76(void)
3373 {
3374 uint32 msr;
3375 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3376
3377 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_76[u32CoreId])
3378 {
3379 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3380 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3381 #else
3382 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3383 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3384 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3385 {
3386 OsIf_SuspendAllInterrupts();
3387 #ifdef _ARM_DS5_C_S32K3XX_
3388 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3389 #endif
3390 }
3391 msr_ADC_EXCLUSIVE_AREA_76[u32CoreId] = msr;
3392 }
3393 reentry_guard_ADC_EXCLUSIVE_AREA_76[u32CoreId]++;
3394 }
3395
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_76(void)3396 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_76(void)
3397 {
3398 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3399
3400 reentry_guard_ADC_EXCLUSIVE_AREA_76[u32CoreId]--;
3401 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_76[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_76[u32CoreId])) /*if interrupts were enabled*/
3402 {
3403 OsIf_ResumeAllInterrupts();
3404 #ifdef _ARM_DS5_C_S32K3XX_
3405 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3406 #endif
3407 }
3408 }
3409
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_77(void)3410 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_77(void)
3411 {
3412 uint32 msr;
3413 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3414
3415 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_77[u32CoreId])
3416 {
3417 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3418 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3419 #else
3420 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3421 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3422 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3423 {
3424 OsIf_SuspendAllInterrupts();
3425 #ifdef _ARM_DS5_C_S32K3XX_
3426 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3427 #endif
3428 }
3429 msr_ADC_EXCLUSIVE_AREA_77[u32CoreId] = msr;
3430 }
3431 reentry_guard_ADC_EXCLUSIVE_AREA_77[u32CoreId]++;
3432 }
3433
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_77(void)3434 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_77(void)
3435 {
3436 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3437
3438 reentry_guard_ADC_EXCLUSIVE_AREA_77[u32CoreId]--;
3439 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_77[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_77[u32CoreId])) /*if interrupts were enabled*/
3440 {
3441 OsIf_ResumeAllInterrupts();
3442 #ifdef _ARM_DS5_C_S32K3XX_
3443 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3444 #endif
3445 }
3446 }
3447
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_78(void)3448 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_78(void)
3449 {
3450 uint32 msr;
3451 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3452
3453 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_78[u32CoreId])
3454 {
3455 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3456 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3457 #else
3458 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3459 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3460 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3461 {
3462 OsIf_SuspendAllInterrupts();
3463 #ifdef _ARM_DS5_C_S32K3XX_
3464 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3465 #endif
3466 }
3467 msr_ADC_EXCLUSIVE_AREA_78[u32CoreId] = msr;
3468 }
3469 reentry_guard_ADC_EXCLUSIVE_AREA_78[u32CoreId]++;
3470 }
3471
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_78(void)3472 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_78(void)
3473 {
3474 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3475
3476 reentry_guard_ADC_EXCLUSIVE_AREA_78[u32CoreId]--;
3477 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_78[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_78[u32CoreId])) /*if interrupts were enabled*/
3478 {
3479 OsIf_ResumeAllInterrupts();
3480 #ifdef _ARM_DS5_C_S32K3XX_
3481 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3482 #endif
3483 }
3484 }
3485
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_79(void)3486 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_79(void)
3487 {
3488 uint32 msr;
3489 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3490
3491 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_79[u32CoreId])
3492 {
3493 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3494 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3495 #else
3496 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3497 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3498 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3499 {
3500 OsIf_SuspendAllInterrupts();
3501 #ifdef _ARM_DS5_C_S32K3XX_
3502 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3503 #endif
3504 }
3505 msr_ADC_EXCLUSIVE_AREA_79[u32CoreId] = msr;
3506 }
3507 reentry_guard_ADC_EXCLUSIVE_AREA_79[u32CoreId]++;
3508 }
3509
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_79(void)3510 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_79(void)
3511 {
3512 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3513
3514 reentry_guard_ADC_EXCLUSIVE_AREA_79[u32CoreId]--;
3515 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_79[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_79[u32CoreId])) /*if interrupts were enabled*/
3516 {
3517 OsIf_ResumeAllInterrupts();
3518 #ifdef _ARM_DS5_C_S32K3XX_
3519 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3520 #endif
3521 }
3522 }
3523
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_80(void)3524 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_80(void)
3525 {
3526 uint32 msr;
3527 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3528
3529 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_80[u32CoreId])
3530 {
3531 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3532 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3533 #else
3534 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3535 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3536 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3537 {
3538 OsIf_SuspendAllInterrupts();
3539 #ifdef _ARM_DS5_C_S32K3XX_
3540 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3541 #endif
3542 }
3543 msr_ADC_EXCLUSIVE_AREA_80[u32CoreId] = msr;
3544 }
3545 reentry_guard_ADC_EXCLUSIVE_AREA_80[u32CoreId]++;
3546 }
3547
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_80(void)3548 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_80(void)
3549 {
3550 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3551
3552 reentry_guard_ADC_EXCLUSIVE_AREA_80[u32CoreId]--;
3553 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_80[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_80[u32CoreId])) /*if interrupts were enabled*/
3554 {
3555 OsIf_ResumeAllInterrupts();
3556 #ifdef _ARM_DS5_C_S32K3XX_
3557 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3558 #endif
3559 }
3560 }
3561
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_81(void)3562 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_81(void)
3563 {
3564 uint32 msr;
3565 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3566
3567 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_81[u32CoreId])
3568 {
3569 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3570 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3571 #else
3572 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3573 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3574 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3575 {
3576 OsIf_SuspendAllInterrupts();
3577 #ifdef _ARM_DS5_C_S32K3XX_
3578 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3579 #endif
3580 }
3581 msr_ADC_EXCLUSIVE_AREA_81[u32CoreId] = msr;
3582 }
3583 reentry_guard_ADC_EXCLUSIVE_AREA_81[u32CoreId]++;
3584 }
3585
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_81(void)3586 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_81(void)
3587 {
3588 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3589
3590 reentry_guard_ADC_EXCLUSIVE_AREA_81[u32CoreId]--;
3591 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_81[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_81[u32CoreId])) /*if interrupts were enabled*/
3592 {
3593 OsIf_ResumeAllInterrupts();
3594 #ifdef _ARM_DS5_C_S32K3XX_
3595 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3596 #endif
3597 }
3598 }
3599
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_82(void)3600 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_82(void)
3601 {
3602 uint32 msr;
3603 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3604
3605 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_82[u32CoreId])
3606 {
3607 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3608 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3609 #else
3610 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3611 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3612 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3613 {
3614 OsIf_SuspendAllInterrupts();
3615 #ifdef _ARM_DS5_C_S32K3XX_
3616 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3617 #endif
3618 }
3619 msr_ADC_EXCLUSIVE_AREA_82[u32CoreId] = msr;
3620 }
3621 reentry_guard_ADC_EXCLUSIVE_AREA_82[u32CoreId]++;
3622 }
3623
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_82(void)3624 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_82(void)
3625 {
3626 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3627
3628 reentry_guard_ADC_EXCLUSIVE_AREA_82[u32CoreId]--;
3629 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_82[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_82[u32CoreId])) /*if interrupts were enabled*/
3630 {
3631 OsIf_ResumeAllInterrupts();
3632 #ifdef _ARM_DS5_C_S32K3XX_
3633 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3634 #endif
3635 }
3636 }
3637
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_83(void)3638 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_83(void)
3639 {
3640 uint32 msr;
3641 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3642
3643 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_83[u32CoreId])
3644 {
3645 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3646 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3647 #else
3648 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3649 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3650 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3651 {
3652 OsIf_SuspendAllInterrupts();
3653 #ifdef _ARM_DS5_C_S32K3XX_
3654 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3655 #endif
3656 }
3657 msr_ADC_EXCLUSIVE_AREA_83[u32CoreId] = msr;
3658 }
3659 reentry_guard_ADC_EXCLUSIVE_AREA_83[u32CoreId]++;
3660 }
3661
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_83(void)3662 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_83(void)
3663 {
3664 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3665
3666 reentry_guard_ADC_EXCLUSIVE_AREA_83[u32CoreId]--;
3667 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_83[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_83[u32CoreId])) /*if interrupts were enabled*/
3668 {
3669 OsIf_ResumeAllInterrupts();
3670 #ifdef _ARM_DS5_C_S32K3XX_
3671 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3672 #endif
3673 }
3674 }
3675
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_84(void)3676 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_84(void)
3677 {
3678 uint32 msr;
3679 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3680
3681 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_84[u32CoreId])
3682 {
3683 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3684 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3685 #else
3686 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3687 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3688 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3689 {
3690 OsIf_SuspendAllInterrupts();
3691 #ifdef _ARM_DS5_C_S32K3XX_
3692 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3693 #endif
3694 }
3695 msr_ADC_EXCLUSIVE_AREA_84[u32CoreId] = msr;
3696 }
3697 reentry_guard_ADC_EXCLUSIVE_AREA_84[u32CoreId]++;
3698 }
3699
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_84(void)3700 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_84(void)
3701 {
3702 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3703
3704 reentry_guard_ADC_EXCLUSIVE_AREA_84[u32CoreId]--;
3705 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_84[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_84[u32CoreId])) /*if interrupts were enabled*/
3706 {
3707 OsIf_ResumeAllInterrupts();
3708 #ifdef _ARM_DS5_C_S32K3XX_
3709 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3710 #endif
3711 }
3712 }
3713
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_85(void)3714 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_85(void)
3715 {
3716 uint32 msr;
3717 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3718
3719 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_85[u32CoreId])
3720 {
3721 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3722 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3723 #else
3724 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3725 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3726 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3727 {
3728 OsIf_SuspendAllInterrupts();
3729 #ifdef _ARM_DS5_C_S32K3XX_
3730 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3731 #endif
3732 }
3733 msr_ADC_EXCLUSIVE_AREA_85[u32CoreId] = msr;
3734 }
3735 reentry_guard_ADC_EXCLUSIVE_AREA_85[u32CoreId]++;
3736 }
3737
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_85(void)3738 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_85(void)
3739 {
3740 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3741
3742 reentry_guard_ADC_EXCLUSIVE_AREA_85[u32CoreId]--;
3743 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_85[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_85[u32CoreId])) /*if interrupts were enabled*/
3744 {
3745 OsIf_ResumeAllInterrupts();
3746 #ifdef _ARM_DS5_C_S32K3XX_
3747 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3748 #endif
3749 }
3750 }
3751
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_86(void)3752 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_86(void)
3753 {
3754 uint32 msr;
3755 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3756
3757 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_86[u32CoreId])
3758 {
3759 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3760 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3761 #else
3762 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3763 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3764 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3765 {
3766 OsIf_SuspendAllInterrupts();
3767 #ifdef _ARM_DS5_C_S32K3XX_
3768 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3769 #endif
3770 }
3771 msr_ADC_EXCLUSIVE_AREA_86[u32CoreId] = msr;
3772 }
3773 reentry_guard_ADC_EXCLUSIVE_AREA_86[u32CoreId]++;
3774 }
3775
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_86(void)3776 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_86(void)
3777 {
3778 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3779
3780 reentry_guard_ADC_EXCLUSIVE_AREA_86[u32CoreId]--;
3781 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_86[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_86[u32CoreId])) /*if interrupts were enabled*/
3782 {
3783 OsIf_ResumeAllInterrupts();
3784 #ifdef _ARM_DS5_C_S32K3XX_
3785 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3786 #endif
3787 }
3788 }
3789
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_87(void)3790 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_87(void)
3791 {
3792 uint32 msr;
3793 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3794
3795 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_87[u32CoreId])
3796 {
3797 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3798 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3799 #else
3800 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3801 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3802 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3803 {
3804 OsIf_SuspendAllInterrupts();
3805 #ifdef _ARM_DS5_C_S32K3XX_
3806 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3807 #endif
3808 }
3809 msr_ADC_EXCLUSIVE_AREA_87[u32CoreId] = msr;
3810 }
3811 reentry_guard_ADC_EXCLUSIVE_AREA_87[u32CoreId]++;
3812 }
3813
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_87(void)3814 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_87(void)
3815 {
3816 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3817
3818 reentry_guard_ADC_EXCLUSIVE_AREA_87[u32CoreId]--;
3819 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_87[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_87[u32CoreId])) /*if interrupts were enabled*/
3820 {
3821 OsIf_ResumeAllInterrupts();
3822 #ifdef _ARM_DS5_C_S32K3XX_
3823 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3824 #endif
3825 }
3826 }
3827
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_88(void)3828 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_88(void)
3829 {
3830 uint32 msr;
3831 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3832
3833 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_88[u32CoreId])
3834 {
3835 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3836 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3837 #else
3838 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3839 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3840 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3841 {
3842 OsIf_SuspendAllInterrupts();
3843 #ifdef _ARM_DS5_C_S32K3XX_
3844 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3845 #endif
3846 }
3847 msr_ADC_EXCLUSIVE_AREA_88[u32CoreId] = msr;
3848 }
3849 reentry_guard_ADC_EXCLUSIVE_AREA_88[u32CoreId]++;
3850 }
3851
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_88(void)3852 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_88(void)
3853 {
3854 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3855
3856 reentry_guard_ADC_EXCLUSIVE_AREA_88[u32CoreId]--;
3857 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_88[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_88[u32CoreId])) /*if interrupts were enabled*/
3858 {
3859 OsIf_ResumeAllInterrupts();
3860 #ifdef _ARM_DS5_C_S32K3XX_
3861 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3862 #endif
3863 }
3864 }
3865
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_89(void)3866 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_89(void)
3867 {
3868 uint32 msr;
3869 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3870
3871 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_89[u32CoreId])
3872 {
3873 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3874 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3875 #else
3876 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3877 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3878 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3879 {
3880 OsIf_SuspendAllInterrupts();
3881 #ifdef _ARM_DS5_C_S32K3XX_
3882 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3883 #endif
3884 }
3885 msr_ADC_EXCLUSIVE_AREA_89[u32CoreId] = msr;
3886 }
3887 reentry_guard_ADC_EXCLUSIVE_AREA_89[u32CoreId]++;
3888 }
3889
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_89(void)3890 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_89(void)
3891 {
3892 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3893
3894 reentry_guard_ADC_EXCLUSIVE_AREA_89[u32CoreId]--;
3895 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_89[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_89[u32CoreId])) /*if interrupts were enabled*/
3896 {
3897 OsIf_ResumeAllInterrupts();
3898 #ifdef _ARM_DS5_C_S32K3XX_
3899 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3900 #endif
3901 }
3902 }
3903
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_90(void)3904 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_90(void)
3905 {
3906 uint32 msr;
3907 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3908
3909 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_90[u32CoreId])
3910 {
3911 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3912 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3913 #else
3914 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3915 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3916 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3917 {
3918 OsIf_SuspendAllInterrupts();
3919 #ifdef _ARM_DS5_C_S32K3XX_
3920 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3921 #endif
3922 }
3923 msr_ADC_EXCLUSIVE_AREA_90[u32CoreId] = msr;
3924 }
3925 reentry_guard_ADC_EXCLUSIVE_AREA_90[u32CoreId]++;
3926 }
3927
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_90(void)3928 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_90(void)
3929 {
3930 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3931
3932 reentry_guard_ADC_EXCLUSIVE_AREA_90[u32CoreId]--;
3933 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_90[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_90[u32CoreId])) /*if interrupts were enabled*/
3934 {
3935 OsIf_ResumeAllInterrupts();
3936 #ifdef _ARM_DS5_C_S32K3XX_
3937 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3938 #endif
3939 }
3940 }
3941
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_91(void)3942 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_91(void)
3943 {
3944 uint32 msr;
3945 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3946
3947 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_91[u32CoreId])
3948 {
3949 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3950 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3951 #else
3952 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3953 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3954 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3955 {
3956 OsIf_SuspendAllInterrupts();
3957 #ifdef _ARM_DS5_C_S32K3XX_
3958 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3959 #endif
3960 }
3961 msr_ADC_EXCLUSIVE_AREA_91[u32CoreId] = msr;
3962 }
3963 reentry_guard_ADC_EXCLUSIVE_AREA_91[u32CoreId]++;
3964 }
3965
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_91(void)3966 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_91(void)
3967 {
3968 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3969
3970 reentry_guard_ADC_EXCLUSIVE_AREA_91[u32CoreId]--;
3971 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_91[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_91[u32CoreId])) /*if interrupts were enabled*/
3972 {
3973 OsIf_ResumeAllInterrupts();
3974 #ifdef _ARM_DS5_C_S32K3XX_
3975 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3976 #endif
3977 }
3978 }
3979
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_92(void)3980 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_92(void)
3981 {
3982 uint32 msr;
3983 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
3984
3985 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_92[u32CoreId])
3986 {
3987 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
3988 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
3989 #else
3990 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
3991 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
3992 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
3993 {
3994 OsIf_SuspendAllInterrupts();
3995 #ifdef _ARM_DS5_C_S32K3XX_
3996 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
3997 #endif
3998 }
3999 msr_ADC_EXCLUSIVE_AREA_92[u32CoreId] = msr;
4000 }
4001 reentry_guard_ADC_EXCLUSIVE_AREA_92[u32CoreId]++;
4002 }
4003
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_92(void)4004 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_92(void)
4005 {
4006 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4007
4008 reentry_guard_ADC_EXCLUSIVE_AREA_92[u32CoreId]--;
4009 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_92[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_92[u32CoreId])) /*if interrupts were enabled*/
4010 {
4011 OsIf_ResumeAllInterrupts();
4012 #ifdef _ARM_DS5_C_S32K3XX_
4013 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4014 #endif
4015 }
4016 }
4017
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_93(void)4018 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_93(void)
4019 {
4020 uint32 msr;
4021 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4022
4023 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_93[u32CoreId])
4024 {
4025 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
4026 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
4027 #else
4028 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
4029 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
4030 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
4031 {
4032 OsIf_SuspendAllInterrupts();
4033 #ifdef _ARM_DS5_C_S32K3XX_
4034 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4035 #endif
4036 }
4037 msr_ADC_EXCLUSIVE_AREA_93[u32CoreId] = msr;
4038 }
4039 reentry_guard_ADC_EXCLUSIVE_AREA_93[u32CoreId]++;
4040 }
4041
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_93(void)4042 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_93(void)
4043 {
4044 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4045
4046 reentry_guard_ADC_EXCLUSIVE_AREA_93[u32CoreId]--;
4047 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_93[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_93[u32CoreId])) /*if interrupts were enabled*/
4048 {
4049 OsIf_ResumeAllInterrupts();
4050 #ifdef _ARM_DS5_C_S32K3XX_
4051 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4052 #endif
4053 }
4054 }
4055
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_94(void)4056 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_94(void)
4057 {
4058 uint32 msr;
4059 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4060
4061 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_94[u32CoreId])
4062 {
4063 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
4064 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
4065 #else
4066 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
4067 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
4068 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
4069 {
4070 OsIf_SuspendAllInterrupts();
4071 #ifdef _ARM_DS5_C_S32K3XX_
4072 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4073 #endif
4074 }
4075 msr_ADC_EXCLUSIVE_AREA_94[u32CoreId] = msr;
4076 }
4077 reentry_guard_ADC_EXCLUSIVE_AREA_94[u32CoreId]++;
4078 }
4079
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_94(void)4080 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_94(void)
4081 {
4082 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4083
4084 reentry_guard_ADC_EXCLUSIVE_AREA_94[u32CoreId]--;
4085 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_94[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_94[u32CoreId])) /*if interrupts were enabled*/
4086 {
4087 OsIf_ResumeAllInterrupts();
4088 #ifdef _ARM_DS5_C_S32K3XX_
4089 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4090 #endif
4091 }
4092 }
4093
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_95(void)4094 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_95(void)
4095 {
4096 uint32 msr;
4097 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4098
4099 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_95[u32CoreId])
4100 {
4101 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
4102 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
4103 #else
4104 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
4105 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
4106 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
4107 {
4108 OsIf_SuspendAllInterrupts();
4109 #ifdef _ARM_DS5_C_S32K3XX_
4110 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4111 #endif
4112 }
4113 msr_ADC_EXCLUSIVE_AREA_95[u32CoreId] = msr;
4114 }
4115 reentry_guard_ADC_EXCLUSIVE_AREA_95[u32CoreId]++;
4116 }
4117
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_95(void)4118 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_95(void)
4119 {
4120 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4121
4122 reentry_guard_ADC_EXCLUSIVE_AREA_95[u32CoreId]--;
4123 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_95[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_95[u32CoreId])) /*if interrupts were enabled*/
4124 {
4125 OsIf_ResumeAllInterrupts();
4126 #ifdef _ARM_DS5_C_S32K3XX_
4127 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4128 #endif
4129 }
4130 }
4131
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_96(void)4132 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_96(void)
4133 {
4134 uint32 msr;
4135 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4136
4137 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_96[u32CoreId])
4138 {
4139 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
4140 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
4141 #else
4142 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
4143 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
4144 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
4145 {
4146 OsIf_SuspendAllInterrupts();
4147 #ifdef _ARM_DS5_C_S32K3XX_
4148 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4149 #endif
4150 }
4151 msr_ADC_EXCLUSIVE_AREA_96[u32CoreId] = msr;
4152 }
4153 reentry_guard_ADC_EXCLUSIVE_AREA_96[u32CoreId]++;
4154 }
4155
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_96(void)4156 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_96(void)
4157 {
4158 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4159
4160 reentry_guard_ADC_EXCLUSIVE_AREA_96[u32CoreId]--;
4161 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_96[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_96[u32CoreId])) /*if interrupts were enabled*/
4162 {
4163 OsIf_ResumeAllInterrupts();
4164 #ifdef _ARM_DS5_C_S32K3XX_
4165 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4166 #endif
4167 }
4168 }
4169
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_97(void)4170 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_97(void)
4171 {
4172 uint32 msr;
4173 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4174
4175 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_97[u32CoreId])
4176 {
4177 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
4178 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
4179 #else
4180 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
4181 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
4182 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
4183 {
4184 OsIf_SuspendAllInterrupts();
4185 #ifdef _ARM_DS5_C_S32K3XX_
4186 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4187 #endif
4188 }
4189 msr_ADC_EXCLUSIVE_AREA_97[u32CoreId] = msr;
4190 }
4191 reentry_guard_ADC_EXCLUSIVE_AREA_97[u32CoreId]++;
4192 }
4193
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_97(void)4194 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_97(void)
4195 {
4196 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4197
4198 reentry_guard_ADC_EXCLUSIVE_AREA_97[u32CoreId]--;
4199 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_97[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_97[u32CoreId])) /*if interrupts were enabled*/
4200 {
4201 OsIf_ResumeAllInterrupts();
4202 #ifdef _ARM_DS5_C_S32K3XX_
4203 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4204 #endif
4205 }
4206 }
4207
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_98(void)4208 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_98(void)
4209 {
4210 uint32 msr;
4211 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4212
4213 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_98[u32CoreId])
4214 {
4215 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
4216 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
4217 #else
4218 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
4219 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
4220 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
4221 {
4222 OsIf_SuspendAllInterrupts();
4223 #ifdef _ARM_DS5_C_S32K3XX_
4224 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4225 #endif
4226 }
4227 msr_ADC_EXCLUSIVE_AREA_98[u32CoreId] = msr;
4228 }
4229 reentry_guard_ADC_EXCLUSIVE_AREA_98[u32CoreId]++;
4230 }
4231
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_98(void)4232 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_98(void)
4233 {
4234 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4235
4236 reentry_guard_ADC_EXCLUSIVE_AREA_98[u32CoreId]--;
4237 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_98[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_98[u32CoreId])) /*if interrupts were enabled*/
4238 {
4239 OsIf_ResumeAllInterrupts();
4240 #ifdef _ARM_DS5_C_S32K3XX_
4241 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4242 #endif
4243 }
4244 }
4245
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_99(void)4246 void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_99(void)
4247 {
4248 uint32 msr;
4249 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4250
4251 if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_99[u32CoreId])
4252 {
4253 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
4254 msr = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
4255 #else
4256 msr = Adc_schm_read_msr(); /*read MSR (to store interrupts state)*/
4257 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
4258 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
4259 {
4260 OsIf_SuspendAllInterrupts();
4261 #ifdef _ARM_DS5_C_S32K3XX_
4262 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4263 #endif
4264 }
4265 msr_ADC_EXCLUSIVE_AREA_99[u32CoreId] = msr;
4266 }
4267 reentry_guard_ADC_EXCLUSIVE_AREA_99[u32CoreId]++;
4268 }
4269
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_99(void)4270 void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_99(void)
4271 {
4272 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4273
4274 reentry_guard_ADC_EXCLUSIVE_AREA_99[u32CoreId]--;
4275 if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_99[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_99[u32CoreId])) /*if interrupts were enabled*/
4276 {
4277 OsIf_ResumeAllInterrupts();
4278 #ifdef _ARM_DS5_C_S32K3XX_
4279 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
4280 #endif
4281 }
4282 }
4283
4284
4285 #ifdef MCAL_TESTING_ENVIRONMENT
4286 /**
4287 @brief This function checks that all entered exclusive areas were also exited.
4288 @details This function checks that all entered exclusive areas were also exited. The check
4289 is done by verifying that all reentry_guard_* static variables are back to the
4290 zero value.
4291
4292 @param[in] void No input parameters
4293 @return void This function does not return a value. Test asserts are used instead.
4294
4295 @pre None
4296 @post None
4297
4298 @remarks Covers
4299 @remarks Implements
4300 */
SchM_Check_adc(void)4301 void SchM_Check_adc(void)
4302 {
4303 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
4304
4305 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId]);
4306 reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_00 for the next test in the suite*/
4307
4308 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId]);
4309 reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_01 for the next test in the suite*/
4310
4311 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId]);
4312 reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_02 for the next test in the suite*/
4313
4314 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId]);
4315 reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_03 for the next test in the suite*/
4316
4317 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId]);
4318 reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_04 for the next test in the suite*/
4319
4320 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId]);
4321 reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_05 for the next test in the suite*/
4322
4323 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId]);
4324 reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_10 for the next test in the suite*/
4325
4326 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_100[u32CoreId]);
4327 reentry_guard_ADC_EXCLUSIVE_AREA_100[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_100 for the next test in the suite*/
4328
4329 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_101[u32CoreId]);
4330 reentry_guard_ADC_EXCLUSIVE_AREA_101[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_101 for the next test in the suite*/
4331
4332 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_102[u32CoreId]);
4333 reentry_guard_ADC_EXCLUSIVE_AREA_102[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_102 for the next test in the suite*/
4334
4335 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_103[u32CoreId]);
4336 reentry_guard_ADC_EXCLUSIVE_AREA_103[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_103 for the next test in the suite*/
4337
4338 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId]);
4339 reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_11 for the next test in the suite*/
4340
4341 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId]);
4342 reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_12 for the next test in the suite*/
4343
4344 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId]);
4345 reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_13 for the next test in the suite*/
4346
4347 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId]);
4348 reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_14 for the next test in the suite*/
4349
4350 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId]);
4351 reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_15 for the next test in the suite*/
4352
4353 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId]);
4354 reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_16 for the next test in the suite*/
4355
4356 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId]);
4357 reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_17 for the next test in the suite*/
4358
4359 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId]);
4360 reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_18 for the next test in the suite*/
4361
4362 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId]);
4363 reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_19 for the next test in the suite*/
4364
4365 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId]);
4366 reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_20 for the next test in the suite*/
4367
4368 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId]);
4369 reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_21 for the next test in the suite*/
4370
4371 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId]);
4372 reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_22 for the next test in the suite*/
4373
4374 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId]);
4375 reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_23 for the next test in the suite*/
4376
4377 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId]);
4378 reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_24 for the next test in the suite*/
4379
4380 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId]);
4381 reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_25 for the next test in the suite*/
4382
4383 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId]);
4384 reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_26 for the next test in the suite*/
4385
4386 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId]);
4387 reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_27 for the next test in the suite*/
4388
4389 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId]);
4390 reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_28 for the next test in the suite*/
4391
4392 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId]);
4393 reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_29 for the next test in the suite*/
4394
4395 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId]);
4396 reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_30 for the next test in the suite*/
4397
4398 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId]);
4399 reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_31 for the next test in the suite*/
4400
4401 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId]);
4402 reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_32 for the next test in the suite*/
4403
4404 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId]);
4405 reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_33 for the next test in the suite*/
4406
4407 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId]);
4408 reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_34 for the next test in the suite*/
4409
4410 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId]);
4411 reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_35 for the next test in the suite*/
4412
4413 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId]);
4414 reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_36 for the next test in the suite*/
4415
4416 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId]);
4417 reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_37 for the next test in the suite*/
4418
4419 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId]);
4420 reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_38 for the next test in the suite*/
4421
4422 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId]);
4423 reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_39 for the next test in the suite*/
4424
4425 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId]);
4426 reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_40 for the next test in the suite*/
4427
4428 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId]);
4429 reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_41 for the next test in the suite*/
4430
4431 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId]);
4432 reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_42 for the next test in the suite*/
4433
4434 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId]);
4435 reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_43 for the next test in the suite*/
4436
4437 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId]);
4438 reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_44 for the next test in the suite*/
4439
4440 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId]);
4441 reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_45 for the next test in the suite*/
4442
4443 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId]);
4444 reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_46 for the next test in the suite*/
4445
4446 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId]);
4447 reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_47 for the next test in the suite*/
4448
4449 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId]);
4450 reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_48 for the next test in the suite*/
4451
4452 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId]);
4453 reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_49 for the next test in the suite*/
4454
4455 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId]);
4456 reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_50 for the next test in the suite*/
4457
4458 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_51[u32CoreId]);
4459 reentry_guard_ADC_EXCLUSIVE_AREA_51[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_51 for the next test in the suite*/
4460
4461 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId]);
4462 reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_54 for the next test in the suite*/
4463
4464 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId]);
4465 reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_55 for the next test in the suite*/
4466
4467 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId]);
4468 reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_56 for the next test in the suite*/
4469
4470 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId]);
4471 reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_57 for the next test in the suite*/
4472
4473 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId]);
4474 reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_58 for the next test in the suite*/
4475
4476 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId]);
4477 reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_59 for the next test in the suite*/
4478
4479 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId]);
4480 reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_60 for the next test in the suite*/
4481
4482 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId]);
4483 reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_61 for the next test in the suite*/
4484
4485 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId]);
4486 reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_62 for the next test in the suite*/
4487
4488 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId]);
4489 reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_63 for the next test in the suite*/
4490
4491 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId]);
4492 reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_64 for the next test in the suite*/
4493
4494 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId]);
4495 reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_65 for the next test in the suite*/
4496
4497 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId]);
4498 reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_66 for the next test in the suite*/
4499
4500 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId]);
4501 reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_67 for the next test in the suite*/
4502
4503 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId]);
4504 reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_68 for the next test in the suite*/
4505
4506 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId]);
4507 reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_69 for the next test in the suite*/
4508
4509 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId]);
4510 reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_70 for the next test in the suite*/
4511
4512 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId]);
4513 reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_71 for the next test in the suite*/
4514
4515 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId]);
4516 reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_72 for the next test in the suite*/
4517
4518 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId]);
4519 reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_73 for the next test in the suite*/
4520
4521 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_74[u32CoreId]);
4522 reentry_guard_ADC_EXCLUSIVE_AREA_74[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_74 for the next test in the suite*/
4523
4524 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_75[u32CoreId]);
4525 reentry_guard_ADC_EXCLUSIVE_AREA_75[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_75 for the next test in the suite*/
4526
4527 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_76[u32CoreId]);
4528 reentry_guard_ADC_EXCLUSIVE_AREA_76[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_76 for the next test in the suite*/
4529
4530 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_77[u32CoreId]);
4531 reentry_guard_ADC_EXCLUSIVE_AREA_77[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_77 for the next test in the suite*/
4532
4533 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_78[u32CoreId]);
4534 reentry_guard_ADC_EXCLUSIVE_AREA_78[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_78 for the next test in the suite*/
4535
4536 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_79[u32CoreId]);
4537 reentry_guard_ADC_EXCLUSIVE_AREA_79[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_79 for the next test in the suite*/
4538
4539 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_80[u32CoreId]);
4540 reentry_guard_ADC_EXCLUSIVE_AREA_80[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_80 for the next test in the suite*/
4541
4542 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_81[u32CoreId]);
4543 reentry_guard_ADC_EXCLUSIVE_AREA_81[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_81 for the next test in the suite*/
4544
4545 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_82[u32CoreId]);
4546 reentry_guard_ADC_EXCLUSIVE_AREA_82[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_82 for the next test in the suite*/
4547
4548 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_83[u32CoreId]);
4549 reentry_guard_ADC_EXCLUSIVE_AREA_83[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_83 for the next test in the suite*/
4550
4551 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_84[u32CoreId]);
4552 reentry_guard_ADC_EXCLUSIVE_AREA_84[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_84 for the next test in the suite*/
4553
4554 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_85[u32CoreId]);
4555 reentry_guard_ADC_EXCLUSIVE_AREA_85[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_85 for the next test in the suite*/
4556
4557 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_86[u32CoreId]);
4558 reentry_guard_ADC_EXCLUSIVE_AREA_86[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_86 for the next test in the suite*/
4559
4560 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_87[u32CoreId]);
4561 reentry_guard_ADC_EXCLUSIVE_AREA_87[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_87 for the next test in the suite*/
4562
4563 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_88[u32CoreId]);
4564 reentry_guard_ADC_EXCLUSIVE_AREA_88[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_88 for the next test in the suite*/
4565
4566 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_89[u32CoreId]);
4567 reentry_guard_ADC_EXCLUSIVE_AREA_89[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_89 for the next test in the suite*/
4568
4569 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_90[u32CoreId]);
4570 reentry_guard_ADC_EXCLUSIVE_AREA_90[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_90 for the next test in the suite*/
4571
4572 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_91[u32CoreId]);
4573 reentry_guard_ADC_EXCLUSIVE_AREA_91[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_91 for the next test in the suite*/
4574
4575 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_92[u32CoreId]);
4576 reentry_guard_ADC_EXCLUSIVE_AREA_92[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_92 for the next test in the suite*/
4577
4578 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_93[u32CoreId]);
4579 reentry_guard_ADC_EXCLUSIVE_AREA_93[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_93 for the next test in the suite*/
4580
4581 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_94[u32CoreId]);
4582 reentry_guard_ADC_EXCLUSIVE_AREA_94[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_94 for the next test in the suite*/
4583
4584 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_95[u32CoreId]);
4585 reentry_guard_ADC_EXCLUSIVE_AREA_95[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_95 for the next test in the suite*/
4586
4587 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_96[u32CoreId]);
4588 reentry_guard_ADC_EXCLUSIVE_AREA_96[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_96 for the next test in the suite*/
4589
4590 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_97[u32CoreId]);
4591 reentry_guard_ADC_EXCLUSIVE_AREA_97[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_97 for the next test in the suite*/
4592
4593 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_98[u32CoreId]);
4594 reentry_guard_ADC_EXCLUSIVE_AREA_98[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_98 for the next test in the suite*/
4595
4596 EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_99[u32CoreId]);
4597 reentry_guard_ADC_EXCLUSIVE_AREA_99[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_99 for the next test in the suite*/
4598
4599
4600 }
4601 #endif /*MCAL_TESTING_ENVIRONMENT*/
4602
4603 #define RTE_STOP_SEC_CODE
4604 #include "Rte_MemMap.h"
4605
4606 #ifdef __cplusplus
4607 }
4608 #endif
4609
4610 /** @} */
4611
