1 /*
2 * Copyright 2021-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Can_43_CANEXCEL.c
9 * @version 1.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Can_43_CANEXCEL.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_CAN_43_CANEXCEL_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_CAN_43_CANEXCEL_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_CAN_43_CANEXCEL_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_CAN_43_CANEXCEL_SW_MAJOR_VERSION_C 1
44 #define SCHM_CAN_43_CANEXCEL_SW_MINOR_VERSION_C 0
45 #define SCHM_CAN_43_CANEXCEL_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_00) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_01) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_02) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_03) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_04) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_05) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_06) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_07) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_08) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_09) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_10) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_11) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_12) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_13) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_14) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_15) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_16) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_17) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_18) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_19) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_19) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_20) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_20) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
144
145 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
146 #include "Rte_MemMap.h"
147 /*==================================================================================================
148 * GLOBAL CONSTANTS
149 ==================================================================================================*/
150
151
152 /*==================================================================================================
153 * GLOBAL VARIABLES
154 ==================================================================================================*/
155
156 /*==================================================================================================
157 * LOCAL FUNCTION PROTOTYPES
158 ==================================================================================================*/
159
160 #ifndef _COSMIC_C_S32ZE_
161 /*================================================================================================*/
162 /**
163 * @brief This function returns the MSR register value (32 bits).
164 * @details This function returns the MSR register value (32 bits).
165 *
166 * @param[in] void No input parameters
167 * @return uint32 msr This function returns the MSR register value (32 bits).
168 *
169 * @pre None
170 * @post None
171 *
172 */
173 uint32 Can_43_CANEXCEL_schm_read_msr(void);
174 #endif /*ifndef _COSMIC_C_S32ZE_*/
175 /*==================================================================================================
176 * LOCAL FUNCTIONS
177 ==================================================================================================*/
178 #define RTE_START_SEC_CODE
179 #include "Rte_MemMap.h"
180
181 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
182 /*================================================================================================*/
183 /**
184 * @brief This macro returns the MSR register value (32 bits).
185 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
186 *
187 * @pre None
188 * @post None
189 *
190 */
191 #ifdef MCAL_PLATFORM_ARM
192 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Can_43_CANEXCEL_schm_read_msr(void)193 ASM_KEYWORD uint32 Can_43_CANEXCEL_schm_read_msr(void)
194 {
195 mrs x0, S3_3_c4_c2_1
196 }
197 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Can_43_CANEXCEL_schm_read_msr(void)198 ASM_KEYWORD uint32 Can_43_CANEXCEL_schm_read_msr(void)
199 {
200 mrs r0, CPSR
201 }
202 #else
Can_43_CANEXCEL_schm_read_msr(void)203 ASM_KEYWORD uint32 Can_43_CANEXCEL_schm_read_msr(void)
204 {
205 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
206 mrs r0, BASEPRI
207 #else
208 mrs r0, PRIMASK
209 #endif
210 }
211 #endif
212 #else
213 #ifdef MCAL_PLATFORM_S12
Can_43_CANEXCEL_schm_read_msr(void)214 ASM_KEYWORD uint32 Can_43_CANEXCEL_schm_read_msr(void)
215 {
216 tfr ccr, d6
217 }
218 #else
Can_43_CANEXCEL_schm_read_msr(void)219 ASM_KEYWORD uint32 Can_43_CANEXCEL_schm_read_msr(void)
220 {
221 mfmsr r3
222 }
223 #endif
224 #endif
225 #endif /*#ifdef GHS||CW*/
226
227 #ifdef _DIABDATA_C_S32ZE_
228 /**
229 * @brief This function returns the MSR register value (32 bits).
230 * @details This function returns the MSR register value (32 bits).
231 *
232 * @param[in] void No input parameters
233 * @return uint32 msr This function returns the MSR register value (32 bits).
234 *
235 * @pre None
236 * @post None
237 *
238 */
239 #ifdef MCAL_PLATFORM_ARM
Can_43_CANEXCEL_schm_read_msr(void)240 uint32 Can_43_CANEXCEL_schm_read_msr(void)
241 {
242 register uint32 reg_tmp;
243 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
244 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
245 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
246 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
247 #else
248 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
249 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
250 #else
251 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
252 #endif
253 #endif
254 return (uint32)reg_tmp;
255 }
256 #else
Can_43_CANEXCEL_schm_read_msr(void)257 ASM_KEYWORD uint32 Can_43_CANEXCEL_schm_read_msr(void)
258 {
259 mfmsr r3
260 }
261 #endif /* MCAL_PLATFORM_ARM */
262
263 #endif /* _DIABDATA_C_S32ZE_*/
264
265 #ifdef _COSMIC_C_S32ZE_
266 /*================================================================================================*/
267 /**
268 * @brief This function returns the MSR register value (32 bits).
269 * @details This function returns the MSR register value (32 bits).
270 *
271 * @param[in] void No input parameters
272 * @return uint32 msr This function returns the MSR register value (32 bits).
273 *
274 * @pre None
275 * @post None
276 *
277 */
278
279 #ifdef MCAL_PLATFORM_S12
280 #define Can_43_CANEXCEL_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
281 #else
282 #define Can_43_CANEXCEL_schm_read_msr() ASM_KEYWORD("mfmsr r3")
283 #endif
284
285 #endif /*Cosmic compiler only*/
286
287
288 #ifdef _HITECH_C_S32ZE_
289 /*================================================================================================*/
290 /**
291 * @brief This function returns the MSR register value (32 bits).
292 * @details This function returns the MSR register value (32 bits).
293 *
294 * @param[in] void No input parameters
295 * @return uint32 msr This function returns the MSR register value (32 bits).
296 *
297 * @pre None
298 * @post None
299 *
300 */
Can_43_CANEXCEL_schm_read_msr(void)301 uint32 Can_43_CANEXCEL_schm_read_msr(void)
302 {
303 uint32 result;
304 __asm volatile("mfmsr %0" : "=r" (result) :);
305 return result;
306 }
307
308 #endif /*HighTec compiler only*/
309 /*================================================================================================*/
310 #ifdef _LINARO_C_S32ZE_
311 /**
312 * @brief This function returns the MSR register value (32 bits).
313 * @details This function returns the MSR register value (32 bits).
314 *
315 * @param[in] void No input parameters
316 * @return uint32 msr This function returns the MSR register value (32 bits).
317 *
318 * @pre None
319 * @post None
320 *
321 */
Can_43_CANEXCEL_schm_read_msr(void)322 uint32 Can_43_CANEXCEL_schm_read_msr(void)
323 {
324 register uint32 reg_tmp;
325 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
326 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
327 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
328 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
329 #else
330 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
331 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
332 #else
333 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
334 #endif
335 #endif
336 return (uint32)reg_tmp;
337 }
338 #endif /* _LINARO_C_S32ZE_*/
339 /*================================================================================================*/
340
341 #ifdef _ARM_DS5_C_S32ZE_
342 /**
343 * @brief This function returns the MSR register value (32 bits).
344 * @details This function returns the MSR register value (32 bits).
345 *
346 * @param[in] void No input parameters
347 * @return uint32 msr This function returns the MSR register value (32 bits).
348 *
349 * @pre None
350 * @post None
351 *
352 */
Can_43_CANEXCEL_schm_read_msr(void)353 uint32 Can_43_CANEXCEL_schm_read_msr(void)
354 {
355 register uint32 reg_tmp;
356 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
357 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
358 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
359 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
360 #else
361 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
362 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
363 #else
364 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
365 #endif
366 #endif
367 return (uint32)reg_tmp;
368 }
369 #endif /* _ARM_DS5_C_S32ZE_ */
370
371 #ifdef _IAR_C_S32ZE_
372 /**
373 * @brief This function returns the MSR register value (32 bits).
374 * @details This function returns the MSR register value (32 bits).
375 *
376 * @param[in] void No input parameters
377 * @return uint32 msr This function returns the MSR register value (32 bits).
378 *
379 * @pre None
380 * @post None
381 *
382 */
Can_43_CANEXCEL_schm_read_msr(void)383 uint32 Can_43_CANEXCEL_schm_read_msr(void)
384 {
385 register uint32 reg_tmp;
386
387 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
388 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
389 #else
390 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
391 #endif
392
393 return (uint32)reg_tmp;
394 }
395 #endif /* _IAR_C_S32ZE_ */
396
397 #define RTE_STOP_SEC_CODE
398 #include "Rte_MemMap.h"
399
400 /*==================================================================================================
401 * GLOBAL FUNCTIONS
402 ==================================================================================================*/
403 #define RTE_START_SEC_CODE
404 #include "Rte_MemMap.h"
405
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_00(void)406 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_00(void)
407 {
408 uint32 msr;
409 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
410
411 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_00[u32CoreId])
412 {
413 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
414 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
415 #else
416 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
417 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
418 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
419 {
420 OsIf_SuspendAllInterrupts();
421 #ifdef _ARM_DS5_C_S32ZE_
422 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
423 #endif
424 }
425 msr_CAN_EXCLUSIVE_AREA_00[u32CoreId] = msr;
426 }
427 reentry_guard_CAN_EXCLUSIVE_AREA_00[u32CoreId]++;
428 }
429
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_00(void)430 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_00(void)
431 {
432 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
433
434 reentry_guard_CAN_EXCLUSIVE_AREA_00[u32CoreId]--;
435 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
436 {
437 OsIf_ResumeAllInterrupts();
438 #ifdef _ARM_DS5_C_S32ZE_
439 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
440 #endif
441 }
442 }
443
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_01(void)444 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_01(void)
445 {
446 uint32 msr;
447 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
448
449 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_01[u32CoreId])
450 {
451 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
452 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
453 #else
454 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
455 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
456 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
457 {
458 OsIf_SuspendAllInterrupts();
459 #ifdef _ARM_DS5_C_S32ZE_
460 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
461 #endif
462 }
463 msr_CAN_EXCLUSIVE_AREA_01[u32CoreId] = msr;
464 }
465 reentry_guard_CAN_EXCLUSIVE_AREA_01[u32CoreId]++;
466 }
467
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_01(void)468 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_01(void)
469 {
470 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
471
472 reentry_guard_CAN_EXCLUSIVE_AREA_01[u32CoreId]--;
473 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
474 {
475 OsIf_ResumeAllInterrupts();
476 #ifdef _ARM_DS5_C_S32ZE_
477 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
478 #endif
479 }
480 }
481
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_02(void)482 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_02(void)
483 {
484 uint32 msr;
485 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
486
487 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_02[u32CoreId])
488 {
489 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
490 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
491 #else
492 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
493 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
494 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
495 {
496 OsIf_SuspendAllInterrupts();
497 #ifdef _ARM_DS5_C_S32ZE_
498 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
499 #endif
500 }
501 msr_CAN_EXCLUSIVE_AREA_02[u32CoreId] = msr;
502 }
503 reentry_guard_CAN_EXCLUSIVE_AREA_02[u32CoreId]++;
504 }
505
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_02(void)506 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_02(void)
507 {
508 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
509
510 reentry_guard_CAN_EXCLUSIVE_AREA_02[u32CoreId]--;
511 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
512 {
513 OsIf_ResumeAllInterrupts();
514 #ifdef _ARM_DS5_C_S32ZE_
515 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
516 #endif
517 }
518 }
519
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_03(void)520 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_03(void)
521 {
522 uint32 msr;
523 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
524
525 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_03[u32CoreId])
526 {
527 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
528 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
529 #else
530 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
531 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
532 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
533 {
534 OsIf_SuspendAllInterrupts();
535 #ifdef _ARM_DS5_C_S32ZE_
536 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
537 #endif
538 }
539 msr_CAN_EXCLUSIVE_AREA_03[u32CoreId] = msr;
540 }
541 reentry_guard_CAN_EXCLUSIVE_AREA_03[u32CoreId]++;
542 }
543
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_03(void)544 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_03(void)
545 {
546 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
547
548 reentry_guard_CAN_EXCLUSIVE_AREA_03[u32CoreId]--;
549 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
550 {
551 OsIf_ResumeAllInterrupts();
552 #ifdef _ARM_DS5_C_S32ZE_
553 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
554 #endif
555 }
556 }
557
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_04(void)558 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_04(void)
559 {
560 uint32 msr;
561 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
562
563 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_04[u32CoreId])
564 {
565 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
566 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
567 #else
568 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
569 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
570 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
571 {
572 OsIf_SuspendAllInterrupts();
573 #ifdef _ARM_DS5_C_S32ZE_
574 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
575 #endif
576 }
577 msr_CAN_EXCLUSIVE_AREA_04[u32CoreId] = msr;
578 }
579 reentry_guard_CAN_EXCLUSIVE_AREA_04[u32CoreId]++;
580 }
581
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_04(void)582 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_04(void)
583 {
584 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
585
586 reentry_guard_CAN_EXCLUSIVE_AREA_04[u32CoreId]--;
587 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
588 {
589 OsIf_ResumeAllInterrupts();
590 #ifdef _ARM_DS5_C_S32ZE_
591 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
592 #endif
593 }
594 }
595
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_05(void)596 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_05(void)
597 {
598 uint32 msr;
599 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
600
601 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_05[u32CoreId])
602 {
603 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
604 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
605 #else
606 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
607 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
608 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
609 {
610 OsIf_SuspendAllInterrupts();
611 #ifdef _ARM_DS5_C_S32ZE_
612 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
613 #endif
614 }
615 msr_CAN_EXCLUSIVE_AREA_05[u32CoreId] = msr;
616 }
617 reentry_guard_CAN_EXCLUSIVE_AREA_05[u32CoreId]++;
618 }
619
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_05(void)620 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_05(void)
621 {
622 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
623
624 reentry_guard_CAN_EXCLUSIVE_AREA_05[u32CoreId]--;
625 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
626 {
627 OsIf_ResumeAllInterrupts();
628 #ifdef _ARM_DS5_C_S32ZE_
629 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
630 #endif
631 }
632 }
633
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_06(void)634 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_06(void)
635 {
636 uint32 msr;
637 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
638
639 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_06[u32CoreId])
640 {
641 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
642 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
643 #else
644 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
645 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
646 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
647 {
648 OsIf_SuspendAllInterrupts();
649 #ifdef _ARM_DS5_C_S32ZE_
650 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
651 #endif
652 }
653 msr_CAN_EXCLUSIVE_AREA_06[u32CoreId] = msr;
654 }
655 reentry_guard_CAN_EXCLUSIVE_AREA_06[u32CoreId]++;
656 }
657
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_06(void)658 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_06(void)
659 {
660 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
661
662 reentry_guard_CAN_EXCLUSIVE_AREA_06[u32CoreId]--;
663 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
664 {
665 OsIf_ResumeAllInterrupts();
666 #ifdef _ARM_DS5_C_S32ZE_
667 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
668 #endif
669 }
670 }
671
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_07(void)672 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_07(void)
673 {
674 uint32 msr;
675 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
676
677 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_07[u32CoreId])
678 {
679 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
680 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
681 #else
682 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
683 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
684 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
685 {
686 OsIf_SuspendAllInterrupts();
687 #ifdef _ARM_DS5_C_S32ZE_
688 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
689 #endif
690 }
691 msr_CAN_EXCLUSIVE_AREA_07[u32CoreId] = msr;
692 }
693 reentry_guard_CAN_EXCLUSIVE_AREA_07[u32CoreId]++;
694 }
695
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_07(void)696 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_07(void)
697 {
698 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
699
700 reentry_guard_CAN_EXCLUSIVE_AREA_07[u32CoreId]--;
701 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
702 {
703 OsIf_ResumeAllInterrupts();
704 #ifdef _ARM_DS5_C_S32ZE_
705 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
706 #endif
707 }
708 }
709
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_08(void)710 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_08(void)
711 {
712 uint32 msr;
713 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
714
715 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_08[u32CoreId])
716 {
717 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
718 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
719 #else
720 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
721 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
722 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
723 {
724 OsIf_SuspendAllInterrupts();
725 #ifdef _ARM_DS5_C_S32ZE_
726 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
727 #endif
728 }
729 msr_CAN_EXCLUSIVE_AREA_08[u32CoreId] = msr;
730 }
731 reentry_guard_CAN_EXCLUSIVE_AREA_08[u32CoreId]++;
732 }
733
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_08(void)734 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_08(void)
735 {
736 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
737
738 reentry_guard_CAN_EXCLUSIVE_AREA_08[u32CoreId]--;
739 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
740 {
741 OsIf_ResumeAllInterrupts();
742 #ifdef _ARM_DS5_C_S32ZE_
743 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
744 #endif
745 }
746 }
747
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_09(void)748 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_09(void)
749 {
750 uint32 msr;
751 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
752
753 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_09[u32CoreId])
754 {
755 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
756 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
757 #else
758 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
759 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
760 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
761 {
762 OsIf_SuspendAllInterrupts();
763 #ifdef _ARM_DS5_C_S32ZE_
764 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
765 #endif
766 }
767 msr_CAN_EXCLUSIVE_AREA_09[u32CoreId] = msr;
768 }
769 reentry_guard_CAN_EXCLUSIVE_AREA_09[u32CoreId]++;
770 }
771
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_09(void)772 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_09(void)
773 {
774 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
775
776 reentry_guard_CAN_EXCLUSIVE_AREA_09[u32CoreId]--;
777 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
778 {
779 OsIf_ResumeAllInterrupts();
780 #ifdef _ARM_DS5_C_S32ZE_
781 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
782 #endif
783 }
784 }
785
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_10(void)786 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_10(void)
787 {
788 uint32 msr;
789 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
790
791 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_10[u32CoreId])
792 {
793 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
794 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
795 #else
796 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
797 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
798 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
799 {
800 OsIf_SuspendAllInterrupts();
801 #ifdef _ARM_DS5_C_S32ZE_
802 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
803 #endif
804 }
805 msr_CAN_EXCLUSIVE_AREA_10[u32CoreId] = msr;
806 }
807 reentry_guard_CAN_EXCLUSIVE_AREA_10[u32CoreId]++;
808 }
809
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_10(void)810 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_10(void)
811 {
812 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
813
814 reentry_guard_CAN_EXCLUSIVE_AREA_10[u32CoreId]--;
815 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
816 {
817 OsIf_ResumeAllInterrupts();
818 #ifdef _ARM_DS5_C_S32ZE_
819 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
820 #endif
821 }
822 }
823
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_11(void)824 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_11(void)
825 {
826 uint32 msr;
827 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
828
829 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_11[u32CoreId])
830 {
831 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
832 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
833 #else
834 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
835 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
836 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
837 {
838 OsIf_SuspendAllInterrupts();
839 #ifdef _ARM_DS5_C_S32ZE_
840 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
841 #endif
842 }
843 msr_CAN_EXCLUSIVE_AREA_11[u32CoreId] = msr;
844 }
845 reentry_guard_CAN_EXCLUSIVE_AREA_11[u32CoreId]++;
846 }
847
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_11(void)848 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_11(void)
849 {
850 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
851
852 reentry_guard_CAN_EXCLUSIVE_AREA_11[u32CoreId]--;
853 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
854 {
855 OsIf_ResumeAllInterrupts();
856 #ifdef _ARM_DS5_C_S32ZE_
857 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
858 #endif
859 }
860 }
861
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_12(void)862 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_12(void)
863 {
864 uint32 msr;
865 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
866
867 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_12[u32CoreId])
868 {
869 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
870 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
871 #else
872 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
873 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
874 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
875 {
876 OsIf_SuspendAllInterrupts();
877 #ifdef _ARM_DS5_C_S32ZE_
878 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
879 #endif
880 }
881 msr_CAN_EXCLUSIVE_AREA_12[u32CoreId] = msr;
882 }
883 reentry_guard_CAN_EXCLUSIVE_AREA_12[u32CoreId]++;
884 }
885
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_12(void)886 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_12(void)
887 {
888 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
889
890 reentry_guard_CAN_EXCLUSIVE_AREA_12[u32CoreId]--;
891 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
892 {
893 OsIf_ResumeAllInterrupts();
894 #ifdef _ARM_DS5_C_S32ZE_
895 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
896 #endif
897 }
898 }
899
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_13(void)900 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_13(void)
901 {
902 uint32 msr;
903 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
904
905 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_13[u32CoreId])
906 {
907 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
908 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
909 #else
910 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
911 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
912 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
913 {
914 OsIf_SuspendAllInterrupts();
915 #ifdef _ARM_DS5_C_S32ZE_
916 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
917 #endif
918 }
919 msr_CAN_EXCLUSIVE_AREA_13[u32CoreId] = msr;
920 }
921 reentry_guard_CAN_EXCLUSIVE_AREA_13[u32CoreId]++;
922 }
923
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_13(void)924 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_13(void)
925 {
926 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
927
928 reentry_guard_CAN_EXCLUSIVE_AREA_13[u32CoreId]--;
929 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
930 {
931 OsIf_ResumeAllInterrupts();
932 #ifdef _ARM_DS5_C_S32ZE_
933 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
934 #endif
935 }
936 }
937
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_14(void)938 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_14(void)
939 {
940 uint32 msr;
941 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
942
943 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_14[u32CoreId])
944 {
945 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
946 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
947 #else
948 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
949 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
950 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
951 {
952 OsIf_SuspendAllInterrupts();
953 #ifdef _ARM_DS5_C_S32ZE_
954 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
955 #endif
956 }
957 msr_CAN_EXCLUSIVE_AREA_14[u32CoreId] = msr;
958 }
959 reentry_guard_CAN_EXCLUSIVE_AREA_14[u32CoreId]++;
960 }
961
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_14(void)962 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_14(void)
963 {
964 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
965
966 reentry_guard_CAN_EXCLUSIVE_AREA_14[u32CoreId]--;
967 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
968 {
969 OsIf_ResumeAllInterrupts();
970 #ifdef _ARM_DS5_C_S32ZE_
971 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
972 #endif
973 }
974 }
975
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_15(void)976 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_15(void)
977 {
978 uint32 msr;
979 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
980
981 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_15[u32CoreId])
982 {
983 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
984 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
985 #else
986 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
987 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
988 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
989 {
990 OsIf_SuspendAllInterrupts();
991 #ifdef _ARM_DS5_C_S32ZE_
992 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
993 #endif
994 }
995 msr_CAN_EXCLUSIVE_AREA_15[u32CoreId] = msr;
996 }
997 reentry_guard_CAN_EXCLUSIVE_AREA_15[u32CoreId]++;
998 }
999
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_15(void)1000 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_15(void)
1001 {
1002 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1003
1004 reentry_guard_CAN_EXCLUSIVE_AREA_15[u32CoreId]--;
1005 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
1006 {
1007 OsIf_ResumeAllInterrupts();
1008 #ifdef _ARM_DS5_C_S32ZE_
1009 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1010 #endif
1011 }
1012 }
1013
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_16(void)1014 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_16(void)
1015 {
1016 uint32 msr;
1017 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1018
1019 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_16[u32CoreId])
1020 {
1021 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1022 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
1023 #else
1024 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
1025 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1026 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1027 {
1028 OsIf_SuspendAllInterrupts();
1029 #ifdef _ARM_DS5_C_S32ZE_
1030 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1031 #endif
1032 }
1033 msr_CAN_EXCLUSIVE_AREA_16[u32CoreId] = msr;
1034 }
1035 reentry_guard_CAN_EXCLUSIVE_AREA_16[u32CoreId]++;
1036 }
1037
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_16(void)1038 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_16(void)
1039 {
1040 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1041
1042 reentry_guard_CAN_EXCLUSIVE_AREA_16[u32CoreId]--;
1043 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
1044 {
1045 OsIf_ResumeAllInterrupts();
1046 #ifdef _ARM_DS5_C_S32ZE_
1047 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1048 #endif
1049 }
1050 }
1051
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_17(void)1052 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_17(void)
1053 {
1054 uint32 msr;
1055 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1056
1057 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_17[u32CoreId])
1058 {
1059 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1060 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
1061 #else
1062 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
1063 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1064 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1065 {
1066 OsIf_SuspendAllInterrupts();
1067 #ifdef _ARM_DS5_C_S32ZE_
1068 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1069 #endif
1070 }
1071 msr_CAN_EXCLUSIVE_AREA_17[u32CoreId] = msr;
1072 }
1073 reentry_guard_CAN_EXCLUSIVE_AREA_17[u32CoreId]++;
1074 }
1075
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_17(void)1076 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_17(void)
1077 {
1078 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1079
1080 reentry_guard_CAN_EXCLUSIVE_AREA_17[u32CoreId]--;
1081 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
1082 {
1083 OsIf_ResumeAllInterrupts();
1084 #ifdef _ARM_DS5_C_S32ZE_
1085 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1086 #endif
1087 }
1088 }
1089
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_18(void)1090 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_18(void)
1091 {
1092 uint32 msr;
1093 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1094
1095 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_18[u32CoreId])
1096 {
1097 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1098 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
1099 #else
1100 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
1101 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1102 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1103 {
1104 OsIf_SuspendAllInterrupts();
1105 #ifdef _ARM_DS5_C_S32ZE_
1106 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1107 #endif
1108 }
1109 msr_CAN_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1110 }
1111 reentry_guard_CAN_EXCLUSIVE_AREA_18[u32CoreId]++;
1112 }
1113
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_18(void)1114 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_18(void)
1115 {
1116 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1117
1118 reentry_guard_CAN_EXCLUSIVE_AREA_18[u32CoreId]--;
1119 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1120 {
1121 OsIf_ResumeAllInterrupts();
1122 #ifdef _ARM_DS5_C_S32ZE_
1123 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1124 #endif
1125 }
1126 }
1127
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_19(void)1128 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_19(void)
1129 {
1130 uint32 msr;
1131 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1132
1133 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_19[u32CoreId])
1134 {
1135 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1136 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
1137 #else
1138 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
1139 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1140 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1141 {
1142 OsIf_SuspendAllInterrupts();
1143 #ifdef _ARM_DS5_C_S32ZE_
1144 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1145 #endif
1146 }
1147 msr_CAN_EXCLUSIVE_AREA_19[u32CoreId] = msr;
1148 }
1149 reentry_guard_CAN_EXCLUSIVE_AREA_19[u32CoreId]++;
1150 }
1151
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_19(void)1152 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_19(void)
1153 {
1154 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1155
1156 reentry_guard_CAN_EXCLUSIVE_AREA_19[u32CoreId]--;
1157 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_19[u32CoreId])) /*if interrupts were enabled*/
1158 {
1159 OsIf_ResumeAllInterrupts();
1160 #ifdef _ARM_DS5_C_S32ZE_
1161 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1162 #endif
1163 }
1164 }
1165
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_20(void)1166 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_20(void)
1167 {
1168 uint32 msr;
1169 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1170
1171 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_20[u32CoreId])
1172 {
1173 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1174 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
1175 #else
1176 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
1177 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1178 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1179 {
1180 OsIf_SuspendAllInterrupts();
1181 #ifdef _ARM_DS5_C_S32ZE_
1182 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1183 #endif
1184 }
1185 msr_CAN_EXCLUSIVE_AREA_20[u32CoreId] = msr;
1186 }
1187 reentry_guard_CAN_EXCLUSIVE_AREA_20[u32CoreId]++;
1188 }
1189
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_20(void)1190 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_20(void)
1191 {
1192 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1193
1194 reentry_guard_CAN_EXCLUSIVE_AREA_20[u32CoreId]--;
1195 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
1196 {
1197 OsIf_ResumeAllInterrupts();
1198 #ifdef _ARM_DS5_C_S32ZE_
1199 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1200 #endif
1201 }
1202 }
1203
1204
1205 #ifdef MCAL_TESTING_ENVIRONMENT
1206 /**
1207 @brief This function checks that all entered exclusive areas were also exited.
1208 @details This function checks that all entered exclusive areas were also exited. The check
1209 is done by verifying that all reentry_guard_* static variables are back to the
1210 zero value.
1211
1212 @param[in] void No input parameters
1213 @return void This function does not return a value. Test asserts are used instead.
1214
1215 @pre None
1216 @post None
1217
1218 @remarks Covers
1219 @remarks Implements
1220 */
SchM_Check_can_43_CANEXCEL(void)1221 void SchM_Check_can_43_CANEXCEL(void)
1222 {
1223 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1224
1225 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_00[u32CoreId]);
1226 reentry_guard_CAN_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_00 for the next test in the suite*/
1227
1228 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_01[u32CoreId]);
1229 reentry_guard_CAN_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_01 for the next test in the suite*/
1230
1231 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_02[u32CoreId]);
1232 reentry_guard_CAN_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_02 for the next test in the suite*/
1233
1234 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_03[u32CoreId]);
1235 reentry_guard_CAN_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_03 for the next test in the suite*/
1236
1237 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_04[u32CoreId]);
1238 reentry_guard_CAN_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_04 for the next test in the suite*/
1239
1240 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_05[u32CoreId]);
1241 reentry_guard_CAN_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_05 for the next test in the suite*/
1242
1243 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_06[u32CoreId]);
1244 reentry_guard_CAN_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_06 for the next test in the suite*/
1245
1246 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_07[u32CoreId]);
1247 reentry_guard_CAN_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_07 for the next test in the suite*/
1248
1249 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_08[u32CoreId]);
1250 reentry_guard_CAN_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_08 for the next test in the suite*/
1251
1252 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_09[u32CoreId]);
1253 reentry_guard_CAN_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_09 for the next test in the suite*/
1254
1255 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_10[u32CoreId]);
1256 reentry_guard_CAN_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_10 for the next test in the suite*/
1257
1258 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_11[u32CoreId]);
1259 reentry_guard_CAN_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_11 for the next test in the suite*/
1260
1261 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_12[u32CoreId]);
1262 reentry_guard_CAN_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_12 for the next test in the suite*/
1263
1264 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_13[u32CoreId]);
1265 reentry_guard_CAN_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_13 for the next test in the suite*/
1266
1267 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_14[u32CoreId]);
1268 reentry_guard_CAN_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_14 for the next test in the suite*/
1269
1270 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_15[u32CoreId]);
1271 reentry_guard_CAN_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_15 for the next test in the suite*/
1272
1273 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_16[u32CoreId]);
1274 reentry_guard_CAN_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_16 for the next test in the suite*/
1275
1276 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_17[u32CoreId]);
1277 reentry_guard_CAN_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_17 for the next test in the suite*/
1278
1279 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_18[u32CoreId]);
1280 reentry_guard_CAN_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_18 for the next test in the suite*/
1281
1282 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_19[u32CoreId]);
1283 reentry_guard_CAN_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_19 for the next test in the suite*/
1284
1285 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_20[u32CoreId]);
1286 reentry_guard_CAN_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_20 for the next test in the suite*/
1287
1288
1289 }
1290 #endif /*MCAL_TESTING_ENVIRONMENT*/
1291
1292 #define RTE_STOP_SEC_CODE
1293 #include "Rte_MemMap.h"
1294
1295 #ifdef __cplusplus
1296 }
1297 #endif
1298
1299 /** @} */
1300
