1 /* 2 * Copyright (c) 2017-2022 ARM Limited. All rights reserved. 3 * Copyright (c) 2019-2023 Cypress Semiconductor Corporation (an Infineon company) 4 * or an affiliate of Cypress Semiconductor Corporation. All rights reserved. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef __REGION_DEFS_H__ 20 #define __REGION_DEFS_H__ 21 22 #include "flash_layout.h" 23 24 #ifdef BL2 25 #error "BL2 configuration is not supported" 26 #endif /* BL2 */ 27 28 #define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE 29 /* 2KB of RAM (at the end of the SRAM) are reserved for system use. Using 30 * this memory region for other purposes will lead to unexpected behavior. 31 * 94KB of RAM (just before the memory reserved for system use) are 32 * allocated and protected by Cypress Bootloader */ 33 /* FixMe: confirm exact available amount of RAM based on the actual 34 system allocation */ 35 #define TOTAL_RAM_SIZE (0x000E8000) /* CY_SRAM_SIZE - 96KB */ 36 37 #ifdef ENABLE_HEAP 38 #define S_HEAP_SIZE (0x0000200) 39 #endif 40 41 #define S_MSP_STACK_SIZE 0x0000800 42 43 #define NS_HEAP_SIZE 0x0001000 44 #define NS_STACK_SIZE (0x0000200) 45 46 /* 47 * MPC granularity is 128 KB on AN519 MPS2 FPGA image. Alignment 48 * of partitions is defined in accordance with this constraint. 49 */ 50 51 #define S_IMAGE_PRIMARY_PARTITION_OFFSET SECURE_IMAGE_OFFSET 52 #define NS_IMAGE_PRIMARY_PARTITION_OFFSET NON_SECURE_IMAGE_OFFSET 53 54 /* TFM PSoC6 CY8CKIT_064 RAM layout: 55 * 56 * 0x0800_0000 - 0x0802_FFFF Secure (192KB) 57 * 0x0800_0000 - 0x0800_7FFF Secure unprivileged data (S_UNPRIV_DATA_SIZE, 32KB) 58 * 0x0800_8000 - 0x0802_F7FF Secure priviliged data (S_PRIV_DATA_SIZE, 158KB) 59 * 0x0802_F800 - 0x0802_FFFF Secure priv code executable from RAM (S_RAM_CODE_SIZE, 2KB) 60 * 61 * 0x0803_0000 - 0x080E_7FFF Non-secure (736KB) 62 * 0x0803_0000 - 0x080E_6FFF Non-secure OS/App (732KB) 63 * 0x080E_6C00 - 0x080E_6FFF PSA NVMEM (PSA_NVMEM_SIZE, 1KB) (if PSA_API_TEST_ENABLED) 64 * 0x080E_7000 - 0x080E_7FFF Shared memory (NS_DATA_SHARED_SIZE, 4KB) 65 * 0x080E_8000 - 0x080F_FFFF System reserved memory (96KB) 66 * 0x0810_0000 End of RAM 67 */ 68 69 /* 70 * Boot partition structure if MCUBoot is used: 71 * 0x0_0000 Bootloader header 72 * 0x0_0400 Image area 73 * 0x1_FC00 Trailer 74 */ 75 /* Image code size is the space available for the software binary image. 76 * It is less than the FLASH_S_PARTITION_SIZE and FLASH_NS_PARTITION_SIZE 77 * because we reserve space for the image header and trailer introduced by the 78 * bootloader. 79 */ 80 /* Even though TFM BL2 is excluded from the build, 81 * CY BL built externally is used and it needs offsets for header and trailer 82 * to be taken in account. 83 * */ 84 #define CYBL_HEADER_SIZE (0x400) 85 #define CYBL_TRAILER_SIZE (0x400) 86 87 #define IMAGE_S_CODE_SIZE \ 88 (FLASH_S_PARTITION_SIZE - CYBL_HEADER_SIZE - CYBL_TRAILER_SIZE) 89 #define IMAGE_NS_CODE_SIZE \ 90 (FLASH_NS_PARTITION_SIZE - CYBL_HEADER_SIZE - CYBL_TRAILER_SIZE) 91 92 /* Alias definitions for secure and non-secure areas*/ 93 #define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) 94 #define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) 95 96 #define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) 97 #define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) 98 99 /* Secure regions */ 100 #define S_IMAGE_PRIMARY_AREA_OFFSET \ 101 (S_IMAGE_PRIMARY_PARTITION_OFFSET + CYBL_HEADER_SIZE) 102 #define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) 103 #define S_CODE_SIZE IMAGE_S_CODE_SIZE 104 #define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) 105 106 #define S_DATA_START (S_RAM_ALIAS(0)) 107 #define S_UNPRIV_DATA_SIZE 0x08000 108 #define S_PRIV_DATA_SIZE 0x27800 109 /* Reserve 2KB for RAM-based executable code */ 110 #define S_RAM_CODE_SIZE 0x800 111 112 /* Secure data area */ 113 #define S_DATA_SIZE (S_UNPRIV_DATA_SIZE + S_PRIV_DATA_SIZE + S_RAM_CODE_SIZE) 114 #define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) 115 116 /* We need the privileged data area to be aligned so that an SMPU 117 * region can cover it. 118 */ 119 /* TODO It would be nice to figure this out automatically. 120 * In theory, in the linker script, we could determine the amount 121 * of secure data space available after all the unprivileged data, 122 * round that down to a power of 2 to get the actual size we want 123 * to use for privileged data, and then determine this value from 124 * that. We'd also potentially have to update the SMPU configs. 125 * 126 * Instead, there's an alignment check in SMPU configuration file. 127 */ 128 #define S_DATA_UNPRIV_OFFSET (0) 129 #define S_DATA_UNPRIV_START S_RAM_ALIAS(S_DATA_UNPRIV_OFFSET) 130 131 #define S_DATA_PRIV_OFFSET (S_DATA_UNPRIV_OFFSET + S_UNPRIV_DATA_SIZE) 132 #define S_DATA_PRIV_START S_RAM_ALIAS(S_DATA_PRIV_OFFSET) 133 134 /* Reserve area for RAM-based executable code right after secure unprivileged 135 * and privileged data areas*/ 136 #define S_RAM_CODE_OFFSET (S_DATA_PRIV_OFFSET + S_PRIV_DATA_SIZE) 137 #define S_RAM_CODE_START S_RAM_ALIAS(S_RAM_CODE_OFFSET) 138 139 /* Size of vector table: 31 interrupt handlers + 4 bytes MPS initial value */ 140 #define S_CODE_VECTOR_TABLE_SIZE (0x80) 141 142 /* Non-secure regions */ 143 #define NS_IMAGE_PRIMARY_AREA_OFFSET \ 144 (NS_IMAGE_PRIMARY_PARTITION_OFFSET + CYBL_HEADER_SIZE) 145 #define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) 146 #define NS_CODE_SIZE IMAGE_NS_CODE_SIZE 147 #define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) 148 149 #define NS_DATA_START (S_RAM_ALIAS(S_DATA_SIZE)) 150 #define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) 151 #define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) 152 153 /* Shared memory */ 154 #define NS_DATA_SHARED_SIZE 0x1000 155 #define NS_DATA_SHARED_START (NS_DATA_START + NS_DATA_SIZE - \ 156 NS_DATA_SHARED_SIZE) 157 #define NS_DATA_SHARED_LIMIT (NS_DATA_SHARED_START + NS_DATA_SHARED_SIZE - 1) 158 159 /* PSA NVMEM: before Shared memory */ 160 #ifdef PSA_API_TEST_ENABLED 161 #define PSA_API_TEST_NVMEM_SIZE 0x400 162 #define PSA_API_TEST_NVMEM_START \ 163 (NS_DATA_SHARED_START - PSA_API_TEST_NVMEM_SIZE) 164 /* PSA NVMEM + Shared memory should <= NS_DATA_SIZE */ 165 #if (PSA_API_TEST_NVMEM_SIZE + NS_DATA_SHARED_SIZE) > NS_DATA_SIZE 166 #error "Non-Secure memory usage overflow" 167 #endif 168 #endif /* PSA_API_TEST_ENABLED */ 169 170 /* Shared variables addresses */ 171 /* ipcWaitMessageStc, cy_flash.c */ 172 #define IPC_WAIT_MESSAGE_STC_SIZE 4 173 #define IPC_WAIT_MESSAGE_STC_ADDR (NS_DATA_SHARED_START + \ 174 NS_DATA_SHARED_SIZE - \ 175 IPC_WAIT_MESSAGE_STC_SIZE) 176 177 /* NS partition information is used for MPC and SAU configuration */ 178 #define NS_PARTITION_START \ 179 (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)) 180 181 #define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) 182 183 /* Shared data area between bootloader and runtime firmware. 184 * Shared data area is allocated at the beginning of the privileged data area, 185 * it is overlapping with TF-M Secure code's MSP stack 186 */ 187 #define BOOT_TFM_SHARED_DATA_BASE (S_RAM_ALIAS(S_DATA_PRIV_OFFSET)) 188 #define BOOT_TFM_SHARED_DATA_SIZE 0x400 189 190 #endif /* __REGION_DEFS_H__ */ 191
