1 /* 2 * Copyright (c) 2017-2022 ARM Limited. All rights reserved. 3 * Copyright (c) 2019-2021 Cypress Semiconductor Corp. All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef __REGION_DEFS_H__ 19 #define __REGION_DEFS_H__ 20 21 #include "flash_layout.h" 22 23 #ifdef BL2 24 #error "BL2 configuration is not supported" 25 #endif /* BL2 */ 26 27 #define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE 28 /* 2KB of RAM (at the end of the SRAM) are reserved for system use. Using 29 * this memory region for other purposes will lead to unexpected behavior. 30 * 94KB of RAM (just before the memory reserved for system use) are 31 * allocated and protected by Cypress Bootloader */ 32 /* FixMe: confirm exact available amount of RAM based on the actual 33 system allocation */ 34 #define TOTAL_RAM_SIZE (0x000E8000) /* CY_SRAM_SIZE - 96KB */ 35 36 #ifdef ENABLE_HEAP 37 #define S_HEAP_SIZE (0x0000200) 38 #endif 39 40 #define S_MSP_STACK_SIZE 0x0000800 41 42 #define NS_HEAP_SIZE 0x0001000 43 #define NS_STACK_SIZE (0x0000200) 44 45 /* 46 * This size of buffer is big enough to store an attestation 47 * token produced by initial attestation service 48 */ 49 #define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE 0x250 50 51 /* 52 * MPC granularity is 128 KB on AN519 MPS2 FPGA image. Alignment 53 * of partitions is defined in accordance with this constraint. 54 */ 55 56 #define S_IMAGE_PRIMARY_PARTITION_OFFSET SECURE_IMAGE_OFFSET 57 #define NS_IMAGE_PRIMARY_PARTITION_OFFSET NON_SECURE_IMAGE_OFFSET 58 59 /* TFM PSoC6 CY8CKIT_064 RAM layout: 60 * 61 * 0x0800_0000 - 0x0802_FFFF Secure (192KB) 62 * 0x0800_0000 - 0x0800_7FFF Secure unprivileged data (S_UNPRIV_DATA_SIZE, 32KB) 63 * 0x0800_8000 - 0x0802_F7FF Secure priviliged data (S_PRIV_DATA_SIZE, 158KB) 64 * 0x0802_F800 - 0x0802_FFFF Secure priv code executable from RAM (S_RAM_CODE_SIZE, 2KB) 65 * 66 * 0x0803_0000 - 0x080E_7FFF Non-secure (736KB) 67 * 0x0803_0000 - 0x080E_6FFF Non-secure OS/App (732KB) 68 * 0x080E_6C00 - 0x080E_6FFF PSA NVMEM (PSA_NVMEM_SIZE, 1KB) (if PSA_API_TEST_ENABLED) 69 * 0x080E_7000 - 0x080E_7FFF Shared memory (NS_DATA_SHARED_SIZE, 4KB) 70 * 0x080E_8000 - 0x080F_FFFF System reserved memory (96KB) 71 * 0x0810_0000 End of RAM 72 */ 73 74 /* 75 * Boot partition structure if MCUBoot is used: 76 * 0x0_0000 Bootloader header 77 * 0x0_0400 Image area 78 * 0x1_FC00 Trailer 79 */ 80 /* Image code size is the space available for the software binary image. 81 * It is less than the FLASH_S_PARTITION_SIZE and FLASH_NS_PARTITION_SIZE 82 * because we reserve space for the image header and trailer introduced by the 83 * bootloader. 84 */ 85 /* Even though TFM BL2 is excluded from the build, 86 * CY BL built externally is used and it needs offsets for header and trailer 87 * to be taken in account. 88 * */ 89 #define CYBL_HEADER_SIZE (0x400) 90 #define CYBL_TRAILER_SIZE (0x400) 91 92 #define IMAGE_S_CODE_SIZE \ 93 (FLASH_S_PARTITION_SIZE - CYBL_HEADER_SIZE - CYBL_TRAILER_SIZE) 94 #define IMAGE_NS_CODE_SIZE \ 95 (FLASH_NS_PARTITION_SIZE - CYBL_HEADER_SIZE - CYBL_TRAILER_SIZE) 96 97 /* Alias definitions for secure and non-secure areas*/ 98 #define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) 99 #define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) 100 101 #define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) 102 #define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) 103 104 /* Secure regions */ 105 #define S_IMAGE_PRIMARY_AREA_OFFSET \ 106 (S_IMAGE_PRIMARY_PARTITION_OFFSET + CYBL_HEADER_SIZE) 107 #define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) 108 #define S_CODE_SIZE IMAGE_S_CODE_SIZE 109 #define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) 110 111 #define S_DATA_START (S_RAM_ALIAS(0)) 112 #define S_UNPRIV_DATA_SIZE 0x08000 113 #define S_PRIV_DATA_SIZE 0x27800 114 /* Reserve 2KB for RAM-based executable code */ 115 #define S_RAM_CODE_SIZE 0x800 116 117 /* Secure data area */ 118 #define S_DATA_SIZE (S_UNPRIV_DATA_SIZE + S_PRIV_DATA_SIZE + S_RAM_CODE_SIZE) 119 #define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) 120 121 /* We need the privileged data area to be aligned so that an SMPU 122 * region can cover it. 123 */ 124 /* TODO It would be nice to figure this out automatically. 125 * In theory, in the linker script, we could determine the amount 126 * of secure data space available after all the unprivileged data, 127 * round that down to a power of 2 to get the actual size we want 128 * to use for privileged data, and then determine this value from 129 * that. We'd also potentially have to update the SMPU configs. 130 * 131 * Instead, there's an alignment check in SMPU configuration file. 132 */ 133 #define S_DATA_UNPRIV_OFFSET (0) 134 #define S_DATA_UNPRIV_START S_RAM_ALIAS(S_DATA_UNPRIV_OFFSET) 135 136 #define S_DATA_PRIV_OFFSET (S_DATA_UNPRIV_OFFSET + S_UNPRIV_DATA_SIZE) 137 #define S_DATA_PRIV_START S_RAM_ALIAS(S_DATA_PRIV_OFFSET) 138 139 /* Reserve area for RAM-based executable code right after secure unprivileged 140 * and privileged data areas*/ 141 #define S_RAM_CODE_OFFSET (S_DATA_PRIV_OFFSET + S_PRIV_DATA_SIZE) 142 #define S_RAM_CODE_START S_RAM_ALIAS(S_RAM_CODE_OFFSET) 143 144 /* Size of vector table: 31 interrupt handlers + 4 bytes MPS initial value */ 145 #define S_CODE_VECTOR_TABLE_SIZE (0x80) 146 147 /* Non-secure regions */ 148 #define NS_IMAGE_PRIMARY_AREA_OFFSET \ 149 (NS_IMAGE_PRIMARY_PARTITION_OFFSET + CYBL_HEADER_SIZE) 150 #define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) 151 #define NS_CODE_SIZE IMAGE_NS_CODE_SIZE 152 #define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) 153 154 #define NS_DATA_START (S_RAM_ALIAS(S_DATA_SIZE)) 155 #define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) 156 #define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) 157 158 /* Shared memory */ 159 #define NS_DATA_SHARED_SIZE 0x1000 160 #define NS_DATA_SHARED_START (NS_DATA_START + NS_DATA_SIZE - \ 161 NS_DATA_SHARED_SIZE) 162 #define NS_DATA_SHARED_LIMIT (NS_DATA_SHARED_START + NS_DATA_SHARED_SIZE - 1) 163 164 /* PSA NVMEM: before Shared memory */ 165 #ifdef PSA_API_TEST_ENABLED 166 #define PSA_API_TEST_NVMEM_SIZE 0x400 167 #define PSA_API_TEST_NVMEM_START \ 168 (NS_DATA_SHARED_START - PSA_API_TEST_NVMEM_SIZE) 169 /* PSA NVMEM + Shared memory should <= NS_DATA_SIZE */ 170 #if (PSA_API_TEST_NVMEM_SIZE + NS_DATA_SHARED_SIZE) > NS_DATA_SIZE 171 #error "Non-Secure memory usage overflow" 172 #endif 173 #endif /* PSA_API_TEST_ENABLED */ 174 175 /* Shared variables addresses */ 176 /* ipcWaitMessageStc, cy_flash.c */ 177 #define IPC_WAIT_MESSAGE_STC_SIZE 4 178 #define IPC_WAIT_MESSAGE_STC_ADDR (NS_DATA_SHARED_START + \ 179 NS_DATA_SHARED_SIZE - \ 180 IPC_WAIT_MESSAGE_STC_SIZE) 181 182 /* NS partition information is used for MPC and SAU configuration */ 183 #define NS_PARTITION_START \ 184 (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)) 185 186 #define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) 187 188 /* Shared data area between bootloader and runtime firmware. 189 * Shared data area is allocated at the beginning of the privileged data area, 190 * it is overlapping with TF-M Secure code's MSP stack 191 */ 192 #define BOOT_TFM_SHARED_DATA_BASE (S_RAM_ALIAS(S_DATA_PRIV_OFFSET)) 193 #define BOOT_TFM_SHARED_DATA_SIZE 0x400 194 195 /* NSPE-to-SPE interrupt */ 196 #define MAILBOX_IRQ NvicMux7_IRQn 197 198 #endif /* __REGION_DEFS_H__ */ 199
