1 /**************************************************************************//** 2 * @file sys_reg.h 3 * @version V1.00 4 * @brief SYS register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __SYS_REG_H__ 10 #define __SYS_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- System Manger Controller -------------------------*/ 19 /** 20 @addtogroup SYS System Manger Controller(SYS) 21 Memory Mapped Structure for SYS Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var SYS_T::PDID 31 * Offset: 0x00 Part Device Identification Number Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[31:0] |PDID |Part Device Identification Number (Read Only) 36 * | | |This register reflects device part number code. 37 * | | |Software can read this register to identify which device is used. 38 * @var SYS_T::RSTSTS 39 * Offset: 0x04 System Reset Status Register 40 * --------------------------------------------------------------------------------------------------- 41 * |Bits |Field |Descriptions 42 * | :----: | :----: | :---- | 43 * |[0] |PORF |POR Reset Flag 44 * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. 45 * | | |0 = No reset from POR or CHIPRST. 46 * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. 47 * | | |Note: Write 1 to clear this bit to 0. 48 * |[1] |PINRF |nRESET Pin Reset Flag 49 * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. 50 * | | |0 = No reset from nRESET pin. 51 * | | |1 = Pin nRESET had issued the reset signal to reset the system. 52 * | | |Note: Write 1 to clear this bit to 0. 53 * |[2] |WDTRF |WDT Reset Flag 54 * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. 55 * | | |0 = No reset from watchdog timer or window watchdog timer. 56 * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. 57 * | | |Note 1: Write 1 to clear this bit to 0. 58 * | | |Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. 59 * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 60 * | | |Note 3: Extra Watchdog Timer register RSTF(EWDT_CTL[2]) bit is set if the system has been reset by EWDT time-out reset. 61 * | | |Extra Window Watchdog Timer register WWDTRF(EWWDT_STATUS[1]) bit is set if the system has been reset by EWWDT time-out reset. 62 * |[3] |LVRF |LVR Reset Flag 63 * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. 64 * | | |0 = No reset from LVR. 65 * | | |1 = LVR controller had issued the reset signal to reset the system. 66 * | | |Note: Write 1 to clear this bit to 0. 67 * |[4] |BODRF |BOD Reset Flag 68 * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-out Detector to indicate the previous reset source. 69 * | | |0 = No reset from BOD. 70 * | | |1 = The BOD had issued the reset signal to reset the system. 71 * | | |Note: Write 1 to clear this bit to 0. 72 * |[5] |SYSRF |System Reset Flag 73 * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M23 Core to indicate the previous reset source. 74 * | | |0 = No reset from Cortex-M23. 75 * | | |1 = The Cortex-M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23 core. 76 * | | |Note: Write 1 to clear this bit to 0. 77 * |[7] |CPURF |CPU Reset Flag 78 * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M23 Core and Flash Memory Controller (FMC). 79 * | | |0 = No reset from CPU. 80 * | | |1 = The Cortex-M23 Core and FMC are reset by software setting CPURST to 1. 81 * | | |Note: Write 1 to clear this bit to 0. 82 * |[8] |CPULKRF |CPU Lockup Reset Flag 83 * | | |The CPULK reset flag is set by hardware if Cortex-M23 lockup happened. 84 * | | |0 = No reset from CPU lockup happened. 85 * | | |1 = The Cortex-M23 lockup happened and chip is reset. 86 * | | |Note1: Write 1 to clear this bit to 0. 87 * | | |Note2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset. 88 * @var SYS_T::IPRST0 89 * Offset: 0x08 Peripheral Reset Control Register 0 90 * --------------------------------------------------------------------------------------------------- 91 * |Bits |Field |Descriptions 92 * | :----: | :----: | :---- | 93 * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) 94 * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. 95 * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. 96 * | | |0 = Chip normal operation. 97 * | | |1 = Chip one-shot reset. 98 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 99 * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) 100 * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. 101 * | | |0 = Processor core normal operation. 102 * | | |1 = Processor core one-shot reset. 103 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 104 * |[2] |PDMA0RST |PDMA0 Controller Reset (Write Protect) 105 * | | |Setting this bit to 1 will generate a reset signal to the PDMA0 (always secure). 106 * | | |User needs to set this bit to 0 to release from reset state. 107 * | | |0 = PDMA0 controller normal operation. 108 * | | |1 = PDMA0 controller reset. 109 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 110 * |[3] |EBIRST |EBI Controller Reset (Write Protect) 111 * | | |Set this bit to 1 will generate a reset signal to the EBI 112 * | | |User needs to set this bit to 0 to release from the reset state. 113 * | | |0 = EBI controller normal operation. 114 * | | |1 = EBI controller reset. 115 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 116 * |[4] |USBHRST |USB Host Controller Reset (Write Protect) 117 * | | |Set this bit to 1 will generate a reset signal to the USB Host. 118 * | | |User needs to set this bit to 0 to release from the reset state. 119 * | | |0 = USB Host controller normal operation. 120 * | | |1 = USB Host controller reset. 121 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 122 * |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect) 123 * | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller 124 * | | |User needs to set this bit to 0 to release from the reset state. 125 * | | |0 = SDHOST0 controller normal operation. 126 * | | |1 = SDHOST0 controller reset. 127 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 128 * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) 129 * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller 130 * | | |User needs to set this bit to 0 to release from the reset state. 131 * | | |0 = CRC calculation controller normal operation. 132 * | | |1 = CRC calculation controller reset. 133 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 134 * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect) 135 * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller. 136 * | | |User needs to set this bit to 0 to release from the reset state. 137 * | | |0 = CRYPTO controller normal operation. 138 * | | |1 = CRYPTO controller reset. 139 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 140 * |[13] |KSRST |Key Store Controller Reset (Write Protect) 141 * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller. 142 * | | |User needs to set this bit to 0 to release from the reset state. 143 * | | |0 = Key Store controller normal operation. 144 * | | |1 = Key Store controller reset. 145 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 146 * |[29] |PDMA1RST |PDMA1 Controller Reset (Write Protect) 147 * | | |Setting this bit to 1 will generate a reset signal to the PDMA1. 148 * | | |User needs to set this bit to 0 to release from reset state. 149 * | | |0 = PDMA1 controller normal operation. 150 * | | |1 = PDMA1 controller reset. 151 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 152 * @var SYS_T::IPRST1 153 * Offset: 0x0C Peripheral Reset Control Register 1 154 * --------------------------------------------------------------------------------------------------- 155 * |Bits |Field |Descriptions 156 * | :----: | :----: | :---- | 157 * |[1] |GPIORST |GPIO Controller Reset 158 * | | |0 = GPIO controller normal operation. 159 * | | |1 = GPIO controller reset. 160 * |[2] |TMR0RST |Timer0 Controller Reset 161 * | | |0 = Timer0 controller normal operation. 162 * | | |1 = Timer0 controller reset. 163 * |[3] |TMR1RST |Timer1 Controller Reset 164 * | | |0 = Timer1 controller normal operation. 165 * | | |1 = Timer1 controller reset. 166 * |[4] |TMR2RST |Timer2 Controller Reset 167 * | | |0 = Timer2 controller normal operation. 168 * | | |1 = Timer2 controller reset. 169 * |[5] |TMR3RST |Timer3 Controller Reset 170 * | | |0 = Timer3 controller normal operation. 171 * | | |1 = Timer3 controller reset. 172 * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset 173 * | | |0 = Analog Comparator 0/1 controller normal operation. 174 * | | |1 = Analog Comparator 0/1 controller reset. 175 * |[8] |I2C0RST |I2C0 Controller Reset 176 * | | |0 = I2C0 controller normal operation. 177 * | | |1 = I2C0 controller reset. 178 * |[9] |I2C1RST |I2C1 Controller Reset 179 * | | |0 = I2C1 controller normal operation. 180 * | | |1 = I2C1 controller reset. 181 * |[10] |I2C2RST |I2C2 Controller Reset 182 * | | |0 = I2C2 controller normal operation. 183 * | | |1 = I2C2 controller reset. 184 * |[12] |QSPI0RST |QSPI0 Controller Reset 185 * | | |0 = QSPI0 controller normal operation. 186 * | | |1 = QSPI0 controller reset. 187 * |[13] |SPI0RST |SPI0 Controller Reset 188 * | | |0 = SPI0 controller normal operation. 189 * | | |1 = SPI0 controller reset. 190 * |[14] |SPI1RST |SPI1 Controller Reset 191 * | | |0 = SPI1 controller normal operation. 192 * | | |1 = SPI1 controller reset. 193 * |[15] |SPI2RST |SPI2 Controller Reset 194 * | | |0 = SPI2 controller normal operation. 195 * | | |1 = SPI2 controller reset. 196 * |[16] |UART0RST |UART0 Controller Reset 197 * | | |0 = UART0 controller normal operation. 198 * | | |1 = UART0 controller reset. 199 * |[17] |UART1RST |UART1 Controller Reset 200 * | | |0 = UART1 controller normal operation. 201 * | | |1 = UART1 controller reset. 202 * |[18] |UART2RST |UART2 Controller Reset 203 * | | |0 = UART2 controller normal operation. 204 * | | |1 = UART2 controller reset. 205 * |[19] |UART3RST |UART3 Controller Reset 206 * | | |0 = UART3 controller normal operation. 207 * | | |1 = UART3 controller reset. 208 * |[20] |UART4RST |UART4 Controller Reset 209 * | | |0 = UART4 controller normal operation. 210 * | | |1 = UART4 controller reset. 211 * |[21] |UART5RST |UART5 Controller Reset 212 * | | |0 = UART5 controller normal operation. 213 * | | |1 = UART5 controller reset. 214 * |[24] |CAN0RST |CAN0 Controller Reset 215 * | | |0 = CAN0 controller normal operation. 216 * | | |1 = CAN0 controller reset. 217 * |[26] |OTGRST |OTG Controller Reset 218 * | | |0 = OTG controller normal operation. 219 * | | |1 = OTG controller reset. 220 * |[27] |USBDRST |USBD Controller Reset 221 * | | |0 = USBD controller normal operation. 222 * | | |1 = USBD controller reset. 223 * |[28] |EADCRST |EADC Controller Reset 224 * | | |0 = EADC controller normal operation. 225 * | | |1 = EADC controller reset. 226 * |[29] |I2S0RST |I2S0 Controller Reset 227 * | | |0 = I2S0 controller normal operation. 228 * | | |1 = I2S0 controller reset. 229 * |[30] |LCDRST |LCD Controller Reset 230 * | | |0 = LCD controller normal operation. 231 * | | |1 = LCD controller reset. 232 * |[31] |TRNGRST |TRNG Controller Reset 233 * | | |0 = TRNG controller normal operation. 234 * | | |1 = TRNG controller reset. 235 * @var SYS_T::IPRST2 236 * Offset: 0x10 Peripheral Reset Control Register 2 237 * --------------------------------------------------------------------------------------------------- 238 * |Bits |Field |Descriptions 239 * | :----: | :----: | :---- | 240 * |[0] |SC0RST |SC0 Controller Reset 241 * | | |0 = SC0 controller normal operation. 242 * | | |1 = SC0 controller reset. 243 * |[1] |SC1RST |SC1 Controller Reset 244 * | | |0 = SC1 controller normal operation. 245 * | | |1 = SC1 controller reset. 246 * |[2] |SC2RST |SC2 Controller Reset 247 * | | |0 = SC2 controller normal operation. 248 * | | |1 = SC2 controller reset. 249 * |[6] |SPI3RST |SPI3 Controller Reset 250 * | | |0 = SPI3 controller normal operation. 251 * | | |1 = SPI3 controller reset. 252 * |[8] |USCI0RST |USCI0 Controller Reset 253 * | | |0 = USCI0 controller normal operation. 254 * | | |1 = USCI0 controller reset. 255 * |[9] |USCI1RST |USCI1 Controller Reset 256 * | | |0 = USCI1 controller normal operation. 257 * | | |1 = USCI1 controller reset. 258 * |[12] |DACRST |DAC Controller Reset 259 * | | |0 = DAC controller normal operation. 260 * | | |1 = DAC controller reset. 261 * |[16] |EPWM0RST |EPWM0 Controller Reset 262 * | | |0 = EPWM0 controller normal operation. 263 * | | |1 = EPWM0 controller reset. 264 * |[17] |EPWM1RST |EPWM1 Controller Reset 265 * | | |0 = EPWM1 controller normal operation. 266 * | | |1 = EPWM1 controller reset. 267 * |[18] |BPWM0RST |BPWM0 Controller Reset 268 * | | |0 = BPWM0 controller normal operation. 269 * | | |1 = BPWM0 controller reset. 270 * |[19] |BPWM1RST |BPWM1 Controller Reset 271 * | | |0 = BPWM1 controller normal operation. 272 * | | |1 = BPWM1 controller reset. 273 * |[20] |TMR4RST |Timer4 Controller Reset 274 * | | |0 = Timer4 controller normal operation. 275 * | | |1 = Timer4 controller reset. 276 * |[21] |TMR5RST |Timer5 Controller Reset 277 * | | |0 = Timer5 controller normal operation. 278 * | | |1 = Timer5 controller reset. 279 * |[22] |QEI0RST |QEI0 Controller Reset 280 * | | |0 = QEI0 controller normal operation. 281 * | | |1 = QEI0 controller reset. 282 * |[23] |QEI1RST |QEI1 Controller Reset 283 * | | |0 = QEI1 controller normal operation. 284 * | | |1 = QEI1 controller reset. 285 * |[26] |ECAP0RST |ECAP0 Controller Reset 286 * | | |0 = ECAP0 controller normal operation. 287 * | | |1 = ECAP0 controller reset. 288 * |[27] |ECAP1RST |ECAP1 Controller Reset 289 * | | |0 = ECAP1 controller normal operation. 290 * | | |1 = ECAP1 controller reset. 291 * @var SYS_T::BODCTL 292 * Offset: 0x18 Brown-out Detector Control Register 293 * --------------------------------------------------------------------------------------------------- 294 * |Bits |Field |Descriptions 295 * | :----: | :----: | :---- | 296 * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) 297 * | | |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]). 298 * | | |0 = Brown-out Detector function Disabled. 299 * | | |1 = Brown-out Detector function Enabled. 300 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 301 * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) 302 * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit . 303 * | | |0 = Brown-out INTERRUPT function Enabled. 304 * | | |1 = Brown-out RESET function Enabled. 305 * | | |Note1: 306 * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). 307 * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if AVDD high.than BODVL, BOD interrupt will keep till to the BODIF set to 0. 308 * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). 309 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 310 * |[4] |BODIF |Brown-out Detector Interrupt Flag 311 * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. 312 * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. 313 * | | |Note: Write 1 to clear this bit to 0. 314 * |[6] |BODOUT |Brown-out Detector Output Status 315 * | | |0 = Brown-out Detector output status is 0. 316 * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. 317 * | | |1 = Brown-out Detector output status is 1. 318 * | | |It means the detected voltage is lower than BODVL setting. 319 * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0. 320 * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) 321 * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. 322 * | | |LVR function is enabled by default. 323 * | | |0 = Low Voltage Reset function Disabled. 324 * | | |1 = Low Voltage Reset function Enabled. 325 * | | |Note1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default). 326 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 327 * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) 328 * | | |000 = BOD output is sampled by LIRC clock. 329 * | | |001 = 4 system clock (HCLK). 330 * | | |010 = 8 system clock (HCLK). 331 * | | |011 = 16 system clock (HCLK). 332 * | | |100 = 32 system clock (HCLK). 333 * | | |101 = 64 system clock (HCLK). 334 * | | |110 = 128 system clock (HCLK). 335 * | | |111 = 256 system clock (HCLK). 336 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 337 * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) 338 * | | |000 = Without de-glitch function. 339 * | | |001 = 4 system clock (HCLK). 340 * | | |010 = 8 system clock (HCLK). 341 * | | |011 = 16 system clock (HCLK). 342 * | | |100 = 32 system clock (HCLK). 343 * | | |101 = 64 system clock (HCLK). 344 * | | |110 = 128 system clock (HCLK). 345 * | | |111 = 256 system clock (HCLK). 346 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 347 * |[23] |STB |Circuit Stable Flag (Read Only) 348 * | | |This bit indicates LVR and BOD already stable, system cannot detect LVR and BOD event when this bit is not set. 349 * | | |0 = LVR and BOD is not stable. 350 * | | |1 = LVR and BOD already stable. 351 * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) 352 * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]). 353 * | | |000 = Brown-out Detector threshold voltage is 1.6V. 354 * | | |001 = Brown-out Detector threshold voltage is 1.8V. 355 * | | |010 = Brown-out Detector threshold voltage is 2.0V. 356 * | | |011 = Brown-out Detector threshold voltage is 2.2V. 357 * | | |100 = Brown-out Detector threshold voltage is 2.4V. 358 * | | |101 = Brown-out Detector threshold voltage is 2.6V. 359 * | | |110 = Brown-out Detector threshold voltage is 2.8V. 360 * | | |111 = Brown-out Detector threshold voltage is 3.0V. 361 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 362 * |[31] |WRBUSY |Write Busy Flag (Read Only) 363 * | | |If SYS_BODCTL is written, this bit is asserted automatically by hardware, and is de-asserted when write procedure is finished. 364 * | | |0 = SYS_BODCTL register is ready for write operation. 365 * | | |1 = SYS_BODCTL register is busy on the last write operation. Other write operations are ignored. 366 * @var SYS_T::IVSCTL 367 * Offset: 0x1C Internal Voltage Source Control Register 368 * --------------------------------------------------------------------------------------------------- 369 * |Bits |Field |Descriptions 370 * | :----: | :----: | :---- | 371 * |[0] |VTEMPEN |Temperature Sensor Enable Bit 372 * | | |This bit is used to enable/disable temperature sensor function. 373 * | | |0 = Temperature sensor function Disabled (default). 374 * | | |1 = Temperature sensor function Enabled. 375 * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9. 376 * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit 377 * | | |This bit is used to enable/disable VBAT unity gain buffer function. 378 * | | |0 = VBAT unity gain buffer function Disabled (default). 379 * | | |1 = VBAT unity gain buffer function Enabled. 380 * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result. 381 * @var SYS_T::PORCTL0 382 * Offset: 0x24 Power-on Reset Controller Register 0 383 * --------------------------------------------------------------------------------------------------- 384 * |Bits |Field |Descriptions 385 * | :----: | :----: | :---- | 386 * |[15:0] |PORMASK |Power-on Reset Mask Enable Bit (Write Protect) 387 * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. 388 * | | |User can mask internal POR signal to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. 389 * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: 390 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. 391 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 392 * @var SYS_T::VREFCTL 393 * Offset: 0x28 VREF Control Register 394 * --------------------------------------------------------------------------------------------------- 395 * |Bits |Field |Descriptions 396 * | :----: | :----: | :---- | 397 * |[4:0] |VREFCTL |VREF Control Bits (Write Protect) 398 * | | |00000 = VREF is from external pin. 399 * | | |00011 = VREF is internal 1.6V. 400 * | | |00111 = VREF is internal 2.0V. 401 * | | |01011 = VREF is internal 2.5V. 402 * | | |01111 = VREF is internal 3.0V. 403 * | | |Others = Reserved. 404 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 405 * |[5] |IBIASSEL |VREF Bias Current Selection (Write Protect) 406 * | | |0 = Bias current from MEGBIAS. 407 * | | |1 = Bias current from internal. 408 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 409 * |[7:6] |PRELOADSEL|Pre-load Timing Selection (Write Protect) 410 * | | |00 = pre-load time is 60us for 0.1uF Capacitor. 411 * | | |01 = pre-load time is 310us for 1uF Capacitor. 412 * | | |10 = pre-load time is 1270us for 4.7uF Capacitor. 413 * | | |11 = pre-load time is 2650us for 10uF Capacitor. 414 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 415 * @var SYS_T::USBPHY 416 * Offset: 0x2C USB PHY Control Register 417 * --------------------------------------------------------------------------------------------------- 418 * |Bits |Field |Descriptions 419 * | :----: | :----: | :---- | 420 * |[1:0] |USBROLE |USB Role Option (Write Protect) 421 * | | |These two bits are used to select the role of USB. 422 * | | |00 = Standard USB Device mode. 423 * | | |01 = Standard USB Host mode. 424 * | | |10 = ID dependent mode. 425 * | | |11 = On-The-Go device mode (default). 426 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 427 * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable. 428 * |[8] |OTGPHYEN |USB OTG PHY Enable 429 * | | |This bit is used to enable/disable OTG PHY function. 430 * | | |0 = OTG PHY function Disabled (default). 431 * | | |1 = OTG PHY function Enabled. 432 * @var SYS_T::GPA_MFPL 433 * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register 434 * --------------------------------------------------------------------------------------------------- 435 * |Bits |Field |Descriptions 436 * | :----: | :----: | :---- | 437 * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection 438 * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection 439 * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection 440 * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection 441 * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection 442 * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection 443 * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection 444 * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection 445 * @var SYS_T::GPA_MFPH 446 * Offset: 0x34 GPIOA High Byte Multiple Function Control Register 447 * --------------------------------------------------------------------------------------------------- 448 * |Bits |Field |Descriptions 449 * | :----: | :----: | :---- | 450 * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection 451 * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection 452 * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection 453 * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection 454 * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection 455 * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection 456 * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection 457 * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection 458 * @var SYS_T::GPB_MFPL 459 * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register 460 * --------------------------------------------------------------------------------------------------- 461 * |Bits |Field |Descriptions 462 * | :----: | :----: | :---- | 463 * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection 464 * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection 465 * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection 466 * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection 467 * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection 468 * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection 469 * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection 470 * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection 471 * @var SYS_T::GPB_MFPH 472 * Offset: 0x3C GPIOB High Byte Multiple Function Control Register 473 * --------------------------------------------------------------------------------------------------- 474 * |Bits |Field |Descriptions 475 * | :----: | :----: | :---- | 476 * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection 477 * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection 478 * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection 479 * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection 480 * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection 481 * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection 482 * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection 483 * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection 484 * @var SYS_T::GPC_MFPL 485 * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register 486 * --------------------------------------------------------------------------------------------------- 487 * |Bits |Field |Descriptions 488 * | :----: | :----: | :---- | 489 * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection 490 * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection 491 * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection 492 * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection 493 * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection 494 * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection 495 * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection 496 * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection 497 * @var SYS_T::GPC_MFPH 498 * Offset: 0x44 GPIOC High Byte Multiple Function Control Register 499 * --------------------------------------------------------------------------------------------------- 500 * |Bits |Field |Descriptions 501 * | :----: | :----: | :---- | 502 * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection 503 * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection 504 * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection 505 * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection 506 * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection 507 * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection 508 * @var SYS_T::GPD_MFPL 509 * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register 510 * --------------------------------------------------------------------------------------------------- 511 * |Bits |Field |Descriptions 512 * | :----: | :----: | :---- | 513 * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection 514 * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection 515 * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection 516 * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection 517 * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection 518 * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection 519 * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection 520 * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection 521 * @var SYS_T::GPD_MFPH 522 * Offset: 0x4C GPIOD High Byte Multiple Function Control Register 523 * --------------------------------------------------------------------------------------------------- 524 * |Bits |Field |Descriptions 525 * | :----: | :----: | :---- | 526 * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection 527 * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection 528 * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection 529 * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection 530 * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection 531 * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection 532 * @var SYS_T::GPE_MFPL 533 * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register 534 * --------------------------------------------------------------------------------------------------- 535 * |Bits |Field |Descriptions 536 * | :----: | :----: | :---- | 537 * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection 538 * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection 539 * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection 540 * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection 541 * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection 542 * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection 543 * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection 544 * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection 545 * @var SYS_T::GPE_MFPH 546 * Offset: 0x54 GPIOE High Byte Multiple Function Control Register 547 * --------------------------------------------------------------------------------------------------- 548 * |Bits |Field |Descriptions 549 * | :----: | :----: | :---- | 550 * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection 551 * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection 552 * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection 553 * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection 554 * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection 555 * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection 556 * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection 557 * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection 558 * @var SYS_T::GPF_MFPL 559 * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register 560 * --------------------------------------------------------------------------------------------------- 561 * |Bits |Field |Descriptions 562 * | :----: | :----: | :---- | 563 * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection 564 * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection 565 * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection 566 * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection 567 * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection 568 * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection 569 * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection 570 * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection 571 * @var SYS_T::GPF_MFPH 572 * Offset: 0x5C GPIOF High Byte Multiple Function Control Register 573 * --------------------------------------------------------------------------------------------------- 574 * |Bits |Field |Descriptions 575 * | :----: | :----: | :---- | 576 * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection 577 * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection 578 * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection 579 * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection 580 * @var SYS_T::GPG_MFPL 581 * Offset: 0x60 GPIOG Low Byte Multiple Function Control Register 582 * --------------------------------------------------------------------------------------------------- 583 * |Bits |Field |Descriptions 584 * | :----: | :----: | :---- | 585 * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection 586 * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection 587 * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection 588 * @var SYS_T::GPG_MFPH 589 * Offset: 0x64 GPIOG High Byte Multiple Function Control Register 590 * --------------------------------------------------------------------------------------------------- 591 * |Bits |Field |Descriptions 592 * | :----: | :----: | :---- | 593 * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection 594 * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection 595 * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection 596 * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection 597 * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection 598 * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection 599 * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection 600 * @var SYS_T::GPH_MFPL 601 * Offset: 0x68 GPIOH Low Byte Multiple Function Control Register 602 * --------------------------------------------------------------------------------------------------- 603 * |Bits |Field |Descriptions 604 * | :----: | :----: | :---- | 605 * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection 606 * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection 607 * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection 608 * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection 609 * @var SYS_T::GPH_MFPH 610 * Offset: 0x6C GPIOH High Byte Multiple Function Control Register 611 * --------------------------------------------------------------------------------------------------- 612 * |Bits |Field |Descriptions 613 * | :----: | :----: | :---- | 614 * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection 615 * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection 616 * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection 617 * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection 618 * @var SYS_T::VTORSET 619 * Offset: 0xA0 VTOR Setting Register 620 * --------------------------------------------------------------------------------------------------- 621 * |Bits |Field |Descriptions 622 * | :----: | :----: | :---- | 623 * |[0] |VTORSET |VTOR Setting After SPD Wakeup (Write Protect) 624 * | | |This is the register to set the address of vector table after chip is waked up from SPD Power-down mode. 625 * | | |The value will be loaded to Vector Table Offset Register, which is at the address 0xE000ED08, when chip wake up from SPD mode. 626 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 627 * @var SYS_T::SRAMICTL 628 * Offset: 0xC0 System SRAM Parity Error Interrupt Enable Control Register 629 * --------------------------------------------------------------------------------------------------- 630 * |Bits |Field |Descriptions 631 * | :----: | :----: | :---- | 632 * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit 633 * | | |0 = SRAM parity check error interrupt Disabled. 634 * | | |1 = SRAM parity check error interrupt Enabled. 635 * @var SYS_T::SRAMSTS 636 * Offset: 0xC4 System SRAM Parity Check Status Register 637 * --------------------------------------------------------------------------------------------------- 638 * |Bits |Field |Descriptions 639 * | :----: | :----: | :---- | 640 * |[0] |PERRIF |SRAM Parity Check Error Flag 641 * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. 642 * | | |0 = No System SRAM parity error. 643 * | | |1 = System SRAM parity error occur. 644 * @var SYS_T::SRAMEADR 645 * Offset: 0xC8 System SRAM Parity Check Error Address Register 646 * --------------------------------------------------------------------------------------------------- 647 * |Bits |Field |Descriptions 648 * | :----: | :----: | :---- | 649 * |[31:0] |ERRADDR |System SRAM Parity Error Address 650 * | | |This register shows system SRAM parity error byte address. 651 * @var SYS_T::SRAMPC0 652 * Offset: 0xDC SRAM Power Mode Control Register 0 653 * --------------------------------------------------------------------------------------------------- 654 * |Bits |Field |Descriptions 655 * | :----: | :----: | :---- | 656 * |[1:0] |SRAM0PM0 |Bank0 SRAM Power Mode Select 0 (Write Protect) 657 * | | |This field can control SRAM bank0 selection 0 (4k) power mode for range 0x2000_0000 - 0x2000_0FFF. 658 * | | |00 = Normal mode. 659 * | | |01 = Retention mode. 660 * | | |10 = Power shut down mode. 661 * | | |11 = Reserved (Write Ignore). 662 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 663 * | | |Note 2: Write ignore when PCBUSY is 1. 664 * |[3:2] |SRAM0PM1 |Bank0 SRAM Power Mode Select 1 (Write Protect) 665 * | | |This field can control SRAM bank0 selection 1 power mode for range 0x2000_1000 - 0x2000_1FFF. 666 * | | |00 = Normal mode. 667 * | | |01 = Retention mode. 668 * | | |10 = Power shut down mode. 669 * | | |11 = Reserved (Write Ignore). 670 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 671 * | | |Note 2: Write ignore when PCBUSY is 1. 672 * |[5:4] |SRAM0PM2 |Bank0 SRAM Power Mode Select 2 (Write Protect) 673 * | | |This field can control SRAM bank0 selection 2 (8k) power mode for range 0x2000_2000 - 0x2000_3FFF. 674 * | | |00 = Normal mode. 675 * | | |01 = Retention mode. 676 * | | |10 = Power shut down mode. 677 * | | |11 = Reserved (Write Ignore). 678 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 679 * | | |Note 2: Write ignore when PCBUSY is 1. 680 * |[7:6] |SRAM0PM3 |Bank0 SRAM Power Mode Select 3 (Write Protect) 681 * | | |This field can control SRAM bank0 selection 3 (8k) power mode for range 0x2000_4000 - 0x2000_5FFF. 682 * | | |00 = Normal mode. 683 * | | |01 = Retention mode. 684 * | | |10 = Power shut down mode. 685 * | | |11 = Reserved (Write Ignore). 686 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 687 * | | |Note 2: Write ignore when PCBUSY is 1. 688 * |[9:8] |SRAM0PM4 |Bank0 SRAM Power Mode Select 4 (Write Protect) 689 * | | |This field can control SRAM0 bank0 selection 4 (8k) power mode for range 0x2000_6000 - 0x2000_7FFF. 690 * | | |00 = Normal mode. 691 * | | |01 = Retention mode. 692 * | | |10 = Power shut down mode. 693 * | | |11 = Reserved (Write Ignore). 694 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 695 * | | |Note 2: Write ignore when PCBUSY is 1. 696 * |[11:10] |SRAM1PM0 |Bank1 SRAM Power Mode Select 0 (Write Protect) 697 * | | |This field can control SRAM bank1 selection 0 (16k) power mode for range 0x2000_8000 - 0x2000_BFFF. 698 * | | |00 = Normal mode. 699 * | | |01 = Retention mode. 700 * | | |10 = Power shut down mode. 701 * | | |11 = Reserved (Write Ignore). 702 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 703 * | | |Note 2: Write ignore when PCBUSY is 1. 704 * |[13:12] |SRAM1PM1 |Bank1 SRAM Power Mode Select 1 (Write Protect) 705 * | | |This field can control SRAM bank1 selection 1 (16k) power mode for range 0x2000_C000 - 0x2000_FFFF. 706 * | | |00 = Normal mode. 707 * | | |01 = Retention mode. 708 * | | |10 = Power shut down mode. 709 * | | |11 = Reserved (Write Ignore). 710 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 711 * | | |Note 2: Write ignore when PCBUSY is 1. 712 * |[15:14] |SRAM1PM2 |Bank1 SRAM Power Mode Select 2 (Write Protect) 713 * | | |This field can control SRAM bank1 selection 2 (16k) power mode for range 0x2001_0000 - 0x2001_3FFF. 714 * | | |00 = Normal mode. 715 * | | |01 = Retention mode. 716 * | | |10 = Power shut down mode. 717 * | | |11 = Reserved (Write Ignore). 718 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 719 * | | |Note 2: Write ignore when PCBUSY is 1. 720 * |[17:16] |SRAM1PM3 |Bank1 SRAM Power Mode Select 3 (Write Protect) 721 * | | |This field can control SRAM bank1 selection 3 (16k) power mode for range 0x2001_4000 - 0x2001_7FFF. 722 * | | |00 = Normal mode. 723 * | | |01 = Retention mode. 724 * | | |10 = Power shut down mode. 725 * | | |11 = Reserved (Write Ignore). 726 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 727 * | | |Note 2: Write ignore when PCBUSY is 1. 728 * |[19:18] |SRAM1PM4 |Bank1 SRAM Power Mode Select 4 (Write Protect) 729 * | | |This field can control SRAM bank1 selection 4 (16k) power mode for range 0x2001_8000 - 0x2001_BFFF. 730 * | | |00 = Normal mode. 731 * | | |01 = Retention mode. 732 * | | |10 = Power shut down mode. 733 * | | |11 = Reserved (Write Ignore). 734 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 735 * | | |Note 2: Write ignore when PCBUSY is 1. 736 * |[21:20] |SRAM1PM5 |Bank1 SRAM Power Mode Select 5 (Write Protect) 737 * | | |This field can control SRAM bank1 selection 5 (16k) power mode for range 0x2001_C000 - 0x2001_FFFF. 738 * | | |00 = Normal mode. 739 * | | |01 = Retention mode. 740 * | | |10 = Power shut down mode. 741 * | | |11 = Reserved (Write Ignore). 742 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 743 * | | |Note 2: Write ignore when PCBUSY is 1. 744 * |[23:22] |SRAM1PM6 |Bank1 SRAM Power Mode Select 6 (Write Protect) 745 * | | |This field can control SRAM bank1 selection 6 (16k) power mode for range 0x2002_0000 - 0x2002_3FFF. 746 * | | |00 = Normal mode. 747 * | | |01 = Retention mode. 748 * | | |10 = Power shut down mode. 749 * | | |11 = Reserved (Write Ignore). 750 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 751 * | | |Note 2: Write ignore when PCBUSY is 1. 752 * |[25:24] |SRAM1PM7 |Bank1 SRAM Power Mode Select 7 (Write Protect) 753 * | | |This field can control SRAM bank1 selection 7 (16k) power mode for range 0x2002_4000 - 0x2002_7FFF. 754 * | | |00 = Normal mode. 755 * | | |01 = Retention mode. 756 * | | |10 = Power shut down mode. 757 * | | |11 = Reserved (Write Ignore). 758 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 759 * | | |Note 2: Write ignore when PCBUSY is 1. 760 * |[27:26] |SRAM2PM0 |Bank2 SRAM Power Mode Select 0 (Write Protect) 761 * | | |This field can control SRAM bank2 selection 0 (16k) power mode for range 0x2002_8000 - 0x2002_BFFF. 762 * | | |00 = Normal mode. 763 * | | |01 = Retention mode. 764 * | | |10 = Power shut down mode. 765 * | | |11 = Reserved (Write Ignore). 766 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 767 * | | |Note 2: Write ignore when PCBUSY is 1. 768 * |[29:28] |SRAM2PM1 |Bank2 SRAM Power Mode Select 1 (Write Protect) 769 * | | |This field can control SRAM bank2 selection 1 (16k) power mode for range 0x2002_C000 - 0x2002_FFFF. 770 * | | |00 = Normal mode. 771 * | | |01 = Retention mode. 772 * | | |10 = Power shut down mode. 773 * | | |11 = Reserved (Write Ignore). 774 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 775 * | | |Note 2: Write ignore when PCBUSY is 1. 776 * |[31] |PCBUSY |Power Changing Busy Flag (Read Only) 777 * | | |This bit indicate SRAM power changing. 778 * | | |0 = SRAM power change finish. 779 * | | |1 = SRAM power changing. 780 * @var SYS_T::SRAMPC1 781 * Offset: 0xE0 SRAM Power Mode Control Register 1 782 * --------------------------------------------------------------------------------------------------- 783 * |Bits |Field |Descriptions 784 * | :----: | :----: | :---- | 785 * |[1:0] |SRAM2PM2 |Bank2 SRAM Power Mode Select 2 (Write Protect) 786 * | | |This field can control SRAM bank2 selection 2 (16k) power mode for range 0x2003_0000 - 0x2003_3FFF. 787 * | | |00 = Normal mode. 788 * | | |01 = Retention mode. 789 * | | |10 = Power shut down mode. 790 * | | |11 = Reserved (Write Ignore). 791 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 792 * | | |Note 2: Write ignore when PCBUSY is 1. 793 * |[3:2] |SRAM2PM3 |Bank2 SRAM Power Mode Select 3 (Write Protect) 794 * | | |This field can control bank2 sram3 (16k) power mode for range 0x2003_4000 - 0x2003_7FFF. 795 * | | |00 = Normal mode. 796 * | | |01 = Retention mode. 797 * | | |10 = Power shut down mode. 798 * | | |11 = Reserved (Write Ignore). 799 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 800 * | | |Note 2: Write ignore when PCBUSY is 1. 801 * |[5:4] |SRAM2PM4 |Bank2 SRAM Power Mode Select 4 (Write Protect) 802 * | | |This field can control SRAM bank2 selection 4 (16k) power mode for range 0x2003_8000 - 0x2003_BFFF. 803 * | | |00 = Normal mode. 804 * | | |01 = Retention mode. 805 * | | |10 = Power shut down mode. 806 * | | |11 = Reserved (Write Ignore). 807 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 808 * | | |Note 2: Write ignore when PCBUSY is 1. 809 * |[7:6] |SRAM2PM5 |Bank2 SRAM Power Mode Select 5 (Write Protect) 810 * | | |This field can control SRAM bank2 selection 5 (16k) power mode for range 0x2003_C000 - 0x2003_FFFF. 811 * | | |00 = Normal mode. 812 * | | |01 = Retention mode. 813 * | | |10 = Power shut down mode. 814 * | | |11 = Reserved (Write Ignore). 815 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 816 * | | |Note 2: Write ignore when PCBUSY is 1. 817 * |[17:16] |CAN |CAN SRAM Power Mode Select (Write Protect) 818 * | | |This field can control CAN sram power mode. 819 * | | |00 = Normal mode. 820 * | | |01 = Retention mode. 821 * | | |10 = Power shut down mode. 822 * | | |11 = Reserved. 823 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 824 * | | |Note 2: Write ignore when PCBUSY is 1. 825 * |[19:18] |USBD |USB Device SRAM Power Mode Select (Write Protect) 826 * | | |This field can control USB device sram power mode. 827 * | | |00 = Normal mode. 828 * | | |01 = Retention mode. 829 * | | |10 = Power shut down mode. 830 * | | |11 = Reserved (Write Ignore). 831 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 832 * | | |Note 2: Write ignore when PCBUSY is 1. 833 * |[21:20] |PDMA0 |PDMA SRAM Power Mode Select (Write Protect) 834 * | | |This field can control PDMA0 (always secure) sram power mode. 835 * | | |00 = Normal mode. 836 * | | |01 = Retention mode. 837 * | | |10 = Power shut down mode. 838 * | | |11 = Reserved (Write Ignore). 839 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 840 * | | |Note 2: Write ignore when PCBUSY is 1. 841 * |[23:22] |PDMA1 |PDMA SRAM Power Mode Select (Write Protect) 842 * | | |This field can control PDMA1 sram power mode. 843 * | | |00 = Normal mode. 844 * | | |01 = Retention mode. 845 * | | |10 = Power shut down mode. 846 * | | |11 = Reserved (Write Ignore). 847 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 848 * | | |Note 2: Write ignore when PCBUSY is 1. 849 * |[25:24] |FMCCACHE |FMC Cache SRAM Power Mode Select (Write Protect) 850 * | | |This field can control FMC cache sram power mode. 851 * | | |00 = Normal mode. 852 * | | |01 = Retention mode. 853 * | | |10 = Power shut down mode. 854 * | | |11 = Reserved (Write Ignore). 855 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 856 * | | |Note 2: Write ignore when PCBUSY is 1. 857 * |[27:26] |RSA |RSA SRAM Power Mode Select (Write Protect) 858 * | | |This field can control RSA sram power mode. 859 * | | |00 = Normal mode. 860 * | | |01 = Retention mode. 861 * | | |10 = Power shut down mode. 862 * | | |11 = Reserved (Write Ignore). 863 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 864 * | | |Note 2: Write ignore when PCBUSY is 1. 865 * | | |Note 3: If CRPTPWREN of SYS_PSWCTL is set to 1, RSA SRAM is auto set to normal mode by hardware. 866 * |[29:28] |KS |Key Store SRAM Power Mode Select (Write Protect) 867 * | | |This field can control Key Store sram power mode. 868 * | | |00 = Normal mode. 869 * | | |01 = Retention mode. 870 * | | |10 = Power shut down mode. 871 * | | |11 = Reserved (Write Ignore). 872 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 873 * | | |Note 2: Write ignore when PCBUSY is 1. 874 * |[31] |PCBUSY |Power Changing Busy Flag (Read Only) 875 * | | |This bit indicate SRAM power changing. 876 * | | |0 = SRAM power change finish. 877 * | | |1 = SRAM power changing. 878 * @var SYS_T::TCTL48M 879 * Offset: 0xE4 HIRC 48M Trim Control Register 880 * --------------------------------------------------------------------------------------------------- 881 * |Bits |Field |Descriptions 882 * | :----: | :----: | :---- | 883 * |[1:0] |FREQSEL |Trim Frequency Selection 884 * | | |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC48) auto trim. 885 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 886 * | | |00 = Disable HIRC auto trim function. 887 * | | |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz. 888 * | | |10 = Reserved. 889 * | | |11 = Reserved. 890 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection 891 * | | |This field defines that trim value calculation is based on how many reference clocks. 892 * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 893 * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 894 * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 895 * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. 896 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 897 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count 898 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. 899 * | | |Once the HIRC locked, the internal trim value update counter will be reset. 900 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 901 * | | |00 = Trim retry count limitation is 64 loops. 902 * | | |01 = Trim retry count limitation is 128 loops. 903 * | | |10 = Trim retry count limitation is 256 loops. 904 * | | |11 = Trim retry count limitation is 512 loops. 905 * |[9] |BOUNDEN |Boundary Enable Bit 906 * | | |0 = Boundary function is disable. 907 * | | |1 = Boundary function is enable. 908 * |[8] |CESTOPEN |Clock Error Stop Enable Bit 909 * | | |0 = The trim operation is keep going if clock is inaccuracy. 910 * | | |1 = The trim operation is stopped if clock is inaccuracy. 911 * |[10] |REFCKSEL |Reference Clock Selection 912 * | | |0 = HIRC trim 48M reference clock is from external 32.768 kHz crystal oscillator. 913 * | | |1 = HIRC trim 48M reference clock is from internal USB synchronous mode. 914 * |[20:16] |BOUNDARY |Boundary Selection 915 * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. 916 * | | |Note: This field is effective only when the BOUNDEN(SYS_TCTL48M [9]) is enable. 917 * @var SYS_T::TIEN48M 918 * Offset: 0xE8 HIRC 48M Trim Interrupt Enable Register 919 * --------------------------------------------------------------------------------------------------- 920 * |Bits |Field |Descriptions 921 * | :----: | :----: | :---- | 922 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit 923 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL48M[1:0]). 924 * | | |If this bit is high and TFAILIF(SYS_TISTS48M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 925 * | | |0 = Disable TFAILIF(SYS_TISTS48M[1]) status to trigger an interrupt to CPU. 926 * | | |1 = Enable TFAILIF(SYS_TISTS48MM[1]) status to trigger an interrupt to CPU. 927 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit 928 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. 929 * | | |If this bit is set to1, and CLKERRIF(SYS_TISTS48M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 930 * | | |0 = Disable CLKERRIF(SYS_TISTS48M[2]) status to trigger an interrupt to CPU. 931 * | | |1 = Enable CLKERRIF(SYS_TISTS48M[2]) status to trigger an interrupt to CPU. 932 * @var SYS_T::TISTS48M 933 * Offset: 0xEC HIRC 48M Trim Interrupt Status Register 934 * --------------------------------------------------------------------------------------------------- 935 * |Bits |Field |Descriptions 936 * | :----: | :----: | :---- | 937 * |[0] |FREQLOCK |HIRC Frequency Lock Status 938 * | | |This bit indicates the HIRC frequency is locked. 939 * | | |This is a status bit and doesn't trigger any interrupt. 940 * | | |Write 1 to clear this to 0. 941 * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 942 * | | |0 = The internal high-speed oscillator frequency doesn't lock at 48 MHz yet. 943 * | | |1 = The internal high-speed oscillator frequency locked at 48 MHz. 944 * |[1] |TFAILIF |Trim Failure Interrupt Status 945 * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. 946 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL48M[1:0]) will be cleared to 00 by hardware automatically. 947 * | | |If this bit is set and TFAILIEN(SYS_TIEN48M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 948 * | | |Write 1 to clear this to 0. 949 * | | |0 = Trim value update limitation count does not reach. 950 * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. 951 * |[2] |CLKERRIF |Clock Error Interrupt Status 952 * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC48) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy 953 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TICTL48M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL48M[8]) is set to 1. 954 * | | |If this bit is set and CLKEIEN(SYS_TIEN48M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. 955 * | | |Write 1 to clear this to 0. 956 * | | |0 = Clock frequency is accuracy. 957 * | | |1 = Clock frequency is inaccuracy. 958 * |[3] |OVBDIF |Over Boundary Status 959 * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. 960 * | | |0 = Over boundary condition did not occur. 961 * | | |1 = Over boundary condition occurred. 962 * | | |Note: Write 1 to clear this flag. 963 * @var SYS_T::TCTL12M 964 * Offset: 0xF0 HIRC 12M Trim Control Register 965 * --------------------------------------------------------------------------------------------------- 966 * |Bits |Field |Descriptions 967 * | :----: | :----: | :---- | 968 * |[1:0] |FREQSEL |Trim Frequency Selection 969 * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. 970 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 971 * | | |00 = Disable HIRC auto trim function. 972 * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. 973 * | | |10 = Reserved. 974 * | | |11 = Reserved. 975 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection 976 * | | |This field defines that trim value calculation is based on how many reference clocks. 977 * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 978 * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 979 * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 980 * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. 981 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 982 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count 983 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. 984 * | | |Once the HIRC locked, the internal trim value update counter will be reset. 985 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 986 * | | |00 = Trim retry count limitation is 64 loops. 987 * | | |01 = Trim retry count limitation is 128 loops. 988 * | | |10 = Trim retry count limitation is 256 loops. 989 * | | |11 = Trim retry count limitation is 512 loops. 990 * |[9] |BOUNDEN |Boundary Enable Bit 991 * | | |0 = Boundary function is disable. 992 * | | |1 = Boundary function is enable. 993 * |[8] |CESTOPEN |Clock Error Stop Enable Bit 994 * | | |0 = The trim operation is keep going if clock is inaccuracy. 995 * | | |1 = The trim operation is stopped if clock is inaccuracy. 996 * |[10] |REFCKSEL |Reference Clock Selection 997 * | | |0 = HIRC trim reference clock is from external 32.768 kHz crystal oscillator. 998 * | | |1 = HIRC trim reference clock is from internal USB synchronous mode. 999 * |[20:16] |BOUNDARY |Boundary Selection 1000 * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. 1001 * | | |Note: This field is effective only when the BOUNDEN(SYS_TCTL12M[9]) is enabled. 1002 * @var SYS_T::TIEN12M 1003 * Offset: 0xF4 HIRC 12M Trim Interrupt Enable Register 1004 * --------------------------------------------------------------------------------------------------- 1005 * |Bits |Field |Descriptions 1006 * | :----: | :----: | :---- | 1007 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit 1008 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL12M[1:0]). 1009 * | | |If this bit is high and TFAILIF(SYS_TISTS12M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 1010 * | | |0 = Disable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU. 1011 * | | |1 = Enable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU. 1012 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit 1013 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. 1014 * | | |If this bit is set to1, and CLKERRIF(SYS_TISTS12M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 1015 * | | |0 = Disable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU. 1016 * | | |1 = Enable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU. 1017 * @var SYS_T::TISTS12M 1018 * Offset: 0xF8 HIRC 12M Trim Interrupt Status Register 1019 * --------------------------------------------------------------------------------------------------- 1020 * |Bits |Field |Descriptions 1021 * | :----: | :----: | :---- | 1022 * |[0] |FREQLOCK |HIRC Frequency Lock Status 1023 * | | |This bit indicates the HIRC frequency is locked. 1024 * | | |This is a status bit and doesn't trigger any interrupt. 1025 * | | |Write 1 to clear this to 0. 1026 * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 1027 * | | |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet. 1028 * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz. 1029 * |[1] |TFAILIF |Trim Failure Interrupt Status 1030 * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. 1031 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL12M[1:0]) will be cleared to 00 by hardware automatically. 1032 * | | |If this bit is set and TFAILIEN(SYS_TIEN12M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 1033 * | | |Write 1 to clear this to 0. 1034 * | | |0 = Trim value update limitation count does not reach. 1035 * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. 1036 * |[2] |CLKERRIF |Clock Error Interrupt Status 1037 * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy 1038 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TICTL12M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL12M[8]) is set to 1. 1039 * | | |If this bit is set and CLKEIEN(SYS_TIEN12M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. 1040 * | | |Write 1 to clear this to 0. 1041 * | | |0 = Clock frequency is accuracy. 1042 * | | |1 = Clock frequency is inaccuracy. 1043 * |[3] |OVBDIF |Over Boundary Status 1044 * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. 1045 * | | |0 = Over boundary condition did not occur. 1046 * | | |1 = Over boundary condition occurred. 1047 * | | |Note: Write 1 to clear this flag. 1048 * @var SYS_T::REGLCTL 1049 * Offset: 0x100 Register Lock Control Register 1050 * --------------------------------------------------------------------------------------------------- 1051 * |Bits |Field |Descriptions 1052 * | :----: | :----: | :---- | 1053 * |[7:0] |REGLCTL |Register Lock Control Code (Write Only) 1054 * | | |Some registers have write-protection function 1055 * | | |Writing these registers have to disable the protected function by writing the sequence value 59h, 16h, 88h to this field. 1056 * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. 1057 * |[0] |REGLCTL[0]|Register Lock Control Disable Index (Read Only) 1058 * | | |0 = Write-protection Enabled for writing protected registers. 1059 * | | |Any write to the protected register is ignored. 1060 * | | |1 = Write-protection Disabled for writing protected registers. 1061 * @var SYS_T::CPUCFG 1062 * Offset: 0x1D8 CPU General Configuration Register 1063 * --------------------------------------------------------------------------------------------------- 1064 * |Bits |Field |Descriptions 1065 * | :----: | :----: | :---- | 1066 * |[0] |INTRTEN |CPU Interrupt Realtime Enable Bit 1067 * | | |When this bit is 0, the latency of CPU entering interrupt service routine (ISR) will be various but shorter. 1068 * | | |When this bit is 1, the latency of CPU entering ISR will be kept constant. 1069 * | | |0 = CPU Interrupt Realtime Disabled. 1070 * | | |1 = CPU Interrupt Realtime Enabled. 1071 * @var SYS_T::PORCTL1 1072 * Offset: 0x1EC Power-on Reset Controller Register 1 1073 * --------------------------------------------------------------------------------------------------- 1074 * |Bits |Field |Descriptions 1075 * | :----: | :----: | :---- | 1076 * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect) 1077 * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. 1078 * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. 1079 * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: 1080 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. 1081 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1082 * @var SYS_T::PSWCTL 1083 * Offset: 0x1F4 Power Switch Control Register 1084 * --------------------------------------------------------------------------------------------------- 1085 * |Bits |Field |Descriptions 1086 * | :----: | :----: | :---- | 1087 * |[12] |CRPTPWREN |Cryptographic Accelerator Power Switch Enable Bit (Write Protect) 1088 * | | |0 = Cryptographic accelerator power supply Disabled. 1089 * | | |1 = Cryptographic accelerator power supply Enabled. 1090 * | | |Note 1: If this bit is set 1, RSA of SYS_SRAMPC1 is set to normal mode by hardware. 1091 * | | |Note 2: Write ignored when PCBUSY(SYS_SRAMPC1[31]) is 1. 1092 * | | |Note 3: This bit is write protected. Refer to the SYS_REGLCTL register. 1093 * @var SYS_T::PLCTL 1094 * Offset: 0x1F8 Power Level Control Register 1095 * --------------------------------------------------------------------------------------------------- 1096 * |Bits |Field |Descriptions 1097 * | :----: | :----: | :---- | 1098 * |[1:0] |PLSEL |Power Level Select (Write Protect) 1099 * | | |00 = Set to Power level 0 (PL0). Support system clock up to 96MHz. 1100 * | | |01 = Set to Power level 1 (PL1). Support system clock up to 84MHz. 1101 * | | |10 = Set to Power level 2 (PL2). Support system clock up to 64MHz. 1102 * | | |11 = Set to Power level 3 (PL3). Support system clock up to 4MHz. 1103 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 1104 * | | |Note 2: These bits not be reset when wake-up from Standby Power-down mode(SPD). 1105 * |[4] |MVRS |Main Voltage Regulator Type Select (Write Protect) 1106 * | | |This bit filed sets main voltage regulator type. 1107 * | | |After setting main voltage regulator type to DCDC (MVRS (SYS_PLCTL[4]) = 1) system will set main voltage regulator type change busy flag MVRCBUSY(SYS_PLSTS[1]), detect inductor connection and update inductor connection status LCONS (SYS_PLSTS[3]). 1108 * | | |If inductor exist LCONS will be cleared and main voltage regulator type can switch to DCDC (CURMVRS (SYS_PLSTS[12])=1). 1109 * | | |0 = Set main voltage regulator to LDO. 1110 * | | |1 = Set main voltage regulator to DCDC. 1111 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 1112 * | | |Note 2: This bit not be reset when wake-up from Standby Power-down mode(SPD). 1113 * |[7] |WRBUSY |Write Busy Flag 1114 * | | |If SYS_PLCTL be written, this bit be asserted automatic by hardware, and be de-asserted when write procedure finish. 1115 * | | |0 = SYS_PLCTL register is ready for write operation. 1116 * | | |1 = SYS_PLCTL register is busy on the last write operation. Other write operations are ignored. 1117 * |[21:16] |LVSSTEP |LDO Voltage Scaling Step (Write Protect) 1118 * | | |The LVSSTEP value is LDO voltage rising step. 1119 * | | |LDO voltage scaling step = (LVSSTEP + 1) * 10mV. 1120 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1121 * |[31:24] |LVSPRD |LDO Voltage Scaling Period (Write Protect) 1122 * | | |The LVSPRD value is the period of each LDO voltage rising step. 1123 * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us. 1124 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1125 * @var SYS_T::PLSTS 1126 * Offset: 0x1FC Power Level Status Register 1127 * --------------------------------------------------------------------------------------------------- 1128 * |Bits |Field |Descriptions 1129 * | :----: | :----: | :---- | 1130 * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) 1131 * | | |This bit is set by hardware when power level is changing. 1132 * | | |After power level change is completed, this bit will be cleared automatically by hardware. 1133 * | | |0 = Power level change is completed. 1134 * | | |1 = Power level change is ongoing. 1135 * |[1] |MVRCBUSY |Main Voltage Regulator Type Change Busy Bit (Read Only) 1136 * | | |This bit is set by hardware when main voltage regulator type is changing. 1137 * | | |After main voltage regulator type change is completed, this bit will be cleared automatically by hardware. 1138 * | | |0 = Main voltage regulator type change is completed. 1139 * | | |1 = Main voltage regulator type change is ongoing. 1140 * |[2] |MVRCERR |Main Voltage Regulator Type Change Error Bit (Write Protect) 1141 * | | |This bit is set to 1 when main voltage regulator type change from LDO to DCDC error, the following conditions will cause change errors: 1142 * | | |1.System change to DC-DC mode but LDO change voltage process not finish. 1143 * | | |2.Detect inductor fail. 1144 * | | |Read: 1145 * | | |0 = No main voltage regulator type change error. 1146 * | | |1 = Main voltage regulator type change to DCDC error occurred. 1147 * | | |Write: 1148 * | | |0 = No effect. 1149 * | | |1 = Clears MVRCERR to 0. 1150 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1151 * |[3] |LCONS |Inductor for DC-DC Connect Status (Read Only) 1152 * | | |0 = Inductor connect between Vsw and LDO_CAP pin. 1153 * | | |This bit is valid when current main voltage regulator type is DCDC (CURMVRS (SYS_PLSTS[12])=1). 1154 * | | |If current main voltage regulator type is LDO (CURMVRS (SYS_PLSTS[12])=0), this bit is set to 1. 1155 * | | |0 = Inductor connect between Vsw and LDO_CAP pin. 1156 * | | |1 = No Inductor connect between Vsw and LDO_CAP pin. 1157 * | | |Note: This bit is 1 when main voltage regulator is LDO. 1158 * |[9:8] |PLSTATUS |Power Level Status (Read Only) 1159 * | | |This bit field reflect the current power level. 1160 * | | |00 = Power level is PL0. Support system clock up to 96MHz. 1161 * | | |01 = Power level is PL1. Support system clock up to 84MHz. 1162 * | | |10 = Power level is PL2. Support system clock up to 48MHz. 1163 * | | |11 = Power level is PL3. Support system clock up to 4MHz. 1164 * |[12] |CURMVR |Current Main Voltage Regulator Type (Read Only) 1165 * | | |This bit field reflects current main voltage regulator type. 1166 * | | |0 = Current main voltage regulator in active and Idle mode is LDO. 1167 * | | |1 = Current main voltage regulator in active and Idle mode is DCDC. 1168 * @var SYS_T::AHBMCTL 1169 * Offset: 0x400 AHB Bus Matrix Priority Control Register 1170 * --------------------------------------------------------------------------------------------------- 1171 * |Bits |Field |Descriptions 1172 * | :----: | :----: | :---- | 1173 * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex-M23 Core Enable Bit (Write Protect) 1174 * | | |Enable Cortex-M23 core with highest AHB bus priority in AHB bus matrix. 1175 * | | |0 = Run robin mode. 1176 * | | |1 = Cortex-M23 CPU with highest bus priority when interrupt occurs. 1177 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1178 */ 1179 1180 __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ 1181 __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ 1182 __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ 1183 __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ 1184 __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ 1185 __I uint32_t RESERVE0[1]; 1186 __IO uint32_t BODCTL; /*!< [0x0018] Brown-out Detector Control Register */ 1187 __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ 1188 __I uint32_t RESERVE1[1]; 1189 __IO uint32_t PORCTL0; /*!< [0x0024] Power-on Reset Controller Register 0 */ 1190 __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ 1191 __IO uint32_t USBPHY; /*!< [0x002C] USB PHY Control Register */ 1192 __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */ 1193 __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */ 1194 __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */ 1195 __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */ 1196 __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */ 1197 __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */ 1198 __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */ 1199 __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */ 1200 __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */ 1201 __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */ 1202 __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */ 1203 __IO uint32_t GPF_MFPH; /*!< [0x005C] GPIOF High Byte Multiple Function Control Register */ 1204 __IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */ 1205 __IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */ 1206 __IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */ 1207 __IO uint32_t GPH_MFPH; /*!< [0x006C] GPIOH High Byte Multiple Function Control Register */ 1208 __I uint32_t RESERVE2[4]; 1209 __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ 1210 __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ 1211 __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ 1212 __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ 1213 __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ 1214 __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ 1215 __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */ 1216 __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */ 1217 __IO uint32_t VTORSET; /*!< [0x00A0] VTOR Setting Register */ 1218 __I uint32_t RESERVE3[7]; 1219 __IO uint32_t SRAMICTL; /*!< [0x00C0] System SRAM Interrupt Enable Control Register */ 1220 __I uint32_t SRAMSTS; /*!< [0x00C4] System SRAM Parity Error Status Register */ 1221 __I uint32_t SRAMEADR; /*!< [0x00C8] System SRAM Parity Check Error Address Register */ 1222 __IO uint32_t RESERVE4[4]; 1223 __IO uint32_t SRAMPC0; /*!< [0x00DC] SRAM Power Mode Control Register 0 */ 1224 __IO uint32_t SRAMPC1; /*!< [0x00E0] SRAM Power Mode Control Register 1 */ 1225 __IO uint32_t TCTL48M; /*!< [0x00E4] HIRC 48M Trim Control Register */ 1226 __IO uint32_t TIEN48M; /*!< [0x00E8] HIRC 48M Trim Interrupt Enable Register */ 1227 __IO uint32_t TISTS48M; /*!< [0x00EC] HIRC 48M Trim Interrupt Status Register */ 1228 __IO uint32_t TCTL12M; /*!< [0x00F0] HIRC 12M Trim Control Register */ 1229 __IO uint32_t TIEN12M; /*!< [0x00F4] HIRC 12M Trim Interrupt Enable Register */ 1230 __IO uint32_t TISTS12M; /*!< [0x00F8] HIRC 12M Trim Interrupt Status Register */ 1231 __I uint32_t RESERVE6[1]; 1232 __IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ 1233 __I uint32_t RESERVE7[53]; 1234 __IO uint32_t CPUCFG; /*!< [0x01D8] CPU General Configuration Register */ 1235 __IO uint32_t BATLDCTL; /*!< [0x01DC] Battery Loss Detector Control Register */ 1236 __IO uint32_t OVDCTL; /*!< [0x01E0] Over Voltage Detector Control Register */ 1237 __I uint32_t RESERVE8[2]; 1238 __IO uint32_t PORCTL1; /*!< [0x01EC] Power-on Reset Controller Register 1 */ 1239 __I uint32_t RESERVE9[1]; 1240 __IO uint32_t PSWCTL; /*!< [0x01F4] Power Switch Control Register */ 1241 __IO uint32_t PLCTL; /*!< [0x01F8] Power Level Control Register */ 1242 __IO uint32_t PLSTS; /*!< [0x01FC] Power Level Status Register */ 1243 __I uint32_t RESERVE10[128]; 1244 __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */ 1245 1246 1247 } SYS_T; 1248 1249 /** 1250 @addtogroup SYS_CONST SYS Bit Field Definition 1251 Constant Definitions for SYS Controller 1252 @{ 1253 */ 1254 1255 #define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ 1256 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ 1257 1258 #define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ 1259 #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ 1260 1261 #define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ 1262 #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ 1263 1264 #define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ 1265 #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ 1266 1267 #define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ 1268 #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ 1269 1270 #define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ 1271 #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ 1272 1273 #define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */ 1274 #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */ 1275 1276 #define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ 1277 #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ 1278 1279 #define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ 1280 #define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ 1281 1282 #define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ 1283 #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ 1284 1285 #define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ 1286 #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ 1287 1288 #define SYS_IPRST0_PDMA0RST_Pos (2) /*!< SYS_T::IPRST0: PDMA0RST Position */ 1289 #define SYS_IPRST0_PDMA0RST_Msk (0x1ul << SYS_IPRST0_PDMA0RST_Pos) /*!< SYS_T::IPRST0: PDMA0RST Mask */ 1290 1291 #define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ 1292 #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ 1293 1294 #define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS_T::IPRST0: USBHRST Position */ 1295 #define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */ 1296 1297 #define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */ 1298 #define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */ 1299 1300 #define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ 1301 #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ 1302 1303 #define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */ 1304 #define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */ 1305 1306 #define SYS_IPRST0_KSRST_Pos (13) /*!< SYS_T::IPRST0: KSRST Position */ 1307 #define SYS_IPRST0_KSRST_Msk (0x1ul << SYS_IPRST0_KSRST_Pos) /*!< SYS_T::IPRST0: KSRST Mask */ 1308 1309 #define SYS_IPRST0_PDMA1RST_Pos (29) /*!< SYS_T::IPRST0: PDMA1RST Position */ 1310 #define SYS_IPRST0_PDMA1RST_Msk (0x1ul << SYS_IPRST0_PDMA1RST_Pos) /*!< SYS_T::IPRST0: PDMA1RST Mask */ 1311 1312 #define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ 1313 #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ 1314 1315 #define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ 1316 #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ 1317 1318 #define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ 1319 #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ 1320 1321 #define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ 1322 #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ 1323 1324 #define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ 1325 #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ 1326 1327 #define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ 1328 #define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ 1329 1330 #define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ 1331 #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ 1332 1333 #define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ 1334 #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ 1335 1336 #define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ 1337 #define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ 1338 1339 #define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ 1340 #define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ 1341 1342 #define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ 1343 #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ 1344 1345 #define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ 1346 #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ 1347 1348 #define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ 1349 #define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ 1350 1351 #define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ 1352 #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ 1353 1354 #define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ 1355 #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ 1356 1357 #define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ 1358 #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ 1359 1360 #define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ 1361 #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ 1362 1363 #define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ 1364 #define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ 1365 1366 #define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ 1367 #define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ 1368 1369 #define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */ 1370 #define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */ 1371 1372 #define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */ 1373 #define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */ 1374 1375 #define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ 1376 #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ 1377 1378 #define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */ 1379 #define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */ 1380 1381 #define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */ 1382 #define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */ 1383 1384 #define SYS_IPRST1_LCDRST_Pos (30) /*!< SYS_T::IPRST1: LCDRST Position */ 1385 #define SYS_IPRST1_LCDRST_Msk (0x1ul << SYS_IPRST1_LCDRST_Pos) /*!< SYS_T::IPRST1: LCDRST Mask */ 1386 1387 #define SYS_IPRST1_TRNGRST_Pos (31) /*!< SYS_T::IPRST1: TRNGRST Position */ 1388 #define SYS_IPRST1_TRNGRST_Msk (0x1ul << SYS_IPRST1_TRNGRST_Pos) /*!< SYS_T::IPRST1: TRNGRST Mask */ 1389 1390 #define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ 1391 #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ 1392 1393 #define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */ 1394 #define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */ 1395 1396 #define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */ 1397 #define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */ 1398 1399 #define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ 1400 #define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ 1401 1402 #define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ 1403 #define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ 1404 1405 #define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */ 1406 #define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */ 1407 1408 #define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ 1409 #define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ 1410 1411 #define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ 1412 #define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ 1413 1414 #define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ 1415 #define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ 1416 1417 #define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */ 1418 #define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */ 1419 1420 #define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */ 1421 #define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */ 1422 1423 #define SYS_IPRST2_TMR4RST_Pos (20) /*!< SYS_T::IPRST2: TMR4RST Position */ 1424 #define SYS_IPRST2_TMR4RST_Msk (0x1ul << SYS_IPRST2_TMR4RST_Pos) /*!< SYS_T::IPRST2: TMR4RST Mask */ 1425 1426 #define SYS_IPRST2_TMR5RST_Pos (21) /*!< SYS_T::IPRST2: TMR5RST Position */ 1427 #define SYS_IPRST2_TMR5RST_Msk (0x1ul << SYS_IPRST2_TMR5RST_Pos) /*!< SYS_T::IPRST2: TMR5RST Mask */ 1428 1429 #define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */ 1430 #define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */ 1431 1432 #define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */ 1433 #define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */ 1434 1435 #define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ 1436 #define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ 1437 1438 #define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ 1439 #define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ 1440 1441 #define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ 1442 #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ 1443 1444 #define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ 1445 #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ 1446 1447 #define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ 1448 #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ 1449 1450 #define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ 1451 #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ 1452 1453 #define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ 1454 #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ 1455 1456 #define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ 1457 #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ 1458 1459 #define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ 1460 #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ 1461 1462 #define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ 1463 #define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ 1464 1465 #define SYS_BODCTL_STB_Pos (23) /*!< SYS_T::BODCTL: STB Position */ 1466 #define SYS_BODCTL_STB_Msk (0x1ul << SYS_BODCTL_STB_Pos) /*!< SYS_T::BODCTL: STB Mask */ 1467 1468 #define SYS_BODCTL_WRBUSY_Pos (31) /*!< SYS_T::BODCTL: WRBUSY Position */ 1469 #define SYS_BODCTL_WRBUSY_Msk (0x1ul << SYS_BODCTL_WRBUSY_Pos) /*!< SYS_T::BODCTL: WRBUSY Mask */ 1470 1471 #define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ 1472 #define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ 1473 1474 #define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ 1475 #define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ 1476 1477 #define SYS_PORCTL0_PORMASK_Pos (0) /*!< SYS_T::PORCTL0: PORMASK Position */ 1478 #define SYS_PORCTL0_PORMASK_Msk (0xfffful << SYS_PORCTL0_PORMASK_Pos) /*!< SYS_T::PORCTL0: PORMASK Mask */ 1479 1480 #define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */ 1481 #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */ 1482 1483 #define SYS_VREFCTL_IBIASSEL_Pos (5) /*!< SYS_T::VREFCTL: IBIASSEL Position */ 1484 #define SYS_VREFCTL_IBIASSEL_Msk (0x1ul << SYS_VREFCTL_IBIASSEL_Pos) /*!< SYS_T::VREFCTL: IBIASSEL Mask */ 1485 1486 #define SYS_VREFCTL_PRELOADSEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOADSEL Position */ 1487 #define SYS_VREFCTL_PRELOADSEL_Msk (0x3ul << SYS_VREFCTL_PRELOADSEL_Pos) /*!< SYS_T::VREFCTL: PRELOADSEL Mask */ 1488 1489 #define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */ 1490 #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */ 1491 1492 #define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */ 1493 #define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */ 1494 1495 #define SYS_USBPHY_OTGPHYEN_Pos (8) /*!< SYS_T::USBPHY: OTGPHYEN Position */ 1496 #define SYS_USBPHY_OTGPHYEN_Msk (0x1ul << SYS_USBPHY_OTGPHYEN_Pos) /*!< SYS_T::USBPHY: OTGPHYEN Mask */ 1497 1498 #define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */ 1499 #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */ 1500 1501 #define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */ 1502 #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */ 1503 1504 #define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */ 1505 #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */ 1506 1507 #define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */ 1508 #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */ 1509 1510 #define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */ 1511 #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */ 1512 1513 #define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */ 1514 #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */ 1515 1516 #define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */ 1517 #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */ 1518 1519 #define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */ 1520 #define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */ 1521 1522 #define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */ 1523 #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */ 1524 1525 #define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */ 1526 #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */ 1527 1528 #define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */ 1529 #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */ 1530 1531 #define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */ 1532 #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */ 1533 1534 #define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */ 1535 #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */ 1536 1537 #define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */ 1538 #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */ 1539 1540 #define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */ 1541 #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */ 1542 1543 #define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */ 1544 #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */ 1545 1546 #define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */ 1547 #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */ 1548 1549 #define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */ 1550 #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */ 1551 1552 #define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */ 1553 #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */ 1554 1555 #define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */ 1556 #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */ 1557 1558 #define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */ 1559 #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */ 1560 1561 #define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */ 1562 #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */ 1563 1564 #define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */ 1565 #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */ 1566 1567 #define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */ 1568 #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */ 1569 1570 #define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */ 1571 #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */ 1572 1573 #define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */ 1574 #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */ 1575 1576 #define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */ 1577 #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */ 1578 1579 #define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */ 1580 #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */ 1581 1582 #define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */ 1583 #define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */ 1584 1585 #define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */ 1586 #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */ 1587 1588 #define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */ 1589 #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */ 1590 1591 #define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */ 1592 #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */ 1593 1594 #define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */ 1595 #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */ 1596 1597 #define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */ 1598 #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */ 1599 1600 #define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */ 1601 #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */ 1602 1603 #define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */ 1604 #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */ 1605 1606 #define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */ 1607 #define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */ 1608 1609 #define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */ 1610 #define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */ 1611 1612 #define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */ 1613 #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */ 1614 1615 #define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */ 1616 #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */ 1617 1618 #define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */ 1619 #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */ 1620 1621 #define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */ 1622 #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */ 1623 1624 #define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */ 1625 #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */ 1626 1627 #define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */ 1628 #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */ 1629 1630 #define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */ 1631 #define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */ 1632 1633 #define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */ 1634 #define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */ 1635 1636 #define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */ 1637 #define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */ 1638 1639 #define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */ 1640 #define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */ 1641 1642 #define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */ 1643 #define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */ 1644 1645 #define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */ 1646 #define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */ 1647 1648 #define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */ 1649 #define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */ 1650 1651 #define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */ 1652 #define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */ 1653 1654 #define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */ 1655 #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */ 1656 1657 #define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */ 1658 #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */ 1659 1660 #define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */ 1661 #define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */ 1662 1663 #define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */ 1664 #define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */ 1665 1666 #define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */ 1667 #define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */ 1668 1669 #define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */ 1670 #define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */ 1671 1672 #define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */ 1673 #define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */ 1674 1675 #define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */ 1676 #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */ 1677 1678 #define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */ 1679 #define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */ 1680 1681 #define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */ 1682 #define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */ 1683 1684 #define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */ 1685 #define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */ 1686 1687 #define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */ 1688 #define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */ 1689 1690 #define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */ 1691 #define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */ 1692 1693 #define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */ 1694 #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */ 1695 1696 #define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */ 1697 #define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */ 1698 1699 #define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */ 1700 #define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */ 1701 1702 #define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */ 1703 #define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */ 1704 1705 #define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */ 1706 #define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */ 1707 1708 #define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */ 1709 #define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */ 1710 1711 #define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */ 1712 #define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */ 1713 1714 #define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */ 1715 #define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */ 1716 1717 #define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */ 1718 #define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */ 1719 1720 #define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */ 1721 #define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */ 1722 1723 #define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */ 1724 #define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */ 1725 1726 #define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */ 1727 #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */ 1728 1729 #define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */ 1730 #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */ 1731 1732 #define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */ 1733 #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */ 1734 1735 #define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */ 1736 #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */ 1737 1738 #define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */ 1739 #define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */ 1740 1741 #define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */ 1742 #define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */ 1743 1744 #define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */ 1745 #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */ 1746 1747 #define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */ 1748 #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */ 1749 1750 #define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */ 1751 #define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */ 1752 1753 #define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */ 1754 #define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */ 1755 1756 #define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */ 1757 #define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */ 1758 1759 #define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */ 1760 #define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */ 1761 1762 #define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */ 1763 #define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */ 1764 1765 #define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */ 1766 #define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */ 1767 1768 #define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */ 1769 #define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */ 1770 1771 #define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */ 1772 #define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */ 1773 1774 #define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */ 1775 #define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */ 1776 1777 #define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */ 1778 #define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */ 1779 1780 #define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */ 1781 #define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */ 1782 1783 #define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */ 1784 #define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */ 1785 1786 #define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */ 1787 #define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */ 1788 1789 #define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */ 1790 #define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */ 1791 1792 #define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */ 1793 #define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */ 1794 1795 #define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */ 1796 #define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */ 1797 1798 #define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */ 1799 #define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */ 1800 1801 #define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */ 1802 #define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */ 1803 1804 #define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */ 1805 #define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */ 1806 1807 #define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */ 1808 #define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */ 1809 1810 #define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */ 1811 #define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */ 1812 1813 #define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */ 1814 #define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */ 1815 1816 #define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ 1817 #define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ 1818 1819 #define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ 1820 #define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ 1821 1822 #define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ 1823 #define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ 1824 1825 #define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ 1826 #define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ 1827 1828 #define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ 1829 #define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ 1830 1831 #define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ 1832 #define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ 1833 1834 #define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ 1835 #define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ 1836 1837 #define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ 1838 #define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ 1839 1840 #define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ 1841 #define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ 1842 1843 #define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ 1844 #define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ 1845 1846 #define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ 1847 #define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ 1848 1849 #define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ 1850 #define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ 1851 1852 #define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ 1853 #define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ 1854 1855 #define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ 1856 #define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ 1857 1858 #define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ 1859 #define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ 1860 1861 #define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ 1862 #define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ 1863 1864 #define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ 1865 #define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ 1866 1867 #define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ 1868 #define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ 1869 1870 #define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ 1871 #define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ 1872 1873 #define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ 1874 #define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ 1875 1876 #define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ 1877 #define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ 1878 1879 #define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ 1880 #define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ 1881 1882 #define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ 1883 #define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ 1884 1885 #define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ 1886 #define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ 1887 1888 #define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ 1889 #define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ 1890 1891 #define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ 1892 #define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ 1893 1894 #define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ 1895 #define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ 1896 1897 #define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ 1898 #define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ 1899 1900 #define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ 1901 #define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ 1902 1903 #define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ 1904 #define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ 1905 1906 #define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ 1907 #define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ 1908 1909 #define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ 1910 #define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ 1911 1912 #define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ 1913 #define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ 1914 1915 #define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ 1916 #define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ 1917 1918 #define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ 1919 #define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ 1920 1921 #define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ 1922 #define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ 1923 1924 #define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ 1925 #define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ 1926 1927 #define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ 1928 #define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ 1929 1930 #define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ 1931 #define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ 1932 1933 #define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ 1934 #define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ 1935 1936 #define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ 1937 #define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ 1938 1939 #define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ 1940 #define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ 1941 1942 #define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ 1943 #define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ 1944 1945 #define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ 1946 #define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ 1947 1948 #define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ 1949 #define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ 1950 1951 #define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ 1952 #define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ 1953 1954 #define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ 1955 #define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ 1956 1957 #define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ 1958 #define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ 1959 1960 #define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ 1961 #define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ 1962 1963 #define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ 1964 #define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ 1965 1966 #define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ 1967 #define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ 1968 1969 #define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ 1970 #define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ 1971 1972 #define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ 1973 #define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ 1974 1975 #define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ 1976 #define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ 1977 1978 #define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ 1979 #define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ 1980 1981 #define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ 1982 #define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ 1983 1984 #define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ 1985 #define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ 1986 1987 #define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ 1988 #define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ 1989 1990 #define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ 1991 #define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ 1992 1993 #define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ 1994 #define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ 1995 1996 #define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ 1997 #define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ 1998 1999 #define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ 2000 #define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ 2001 2002 #define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ 2003 #define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ 2004 2005 #define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ 2006 #define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ 2007 2008 #define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ 2009 #define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ 2010 2011 #define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ 2012 #define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ 2013 2014 #define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ 2015 #define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ 2016 2017 #define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ 2018 #define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ 2019 2020 #define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ 2021 #define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ 2022 2023 #define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ 2024 #define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ 2025 2026 #define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ 2027 #define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ 2028 2029 #define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ 2030 #define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ 2031 2032 #define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ 2033 #define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ 2034 2035 #define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ 2036 #define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ 2037 2038 #define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ 2039 #define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ 2040 2041 #define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ 2042 #define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ 2043 2044 #define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ 2045 #define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ 2046 2047 #define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ 2048 #define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ 2049 2050 #define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ 2051 #define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ 2052 2053 #define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ 2054 #define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ 2055 2056 #define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ 2057 #define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ 2058 2059 #define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ 2060 #define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ 2061 2062 #define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ 2063 #define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ 2064 2065 #define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ 2066 #define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ 2067 2068 #define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ 2069 #define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ 2070 2071 #define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ 2072 #define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ 2073 2074 #define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ 2075 #define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ 2076 2077 #define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ 2078 #define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ 2079 2080 #define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */ 2081 #define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */ 2082 2083 #define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */ 2084 #define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */ 2085 2086 #define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */ 2087 #define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */ 2088 2089 #define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */ 2090 #define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */ 2091 2092 #define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */ 2093 #define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */ 2094 2095 #define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */ 2096 #define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */ 2097 2098 #define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */ 2099 #define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */ 2100 2101 #define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */ 2102 #define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */ 2103 2104 #define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */ 2105 #define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */ 2106 2107 #define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */ 2108 #define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */ 2109 2110 #define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */ 2111 #define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */ 2112 2113 #define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */ 2114 #define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */ 2115 2116 #define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */ 2117 #define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */ 2118 2119 #define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */ 2120 #define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */ 2121 2122 #define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */ 2123 #define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */ 2124 2125 #define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */ 2126 #define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */ 2127 2128 #define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */ 2129 #define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */ 2130 2131 #define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */ 2132 #define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */ 2133 2134 #define SYS_VTORSET_VTORSET_Pos (11) /*!< SYS_T::VTORSET: VTORSET Position */ 2135 #define SYS_VTORSET_VTORSET_Msk (0x3fffful << SYS_VTORSET_VTORSET_Pos) /*!< SYS_T::VTORSET: VTORSET Mask */ 2136 2137 #define SYS_SRAMICTL_PERRIEN_Pos (0) /*!< SYS_T::SRAMICTL: PERRIEN Position */ 2138 #define SYS_SRAMICTL_PERRIEN_Msk (0x1ul << SYS_SRAMICTL_PERRIEN_Pos) /*!< SYS_T::SRAMICTL: PERRIEN Mask */ 2139 2140 #define SYS_SRAMSTS_PERRIF_Pos (0) /*!< SYS_T::SRAMSTS: PERRIF Position */ 2141 #define SYS_SRAMSTS_PERRIF_Msk (0x1ul << SYS_SRAMSTS_PERRIF_Pos) /*!< SYS_T::SRAMSTS: PERRIF Mask */ 2142 2143 #define SYS_SRAMEADR_ERRADDR_Pos (0) /*!< SYS_T::SRAMEADR: ERRADDR Position */ 2144 #define SYS_SRAMEADR_ERRADDR_Msk (0xfffffffful << SYS_SRAMEADR_ERRADDR_Pos) /*!< SYS_T::SRAMEADR: ERRADDR Mask */ 2145 2146 #define SYS_SRAMPC0_SRAM0PM0_Pos (0) /*!< SYS_T::SRAMPC0: SRAM0PM0 Position */ 2147 #define SYS_SRAMPC0_SRAM0PM0_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM0_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM0 Mask */ 2148 2149 #define SYS_SRAMPC0_SRAM0PM1_Pos (2) /*!< SYS_T::SRAMPC0: SRAM0PM1 Position */ 2150 #define SYS_SRAMPC0_SRAM0PM1_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM1_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM1 Mask */ 2151 2152 #define SYS_SRAMPC0_SRAM0PM2_Pos (4) /*!< SYS_T::SRAMPC0: SRAM0PM2 Position */ 2153 #define SYS_SRAMPC0_SRAM0PM2_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM2_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM2 Mask */ 2154 2155 #define SYS_SRAMPC0_SRAM0PM3_Pos (6) /*!< SYS_T::SRAMPC0: SRAM0PM3 Position */ 2156 #define SYS_SRAMPC0_SRAM0PM3_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM3_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM3 Mask */ 2157 2158 #define SYS_SRAMPC0_SRAM0PM4_Pos (8) /*!< SYS_T::SRAMPC0: SRAM0PM4 Position */ 2159 #define SYS_SRAMPC0_SRAM0PM4_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM4_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM4 Mask */ 2160 2161 #define SYS_SRAMPC0_SRAM1PM0_Pos (10) /*!< SYS_T::SRAMPC0: SRAM1PM0 Position */ 2162 #define SYS_SRAMPC0_SRAM1PM0_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM0_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM0 Mask */ 2163 2164 #define SYS_SRAMPC0_SRAM1PM1_Pos (12) /*!< SYS_T::SRAMPC0: SRAM1PM1 Position */ 2165 #define SYS_SRAMPC0_SRAM1PM1_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM1_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM1 Mask */ 2166 2167 #define SYS_SRAMPC0_SRAM1PM2_Pos (14) /*!< SYS_T::SRAMPC0: SRAM1PM2 Position */ 2168 #define SYS_SRAMPC0_SRAM1PM2_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM2_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM2 Mask */ 2169 2170 #define SYS_SRAMPC0_SRAM1PM3_Pos (16) /*!< SYS_T::SRAMPC0: SRAM1PM3 Position */ 2171 #define SYS_SRAMPC0_SRAM1PM3_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM3_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM3 Mask */ 2172 2173 #define SYS_SRAMPC0_SRAM1PM4_Pos (18) /*!< SYS_T::SRAMPC0: SRAM1PM4 Position */ 2174 #define SYS_SRAMPC0_SRAM1PM4_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM4_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM4 Mask */ 2175 2176 #define SYS_SRAMPC0_SRAM1PM5_Pos (20) /*!< SYS_T::SRAMPC0: SRAM1PM5 Position */ 2177 #define SYS_SRAMPC0_SRAM1PM5_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM5_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM5 Mask */ 2178 2179 #define SYS_SRAMPC0_SRAM1PM6_Pos (22) /*!< SYS_T::SRAMPC0: SRAM1PM6 Position */ 2180 #define SYS_SRAMPC0_SRAM1PM6_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM6_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM6 Mask */ 2181 2182 #define SYS_SRAMPC0_SRAM1PM7_Pos (24) /*!< SYS_T::SRAMPC0: SRAM1PM7 Position */ 2183 #define SYS_SRAMPC0_SRAM1PM7_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM7_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM7 Mask */ 2184 2185 #define SYS_SRAMPC0_SRAM2PM0_Pos (26) /*!< SYS_T::SRAMPC0: SRAM2PM0 Position */ 2186 #define SYS_SRAMPC0_SRAM2PM0_Msk (0x3ul << SYS_SRAMPC0_SRAM2PM0_Pos) /*!< SYS_T::SRAMPC0: SRAM2PM0 Mask */ 2187 2188 #define SYS_SRAMPC0_SRAM2PM1_Pos (28) /*!< SYS_T::SRAMPC0: SRAM2PM1 Position */ 2189 #define SYS_SRAMPC0_SRAM2PM1_Msk (0x3ul << SYS_SRAMPC0_SRAM2PM1_Pos) /*!< SYS_T::SRAMPC0: SRAM2PM1 Mask */ 2190 2191 #define SYS_SRAMPC0_PCBUSY_Pos (31) /*!< SYS_T::SRAMPC0: PCBUSY Position */ 2192 #define SYS_SRAMPC0_PCBUSY_Msk (0x1ul << SYS_SRAMPC0_PCBUSY_Pos) /*!< SYS_T::SRAMPC0: PCBUSY Mask */ 2193 2194 #define SYS_SRAMPC1_SRAM2PM2_Pos (0) /*!< SYS_T::SRAMPC1: SRAM2PM2 Position */ 2195 #define SYS_SRAMPC1_SRAM2PM2_Msk (0x3ul << SYS_SRAMPC1_SRAM2PM2_Pos) /*!< SYS_T::SRAMPC1: SRAM2PM2 Mask */ 2196 2197 #define SYS_SRAMPC1_SRAM2PM3_Pos (2) /*!< SYS_T::SRAMPC1: SRAM2PM3 Position */ 2198 #define SYS_SRAMPC1_SRAM2PM3_Msk (0x3ul << SYS_SRAMPC1_SRAM2PM3_Pos) /*!< SYS_T::SRAMPC1: SRAM2PM3 Mask */ 2199 2200 #define SYS_SRAMPC1_SRAM2PM4_Pos (4) /*!< SYS_T::SRAMPC1: SRAM2PM4 Position */ 2201 #define SYS_SRAMPC1_SRAM2PM4_Msk (0x3ul << SYS_SRAMPC1_SRAM2PM4_Pos) /*!< SYS_T::SRAMPC1: SRAM2PM4 Mask */ 2202 2203 #define SYS_SRAMPC1_SRAM2PM5_Pos (6) /*!< SYS_T::SRAMPC1: SRAM2PM5 Position */ 2204 #define SYS_SRAMPC1_SRAM2PM5_Msk (0x3ul << SYS_SRAMPC1_SRAM2PM5_Pos) /*!< SYS_T::SRAMPC1: SRAM2PM5 Mask */ 2205 2206 #define SYS_SRAMPC1_CAN_Pos (16) /*!< SYS_T::SRAMPC1: CAN Position */ 2207 #define SYS_SRAMPC1_CAN_Msk (0x3ul << SYS_SRAMPC1_CAN_Pos) /*!< SYS_T::SRAMPC1: CAN Mask */ 2208 2209 #define SYS_SRAMPC1_USBD_Pos (18) /*!< SYS_T::SRAMPC1: USBD Position */ 2210 #define SYS_SRAMPC1_USBD_Msk (0x3ul << SYS_SRAMPC1_USBD_Pos) /*!< SYS_T::SRAMPC1: USBD Mask */ 2211 2212 #define SYS_SRAMPC1_PDMA0_Pos (20) /*!< SYS_T::SRAMPC1: PDMA0 Position */ 2213 #define SYS_SRAMPC1_PDMA0_Msk (0x3ul << SYS_SRAMPC1_PDMA0_Pos) /*!< SYS_T::SRAMPC1: PDMA0 Mask */ 2214 2215 #define SYS_SRAMPC1_PDMA1_Pos (22) /*!< SYS_T::SRAMPC1: PDMA1 Position */ 2216 #define SYS_SRAMPC1_PDMA1_Msk (0x3ul << SYS_SRAMPC1_PDMA1_Pos) /*!< SYS_T::SRAMPC1: PDMA1 Mask */ 2217 2218 #define SYS_SRAMPC1_FMCCACHE_Pos (24) /*!< SYS_T::SRAMPC1: FMCCACHE Position */ 2219 #define SYS_SRAMPC1_FMCCACHE_Msk (0x3ul << SYS_SRAMPC1_FMCCACHE_Pos) /*!< SYS_T::SRAMPC1: FMCCACHE Mask */ 2220 2221 #define SYS_SRAMPC1_RSA_Pos (26) /*!< SYS_T::SRAMPC1: RSA Position */ 2222 #define SYS_SRAMPC1_RSA_Msk (0x3ul << SYS_SRAMPC1_RSA_Pos) /*!< SYS_T::SRAMPC1: RSA Mask */ 2223 2224 #define SYS_SRAMPC1_KS_Pos (28) /*!< SYS_T::SRAMPC1: KS Position */ 2225 #define SYS_SRAMPC1_KS_Msk (0x3ul << SYS_SRAMPC1_KS_Pos) /*!< SYS_T::SRAMPC1: KS Mask */ 2226 2227 #define SYS_SRAMPC1_PCBUSY_Pos (31) /*!< SYS_T::SRAMPC1: PCBUSY Position */ 2228 #define SYS_SRAMPC1_PCBUSY_Msk (0x1ul << SYS_SRAMPC1_PCBUSY_Pos) /*!< SYS_T::SRAMPC1: PCBUSY Mask */ 2229 2230 #define SYS_TCTL48M_FREQSEL_Pos (0) /*!< SYS_T::TCTL48M: FREQSEL Position */ 2231 #define SYS_TCTL48M_FREQSEL_Msk (0x3ul << SYS_TCTL48M_FREQSEL_Pos) /*!< SYS_T::TCTL48M: FREQSEL Mask */ 2232 2233 #define SYS_TCTL48M_LOOPSEL_Pos (4) /*!< SYS_T::TCTL48M: LOOPSEL Position */ 2234 #define SYS_TCTL48M_LOOPSEL_Msk (0x3ul << SYS_TCTL48M_LOOPSEL_Pos) /*!< SYS_T::TCTL48M: LOOPSEL Mask */ 2235 2236 #define SYS_TCTL48M_RETRYCNT_Pos (6) /*!< SYS_T::TCTL48M: RETRYCNT Position */ 2237 #define SYS_TCTL48M_RETRYCNT_Msk (0x3ul << SYS_TCTL48M_RETRYCNT_Pos) /*!< SYS_T::TCTL48M: RETRYCNT Mask */ 2238 2239 #define SYS_TCTL48M_CESTOPEN_Pos (8) /*!< SYS_T::TCTL48M: CESTOPEN Position */ 2240 #define SYS_TCTL48M_CESTOPEN_Msk (0x1ul << SYS_TCTL48M_CESTOPEN_Pos) /*!< SYS_T::TCTL48M: CESTOPEN Mask */ 2241 2242 #define SYS_TCTL48M_BOUNDEN_Pos (9) /*!< SYS_T::TCTL48M: BOUNDEN Position */ 2243 #define SYS_TCTL48M_BOUNDEN_Msk (0x1ul << SYS_TCTL48M_BOUNDEN_Pos) /*!< SYS_T::TCTL48M: BOUNDEN Mask */ 2244 2245 #define SYS_TCTL48M_REFCKSEL_Pos (10) /*!< SYS_T::TCTL48M: REFCKSEL Position */ 2246 #define SYS_TCTL48M_REFCKSEL_Msk (0x1ul << SYS_TCTL48M_REFCKSEL_Pos) /*!< SYS_T::TCTL48M: REFCKSEL Mask */ 2247 2248 #define SYS_TCTL48M_BOUNDARY_Pos (16) /*!< SYS_T::TCTL48M: BOUNDARY Position */ 2249 #define SYS_TCTL48M_BOUNDARY_Msk (0x1ful << SYS_TCTL48M_BOUNDARY_Pos) /*!< SYS_T::TCTL48M: BOUNDARY Mask */ 2250 2251 #define SYS_TIEN48M_TFAILIEN_Pos (1) /*!< SYS_T::TIEN48M: TFAILIEN Position */ 2252 #define SYS_TIEN48M_TFAILIEN_Msk (0x1ul << SYS_TIEN48M_TFAILIEN_Pos) /*!< SYS_T::TIEN48M: TFAILIEN Mask */ 2253 2254 #define SYS_TIEN48M_CLKEIEN_Pos (2) /*!< SYS_T::TIEN48M: CLKEIEN Position */ 2255 #define SYS_TIEN48M_CLKEIEN_Msk (0x1ul << SYS_TIEN48M_CLKEIEN_Pos) /*!< SYS_T::TIEN48M: CLKEIEN Mask */ 2256 2257 #define SYS_TISTS48M_FREQLOCK_Pos (0) /*!< SYS_T::TISTS48M: FREQLOCK Position */ 2258 #define SYS_TISTS48M_FREQLOCK_Msk (0x1ul << SYS_TISTS48M_FREQLOCK_Pos) /*!< SYS_T::TISTS48M: FREQLOCK Mask */ 2259 2260 #define SYS_TISTS48M_TFAILIF_Pos (1) /*!< SYS_T::TISTS48M: TFAILIF Position */ 2261 #define SYS_TISTS48M_TFAILIF_Msk (0x1ul << SYS_TISTS48M_TFAILIF_Pos) /*!< SYS_T::TISTS48M: TFAILIF Mask */ 2262 2263 #define SYS_TISTS48M_CLKERRIF_Pos (2) /*!< SYS_T::TISTS48M: CLKERRIF Position */ 2264 #define SYS_TISTS48M_CLKERRIF_Msk (0x1ul << SYS_TISTS48M_CLKERRIF_Pos) /*!< SYS_T::TISTS48M: CLKERRIF Mask */ 2265 2266 #define SYS_TISTS48M_OVBDIF_Pos (3) /*!< SYS_T::TISTS48M: OVBDIF Position */ 2267 #define SYS_TISTS48M_OVBDIF_Msk (0x1ul << SYS_TISTS48M_OVBDIF_Pos) /*!< SYS_T::TISTS48M: OVBDIF Mask */ 2268 2269 #define SYS_TCTL12M_FREQSEL_Pos (0) /*!< SYS_T::TCTL12M: FREQSEL Position */ 2270 #define SYS_TCTL12M_FREQSEL_Msk (0x3ul << SYS_TCTL12M_FREQSEL_Pos) /*!< SYS_T::TCTL12M: FREQSEL Mask */ 2271 2272 #define SYS_TCTL12M_LOOPSEL_Pos (4) /*!< SYS_T::TCTL12M: LOOPSEL Position */ 2273 #define SYS_TCTL12M_LOOPSEL_Msk (0x3ul << SYS_TCTL12M_LOOPSEL_Pos) /*!< SYS_T::TCTL12M: LOOPSEL Mask */ 2274 2275 #define SYS_TCTL12M_RETRYCNT_Pos (6) /*!< SYS_T::TCTL12M: RETRYCNT Position */ 2276 #define SYS_TCTL12M_RETRYCNT_Msk (0x3ul << SYS_TCTL12M_RETRYCNT_Pos) /*!< SYS_T::TCTL12M: RETRYCNT Mask */ 2277 2278 #define SYS_TCTL12M_CESTOPEN_Pos (8) /*!< SYS_T::TCTL12M: CESTOPEN Position */ 2279 #define SYS_TCTL12M_CESTOPEN_Msk (0x1ul << SYS_TCTL12M_CESTOPEN_Pos) /*!< SYS_T::TCTL12M: CESTOPEN Mask */ 2280 2281 #define SYS_TCTL12M_BOUNDEN_Pos (9) /*!< SYS_T::TCTL12M: BOUNDEN Position */ 2282 #define SYS_TCTL12M_BOUNDEN_Msk (0x1ul << SYS_TCTL12M_BOUNDEN_Pos) /*!< SYS_T::TCTL12M: BOUNDEN Mask */ 2283 2284 #define SYS_TCTL12M_REFCKSEL_Pos (10) /*!< SYS_T::TCTL12M: REFCKSEL Position */ 2285 #define SYS_TCTL12M_REFCKSEL_Msk (0x1ul << SYS_TCTL12M_REFCKSEL_Pos) /*!< SYS_T::TCTL12M: REFCKSEL Mask */ 2286 2287 #define SYS_TCTL12M_BOUNDARY_Pos (16) /*!< SYS_T::TCTL12M: BOUNDARY Position */ 2288 #define SYS_TCTL12M_BOUNDARY_Msk (0x1ful << SYS_TCTL12M_BOUNDARY_Pos) /*!< SYS_T::TCTL12M: BOUNDARY Mask */ 2289 2290 #define SYS_TIEN12M_TFAILIEN_Pos (1) /*!< SYS_T::TIEN12M: TFAILIEN Position */ 2291 #define SYS_TIEN12M_TFAILIEN_Msk (0x1ul << SYS_TIEN12M_TFAILIEN_Pos) /*!< SYS_T::TIEN12M: TFAILIEN Mask */ 2292 2293 #define SYS_TIEN12M_CLKEIEN_Pos (2) /*!< SYS_T::TIEN12M: CLKEIEN Position */ 2294 #define SYS_TIEN12M_CLKEIEN_Msk (0x1ul << SYS_TIEN12M_CLKEIEN_Pos) /*!< SYS_T::TIEN12M: CLKEIEN Mask */ 2295 2296 #define SYS_TISTS12M_FREQLOCK_Pos (0) /*!< SYS_T::TISTS12M: FREQLOCK Position */ 2297 #define SYS_TISTS12M_FREQLOCK_Msk (0x1ul << SYS_TISTS12M_FREQLOCK_Pos) /*!< SYS_T::TISTS12M: FREQLOCK Mask */ 2298 2299 #define SYS_TISTS12M_TFAILIF_Pos (1) /*!< SYS_T::TISTS12M: TFAILIF Position */ 2300 #define SYS_TISTS12M_TFAILIF_Msk (0x1ul << SYS_TISTS12M_TFAILIF_Pos) /*!< SYS_T::TISTS12M: TFAILIF Mask */ 2301 2302 #define SYS_TISTS12M_CLKERRIF_Pos (2) /*!< SYS_T::TISTS12M: CLKERRIF Position */ 2303 #define SYS_TISTS12M_CLKERRIF_Msk (0x1ul << SYS_TISTS12M_CLKERRIF_Pos) /*!< SYS_T::TISTS12M: CLKERRIF Mask */ 2304 2305 #define SYS_TISTS12M_OVBDIF_Pos (3) /*!< SYS_T::TISTS12M: OVBDIF Position */ 2306 #define SYS_TISTS12M_OVBDIF_Msk (0x1ul << SYS_TISTS12M_OVBDIF_Pos) /*!< SYS_T::TISTS12M: OVBDIF Mask */ 2307 2308 #define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ 2309 #define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ 2310 2311 #define SYS_CPUCFG_INTRTEN_Pos (0) /*!< SYS_T::CPUCFG: INTRTEN Position */ 2312 #define SYS_CPUCFG_INTRTEN_Msk (0x1ul << SYS_CPUCFG_INTRTEN_Pos) /*!< SYS_T::CPUCFG: INTRTEN Mask */ 2313 2314 #define SYS_OVDCTL_OVDEN_Pos (0) /*!< SYS_T::OVDCTL: OVDEN Position */ 2315 #define SYS_OVDCTL_OVDEN_Msk (0x1ul << SYS_OVDCTL_OVDEN_Pos) /*!< SYS_T::OVDCTL: OVDEN Mask */ 2316 2317 #define SYS_OVDCTL_OVDSTB_Pos (31) /*!< SYS_T::OVDCTL: OVDSTB Position */ 2318 #define SYS_OVDCTL_OVDSTB_Msk (0x1ul << SYS_OVDCTL_OVDSTB_Pos) /*!< SYS_T::OVDCTL: OVDSTB Mask */ 2319 2320 #define SYS_PORCTL1_POROFF_Pos (0) /*!< SYS_T::PORCTL1: POROFF Position */ 2321 #define SYS_PORCTL1_POROFF_Msk (0xfffful << SYS_PORCTL1_POROFF_Pos) /*!< SYS_T::PORCTL1: POROFF Mask */ 2322 2323 #define SYS_PSWCTL_CRPTPWREN_Pos (12) /*!< SYS_T::PSWCTL: CRPTPWREN Position */ 2324 #define SYS_PSWCTL_CRPTPWREN_Msk (0x1ul << SYS_PSWCTL_CRPTPWREN_Pos) /*!< SYS_T::PSWCTL: CRPTPWREN Mask */ 2325 2326 #define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ 2327 #define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ 2328 2329 #define SYS_PLCTL_MVRS_Pos (4) /*!< SYS_T::PLCTL: MVRS Position */ 2330 #define SYS_PLCTL_MVRS_Msk (0x1ul << SYS_PLCTL_MVRS_Pos) /*!< SYS_T::PLCTL: MVRS Mask */ 2331 2332 #define SYS_PLCTL_WRBUSY_Pos (7) /*!< SYS_T::PLCTL: WRBUSY Position */ 2333 #define SYS_PLCTL_WRBUSY_Msk (0x1ul << SYS_PLCTL_WRBUSY_Pos) /*!< SYS_T::PLCTL: WRBUSY Mask */ 2334 2335 #define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */ 2336 #define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */ 2337 2338 #define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */ 2339 #define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */ 2340 2341 #define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ 2342 #define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ 2343 2344 #define SYS_PLSTS_MVRCBUSY_Pos (1) /*!< SYS_T::PLSTS: MVRCBUSY Position */ 2345 #define SYS_PLSTS_MVRCBUSY_Msk (0x1ul << SYS_PLSTS_MVRCBUSY_Pos) /*!< SYS_T::PLSTS: MVRCBUSY Mask */ 2346 2347 #define SYS_PLSTS_MVRCERR_Pos (2) /*!< SYS_T::PLSTS: MVRCERR Position */ 2348 #define SYS_PLSTS_MVRCERR_Msk (0x1ul << SYS_PLSTS_MVRCERR_Pos) /*!< SYS_T::PLSTS: MVRCERR Mask */ 2349 2350 #define SYS_PLSTS_LCONS_Pos (3) /*!< SYS_T::PLSTS: LCONS Position */ 2351 #define SYS_PLSTS_LCONS_Msk (0x1ul << SYS_PLSTS_LCONS_Pos) /*!< SYS_T::PLSTS: LCONS Mask */ 2352 2353 #define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */ 2354 #define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */ 2355 2356 #define SYS_PLSTS_CURMVR_Pos (12) /*!< SYS_T::PLSTS: CURMVR Position */ 2357 #define SYS_PLSTS_CURMVR_Msk (0x1ul << SYS_PLSTS_CURMVR_Pos) /*!< SYS_T::PLSTS: CURMVR Mask */ 2358 2359 #define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */ 2360 #define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */ 2361 2362 2363 /**@}*/ /* SYS_CONST */ 2364 typedef struct 2365 { 2366 2367 /** 2368 * @var SYS_INT_T::NMIEN 2369 * Offset: 0x00 NMI Source Interrupt Enable Register 2370 * --------------------------------------------------------------------------------------------------- 2371 * |Bits |Field |Descriptions 2372 * | :----: | :----: | :---- | 2373 * |[0] |BODOUT |BOD NMI Source Enable (Write Protect) 2374 * | | |0 = BOD NMI source Disabled. 2375 * | | |1 = BOD NMI source Enabled. 2376 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2377 * |[1] |IRCINT |IRC TRIM NMI Source Enable (Write Protect) 2378 * | | |0 = IRC TRIM NMI source Disabled. 2379 * | | |1 = IRC TRIM NMI source Enabled. 2380 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2381 * |[2] |PWRWUINT |Power-down Mode Wake-up NMI Source Enable (Write Protect) 2382 * | | |0 = Power-down mode wake-up NMI source Disabled. 2383 * | | |1 = Power-down mode wake-up NMI source Enabled. 2384 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2385 * |[3] |SRAMPERR |SRAM Parity Check Error NMI Source Enable (Write Protect) 2386 * | | |0 = SRAM parity check error NMI source Disabled. 2387 * | | |1 = SRAM parity check error NMI source Enabled. 2388 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2389 * |[4] |CLKFAIL |Clock Fail Detected NMI Source Enable (Write Protect) 2390 * | | |0 = Clock fail detected interrupt NMI source Disabled. 2391 * | | |1 = Clock fail detected interrupt NMI source Enabled. 2392 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2393 * |[6] |RTCINT |RTC NMI Source Enable (Write Protect) 2394 * | | |0 = RTC NMI source Disabled. 2395 * | | |1 = RTC NMI source Enabled. 2396 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2397 * |[7] |TAMPERINT |Tamper Interrupt NMI Source Enable (Write Protect) 2398 * | | |0 = Backup register tamper detected interrupt NMI source Disabled. 2399 * | | |1 = Backup register tamper detected interrupt NMI source Enabled. 2400 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2401 * |[8] |EINT0 |External Interrupt From PA.6, or PB.5 Pin NMI Source Enable (Write Protect) 2402 * | | |0 = External interrupt from PA.6, or PB.5 pin NMI source Disabled. 2403 * | | |1 = External interrupt from PA.6, or PB.5 pin NMI source Enabled. 2404 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2405 * |[9] |EINT1 |External Interrupt From PA.7 or PB.4 Pin NMI Source Enable (Write Protect) 2406 * | | |0 = External interrupt from PA.7 or PB.4 pin NMI source Disabled. 2407 * | | |1 = External interrupt from PA.7 or P4.4 pin NMI source Enabled. 2408 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2409 * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect) 2410 * | | |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled. 2411 * | | |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled. 2412 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2413 * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect) 2414 * | | |0 = External interrupt from PB.2 or PC.7pin NMI source Disabled. 2415 * | | |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled. 2416 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2417 * |[12] |EINT4 |External Interrupt From PA.8 or PB.6 Pin NMI Source Enable (Write Protect) 2418 * | | |0 = External interrupt from PA.8 or PB.6 pin NMI source Disabled. 2419 * | | |1 = External interrupt from PA.8 or PB.6 pin NMI source Enabled. 2420 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2421 * |[13] |EINT5 |External Interrupt From PB.7 or PD.12 Pin NMI Source Enable (Write Protect) 2422 * | | |0 = External interrupt from PB.7 or PD.12 pin NMI source Disabled. 2423 * | | |1 = External interrupt from PB.7 or PD.12 pin NMI source Enabled. 2424 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2425 * |[14] |UART0INT |UART0 NMI Source Enable (Write Protect) 2426 * | | |0 = UART0 NMI source Disabled. 2427 * | | |1 = UART0 NMI source Enabled. 2428 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2429 * |[15] |UART1INT |UART1 NMI Source Enable (Write Protect) 2430 * | | |0 = UART1 NMI source Disabled. 2431 * | | |1 = UART1 NMI source Enabled. 2432 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2433 * |[16] |EINT6 |External Interrupt From PB.8 or PD.11 Pin NMI Source Enable (Write Protect) 2434 * | | |0 = External interrupt from PB.8 or PD.11 pin NMI source Disabled. 2435 * | | |1 = External interrupt from PB.8 or PD.11 pin NMI source Enabled. 2436 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2437 * |[17] |EINT7 |External Interrupt From PB.9 or PD.10 Pin NMI Source Enable (Write Protect) 2438 * | | |0 = External interrupt from PB.9 or PD.10 pin NMI source Disabled. 2439 * | | |1 = External interrupt from PB.9 or PD.10 pin NMI source Enabled. 2440 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2441 * @var SYS_INT_T::NMISTS 2442 * Offset: 0x04 NMI source interrupt Status Register 2443 * --------------------------------------------------------------------------------------------------- 2444 * |Bits |Field |Descriptions 2445 * | :----: | :----: | :---- | 2446 * |[0] |BODOUT |BOD Interrupt Flag (Read Only) 2447 * | | |0 = BOD interrupt is de-asserted. 2448 * | | |1 = BOD interrupt is asserted. 2449 * |[1] |IRCINT |IRC TRIM Interrupt Flag (Read Only) 2450 * | | |0 = HIRC TRIM interrupt is de-asserted. 2451 * | | |1 = HIRC TRIM interrupt is asserted. 2452 * |[2] |PWRWUINT |Power-down Mode Wake-up Interrupt Flag (Read Only) 2453 * | | |0 = Power-down mode wake-up interrupt is de-asserted. 2454 * | | |1 = Power-down mode wake-up interrupt is asserted. 2455 * |[3] |SRAMPERR |SRAM Parity Check Error Interrupt Flag (Read Only) 2456 * | | |0 = SRAM parity check error interrupt is de-asserted. 2457 * | | |1 = SRAM parity check error interrupt is asserted. 2458 * |[4] |CLKFAIL |Clock Fail Detected Interrupt Flag (Read Only) 2459 * | | |0 = Clock fail detected interrupt is de-asserted. 2460 * | | |1 = Clock fail detected interrupt is asserted. 2461 * |[6] |RTCINT |RTC Interrupt Flag (Read Only) 2462 * | | |0 = RTC interrupt is de-asserted. 2463 * | | |1 = RTC interrupt is asserted. 2464 * |[7] |TAMPERINT |Tamper Interrupt Flag (Read Only) 2465 * | | |0 = Backup register tamper detected interrupt is de-asserted. 2466 * | | |1 = Backup register tamper detected interrupt is asserted. 2467 * |[8] |EINT0 |External Interrupt From PA.6, or PB.5 Pin Interrupt Flag (Read Only) 2468 * | | |0 = External Interrupt from PA.6, or PB.5 interrupt is deasserted. 2469 * | | |1 = External Interrupt from PA.6, or PB.5 interrupt is asserted. 2470 * |[9] |EINT1 |External Interrupt From PA.7, or PB.4 Pin Interrupt Flag (Read Only) 2471 * | | |0 = External Interrupt from PA.7, or PB.4 interrupt is deasserted. 2472 * | | |1 = External Interrupt from PA.7, or PB.4 interrupt is asserted. 2473 * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only) 2474 * | | |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted. 2475 * | | |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted. 2476 * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only) 2477 * | | |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted. 2478 * | | |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted. 2479 * |[12] |EINT4 |External Interrupt From PA.8 or PB.6 Pin Interrupt Flag (Read Only) 2480 * | | |0 = External Interrupt from PA.8 or PB.6 interrupt is deasserted. 2481 * | | |1 = External Interrupt from PA.8 or PB.6 interrupt is asserted. 2482 * |[13] |EINT5 |External Interrupt From PB.7 or PD.12 Pin Interrupt Flag (Read Only) 2483 * | | |0 = External Interrupt from PB.7 or PD.12 interrupt is deasserted. 2484 * | | |1 = External Interrupt from PB.7 or PD.12 interrupt is asserted. 2485 * |[14] |UART0INT |UART0 Interrupt Flag (Read Only) 2486 * | | |0 = UART1 interrupt is de-asserted. 2487 * | | |1 = UART1 interrupt is asserted. 2488 * |[15] |UART1INT |UART1 Interrupt Flag (Read Only) 2489 * | | |0 = UART1 interrupt is de-asserted. 2490 * | | |1 = UART1 interrupt is asserted. 2491 * |[16] |EINT6 |External Interrupt From PB.8 or PD.11 Pin Interrupt Flag (Read Only) 2492 * | | |0 = External Interrupt from PB.8 or PD.11 interrupt is deasserted. 2493 * | | |1 = External Interrupt from PB.8 or PD.11 interrupt is asserted. 2494 * |[17] |EINT7 |External Interrupt From PB.9 or PD.10 Pin Interrupt Flag (Read Only) 2495 * | | |0 = External Interrupt from PB.9 or PD.10 interrupt is deasserted. 2496 * | | |1 = External Interrupt from PB.9 or PD.10 interrupt is asserted. 2497 */ 2498 2499 __IO uint32_t NMIEN; /* Offset: 0x00 NMI Source Interrupt Enable Register */ 2500 __I uint32_t NMISTS; /* Offset: 0x04 NMI source interrupt Status Register */ 2501 2502 } SYS_INT_T; 2503 /** 2504 @addtogroup INT_CONST INT Bit Field Definition 2505 Constant Definitions for INT Controller 2506 @{ 2507 */ 2508 2509 #define SYS_NMIEN_BODOUT_Pos (0) /*!< SYS_INT_T::NMIEN: BODOUT Position */ 2510 #define SYS_NMIEN_BODOUT_Msk (0x1ul << SYS_NMIEN_BODOUT_Pos ) /*!< SYS_INT_T::NMIEN: BODOUT Mask */ 2511 2512 #define SYS_NMIEN_IRCINT_Pos (1) /*!< SYS_INT_T::NMIEN: IRCINT Position */ 2513 #define SYS_NMIEN_IRCINT_Msk (0x1ul << SYS_NMIEN_IRCINT_Pos ) /*!< SYS_INT_T::NMIEN: IRCINT Mask */ 2514 2515 #define SYS_NMIEN_PWRWUINT_Pos (2) /*!< SYS_INT_T::NMIEN: PWRWUINT Position */ 2516 #define SYS_NMIEN_PWRWUINT_Msk (0x1ul << SYS_NMIEN_PWRWUINT_Pos ) /*!< SYS_INT_T::NMIEN: PWRWUINT Mask */ 2517 2518 #define SYS_NMIEN_SRAMPERR_Pos (3) /*!< SYS_INT_T::NMIEN: SRAMPERR Position */ 2519 #define SYS_NMIEN_SRAMPERR_Msk (0x1ul << SYS_NMIEN_SRAMPERR_Pos ) /*!< SYS_INT_T::NMIEN: SRAMPERR Mask */ 2520 2521 #define SYS_NMIEN_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMIEN: CLKFAIL Position */ 2522 #define SYS_NMIEN_CLKFAIL_Msk (0x1ul << SYS_NMIEN_CLKFAIL_Pos ) /*!< SYS_INT_T::NMIEN: CLKFAIL Mask */ 2523 2524 #define SYS_NMIEN_RTCINT_Pos (6) /*!< SYS_INT_T::NMIEN: RTCINT Position */ 2525 #define SYS_NMIEN_RTCINT_Msk (0x1ul << SYS_NMIEN_RTCINT_Pos ) /*!< SYS_INT_T::NMIEN: RTCINT Mask */ 2526 2527 #define SYS_NMIEN_TAMPERINT_Pos (7) /*!< SYS_INT_T::NMIEN: TAMPERINT Position */ 2528 #define SYS_NMIEN_TAMPERINT_Msk (0x1ul << SYS_NMIEN_TAMPERINT_Pos ) /*!< SYS_INT_T::NMIEN: TAMPERINT Mask */ 2529 2530 #define SYS_NMIEN_EINT0_Pos (8) /*!< SYS_INT_T::NMIEN: EINT0 Position */ 2531 #define SYS_NMIEN_EINT0_Msk (0x1ul << SYS_NMIEN_EINT0_Pos ) /*!< SYS_INT_T::NMIEN: EINT0 Mask */ 2532 2533 #define SYS_NMIEN_EINT1_Pos (9) /*!< SYS_INT_T::NMIEN: EINT1 Position */ 2534 #define SYS_NMIEN_EINT1_Msk (0x1ul << SYS_NMIEN_EINT1_Pos ) /*!< SYS_INT_T::NMIEN: EINT1 Mask */ 2535 2536 #define SYS_NMIEN_EINT2_Pos (10) /*!< SYS_INT_T::NMIEN: EINT2 Position */ 2537 #define SYS_NMIEN_EINT2_Msk (0x1ul << SYS_NMIEN_EINT2_Pos ) /*!< SYS_INT_T::NMIEN: EINT2 Mask */ 2538 2539 #define SYS_NMIEN_EINT3_Pos (11) /*!< SYS_INT_T::NMIEN: EINT3 Position */ 2540 #define SYS_NMIEN_EINT3_Msk (0x1ul << SYS_NMIEN_EINT3_Pos ) /*!< SYS_INT_T::NMIEN: EINT3 Mask */ 2541 2542 #define SYS_NMIEN_EINT4_Pos (12) /*!< SYS_INT_T::NMIEN: EINT4 Position */ 2543 #define SYS_NMIEN_EINT4_Msk (0x1ul << SYS_NMIEN_EINT4_Pos ) /*!< SYS_INT_T::NMIEN: EINT4 Mask */ 2544 2545 #define SYS_NMIEN_EINT5_Pos (13) /*!< SYS_INT_T::NMIEN: EINT5 Position */ 2546 #define SYS_NMIEN_EINT5_Msk (0x1ul << SYS_NMIEN_EINT5_Pos ) /*!< SYS_INT_T::NMIEN: EINT5 Mask */ 2547 2548 #define SYS_NMIEN_UART0INT_Pos (14) /*!< SYS_INT_T::NMIEN: UART0INT Position */ 2549 #define SYS_NMIEN_UART0INT_Msk (0x1ul << SYS_NMIEN_UART0INT_Pos ) /*!< SYS_INT_T::NMIEN: UART0INT Mask */ 2550 2551 #define SYS_NMIEN_UART1INT_Pos (15) /*!< SYS_INT_T::NMIEN: UART1INT Position */ 2552 #define SYS_NMIEN_UART1INT_Msk (0x1ul << SYS_NMIEN_UART1INT_Pos ) /*!< SYS_INT_T::NMIEN: UART1INT Mask */ 2553 2554 #define SYS_NMIEN_EINT6_Pos (16) /*!< SYS_INT_T::NMIEN: EINT6 Position */ 2555 #define SYS_NMIEN_EINT6_Msk (0x1ul << SYS_NMIEN_EINT6_Pos ) /*!< SYS_INT_T::NMIEN: EINT6 Mask */ 2556 2557 #define SYS_NMIEN_EINT7_Pos (17) /*!< SYS_INT_T::NMIEN: EINT7 Position */ 2558 #define SYS_NMIEN_EINT7_Msk (0x1ul << SYS_NMIEN_EINT7_Pos ) /*!< SYS_INT_T::NMIEN: EINT7 Mask */ 2559 2560 #define SYS_NMISTS_BODOUT_Pos (0) /*!< SYS_INT_T::NMISTS: BODOUT Position */ 2561 #define SYS_NMISTS_BODOUT_Msk (0x1ul << SYS_NMISTS_BODOUT_Pos ) /*!< SYS_INT_T::NMISTS: BODOUT Mask */ 2562 2563 #define SYS_NMISTS_IRCINT_Pos (1) /*!< SYS_INT_T::NMISTS: IRCINT Position */ 2564 #define SYS_NMISTS_IRCINT_Msk (0x1ul << SYS_NMISTS_IRCINT_Pos ) /*!< SYS_INT_T::NMISTS: IRCINT Mask */ 2565 2566 #define SYS_NMISTS_PWRWUINT_Pos (2) /*!< SYS_INT_T::NMISTS: PWRWUINT Position */ 2567 #define SYS_NMISTS_PWRWUINT_Msk (0x1ul << SYS_NMISTS_PWRWUINT_Pos ) /*!< SYS_INT_T::NMISTS: PWRWUINT Mask */ 2568 2569 #define SYS_NMISTS_SRAMPERR_Pos (3) /*!< SYS_INT_T::NMISTS: SRAMPERR Position */ 2570 #define SYS_NMISTS_SRAMPERR_Msk (0x1ul << SYS_NMISTS_SRAMPERR_Pos ) /*!< SYS_INT_T::NMISTS: SRAMPERR Mask */ 2571 2572 #define SYS_NMISTS_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMISTS: CLKFAIL Position */ 2573 #define SYS_NMISTS_CLKFAIL_Msk (0x1ul << SYS_NMISTS_CLKFAIL_Pos ) /*!< SYS_INT_T::NMISTS: CLKFAIL Mask */ 2574 2575 #define SYS_NMISTS_RTCINT_Pos (6) /*!< SYS_INT_T::NMISTS: RTCINT Position */ 2576 #define SYS_NMISTS_RTCINT_Msk (0x1ul << SYS_NMISTS_RTCINT_Pos ) /*!< SYS_INT_T::NMISTS: RTCINT Mask */ 2577 2578 #define SYS_NMISTS_TAMPERINT_Pos (7) /*!< SYS_INT_T::NMISTS: TAMPERINT Position */ 2579 #define SYS_NMISTS_TAMPERINT_Msk (0x1ul << SYS_NMISTS_TAMPERINT_Pos ) /*!< SYS_INT_T::NMISTS: TAMPERINT Mask */ 2580 2581 #define SYS_NMISTS_EINT0_Pos (8) /*!< SYS_INT_T::NMISTS: EINT0 Position */ 2582 #define SYS_NMISTS_EINT0_Msk (0x1ul << SYS_NMISTS_EINT0_Pos ) /*!< SYS_INT_T::NMISTS: EINT0 Mask */ 2583 2584 #define SYS_NMISTS_EINT1_Pos (9) /*!< SYS_INT_T::NMISTS: EINT1 Position */ 2585 #define SYS_NMISTS_EINT1_Msk (0x1ul << SYS_NMISTS_EINT1_Pos ) /*!< SYS_INT_T::NMISTS: EINT1 Mask */ 2586 2587 #define SYS_NMISTS_EINT2_Pos (10) /*!< SYS_INT_T::NMISTS: EINT2 Position */ 2588 #define SYS_NMISTS_EINT2_Msk (0x1ul << SYS_NMISTS_EINT2_Pos ) /*!< SYS_INT_T::NMISTS: EINT2 Mask */ 2589 2590 #define SYS_NMISTS_EINT3_Pos (11) /*!< SYS_INT_T::NMISTS: EINT3 Position */ 2591 #define SYS_NMISTS_EINT3_Msk (0x1ul << SYS_NMISTS_EINT3_Pos ) /*!< SYS_INT_T::NMISTS: EINT3 Mask */ 2592 2593 #define SYS_NMISTS_EINT4_Pos (12) /*!< SYS_INT_T::NMISTS: EINT4 Position */ 2594 #define SYS_NMISTS_EINT4_Msk (0x1ul << SYS_NMISTS_EINT4_Pos ) /*!< SYS_INT_T::NMISTS: EINT4 Mask */ 2595 2596 #define SYS_NMISTS_EINT5_Pos (13) /*!< SYS_INT_T::NMISTS: EINT5 Position */ 2597 #define SYS_NMISTS_EINT5_Msk (0x1ul << SYS_NMISTS_EINT5_Pos ) /*!< SYS_INT_T::NMISTS: EINT5 Mask */ 2598 2599 #define SYS_NMISTS_UART0INT_Pos (14) /*!< SYS_INT_T::NMISTS: UART0_INT Position */ 2600 #define SYS_NMISTS_UART0INT_Msk (0x1ul << SYS_NMISTS_UART0INT_Pos ) /*!< SYS_INT_T::NMISTS: UART0_INT Mask */ 2601 2602 #define SYS_NMISTS_UART1INT_Pos (15) /*!< SYS_INT_T::NMISTS: UART1_INT Position */ 2603 #define SYS_NMISTS_UART1INT_Msk (0x1ul << SYS_NMISTS_UART1INT_Pos ) /*!< SYS_INT_T::NMISTS: UART1_INT Mask */ 2604 2605 #define SYS_NMISTS_EINT6_Pos (16) /*!< SYS_INT_T::NMISTS: EINT6 Position */ 2606 #define SYS_NMISTS_EINT6_Msk (0x1ul << SYS_NMISTS_EINT6_Pos ) /*!< SYS_INT_T::NMISTS: EINT6 Mask */ 2607 2608 #define SYS_NMISTS_EINT7_Pos (17) /*!< SYS_INT_T::NMISTS: EINT7 Position */ 2609 #define SYS_NMISTS_EINT7_Msk (0x1ul << SYS_NMISTS_EINT7_Pos ) /*!< SYS_INT_T::NMISTS: EINT7 Mask */ 2610 2611 2612 /**@}*/ /* INT_CONST */ 2613 /**@}*/ /* end of SYS register group */ 2614 /**@}*/ /* end of REGISTER group */ 2615 2616 2617 #endif /* __SYS_REG_H__ */ 2618
