1 /* 2 * Copyright (c) 2019-2022 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __DEVICE_CFG_H__ 18 #define __DEVICE_CFG_H__ 19 20 /** 21 * \file device_cfg.h 22 * \brief 23 * This is the device configuration file with only used peripherals 24 * defined and configured via the secure and/or non-secure base address. 25 */ 26 27 /* ARM Memory Protection Controller (MPC) */ 28 #define MPC_ISRAM0_S 29 #define MPC_ISRAM1_S 30 #define MPC_SRAM_S 31 #define MPC_QSPI_S 32 33 /* ARM Peripheral Protection Controllers (PPC) */ 34 #define PPC_SSE300_MAIN0_S 35 #define PPC_SSE300_MAIN_EXP0_S 36 #define PPC_SSE300_MAIN_EXP1_S 37 #define PPC_SSE300_MAIN_EXP2_S 38 #define PPC_SSE300_MAIN_EXP3_S 39 #define PPC_SSE300_PERIPH0_S 40 #define PPC_SSE300_PERIPH1_S 41 #define PPC_SSE300_PERIPH_EXP0_S 42 #define PPC_SSE300_PERIPH_EXP1_S 43 #define PPC_SSE300_PERIPH_EXP2_S 44 #define PPC_SSE300_PERIPH_EXP3_S 45 46 /* ARM UART CMSDK */ 47 #define DEFAULT_UART_BAUDRATE 115200 48 #define UART0_CMSDK_NS 49 50 /** System Counter Armv8-M */ 51 #define SYSCOUNTER_CNTRL_ARMV8_M_S 52 #define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S 53 54 /** 55 * Arbitrary scaling values for test purposes 56 */ 57 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u 58 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u 59 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u 60 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u 61 62 63 /* System Timer Armv8-M */ 64 #define SYSTIMER0_ARMV8_M_S 65 66 #define SYSTIMER1_ARMV8_M_NS 67 68 #define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) 69 #define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) 70 71 #endif /* __DEVICE_CFG_H__ */ 72
