1 /***************************************************************************//** 2 * \file cyip_cpuss.h 3 * 4 * \brief 5 * CPUSS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_CPUSS_H_ 28 #define _CYIP_CPUSS_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * CPUSS 34 *******************************************************************************/ 35 36 #define CPUSS_SECTION_SIZE 0x00004000UL 37 38 /** 39 * \brief SYSCPUSS registers (CPUSS) 40 */ 41 typedef struct { 42 __IM uint32_t IDENTITY; /*!< 0x00000000 Identity */ 43 __IM uint32_t RESERVED[3]; 44 __IM uint32_t PRODUCT_ID; /*!< 0x00000010 Product identifier and version (same as CoreSight RomTables) */ 45 __IM uint32_t RESERVED1[3]; 46 __IM uint32_t DP_STATUS; /*!< 0x00000020 Debug port status */ 47 __IM uint32_t RESERVED2[3]; 48 __IOM uint32_t BUFF_CTL; /*!< 0x00000030 Buffer control */ 49 __IM uint32_t RESERVED3[3]; 50 __IOM uint32_t CAL_SUP_SET; /*!< 0x00000040 Calibration support set and read */ 51 __IOM uint32_t CAL_SUP_CLR; /*!< 0x00000044 Calibration support clear and reset */ 52 __IM uint32_t RESERVED4[2]; 53 __IOM uint32_t INFRA_CTL; /*!< 0x00000050 Infrastructure Control */ 54 __IM uint32_t RESERVED5[43]; 55 __IOM uint32_t SYSTICK_S_CTL; /*!< 0x00000100 Secure SysTick timer control */ 56 __IM uint32_t RESERVED6[7]; 57 __IOM uint32_t SYSTICK_NS_CTL; /*!< 0x00000120 Non Secure SysTick timer control */ 58 __IM uint32_t RESERVED7[55]; 59 __IOM uint32_t INTR_MSC; /*!< 0x00000200 Master security controller Interrupt */ 60 __IM uint32_t RESERVED8; 61 __IOM uint32_t INTR_MASK_MSC; /*!< 0x00000208 Master security controller Interrupt mask */ 62 __IM uint32_t INTR_MASKED_MSC; /*!< 0x0000020C Master security controller Interrupt masked */ 63 __IM uint32_t AHB_ERROR_STATUS1; /*!< 0x00000210 AHB Error status1 */ 64 __IM uint32_t AHB_ERROR_STATUS2; /*!< 0x00000214 AHB Error status2 */ 65 __IM uint32_t RESERVED9[2]; 66 __IOM uint32_t INTR_AHB_ERROR; /*!< 0x00000220 Interrupt AHB ERROR */ 67 __IOM uint32_t INTR_SET_AHB_ERROR; /*!< 0x00000224 Interrupt AHB ERROR set */ 68 __IOM uint32_t INTR_MASK_AHB_ERROR; /*!< 0x00000228 Interrupt AHB ERROR mask */ 69 __IM uint32_t INTR_MASKED_AHB_ERROR; /*!< 0x0000022C Interrupt AHB ERROR masked */ 70 __IM uint32_t RESERVED10[884]; 71 __IOM uint32_t AP_CTL; /*!< 0x00001000 Access port control */ 72 __IM uint32_t RESERVED11[1024]; 73 __IOM uint32_t PROTECTION; /*!< 0x00002004 Protection status */ 74 __IM uint32_t RESERVED12[62]; 75 __IOM uint32_t TRIM_ROM_CTL; /*!< 0x00002100 ROM trim control */ 76 __IM uint32_t RESERVED13[3]; 77 __IOM uint32_t TRIM_RAM_CTL; /*!< 0x00002110 RAM trim control */ 78 __IOM uint32_t TRIM_RAM_CTL2; /*!< 0x00002114 RAM trim control2 */ 79 __IOM uint32_t TRIM_RAM_CTL3; /*!< 0x00002118 RAM trim control3 */ 80 __IOM uint32_t TRIM_RAM_CTL4; /*!< 0x0000211C RAM trim control4 */ 81 } CPUSS_Type; /*!< Size = 8480 (0x2120) */ 82 83 84 /* CPUSS.IDENTITY */ 85 #define CPUSS_IDENTITY_P_Pos 0UL 86 #define CPUSS_IDENTITY_P_Msk 0x1UL 87 #define CPUSS_IDENTITY_NS_Pos 1UL 88 #define CPUSS_IDENTITY_NS_Msk 0x2UL 89 #define CPUSS_IDENTITY_PC_Pos 4UL 90 #define CPUSS_IDENTITY_PC_Msk 0xF0UL 91 #define CPUSS_IDENTITY_MS_Pos 8UL 92 #define CPUSS_IDENTITY_MS_Msk 0xFF00UL 93 /* CPUSS.PRODUCT_ID */ 94 #define CPUSS_PRODUCT_ID_FAMILY_ID_Pos 0UL 95 #define CPUSS_PRODUCT_ID_FAMILY_ID_Msk 0xFFFUL 96 #define CPUSS_PRODUCT_ID_MAJOR_REV_Pos 16UL 97 #define CPUSS_PRODUCT_ID_MAJOR_REV_Msk 0xF0000UL 98 #define CPUSS_PRODUCT_ID_MINOR_REV_Pos 20UL 99 #define CPUSS_PRODUCT_ID_MINOR_REV_Msk 0xF00000UL 100 /* CPUSS.DP_STATUS */ 101 #define CPUSS_DP_STATUS_SWJ_CONNECTED_Pos 0UL 102 #define CPUSS_DP_STATUS_SWJ_CONNECTED_Msk 0x1UL 103 #define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Pos 1UL 104 #define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Msk 0x2UL 105 #define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Pos 2UL 106 #define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Msk 0x4UL 107 /* CPUSS.BUFF_CTL */ 108 #define CPUSS_BUFF_CTL_WRITE_BUFF_Pos 0UL 109 #define CPUSS_BUFF_CTL_WRITE_BUFF_Msk 0x1UL 110 /* CPUSS.CAL_SUP_SET */ 111 #define CPUSS_CAL_SUP_SET_DATA_Pos 0UL 112 #define CPUSS_CAL_SUP_SET_DATA_Msk 0xFFFFFFFFUL 113 /* CPUSS.CAL_SUP_CLR */ 114 #define CPUSS_CAL_SUP_CLR_DATA_Pos 0UL 115 #define CPUSS_CAL_SUP_CLR_DATA_Msk 0xFFFFFFFFUL 116 /* CPUSS.INFRA_CTL */ 117 #define CPUSS_INFRA_CTL_CLOCK_FORCE_Pos 0UL 118 #define CPUSS_INFRA_CTL_CLOCK_FORCE_Msk 0x1UL 119 /* CPUSS.SYSTICK_S_CTL */ 120 #define CPUSS_SYSTICK_S_CTL_TENMS_Pos 0UL 121 #define CPUSS_SYSTICK_S_CTL_TENMS_Msk 0xFFFFFFUL 122 #define CPUSS_SYSTICK_S_CTL_CLOCK_SOURCE_Pos 24UL 123 #define CPUSS_SYSTICK_S_CTL_CLOCK_SOURCE_Msk 0x3000000UL 124 #define CPUSS_SYSTICK_S_CTL_SKEW_Pos 30UL 125 #define CPUSS_SYSTICK_S_CTL_SKEW_Msk 0x40000000UL 126 #define CPUSS_SYSTICK_S_CTL_NOREF_Pos 31UL 127 #define CPUSS_SYSTICK_S_CTL_NOREF_Msk 0x80000000UL 128 /* CPUSS.SYSTICK_NS_CTL */ 129 #define CPUSS_SYSTICK_NS_CTL_TENMS_Pos 0UL 130 #define CPUSS_SYSTICK_NS_CTL_TENMS_Msk 0xFFFFFFUL 131 #define CPUSS_SYSTICK_NS_CTL_CLOCK_SOURCE_Pos 24UL 132 #define CPUSS_SYSTICK_NS_CTL_CLOCK_SOURCE_Msk 0x3000000UL 133 #define CPUSS_SYSTICK_NS_CTL_SKEW_Pos 30UL 134 #define CPUSS_SYSTICK_NS_CTL_SKEW_Msk 0x40000000UL 135 #define CPUSS_SYSTICK_NS_CTL_NOREF_Pos 31UL 136 #define CPUSS_SYSTICK_NS_CTL_NOREF_Msk 0x80000000UL 137 /* CPUSS.INTR_MSC */ 138 #define CPUSS_INTR_MSC_CODE_MS0_MSC_Pos 0UL 139 #define CPUSS_INTR_MSC_CODE_MS0_MSC_Msk 0x1UL 140 #define CPUSS_INTR_MSC_SYS_MS0_MSC_Pos 1UL 141 #define CPUSS_INTR_MSC_SYS_MS0_MSC_Msk 0x2UL 142 #define CPUSS_INTR_MSC_SYS_MS1_MSC_Pos 2UL 143 #define CPUSS_INTR_MSC_SYS_MS1_MSC_Msk 0x4UL 144 #define CPUSS_INTR_MSC_EXP_MS_MSC_Pos 3UL 145 #define CPUSS_INTR_MSC_EXP_MS_MSC_Msk 0x8UL 146 #define CPUSS_INTR_MSC_DMAC0_MSC_Pos 4UL 147 #define CPUSS_INTR_MSC_DMAC0_MSC_Msk 0x10UL 148 #define CPUSS_INTR_MSC_DMAC1_MSC_Pos 5UL 149 #define CPUSS_INTR_MSC_DMAC1_MSC_Msk 0x20UL 150 /* CPUSS.INTR_MASK_MSC */ 151 #define CPUSS_INTR_MASK_MSC_CODE_MS0_MSC_Pos 0UL 152 #define CPUSS_INTR_MASK_MSC_CODE_MS0_MSC_Msk 0x1UL 153 #define CPUSS_INTR_MASK_MSC_SYS_MS0_MSC_Pos 1UL 154 #define CPUSS_INTR_MASK_MSC_SYS_MS0_MSC_Msk 0x2UL 155 #define CPUSS_INTR_MASK_MSC_SYS_MS1_MSC_Pos 2UL 156 #define CPUSS_INTR_MASK_MSC_SYS_MS1_MSC_Msk 0x4UL 157 #define CPUSS_INTR_MASK_MSC_EXP_MS_MSC_Pos 3UL 158 #define CPUSS_INTR_MASK_MSC_EXP_MS_MSC_Msk 0x8UL 159 #define CPUSS_INTR_MASK_MSC_DMAC0_MSC_Pos 4UL 160 #define CPUSS_INTR_MASK_MSC_DMAC0_MSC_Msk 0x10UL 161 #define CPUSS_INTR_MASK_MSC_DMAC1_MSC_Pos 5UL 162 #define CPUSS_INTR_MASK_MSC_DMAC1_MSC_Msk 0x20UL 163 /* CPUSS.INTR_MASKED_MSC */ 164 #define CPUSS_INTR_MASKED_MSC_CODE_MS0_MSC_Pos 0UL 165 #define CPUSS_INTR_MASKED_MSC_CODE_MS0_MSC_Msk 0x1UL 166 #define CPUSS_INTR_MASKED_MSC_SYS_MS0_MSC_Pos 1UL 167 #define CPUSS_INTR_MASKED_MSC_SYS_MS0_MSC_Msk 0x2UL 168 #define CPUSS_INTR_MASKED_MSC_SYS_MS1_MSC_Pos 2UL 169 #define CPUSS_INTR_MASKED_MSC_SYS_MS1_MSC_Msk 0x4UL 170 #define CPUSS_INTR_MASKED_MSC_EXP_MS_MSC_Pos 3UL 171 #define CPUSS_INTR_MASKED_MSC_EXP_MS_MSC_Msk 0x8UL 172 #define CPUSS_INTR_MASKED_MSC_DMAC0_MSC_Pos 4UL 173 #define CPUSS_INTR_MASKED_MSC_DMAC0_MSC_Msk 0x10UL 174 #define CPUSS_INTR_MASKED_MSC_DMAC1_MSC_Pos 5UL 175 #define CPUSS_INTR_MASKED_MSC_DMAC1_MSC_Msk 0x20UL 176 /* CPUSS.AHB_ERROR_STATUS1 */ 177 #define CPUSS_AHB_ERROR_STATUS1_ADDR_Pos 0UL 178 #define CPUSS_AHB_ERROR_STATUS1_ADDR_Msk 0xFFFFFFFFUL 179 /* CPUSS.AHB_ERROR_STATUS2 */ 180 #define CPUSS_AHB_ERROR_STATUS2_P_Pos 0UL 181 #define CPUSS_AHB_ERROR_STATUS2_P_Msk 0x1UL 182 #define CPUSS_AHB_ERROR_STATUS2_NS_Pos 1UL 183 #define CPUSS_AHB_ERROR_STATUS2_NS_Msk 0x2UL 184 #define CPUSS_AHB_ERROR_STATUS2_W_Pos 2UL 185 #define CPUSS_AHB_ERROR_STATUS2_W_Msk 0x4UL 186 #define CPUSS_AHB_ERROR_STATUS2_PC_Pos 4UL 187 #define CPUSS_AHB_ERROR_STATUS2_PC_Msk 0xF0UL 188 #define CPUSS_AHB_ERROR_STATUS2_MS_Pos 8UL 189 #define CPUSS_AHB_ERROR_STATUS2_MS_Msk 0xFF00UL 190 /* CPUSS.INTR_AHB_ERROR */ 191 #define CPUSS_INTR_AHB_ERROR_AHB_ERROR_Pos 0UL 192 #define CPUSS_INTR_AHB_ERROR_AHB_ERROR_Msk 0x1UL 193 /* CPUSS.INTR_SET_AHB_ERROR */ 194 #define CPUSS_INTR_SET_AHB_ERROR_AHB_ERROR_Pos 0UL 195 #define CPUSS_INTR_SET_AHB_ERROR_AHB_ERROR_Msk 0x1UL 196 /* CPUSS.INTR_MASK_AHB_ERROR */ 197 #define CPUSS_INTR_MASK_AHB_ERROR_AHB_ERROR_Pos 0UL 198 #define CPUSS_INTR_MASK_AHB_ERROR_AHB_ERROR_Msk 0x1UL 199 /* CPUSS.INTR_MASKED_AHB_ERROR */ 200 #define CPUSS_INTR_MASKED_AHB_ERROR_AHB_ERROR_Pos 0UL 201 #define CPUSS_INTR_MASKED_AHB_ERROR_AHB_ERROR_Msk 0x1UL 202 /* CPUSS.AP_CTL */ 203 #define CPUSS_AP_CTL_CM33_0_ENABLE_Pos 0UL 204 #define CPUSS_AP_CTL_CM33_0_ENABLE_Msk 0x1UL 205 #define CPUSS_AP_CTL_CM33_1_ENABLE_Pos 1UL 206 #define CPUSS_AP_CTL_CM33_1_ENABLE_Msk 0x2UL 207 #define CPUSS_AP_CTL_SYS_ENABLE_Pos 2UL 208 #define CPUSS_AP_CTL_SYS_ENABLE_Msk 0x4UL 209 #define CPUSS_AP_CTL_CM33_0_DBG_ENABLE_Pos 4UL 210 #define CPUSS_AP_CTL_CM33_0_DBG_ENABLE_Msk 0x10UL 211 #define CPUSS_AP_CTL_CM33_0_NID_ENABLE_Pos 5UL 212 #define CPUSS_AP_CTL_CM33_0_NID_ENABLE_Msk 0x20UL 213 #define CPUSS_AP_CTL_CM33_0_SPID_ENABLE_Pos 6UL 214 #define CPUSS_AP_CTL_CM33_0_SPID_ENABLE_Msk 0x40UL 215 #define CPUSS_AP_CTL_CM33_0_SPNID_ENABLE_Pos 7UL 216 #define CPUSS_AP_CTL_CM33_0_SPNID_ENABLE_Msk 0x80UL 217 #define CPUSS_AP_CTL_CM33_1_DBG_ENABLE_Pos 8UL 218 #define CPUSS_AP_CTL_CM33_1_DBG_ENABLE_Msk 0x100UL 219 #define CPUSS_AP_CTL_CM33_1_NID_ENABLE_Pos 9UL 220 #define CPUSS_AP_CTL_CM33_1_NID_ENABLE_Msk 0x200UL 221 #define CPUSS_AP_CTL_CM33_1_SPID_ENABLE_Pos 10UL 222 #define CPUSS_AP_CTL_CM33_1_SPID_ENABLE_Msk 0x400UL 223 #define CPUSS_AP_CTL_CM33_1_SPNID_ENABLE_Pos 11UL 224 #define CPUSS_AP_CTL_CM33_1_SPNID_ENABLE_Msk 0x800UL 225 #define CPUSS_AP_CTL_CM33_0_DISABLE_Pos 16UL 226 #define CPUSS_AP_CTL_CM33_0_DISABLE_Msk 0x10000UL 227 #define CPUSS_AP_CTL_CM33_1_DISABLE_Pos 17UL 228 #define CPUSS_AP_CTL_CM33_1_DISABLE_Msk 0x20000UL 229 #define CPUSS_AP_CTL_SYS_DISABLE_Pos 18UL 230 #define CPUSS_AP_CTL_SYS_DISABLE_Msk 0x40000UL 231 #define CPUSS_AP_CTL_CM33_0_DBG_DISABLE_Pos 20UL 232 #define CPUSS_AP_CTL_CM33_0_DBG_DISABLE_Msk 0x100000UL 233 #define CPUSS_AP_CTL_CM33_0_NID_DISABLE_Pos 21UL 234 #define CPUSS_AP_CTL_CM33_0_NID_DISABLE_Msk 0x200000UL 235 #define CPUSS_AP_CTL_CM33_0_SPID_DISABLE_Pos 22UL 236 #define CPUSS_AP_CTL_CM33_0_SPID_DISABLE_Msk 0x400000UL 237 #define CPUSS_AP_CTL_CM33_0_SPNID_DISABLE_Pos 23UL 238 #define CPUSS_AP_CTL_CM33_0_SPNID_DISABLE_Msk 0x800000UL 239 #define CPUSS_AP_CTL_CM33_1_DBG_DISABLE_Pos 24UL 240 #define CPUSS_AP_CTL_CM33_1_DBG_DISABLE_Msk 0x1000000UL 241 #define CPUSS_AP_CTL_CM33_1_NID_DISABLE_Pos 25UL 242 #define CPUSS_AP_CTL_CM33_1_NID_DISABLE_Msk 0x2000000UL 243 #define CPUSS_AP_CTL_CM33_1_SPID_DISABLE_Pos 26UL 244 #define CPUSS_AP_CTL_CM33_1_SPID_DISABLE_Msk 0x4000000UL 245 #define CPUSS_AP_CTL_CM33_1_SPNID_DISABLE_Pos 27UL 246 #define CPUSS_AP_CTL_CM33_1_SPNID_DISABLE_Msk 0x8000000UL 247 /* CPUSS.PROTECTION */ 248 #define CPUSS_PROTECTION_STATE_Pos 0UL 249 #define CPUSS_PROTECTION_STATE_Msk 0xFFFFFFFFUL 250 /* CPUSS.TRIM_ROM_CTL */ 251 #define CPUSS_TRIM_ROM_CTL_TRIM_Pos 0UL 252 #define CPUSS_TRIM_ROM_CTL_TRIM_Msk 0xFFFFFFFFUL 253 /* CPUSS.TRIM_RAM_CTL */ 254 #define CPUSS_TRIM_RAM_CTL_TRIM_Pos 0UL 255 #define CPUSS_TRIM_RAM_CTL_TRIM_Msk 0xFFFFFFFFUL 256 /* CPUSS.TRIM_RAM_CTL2 */ 257 #define CPUSS_TRIM_RAM_CTL2_TRIM_Pos 0UL 258 #define CPUSS_TRIM_RAM_CTL2_TRIM_Msk 0xFFFFFFFFUL 259 /* CPUSS.TRIM_RAM_CTL3 */ 260 #define CPUSS_TRIM_RAM_CTL3_TRIM_Pos 0UL 261 #define CPUSS_TRIM_RAM_CTL3_TRIM_Msk 0xFFFFFFFFUL 262 /* CPUSS.TRIM_RAM_CTL4 */ 263 #define CPUSS_TRIM_RAM_CTL4_TRIM_Pos 0UL 264 #define CPUSS_TRIM_RAM_CTL4_TRIM_Msk 0xFFFFFFFFUL 265 266 267 #endif /* _CYIP_CPUSS_H_ */ 268 269 270 /* [] END OF FILE */ 271
