1 /** 2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _SOC_SYSCON_REG_H_ 7 #define _SOC_SYSCON_REG_H_ 8 9 10 #include "soc.h" 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0) 16 /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ 17 /*description: .*/ 18 #define SYSCON_RST_TICK_CNT (BIT(12)) 19 #define SYSCON_RST_TICK_CNT_M (BIT(12)) 20 #define SYSCON_RST_TICK_CNT_V 0x1 21 #define SYSCON_RST_TICK_CNT_S 12 22 /* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 23 /*description: .*/ 24 #define SYSCON_CLK_EN (BIT(11)) 25 #define SYSCON_CLK_EN_M (BIT(11)) 26 #define SYSCON_CLK_EN_V 0x1 27 #define SYSCON_CLK_EN_S 11 28 /* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 29 /*description: .*/ 30 #define SYSCON_CLK_320M_EN (BIT(10)) 31 #define SYSCON_CLK_320M_EN_M (BIT(10)) 32 #define SYSCON_CLK_320M_EN_V 0x1 33 #define SYSCON_CLK_320M_EN_S 10 34 /* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ 35 /*description: .*/ 36 #define SYSCON_PRE_DIV_CNT 0x000003FF 37 #define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S)) 38 #define SYSCON_PRE_DIV_CNT_V 0x3FF 39 #define SYSCON_PRE_DIV_CNT_S 0 40 41 #define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4) 42 /* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ 43 /*description: .*/ 44 #define SYSCON_TICK_ENABLE (BIT(16)) 45 #define SYSCON_TICK_ENABLE_M (BIT(16)) 46 #define SYSCON_TICK_ENABLE_V 0x1 47 #define SYSCON_TICK_ENABLE_S 16 48 /* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ 49 /*description: .*/ 50 #define SYSCON_CK8M_TICK_NUM 0x000000FF 51 #define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S)) 52 #define SYSCON_CK8M_TICK_NUM_V 0xFF 53 #define SYSCON_CK8M_TICK_NUM_S 8 54 /* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ 55 /*description: .*/ 56 #define SYSCON_XTAL_TICK_NUM 0x000000FF 57 #define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S)) 58 #define SYSCON_XTAL_TICK_NUM_V 0xFF 59 #define SYSCON_XTAL_TICK_NUM_S 0 60 61 #define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x8) 62 /* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ 63 /*description: .*/ 64 #define SYSCON_CLK_XTAL_OEN (BIT(10)) 65 #define SYSCON_CLK_XTAL_OEN_M (BIT(10)) 66 #define SYSCON_CLK_XTAL_OEN_V 0x1 67 #define SYSCON_CLK_XTAL_OEN_S 10 68 /* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ 69 /*description: .*/ 70 #define SYSCON_CLK40X_BB_OEN (BIT(9)) 71 #define SYSCON_CLK40X_BB_OEN_M (BIT(9)) 72 #define SYSCON_CLK40X_BB_OEN_V 0x1 73 #define SYSCON_CLK40X_BB_OEN_S 9 74 /* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ 75 /*description: .*/ 76 #define SYSCON_CLK_DAC_CPU_OEN (BIT(8)) 77 #define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8)) 78 #define SYSCON_CLK_DAC_CPU_OEN_V 0x1 79 #define SYSCON_CLK_DAC_CPU_OEN_S 8 80 /* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ 81 /*description: .*/ 82 #define SYSCON_CLK_ADC_INF_OEN (BIT(7)) 83 #define SYSCON_CLK_ADC_INF_OEN_M (BIT(7)) 84 #define SYSCON_CLK_ADC_INF_OEN_V 0x1 85 #define SYSCON_CLK_ADC_INF_OEN_S 7 86 /* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 87 /*description: .*/ 88 #define SYSCON_CLK_320M_OEN (BIT(6)) 89 #define SYSCON_CLK_320M_OEN_M (BIT(6)) 90 #define SYSCON_CLK_320M_OEN_V 0x1 91 #define SYSCON_CLK_320M_OEN_S 6 92 /* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 93 /*description: .*/ 94 #define SYSCON_CLK160_OEN (BIT(5)) 95 #define SYSCON_CLK160_OEN_M (BIT(5)) 96 #define SYSCON_CLK160_OEN_V 0x1 97 #define SYSCON_CLK160_OEN_S 5 98 /* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ 99 /*description: .*/ 100 #define SYSCON_CLK80_OEN (BIT(4)) 101 #define SYSCON_CLK80_OEN_M (BIT(4)) 102 #define SYSCON_CLK80_OEN_V 0x1 103 #define SYSCON_CLK80_OEN_S 4 104 /* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 105 /*description: .*/ 106 #define SYSCON_CLK_BB_OEN (BIT(3)) 107 #define SYSCON_CLK_BB_OEN_M (BIT(3)) 108 #define SYSCON_CLK_BB_OEN_V 0x1 109 #define SYSCON_CLK_BB_OEN_S 3 110 /* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ 111 /*description: .*/ 112 #define SYSCON_CLK44_OEN (BIT(2)) 113 #define SYSCON_CLK44_OEN_M (BIT(2)) 114 #define SYSCON_CLK44_OEN_V 0x1 115 #define SYSCON_CLK44_OEN_S 2 116 /* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ 117 /*description: .*/ 118 #define SYSCON_CLK22_OEN (BIT(1)) 119 #define SYSCON_CLK22_OEN_M (BIT(1)) 120 #define SYSCON_CLK22_OEN_V 0x1 121 #define SYSCON_CLK22_OEN_S 1 122 /* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 123 /*description: .*/ 124 #define SYSCON_CLK20_OEN (BIT(0)) 125 #define SYSCON_CLK20_OEN_M (BIT(0)) 126 #define SYSCON_CLK20_OEN_V 0x1 127 #define SYSCON_CLK20_OEN_S 0 128 129 #define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xC) 130 /* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 131 /*description: .*/ 132 #define SYSCON_WIFI_BB_CFG 0xFFFFFFFF 133 #define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S)) 134 #define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF 135 #define SYSCON_WIFI_BB_CFG_S 0 136 137 #define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10) 138 /* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 139 /*description: .*/ 140 #define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF 141 #define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S)) 142 #define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF 143 #define SYSCON_WIFI_BB_CFG_2_S 0 144 145 #define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x14) 146 /* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 147 /*description: .*/ 148 #define SYSCON_WIFI_CLK_EN 0xFFFFFFFF 149 #define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S)) 150 #define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF 151 #define SYSCON_WIFI_CLK_EN_S 0 152 153 #define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x18) 154 /* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 155 /*description: .*/ 156 #define SYSCON_WIFI_RST 0xFFFFFFFF 157 #define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S)) 158 #define SYSCON_WIFI_RST_V 0xFFFFFFFF 159 #define SYSCON_WIFI_RST_S 0 160 161 #define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG 162 /* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 163 /*description: */ 164 #define SYSTEM_WIFI_CLK_EN 0x00FB9FCF 165 #define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V) << (SYSTEM_WIFI_CLK_EN_S)) 166 #define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF 167 #define SYSTEM_WIFI_CLK_EN_S 0 168 169 /* Mask for all Wifi clock bits, 6 */ 170 #define SYSTEM_WIFI_CLK_WIFI_EN 0x0 171 #define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S)) 172 #define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0 173 #define SYSTEM_WIFI_CLK_WIFI_EN_S 0 174 /* Mask for all Bluetooth clock bits, 11, 16, 17 */ 175 #define SYSTEM_WIFI_CLK_BT_EN 0x0 176 #define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S)) 177 #define SYSTEM_WIFI_CLK_BT_EN_V 0x0 178 #define SYSTEM_WIFI_CLK_BT_EN_S 0 179 /* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */ 180 #define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F 181 182 //bluetooth baseband bit11 183 #define SYSTEM_BT_BASEBAND_EN BIT(11) 184 //bluetooth LC bit16 and bit17 185 #define SYSTEM_BT_LC_EN (BIT(16) | BIT(17)) 186 187 /* Remaining single bit clock masks */ 188 #define SYSTEM_WIFI_CLK_I2C_CLK_EN BIT(5) 189 #define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12) 190 #define SYSTEM_WIFI_CLK_SDIO_HOST_EN BIT(13) 191 #define SYSTEM_WIFI_CLK_EMAC_EN BIT(14) 192 #define SYSTEM_WIFI_CLK_RNG_EN BIT(15) 193 194 #define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG 195 #define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG 196 /* SYSTEM_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 197 /*description: */ 198 #define SYSTEM_WIFI_RST 0xFFFFFFFF 199 #define SYSTEM_WIFI_RST_M ((SYSTEM_WIFI_RST_V) << (SYSTEM_WIFI_RST_S)) 200 #define SYSTEM_WIFI_RST_V 0xFFFFFFFF 201 #define SYSTEM_WIFI_RST_S 0 202 203 #define SYSTEM_WIFIBB_RST BIT(0) 204 #define SYSTEM_FE_RST BIT(1) 205 #define SYSTEM_WIFIMAC_RST BIT(2) 206 #define SYSTEM_BTBB_RST BIT(3) /* Bluetooth Baseband */ 207 #define SYSTEM_BTMAC_RST BIT(4) /* deprecated */ 208 #define SYSTEM_SDIO_RST BIT(5) 209 #define SYSTEM_EMAC_RST BIT(7) 210 #define SYSTEM_MACPWR_RST BIT(8) 211 #define SYSTEM_RW_BTMAC_RST BIT(9) /* Bluetooth MAC */ 212 #define SYSTEM_RW_BTLP_RST BIT(10) /* Bluetooth Low Power Module */ 213 #define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Regsiters */ 214 #define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */ 215 #define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */ 216 217 #define MODEM_RESET_FIELD_WHEN_PU (SYSTEM_WIFIBB_RST | \ 218 SYSTEM_FE_RST | \ 219 SYSTEM_WIFIMAC_RST | \ 220 SYSTEM_BTBB_RST | \ 221 SYSTEM_BTMAC_RST | \ 222 SYSTEM_RW_BTMAC_RST | \ 223 SYSTEM_RW_BTMAC_REG_RST | \ 224 SYSTEM_BTBB_REG_RST) 225 226 #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C) 227 /* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 228 /*description: .*/ 229 #define SYSCON_PERI_IO_SWAP 0x000000FF 230 #define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S)) 231 #define SYSCON_PERI_IO_SWAP_V 0xFF 232 #define SYSCON_PERI_IO_SWAP_S 0 233 234 #define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20) 235 /* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 236 /*description: .*/ 237 #define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) 238 #define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0)) 239 #define SYSCON_EXT_MEM_PMS_LOCK_V 0x1 240 #define SYSCON_EXT_MEM_PMS_LOCK_S 0 241 242 #define SYSCON_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_SYSCON_BASE + 0x24) 243 /* SYSCON_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ 244 /*description: Set 1 to bypass cache writeback request to external memory so that spi will not 245 check its attribute..*/ 246 #define SYSCON_WRITEBACK_BYPASS (BIT(0)) 247 #define SYSCON_WRITEBACK_BYPASS_M (BIT(0)) 248 #define SYSCON_WRITEBACK_BYPASS_V 0x1 249 #define SYSCON_WRITEBACK_BYPASS_S 0 250 251 #define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x28) 252 /* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 253 /*description: .*/ 254 #define SYSCON_FLASH_ACE0_ATTR 0x000001FF 255 #define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S)) 256 #define SYSCON_FLASH_ACE0_ATTR_V 0x1FF 257 #define SYSCON_FLASH_ACE0_ATTR_S 0 258 259 #define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2C) 260 /* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 261 /*description: .*/ 262 #define SYSCON_FLASH_ACE1_ATTR 0x000001FF 263 #define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S)) 264 #define SYSCON_FLASH_ACE1_ATTR_V 0x1FF 265 #define SYSCON_FLASH_ACE1_ATTR_S 0 266 267 #define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30) 268 /* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 269 /*description: .*/ 270 #define SYSCON_FLASH_ACE2_ATTR 0x000001FF 271 #define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S)) 272 #define SYSCON_FLASH_ACE2_ATTR_V 0x1FF 273 #define SYSCON_FLASH_ACE2_ATTR_S 0 274 275 #define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x34) 276 /* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 277 /*description: .*/ 278 #define SYSCON_FLASH_ACE3_ATTR 0x000001FF 279 #define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S)) 280 #define SYSCON_FLASH_ACE3_ATTR_V 0x1FF 281 #define SYSCON_FLASH_ACE3_ATTR_S 0 282 283 #define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38) 284 /* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 285 /*description: .*/ 286 #define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF 287 #define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S)) 288 #define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF 289 #define SYSCON_FLASH_ACE0_ADDR_S_S 0 290 291 #define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3C) 292 /* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ 293 /*description: .*/ 294 #define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF 295 #define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S)) 296 #define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF 297 #define SYSCON_FLASH_ACE1_ADDR_S_S 0 298 299 #define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x40) 300 /* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ 301 /*description: .*/ 302 #define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF 303 #define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S)) 304 #define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF 305 #define SYSCON_FLASH_ACE2_ADDR_S_S 0 306 307 #define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44) 308 /* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ 309 /*description: .*/ 310 #define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF 311 #define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S)) 312 #define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF 313 #define SYSCON_FLASH_ACE3_ADDR_S_S 0 314 315 #define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48) 316 /* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 317 /*description: .*/ 318 #define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF 319 #define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S)) 320 #define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF 321 #define SYSCON_FLASH_ACE0_SIZE_S 0 322 323 #define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x4C) 324 /* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 325 /*description: .*/ 326 #define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF 327 #define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S)) 328 #define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF 329 #define SYSCON_FLASH_ACE1_SIZE_S 0 330 331 #define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50) 332 /* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 333 /*description: .*/ 334 #define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF 335 #define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S)) 336 #define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF 337 #define SYSCON_FLASH_ACE2_SIZE_S 0 338 339 #define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54) 340 /* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 341 /*description: .*/ 342 #define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF 343 #define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S)) 344 #define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF 345 #define SYSCON_FLASH_ACE3_SIZE_S 0 346 347 #define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x58) 348 /* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 349 /*description: .*/ 350 #define SYSCON_SRAM_ACE0_ATTR 0x000001FF 351 #define SYSCON_SRAM_ACE0_ATTR_M ((SYSCON_SRAM_ACE0_ATTR_V)<<(SYSCON_SRAM_ACE0_ATTR_S)) 352 #define SYSCON_SRAM_ACE0_ATTR_V 0x1FF 353 #define SYSCON_SRAM_ACE0_ATTR_S 0 354 355 #define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x5C) 356 /* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 357 /*description: .*/ 358 #define SYSCON_SRAM_ACE1_ATTR 0x000001FF 359 #define SYSCON_SRAM_ACE1_ATTR_M ((SYSCON_SRAM_ACE1_ATTR_V)<<(SYSCON_SRAM_ACE1_ATTR_S)) 360 #define SYSCON_SRAM_ACE1_ATTR_V 0x1FF 361 #define SYSCON_SRAM_ACE1_ATTR_S 0 362 363 #define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x60) 364 /* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 365 /*description: .*/ 366 #define SYSCON_SRAM_ACE2_ATTR 0x000001FF 367 #define SYSCON_SRAM_ACE2_ATTR_M ((SYSCON_SRAM_ACE2_ATTR_V)<<(SYSCON_SRAM_ACE2_ATTR_S)) 368 #define SYSCON_SRAM_ACE2_ATTR_V 0x1FF 369 #define SYSCON_SRAM_ACE2_ATTR_S 0 370 371 #define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x64) 372 /* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 373 /*description: .*/ 374 #define SYSCON_SRAM_ACE3_ATTR 0x000001FF 375 #define SYSCON_SRAM_ACE3_ATTR_M ((SYSCON_SRAM_ACE3_ATTR_V)<<(SYSCON_SRAM_ACE3_ATTR_S)) 376 #define SYSCON_SRAM_ACE3_ATTR_V 0x1FF 377 #define SYSCON_SRAM_ACE3_ATTR_S 0 378 379 #define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x68) 380 /* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 381 /*description: .*/ 382 #define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF 383 #define SYSCON_SRAM_ACE0_ADDR_S_M ((SYSCON_SRAM_ACE0_ADDR_S_V)<<(SYSCON_SRAM_ACE0_ADDR_S_S)) 384 #define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF 385 #define SYSCON_SRAM_ACE0_ADDR_S_S 0 386 387 #define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x6C) 388 /* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ 389 /*description: .*/ 390 #define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF 391 #define SYSCON_SRAM_ACE1_ADDR_S_M ((SYSCON_SRAM_ACE1_ADDR_S_V)<<(SYSCON_SRAM_ACE1_ADDR_S_S)) 392 #define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF 393 #define SYSCON_SRAM_ACE1_ADDR_S_S 0 394 395 #define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x70) 396 /* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ 397 /*description: .*/ 398 #define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF 399 #define SYSCON_SRAM_ACE2_ADDR_S_M ((SYSCON_SRAM_ACE2_ADDR_S_V)<<(SYSCON_SRAM_ACE2_ADDR_S_S)) 400 #define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF 401 #define SYSCON_SRAM_ACE2_ADDR_S_S 0 402 403 #define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x74) 404 /* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ 405 /*description: .*/ 406 #define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF 407 #define SYSCON_SRAM_ACE3_ADDR_S_M ((SYSCON_SRAM_ACE3_ADDR_S_V)<<(SYSCON_SRAM_ACE3_ADDR_S_S)) 408 #define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF 409 #define SYSCON_SRAM_ACE3_ADDR_S_S 0 410 411 #define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x78) 412 /* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 413 /*description: .*/ 414 #define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF 415 #define SYSCON_SRAM_ACE0_SIZE_M ((SYSCON_SRAM_ACE0_SIZE_V)<<(SYSCON_SRAM_ACE0_SIZE_S)) 416 #define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF 417 #define SYSCON_SRAM_ACE0_SIZE_S 0 418 419 #define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x7C) 420 /* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 421 /*description: .*/ 422 #define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF 423 #define SYSCON_SRAM_ACE1_SIZE_M ((SYSCON_SRAM_ACE1_SIZE_V)<<(SYSCON_SRAM_ACE1_SIZE_S)) 424 #define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF 425 #define SYSCON_SRAM_ACE1_SIZE_S 0 426 427 #define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x80) 428 /* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 429 /*description: .*/ 430 #define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF 431 #define SYSCON_SRAM_ACE2_SIZE_M ((SYSCON_SRAM_ACE2_SIZE_V)<<(SYSCON_SRAM_ACE2_SIZE_S)) 432 #define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF 433 #define SYSCON_SRAM_ACE2_SIZE_S 0 434 435 #define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x84) 436 /* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 437 /*description: .*/ 438 #define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF 439 #define SYSCON_SRAM_ACE3_SIZE_M ((SYSCON_SRAM_ACE3_SIZE_V)<<(SYSCON_SRAM_ACE3_SIZE_S)) 440 #define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF 441 #define SYSCON_SRAM_ACE3_SIZE_S 0 442 443 #define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x88) 444 /* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ 445 /*description: .*/ 446 #define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F 447 #define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S)) 448 #define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F 449 #define SYSCON_SPI_MEM_REJECT_CDE_S 2 450 /* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 451 /*description: .*/ 452 #define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) 453 #define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1)) 454 #define SYSCON_SPI_MEM_REJECT_CLR_V 0x1 455 #define SYSCON_SPI_MEM_REJECT_CLR_S 1 456 /* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ 457 /*description: .*/ 458 #define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) 459 #define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0)) 460 #define SYSCON_SPI_MEM_REJECT_INT_V 0x1 461 #define SYSCON_SPI_MEM_REJECT_INT_S 0 462 463 #define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x8C) 464 /* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 465 /*description: .*/ 466 #define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF 467 #define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S)) 468 #define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF 469 #define SYSCON_SPI_MEM_REJECT_ADDR_S 0 470 471 #define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x90) 472 /* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 473 /*description: .*/ 474 #define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) 475 #define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0)) 476 #define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1 477 #define SYSCON_SDIO_WIN_ACCESS_EN_S 0 478 479 #define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94) 480 /* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ 481 /*description: .*/ 482 #define SYSCON_REDCY_ANDOR (BIT(31)) 483 #define SYSCON_REDCY_ANDOR_M (BIT(31)) 484 #define SYSCON_REDCY_ANDOR_V 0x1 485 #define SYSCON_REDCY_ANDOR_S 31 486 /* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ 487 /*description: .*/ 488 #define SYSCON_REDCY_SIG0 0x7FFFFFFF 489 #define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S)) 490 #define SYSCON_REDCY_SIG0_V 0x7FFFFFFF 491 #define SYSCON_REDCY_SIG0_S 0 492 493 #define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x98) 494 /* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ 495 /*description: .*/ 496 #define SYSCON_REDCY_NANDOR (BIT(31)) 497 #define SYSCON_REDCY_NANDOR_M (BIT(31)) 498 #define SYSCON_REDCY_NANDOR_V 0x1 499 #define SYSCON_REDCY_NANDOR_S 31 500 /* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ 501 /*description: .*/ 502 #define SYSCON_REDCY_SIG1 0x7FFFFFFF 503 #define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S)) 504 #define SYSCON_REDCY_SIG1_V 0x7FFFFFFF 505 #define SYSCON_REDCY_SIG1_S 0 506 507 #define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9C) 508 /* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 509 /*description: .*/ 510 #define SYSCON_FREQ_MEM_FORCE_PD (BIT(7)) 511 #define SYSCON_FREQ_MEM_FORCE_PD_M (BIT(7)) 512 #define SYSCON_FREQ_MEM_FORCE_PD_V 0x1 513 #define SYSCON_FREQ_MEM_FORCE_PD_S 7 514 /* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */ 515 /*description: .*/ 516 #define SYSCON_FREQ_MEM_FORCE_PU (BIT(6)) 517 #define SYSCON_FREQ_MEM_FORCE_PU_M (BIT(6)) 518 #define SYSCON_FREQ_MEM_FORCE_PU_V 0x1 519 #define SYSCON_FREQ_MEM_FORCE_PU_S 6 520 /* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ 521 /*description: .*/ 522 #define SYSCON_DC_MEM_FORCE_PD (BIT(5)) 523 #define SYSCON_DC_MEM_FORCE_PD_M (BIT(5)) 524 #define SYSCON_DC_MEM_FORCE_PD_V 0x1 525 #define SYSCON_DC_MEM_FORCE_PD_S 5 526 /* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ 527 /*description: .*/ 528 #define SYSCON_DC_MEM_FORCE_PU (BIT(4)) 529 #define SYSCON_DC_MEM_FORCE_PU_M (BIT(4)) 530 #define SYSCON_DC_MEM_FORCE_PU_V 0x1 531 #define SYSCON_DC_MEM_FORCE_PU_S 4 532 /* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 533 /*description: .*/ 534 #define SYSCON_PBUS_MEM_FORCE_PD (BIT(3)) 535 #define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3)) 536 #define SYSCON_PBUS_MEM_FORCE_PD_V 0x1 537 #define SYSCON_PBUS_MEM_FORCE_PD_S 3 538 /* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 539 /*description: .*/ 540 #define SYSCON_PBUS_MEM_FORCE_PU (BIT(2)) 541 #define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2)) 542 #define SYSCON_PBUS_MEM_FORCE_PU_V 0x1 543 #define SYSCON_PBUS_MEM_FORCE_PU_S 2 544 /* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 545 /*description: .*/ 546 #define SYSCON_AGC_MEM_FORCE_PD (BIT(1)) 547 #define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1)) 548 #define SYSCON_AGC_MEM_FORCE_PD_V 0x1 549 #define SYSCON_AGC_MEM_FORCE_PD_S 1 550 /* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ 551 /*description: .*/ 552 #define SYSCON_AGC_MEM_FORCE_PU (BIT(0)) 553 #define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0)) 554 #define SYSCON_AGC_MEM_FORCE_PU_V 0x1 555 #define SYSCON_AGC_MEM_FORCE_PU_S 0 556 557 #define SYSCON_SPI_MEM_ECC_CTRL_REG (DR_REG_SYSCON_BASE + 0xA0) 558 /* SYSCON_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */ 559 /*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 560 1024 bytes. 3: 2048 bytes..*/ 561 #define SYSCON_SRAM_PAGE_SIZE 0x00000003 562 #define SYSCON_SRAM_PAGE_SIZE_M ((SYSCON_SRAM_PAGE_SIZE_V)<<(SYSCON_SRAM_PAGE_SIZE_S)) 563 #define SYSCON_SRAM_PAGE_SIZE_V 0x3 564 #define SYSCON_SRAM_PAGE_SIZE_S 20 565 /* SYSCON_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ 566 /*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 by 567 tes. 3: 2048 bytes..*/ 568 #define SYSCON_FLASH_PAGE_SIZE 0x00000003 569 #define SYSCON_FLASH_PAGE_SIZE_M ((SYSCON_FLASH_PAGE_SIZE_V)<<(SYSCON_FLASH_PAGE_SIZE_S)) 570 #define SYSCON_FLASH_PAGE_SIZE_V 0x3 571 #define SYSCON_FLASH_PAGE_SIZE_S 18 572 573 #define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0xA8) 574 /* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */ 575 /*description: .*/ 576 #define SYSCON_SRAM_CLKGATE_FORCE_ON 0x000007FF 577 #define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S)) 578 #define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0x7FF 579 #define SYSCON_SRAM_CLKGATE_FORCE_ON_S 3 580 /* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ 581 /*description: .*/ 582 #define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000007 583 #define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S)) 584 #define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x7 585 #define SYSCON_ROM_CLKGATE_FORCE_ON_S 0 586 587 #define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xAC) 588 /* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */ 589 /*description: .*/ 590 #define SYSCON_SRAM_POWER_DOWN 0x000007FF 591 #define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S)) 592 #define SYSCON_SRAM_POWER_DOWN_V 0x7FF 593 #define SYSCON_SRAM_POWER_DOWN_S 3 594 /* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ 595 /*description: .*/ 596 #define SYSCON_ROM_POWER_DOWN 0x00000007 597 #define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S)) 598 #define SYSCON_ROM_POWER_DOWN_V 0x7 599 #define SYSCON_ROM_POWER_DOWN_S 0 600 601 #define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xB0) 602 /* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */ 603 /*description: .*/ 604 #define SYSCON_SRAM_POWER_UP 0x000007FF 605 #define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S)) 606 #define SYSCON_SRAM_POWER_UP_V 0x7FF 607 #define SYSCON_SRAM_POWER_UP_S 3 608 /* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ 609 /*description: .*/ 610 #define SYSCON_ROM_POWER_UP 0x00000007 611 #define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S)) 612 #define SYSCON_ROM_POWER_UP_V 0x7 613 #define SYSCON_ROM_POWER_UP_S 0 614 615 #define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xB4) 616 /* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ 617 /*description: .*/ 618 #define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27)) 619 #define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27)) 620 #define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1 621 #define SYSCON_NOBYPASS_CPU_ISO_RST_S 27 622 /* SYSCON_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ 623 /*description: .*/ 624 #define SYSCON_RETENTION_CPU_LINK_ADDR 0x07FFFFFF 625 #define SYSCON_RETENTION_CPU_LINK_ADDR_M ((SYSCON_RETENTION_CPU_LINK_ADDR_V)<<(SYSCON_RETENTION_CPU_LINK_ADDR_S)) 626 #define SYSCON_RETENTION_CPU_LINK_ADDR_V 0x7FFFFFF 627 #define SYSCON_RETENTION_CPU_LINK_ADDR_S 0 628 629 #define SYSCON_RETENTION_CTRL1_REG (DR_REG_SYSCON_BASE + 0xB8) 630 /* SYSCON_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ 631 /*description: .*/ 632 #define SYSCON_RETENTION_TAG_LINK_ADDR 0x07FFFFFF 633 #define SYSCON_RETENTION_TAG_LINK_ADDR_M ((SYSCON_RETENTION_TAG_LINK_ADDR_V)<<(SYSCON_RETENTION_TAG_LINK_ADDR_S)) 634 #define SYSCON_RETENTION_TAG_LINK_ADDR_V 0x7FFFFFF 635 #define SYSCON_RETENTION_TAG_LINK_ADDR_S 0 636 637 #define SYSCON_RETENTION_CTRL2_REG (DR_REG_SYSCON_BASE + 0xBC) 638 /* SYSCON_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 639 /*description: .*/ 640 #define SYSCON_RET_ICACHE_ENABLE (BIT(31)) 641 #define SYSCON_RET_ICACHE_ENABLE_M (BIT(31)) 642 #define SYSCON_RET_ICACHE_ENABLE_V 0x1 643 #define SYSCON_RET_ICACHE_ENABLE_S 31 644 /* SYSCON_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */ 645 /*description: .*/ 646 #define SYSCON_RET_ICACHE_START_POINT 0x000000FF 647 #define SYSCON_RET_ICACHE_START_POINT_M ((SYSCON_RET_ICACHE_START_POINT_V)<<(SYSCON_RET_ICACHE_START_POINT_S)) 648 #define SYSCON_RET_ICACHE_START_POINT_V 0xFF 649 #define SYSCON_RET_ICACHE_START_POINT_S 22 650 /* SYSCON_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */ 651 /*description: .*/ 652 #define SYSCON_RET_ICACHE_VLD_SIZE 0x000000FF 653 #define SYSCON_RET_ICACHE_VLD_SIZE_M ((SYSCON_RET_ICACHE_VLD_SIZE_V)<<(SYSCON_RET_ICACHE_VLD_SIZE_S)) 654 #define SYSCON_RET_ICACHE_VLD_SIZE_V 0xFF 655 #define SYSCON_RET_ICACHE_VLD_SIZE_S 13 656 /* SYSCON_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */ 657 /*description: .*/ 658 #define SYSCON_RET_ICACHE_SIZE 0x000000FF 659 #define SYSCON_RET_ICACHE_SIZE_M ((SYSCON_RET_ICACHE_SIZE_V)<<(SYSCON_RET_ICACHE_SIZE_S)) 660 #define SYSCON_RET_ICACHE_SIZE_V 0xFF 661 #define SYSCON_RET_ICACHE_SIZE_S 4 662 663 #define SYSCON_RETENTION_CTRL3_REG (DR_REG_SYSCON_BASE + 0xC0) 664 /* SYSCON_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 665 /*description: .*/ 666 #define SYSCON_RET_DCACHE_ENABLE (BIT(31)) 667 #define SYSCON_RET_DCACHE_ENABLE_M (BIT(31)) 668 #define SYSCON_RET_DCACHE_ENABLE_V 0x1 669 #define SYSCON_RET_DCACHE_ENABLE_S 31 670 /* SYSCON_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */ 671 /*description: .*/ 672 #define SYSCON_RET_DCACHE_START_POINT 0x000001FF 673 #define SYSCON_RET_DCACHE_START_POINT_M ((SYSCON_RET_DCACHE_START_POINT_V)<<(SYSCON_RET_DCACHE_START_POINT_S)) 674 #define SYSCON_RET_DCACHE_START_POINT_V 0x1FF 675 #define SYSCON_RET_DCACHE_START_POINT_S 22 676 /* SYSCON_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */ 677 /*description: .*/ 678 #define SYSCON_RET_DCACHE_VLD_SIZE 0x000001FF 679 #define SYSCON_RET_DCACHE_VLD_SIZE_M ((SYSCON_RET_DCACHE_VLD_SIZE_V)<<(SYSCON_RET_DCACHE_VLD_SIZE_S)) 680 #define SYSCON_RET_DCACHE_VLD_SIZE_V 0x1FF 681 #define SYSCON_RET_DCACHE_VLD_SIZE_S 13 682 /* SYSCON_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */ 683 /*description: .*/ 684 #define SYSCON_RET_DCACHE_SIZE 0x000001FF 685 #define SYSCON_RET_DCACHE_SIZE_M ((SYSCON_RET_DCACHE_SIZE_V)<<(SYSCON_RET_DCACHE_SIZE_S)) 686 #define SYSCON_RET_DCACHE_SIZE_V 0x1FF 687 #define SYSCON_RET_DCACHE_SIZE_S 4 688 689 #define SYSCON_RETENTION_CTRL4_REG (DR_REG_SYSCON_BASE + 0xC4) 690 /* SYSCON_RETENTION_INV_CFG : R/W ;bitpos:[31:0] ;default: ~32'h0 ; */ 691 /*description: .*/ 692 #define SYSCON_RETENTION_INV_CFG 0xFFFFFFFF 693 #define SYSCON_RETENTION_INV_CFG_M ((SYSCON_RETENTION_INV_CFG_V)<<(SYSCON_RETENTION_INV_CFG_S)) 694 #define SYSCON_RETENTION_INV_CFG_V 0xFFFFFFFF 695 #define SYSCON_RETENTION_INV_CFG_S 0 696 697 #define SYSCON_RETENTION_CTRL5_REG (DR_REG_SYSCON_BASE + 0xC8) 698 /* SYSCON_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 699 /*description: .*/ 700 #define SYSCON_RETENTION_DISABLE (BIT(0)) 701 #define SYSCON_RETENTION_DISABLE_M (BIT(0)) 702 #define SYSCON_RETENTION_DISABLE_V 0x1 703 #define SYSCON_RETENTION_DISABLE_S 0 704 705 #define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) 706 /* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */ 707 /*description: Version control.*/ 708 #define SYSCON_DATE 0xFFFFFFFF 709 #define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S)) 710 #define SYSCON_DATE_V 0xFFFFFFFF 711 #define SYSCON_DATE_S 0 712 713 714 #ifdef __cplusplus 715 } 716 #endif 717 718 719 720 #endif /*_SOC_SYSCON_REG_H_ */ 721
