1 /* 2 * Copyright 2021-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CLOCK_IP_TYPES_H 8 #define CLOCK_IP_TYPES_H 9 10 /** 11 * @file Clock_Ip_Types.h 12 * @version 1.0.0 13 * 14 * @brief CLOCK IP type header file. 15 * @details CLOCK IP type header file. 16 17 * @addtogroup CLOCK_DRIVER Clock Ip Driver 18 * @{ 19 */ 20 21 #if defined(__cplusplus) 22 extern "C"{ 23 #endif 24 /*================================================================================================== 25 * INCLUDE FILES 26 * 1) system and project includes 27 * 2) needed interfaces from external units 28 * 3) internal and external interfaces from this unit 29 ==================================================================================================*/ 30 #include "StandardTypes.h" 31 #include "Clock_Ip_Cfg_Defines.h" 32 #include "Mcal.h" 33 /*================================================================================================== 34 SOURCE FILE VERSION INFORMATION 35 ==================================================================================================*/ 36 #define CLOCK_IP_TYPES_VENDOR_ID 43 37 #define CLOCK_IP_TYPES_AR_RELEASE_MAJOR_VERSION 4 38 #define CLOCK_IP_TYPES_AR_RELEASE_MINOR_VERSION 7 39 #define CLOCK_IP_TYPES_AR_RELEASE_REVISION_VERSION 0 40 #define CLOCK_IP_TYPES_SW_MAJOR_VERSION 1 41 #define CLOCK_IP_TYPES_SW_MINOR_VERSION 0 42 #define CLOCK_IP_TYPES_SW_PATCH_VERSION 0 43 44 /*================================================================================================== 45 FILE VERSION CHECKS 46 ==================================================================================================*/ 47 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 48 /* Check if Clock_Ip_Types.h file and StandardTypes.h file are of the same Autosar version */ 49 #if ((CLOCK_IP_TYPES_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \ 50 (CLOCK_IP_TYPES_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION)) 51 #error "AutoSar Version Numbers of Clock_Ip_Types.h and StandardTypes.h are different" 52 #endif 53 #endif 54 55 /* Check if Clock_Ip_Types.h file and Clock_Ip_Cfg_Defines.h file have same versions */ 56 #if (CLOCK_IP_TYPES_VENDOR_ID != CLOCK_IP_CFG_DEFINES_VENDOR_ID) 57 #error "Clock_Ip_Types.h and Clock_Ip_Cfg_Defines.h have different vendor IDs" 58 #endif 59 60 /* Check if Clock_Ip_Types.h file and Clock_Ip_Cfg_Defines.h file are of the same Autosar version */ 61 #if ((CLOCK_IP_TYPES_AR_RELEASE_MAJOR_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ 62 (CLOCK_IP_TYPES_AR_RELEASE_MINOR_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ 63 (CLOCK_IP_TYPES_AR_RELEASE_REVISION_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION)) 64 #error "AutoSar Version Numbers of Clock_Ip_Types.h and Clock_Ip_Cfg_Defines.h are different" 65 #endif 66 67 /* Check if Clock_Ip_Types.h file and Clock_Ip_Cfg_Defines.h file are of the same Software version */ 68 #if ((CLOCK_IP_TYPES_SW_MAJOR_VERSION != CLOCK_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ 69 (CLOCK_IP_TYPES_SW_MINOR_VERSION != CLOCK_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ 70 (CLOCK_IP_TYPES_SW_PATCH_VERSION != CLOCK_IP_CFG_DEFINES_SW_PATCH_VERSION)) 71 #error "Software Version Numbers of Clock_Ip_Types.h and Clock_Ip_Cfg_Defines.h are different" 72 #endif 73 74 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 75 /* Check if Clock_Ip_Types.h file and Mcal.h file are of the same Autosar version */ 76 #if ((CLOCK_IP_TYPES_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \ 77 (CLOCK_IP_TYPES_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION)) 78 #error "AutoSar Version Numbers of Clock_Ip_Types.h and Mcal.h are different" 79 #endif 80 #endif 81 /*================================================================================================== 82 * CONSTANTS 83 ==================================================================================================*/ 84 85 /*================================================================================================== 86 * DEFINES AND MACROS 87 ==================================================================================================*/ 88 89 /*================================================================================================== 90 * ENUMS 91 ==================================================================================================*/ 92 #if (defined(CLOCK_IP_POWER_NOTIFICATIONS)) 93 /** @brief Power modes. */ 94 typedef enum { 95 96 #if defined(CLOCK_IP_HAS_RUN_MODE) 97 RUN_MODE = CLOCK_IP_HAS_RUN_MODE, 98 VLPR_MODE = 1U, 99 VLPS_MODE = 2U, 100 HSRUN_MODE = 3U, 101 #endif 102 } Clock_Ip_PowerModesType; 103 104 /** @brief Power mode notification. */ 105 typedef enum { 106 107 BEFORE_POWER_MODE_CHANGE, /* Before power mode change command is sent */ 108 POWER_MODE_CHANGE_IN_PROGRESS, /* Power mode transition is in progress */ 109 POWER_MODE_CHANGED, /* Power mode transition completed */ 110 111 } Clock_Ip_PowerNotificationType; 112 #endif 113 114 /** @brief Clock names. */ 115 typedef enum { 116 117 CLOCK_IS_OFF = 0U, 118 119 #if defined(CLOCK_IP_HAS_FIRC_CLK) 120 FIRC_CLK = CLOCK_IP_HAS_FIRC_CLK, 121 #endif 122 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 123 FIRC_AE_CLK = CLOCK_IP_HAS_FIRC_AE_CLK, 124 #endif 125 #if defined(CLOCK_IP_HAS_FIRC_MUXED_CLK) 126 FIRC_MUXED_CLK = CLOCK_IP_HAS_FIRC_MUXED_CLK, 127 #endif 128 #if defined(CLOCK_IP_HAS_FIRC_VLP_CLK) 129 FIRC_VLP_CLK = CLOCK_IP_HAS_FIRC_VLP_CLK, 130 #endif 131 #if defined(CLOCK_IP_HAS_FIRC_STOP_CLK) 132 FIRC_STOP_CLK = CLOCK_IP_HAS_FIRC_STOP_CLK, 133 #endif 134 #if defined(CLOCK_IP_HAS_FIRC_STANDBY_CLK) 135 FIRC_STANDBY_CLK = CLOCK_IP_HAS_FIRC_STANDBY_CLK, 136 #endif 137 #if defined(CLOCK_IP_HAS_FIRC_POSTDIV_CLK) 138 FIRC_POSTDIV_CLK = CLOCK_IP_HAS_FIRC_POSTDIV_CLK, 139 #endif 140 #if defined(CLOCK_IP_HAS_FRO_CLK) 141 FRO_CLK = CLOCK_IP_HAS_FRO_CLK, 142 #endif 143 #if defined(CLOCK_IP_HAS_SAFE_CLK) 144 SAFE_CLK = CLOCK_IP_HAS_SAFE_CLK, 145 #endif 146 #if defined(CLOCK_IP_HAS_SIRC_CLK) 147 SIRC_CLK = CLOCK_IP_HAS_SIRC_CLK, 148 #endif 149 #if defined(CLOCK_IP_HAS_SIRC_VLP_CLK) 150 SIRC_VLP_CLK = CLOCK_IP_HAS_SIRC_VLP_CLK, 151 #endif 152 #if defined(CLOCK_IP_HAS_SIRC_STOP_CLK) 153 SIRC_STOP_CLK = CLOCK_IP_HAS_SIRC_STOP_CLK, 154 #endif 155 #if defined(CLOCK_IP_HAS_SIRC_STANDBY_CLK) 156 SIRC_STANDBY_CLK = CLOCK_IP_HAS_SIRC_STANDBY_CLK, 157 #endif 158 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 159 SYSTEM_CLK = CLOCK_IP_HAS_SYSTEM_CLK, 160 #endif 161 #if defined(CLOCK_IP_HAS_LPO_128K_CLK) 162 LPO_128K_CLK = CLOCK_IP_HAS_LPO_128K_CLK, 163 #endif 164 #if defined(CLOCK_IP_HAS_FXOSC_CLK) 165 FXOSC_CLK = CLOCK_IP_HAS_FXOSC_CLK, 166 #endif 167 #if defined(CLOCK_IP_HAS_SXOSC_CLK) 168 SXOSC_CLK = CLOCK_IP_HAS_SXOSC_CLK, 169 #endif 170 #if defined(CLOCK_IP_HAS_SOSC_CLK) 171 SOSC_CLK = CLOCK_IP_HAS_SOSC_CLK, 172 #endif 173 #if defined(CLOCK_IP_HAS_ACCELPLL_CLK) 174 ACCELPLL_CLK = CLOCK_IP_HAS_ACCELPLL_CLK, 175 #endif 176 #if defined(CLOCK_IP_HAS_COREPLL_CLK) 177 COREPLL_CLK = CLOCK_IP_HAS_COREPLL_CLK, 178 #endif 179 #if defined(CLOCK_IP_HAS_DDRPLL_CLK) 180 DDRPLL_CLK = CLOCK_IP_HAS_DDRPLL_CLK, 181 #endif 182 #if defined(CLOCK_IP_HAS_PERIPHPLL_CLK) 183 PERIPHPLL_CLK = CLOCK_IP_HAS_PERIPHPLL_CLK, 184 #endif 185 #if defined(CLOCK_IP_HAS_LFAST0_PLL_CLK) 186 LFAST0_PLL_CLK = CLOCK_IP_HAS_LFAST0_PLL_CLK, 187 #endif 188 #if defined(CLOCK_IP_HAS_LFAST1_PLL_CLK) 189 LFAST1_PLL_CLK = CLOCK_IP_HAS_LFAST1_PLL_CLK, 190 #endif 191 #if defined(CLOCK_IP_HAS_PLL_CLK) 192 PLL_CLK = CLOCK_IP_HAS_PLL_CLK, 193 #endif 194 #if defined(CLOCK_IP_HAS_PLL0_CLK) 195 PLL0_CLK = CLOCK_IP_HAS_PLL0_CLK, 196 #endif 197 #if defined(CLOCK_IP_HAS_PLL1_CLK) 198 PLL1_CLK = CLOCK_IP_HAS_PLL1_CLK, 199 #endif 200 #if defined(CLOCK_IP_HAS_PLLAUX_CLK) 201 PLLAUX_CLK = CLOCK_IP_HAS_PLLAUX_CLK, 202 #endif 203 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK) 204 PLLAUX_PHI0_CLK = CLOCK_IP_HAS_PLLAUX_PHI0_CLK, 205 #endif 206 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK) 207 PLLAUX_PHI1_CLK = CLOCK_IP_HAS_PLLAUX_PHI1_CLK, 208 #endif 209 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK) 210 PLLAUX_PHI2_CLK = CLOCK_IP_HAS_PLLAUX_PHI2_CLK, 211 #endif 212 #if defined(CLOCK_IP_HAS_SPLL_CLK) 213 SPLL_CLK = CLOCK_IP_HAS_SPLL_CLK, 214 #endif 215 #if defined(CLOCK_IP_HAS_AURORAPLL_CLK) 216 AURORAPLL_CLK = CLOCK_IP_HAS_AURORAPLL_CLK, 217 #endif 218 #if defined(CLOCK_IP_HAS_ACCEL_PLL_PHI0_CLK) 219 ACCEL_PLL_PHI0_CLK = CLOCK_IP_HAS_ACCEL_PLL_PHI0_CLK, 220 #endif 221 #if defined(CLOCK_IP_HAS_ACCEL_PLL_PHI1_CLK) 222 ACCEL_PLL_PHI1_CLK = CLOCK_IP_HAS_ACCEL_PLL_PHI1_CLK, 223 #endif 224 #if defined(CLOCK_IP_HAS_CORE_PLL_PHI0_CLK) 225 CORE_PLL_PHI0_CLK = CLOCK_IP_HAS_CORE_PLL_PHI0_CLK, 226 #endif 227 #if defined(CLOCK_IP_HAS_CORE_PLL_PHI1_CLK) 228 CORE_PLL_PHI1_CLK = CLOCK_IP_HAS_CORE_PLL_PHI1_CLK, 229 #endif 230 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS0_CLK) 231 CORE_PLL_DFS0_CLK = CLOCK_IP_HAS_CORE_PLL_DFS0_CLK, 232 #endif 233 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS1_CLK) 234 CORE_PLL_DFS1_CLK = CLOCK_IP_HAS_CORE_PLL_DFS1_CLK, 235 #endif 236 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS2_CLK) 237 CORE_PLL_DFS2_CLK = CLOCK_IP_HAS_CORE_PLL_DFS2_CLK, 238 #endif 239 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS3_CLK) 240 CORE_PLL_DFS3_CLK = CLOCK_IP_HAS_CORE_PLL_DFS3_CLK, 241 #endif 242 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS4_CLK) 243 CORE_PLL_DFS4_CLK = CLOCK_IP_HAS_CORE_PLL_DFS4_CLK, 244 #endif 245 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS5_CLK) 246 CORE_PLL_DFS5_CLK = CLOCK_IP_HAS_CORE_PLL_DFS5_CLK, 247 #endif 248 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS6_CLK) 249 CORE_PLL_DFS6_CLK = CLOCK_IP_HAS_CORE_PLL_DFS6_CLK, 250 #endif 251 #if defined(CLOCK_IP_HAS_DDR_PLL_PHI0_CLK) 252 DDR_PLL_PHI0_CLK = CLOCK_IP_HAS_DDR_PLL_PHI0_CLK, 253 #endif 254 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI0_CLK) 255 PERIPH_PLL_PHI0_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI0_CLK, 256 #endif 257 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI1_CLK) 258 PERIPH_PLL_PHI1_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI1_CLK, 259 #endif 260 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI2_CLK) 261 PERIPH_PLL_PHI2_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI2_CLK, 262 #endif 263 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI3_CLK) 264 PERIPH_PLL_PHI3_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI3_CLK, 265 #endif 266 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI4_CLK) 267 PERIPH_PLL_PHI4_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI4_CLK, 268 #endif 269 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI5_CLK) 270 PERIPH_PLL_PHI5_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI5_CLK, 271 #endif 272 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI6_CLK) 273 PERIPH_PLL_PHI6_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI6_CLK, 274 #endif 275 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI7_CLK) 276 PERIPH_PLL_PHI7_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI7_CLK, 277 #endif 278 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS0_CLK) 279 PERIPH_PLL_DFS0_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS0_CLK, 280 #endif 281 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS1_CLK) 282 PERIPH_PLL_DFS1_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS1_CLK, 283 #endif 284 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS2_CLK) 285 PERIPH_PLL_DFS2_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS2_CLK, 286 #endif 287 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS3_CLK) 288 PERIPH_PLL_DFS3_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS3_CLK, 289 #endif 290 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS4_CLK) 291 PERIPH_PLL_DFS4_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS4_CLK, 292 #endif 293 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS5_CLK) 294 PERIPH_PLL_DFS5_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS5_CLK, 295 #endif 296 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS6_CLK) 297 PERIPH_PLL_DFS6_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS6_CLK, 298 #endif 299 #if defined(CLOCK_IP_HAS_COREPLL_PHI0_CLK) 300 COREPLL_PHI0_CLK = CLOCK_IP_HAS_COREPLL_PHI0_CLK, 301 #endif 302 #if defined(CLOCK_IP_HAS_COREPLL_PHI1_CLK) 303 COREPLL_PHI1_CLK = CLOCK_IP_HAS_COREPLL_PHI1_CLK, 304 #endif 305 #if defined(CLOCK_IP_HAS_COREPLL_PHI2_CLK) 306 COREPLL_PHI2_CLK = CLOCK_IP_HAS_COREPLL_PHI2_CLK, 307 #endif 308 #if defined(CLOCK_IP_HAS_COREPLL_PHI3_CLK) 309 COREPLL_PHI3_CLK = CLOCK_IP_HAS_COREPLL_PHI3_CLK, 310 #endif 311 #if defined(CLOCK_IP_HAS_COREPLL_PHI4_CLK) 312 COREPLL_PHI4_CLK = CLOCK_IP_HAS_COREPLL_PHI4_CLK, 313 #endif 314 #if defined(CLOCK_IP_HAS_COREPLL_PHI5_CLK) 315 COREPLL_PHI5_CLK = CLOCK_IP_HAS_COREPLL_PHI5_CLK, 316 #endif 317 #if defined(CLOCK_IP_HAS_COREPLL_PHI6_CLK) 318 COREPLL_PHI6_CLK = CLOCK_IP_HAS_COREPLL_PHI6_CLK, 319 #endif 320 #if defined(CLOCK_IP_HAS_COREPLL_PHI7_CLK) 321 COREPLL_PHI7_CLK = CLOCK_IP_HAS_COREPLL_PHI7_CLK, 322 #endif 323 #if defined(CLOCK_IP_HAS_COREPLL_PHI8_CLK) 324 COREPLL_PHI8_CLK = CLOCK_IP_HAS_COREPLL_PHI8_CLK, 325 #endif 326 #if defined(CLOCK_IP_HAS_COREPLL_PHI9_CLK) 327 COREPLL_PHI9_CLK = CLOCK_IP_HAS_COREPLL_PHI9_CLK, 328 #endif 329 #if defined(CLOCK_IP_HAS_COREPLL_DFS0_CLK) 330 COREPLL_DFS0_CLK = CLOCK_IP_HAS_COREPLL_DFS0_CLK, 331 #endif 332 #if defined(CLOCK_IP_HAS_COREPLL_DFS1_CLK) 333 COREPLL_DFS1_CLK = CLOCK_IP_HAS_COREPLL_DFS1_CLK, 334 #endif 335 #if defined(CLOCK_IP_HAS_COREPLL_DFS2_CLK) 336 COREPLL_DFS2_CLK = CLOCK_IP_HAS_COREPLL_DFS2_CLK, 337 #endif 338 #if defined(CLOCK_IP_HAS_COREPLL_DFS3_CLK) 339 COREPLL_DFS3_CLK = CLOCK_IP_HAS_COREPLL_DFS3_CLK, 340 #endif 341 #if defined(CLOCK_IP_HAS_COREPLL_DFS4_CLK) 342 COREPLL_DFS4_CLK = CLOCK_IP_HAS_COREPLL_DFS4_CLK, 343 #endif 344 #if defined(CLOCK_IP_HAS_COREPLL_DFS5_CLK) 345 COREPLL_DFS5_CLK = CLOCK_IP_HAS_COREPLL_DFS5_CLK, 346 #endif 347 #if defined(CLOCK_IP_HAS_COREPLL_DFS6_CLK) 348 COREPLL_DFS6_CLK = CLOCK_IP_HAS_COREPLL_DFS6_CLK, 349 #endif 350 #if defined(CLOCK_IP_HAS_DDRPLL_PHI0_CLK) 351 DDRPLL_PHI0_CLK = CLOCK_IP_HAS_DDRPLL_PHI0_CLK, 352 #endif 353 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI0_CLK) 354 PERIPHPLL_PHI0_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI0_CLK, 355 #endif 356 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI1_CLK) 357 PERIPHPLL_PHI1_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI1_CLK, 358 #endif 359 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI2_CLK) 360 PERIPHPLL_PHI2_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI2_CLK, 361 #endif 362 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI3_CLK) 363 PERIPHPLL_PHI3_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI3_CLK, 364 #endif 365 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI4_CLK) 366 PERIPHPLL_PHI4_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI4_CLK, 367 #endif 368 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI5_CLK) 369 PERIPHPLL_PHI5_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI5_CLK, 370 #endif 371 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI6_CLK) 372 PERIPHPLL_PHI6_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI6_CLK, 373 #endif 374 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI7_CLK) 375 PERIPHPLL_PHI7_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI7_CLK, 376 #endif 377 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI8_CLK) 378 PERIPHPLL_PHI8_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI8_CLK, 379 #endif 380 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI9_CLK) 381 PERIPHPLL_PHI9_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI9_CLK, 382 #endif 383 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS0_CLK) 384 PERIPHPLL_DFS0_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS0_CLK, 385 #endif 386 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS1_CLK) 387 PERIPHPLL_DFS1_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS1_CLK, 388 #endif 389 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS2_CLK) 390 PERIPHPLL_DFS2_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS2_CLK, 391 #endif 392 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS3_CLK) 393 PERIPHPLL_DFS3_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS3_CLK, 394 #endif 395 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS4_CLK) 396 PERIPHPLL_DFS4_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS4_CLK, 397 #endif 398 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS5_CLK) 399 PERIPHPLL_DFS5_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS5_CLK, 400 #endif 401 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS6_CLK) 402 PERIPHPLL_DFS6_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS6_CLK, 403 #endif 404 #if defined(CLOCK_IP_HAS_PLL_PHI0_CLK) 405 PLL_PHI0_CLK = CLOCK_IP_HAS_PLL_PHI0_CLK, 406 #endif 407 #if defined(CLOCK_IP_HAS_PLL_PHI1_CLK) 408 PLL_PHI1_CLK = CLOCK_IP_HAS_PLL_PHI1_CLK, 409 #endif 410 #if defined(CLOCK_IP_HAS_AURORAPLL_PHI0_CLK) 411 AURORAPLL_PHI0_CLK = CLOCK_IP_HAS_AURORAPLL_PHI0_CLK, 412 #endif 413 #if defined(CLOCK_IP_HAS_AURORAPLL_PHI1_CLK) 414 AURORAPLL_PHI1_CLK = CLOCK_IP_HAS_AURORAPLL_PHI1_CLK, 415 #endif 416 #if defined(CLOCK_IP_HAS_AURORAPLL_PHI2_CLK) 417 AURORAPLL_PHI2_CLK = CLOCK_IP_HAS_AURORAPLL_PHI2_CLK, 418 #endif 419 #if defined(CLOCK_IP_HAS_LFAST0_PLL_PH0_CLK) 420 LFAST0_PLL_PH0_CLK = CLOCK_IP_HAS_LFAST0_PLL_PH0_CLK, 421 #endif 422 #if defined(CLOCK_IP_HAS_LFAST1_PLL_PH0_CLK) 423 LFAST1_PLL_PH0_CLK = CLOCK_IP_HAS_LFAST1_PLL_PH0_CLK, 424 #endif 425 #if defined(CLOCK_IP_HAS_PLL_POSTDIV_CLK) 426 PLL_POSTDIV_CLK = CLOCK_IP_HAS_PLL_POSTDIV_CLK, 427 #endif 428 #if defined(CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK) 429 PLLAUX_POSTDIV_CLK = CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK, 430 #endif 431 #if defined(CLOCK_IP_HAS_SIRCDIV1_CLK) 432 SIRCDIV1_CLK = CLOCK_IP_HAS_SIRCDIV1_CLK, 433 #endif 434 #if defined(CLOCK_IP_HAS_SIRCDIV2_CLK) 435 SIRCDIV2_CLK = CLOCK_IP_HAS_SIRCDIV2_CLK, 436 #endif 437 #if defined(CLOCK_IP_HAS_FDIV0_CLK) 438 FDIV0_CLK = CLOCK_IP_HAS_FDIV0_CLK, 439 #endif 440 #if defined(CLOCK_IP_HAS_FIRCDIV1_CLK) 441 FIRCDIV1_CLK = CLOCK_IP_HAS_FIRCDIV1_CLK, 442 #endif 443 #if defined(CLOCK_IP_HAS_FIRCDIV2_CLK) 444 FIRCDIV2_CLK = CLOCK_IP_HAS_FIRCDIV2_CLK, 445 #endif 446 #if defined(CLOCK_IP_HAS_SOSCDIV1_CLK) 447 SOSCDIV1_CLK = CLOCK_IP_HAS_SOSCDIV1_CLK, 448 #endif 449 #if defined(CLOCK_IP_HAS_SOSCDIV2_CLK) 450 SOSCDIV2_CLK = CLOCK_IP_HAS_SOSCDIV2_CLK, 451 #endif 452 #if defined(CLOCK_IP_HAS_SPLLDIV1_CLK) 453 SPLLDIV1_CLK = CLOCK_IP_HAS_SPLLDIV1_CLK, 454 #endif 455 #if defined(CLOCK_IP_HAS_SPLLDIV2_CLK) 456 SPLLDIV2_CLK = CLOCK_IP_HAS_SPLLDIV2_CLK, 457 #endif 458 #if defined(CLOCK_IP_HAS_LPO_32K_CLK) 459 LPO_32K_CLK = CLOCK_IP_HAS_LPO_32K_CLK, 460 #endif 461 #if defined(CLOCK_IP_HAS_LPO_1K_CLK) 462 LPO_1K_CLK = CLOCK_IP_HAS_LPO_1K_CLK, 463 #endif 464 #if defined(CLOCK_IP_HAS_SERDES_0_LANE_0_TX) 465 SERDES_0_LANE_0_TX = CLOCK_IP_HAS_SERDES_0_LANE_0_TX, 466 #endif 467 #if defined(CLOCK_IP_HAS_SERDES_0_LANE_0_CDR) 468 SERDES_0_LANE_0_CDR = CLOCK_IP_HAS_SERDES_0_LANE_0_CDR, 469 #endif 470 #if defined(CLOCK_IP_HAS_SERDES_0_LANE_1_TX) 471 SERDES_0_LANE_1_TX = CLOCK_IP_HAS_SERDES_0_LANE_1_TX, 472 #endif 473 #if defined(CLOCK_IP_HAS_SERDES_0_LANE_1_CDR) 474 SERDES_0_LANE_1_CDR = CLOCK_IP_HAS_SERDES_0_LANE_1_CDR, 475 #endif 476 #if defined(CLOCK_IP_HAS_SERDES_1_LANE_0_TX) 477 SERDES_1_LANE_0_TX = CLOCK_IP_HAS_SERDES_1_LANE_0_TX, 478 #endif 479 #if defined(CLOCK_IP_HAS_SERDES_1_LANE_0_CDR) 480 SERDES_1_LANE_0_CDR = CLOCK_IP_HAS_SERDES_1_LANE_0_CDR, 481 #endif 482 #if defined(CLOCK_IP_HAS_SERDES_1_LANE_1_TX) 483 SERDES_1_LANE_1_TX = CLOCK_IP_HAS_SERDES_1_LANE_1_TX, 484 #endif 485 #if defined(CLOCK_IP_HAS_SERDES_1_LANE_1_CDR) 486 SERDES_1_LANE_1_CDR = CLOCK_IP_HAS_SERDES_1_LANE_1_CDR, 487 #endif 488 #if defined(CLOCK_IP_HAS_SERDES_0_XPCS_0_TX) 489 SERDES_0_XPCS_0_TX = CLOCK_IP_HAS_SERDES_0_XPCS_0_TX, 490 #endif 491 #if defined(CLOCK_IP_HAS_SERDES_0_XPCS_0_CDR) 492 SERDES_0_XPCS_0_CDR = CLOCK_IP_HAS_SERDES_0_XPCS_0_CDR, 493 #endif 494 #if defined(CLOCK_IP_HAS_SERDES_0_XPCS_1_TX) 495 SERDES_0_XPCS_1_TX = CLOCK_IP_HAS_SERDES_0_XPCS_1_TX, 496 #endif 497 #if defined(CLOCK_IP_HAS_SERDES_0_XPCS_1_CDR) 498 SERDES_0_XPCS_1_CDR = CLOCK_IP_HAS_SERDES_0_XPCS_1_CDR, 499 #endif 500 #if defined(CLOCK_IP_HAS_SERDES_1_XPCS_0_TX) 501 SERDES_1_XPCS_0_TX = CLOCK_IP_HAS_SERDES_1_XPCS_0_TX, 502 #endif 503 #if defined(CLOCK_IP_HAS_SERDES_1_XPCS_0_CDR) 504 SERDES_1_XPCS_0_CDR = CLOCK_IP_HAS_SERDES_1_XPCS_0_CDR, 505 #endif 506 #if defined(CLOCK_IP_HAS_SERDES_1_XPCS_1_TX) 507 SERDES_1_XPCS_1_TX = CLOCK_IP_HAS_SERDES_1_XPCS_1_TX, 508 #endif 509 #if defined(CLOCK_IP_HAS_SERDES_1_XPCS_1_CDR) 510 SERDES_1_XPCS_1_CDR = CLOCK_IP_HAS_SERDES_1_XPCS_1_CDR, 511 #endif 512 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK) 513 EMAC_MII_RX_CLK = CLOCK_IP_HAS_EMAC_MII_RX_CLK, 514 #endif 515 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK) 516 EMAC_MII_RMII_TX_CLK = CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK, 517 #endif 518 #if defined(CLOCK_IP_HAS_ETH_RGMII_REF_CLK) 519 ETH_RGMII_REF_CLK = CLOCK_IP_HAS_ETH_RGMII_REF_CLK, 520 #endif 521 #if defined(CLOCK_IP_HAS_TMR_1588_CLK) 522 TMR_1588_CLK = CLOCK_IP_HAS_TMR_1588_CLK, 523 #endif 524 #if defined(CLOCK_IP_HAS_ETH_EXT_TS_CLK) 525 ETH_EXT_TS_CLK = CLOCK_IP_HAS_ETH_EXT_TS_CLK, 526 #endif 527 #if defined(CLOCK_IP_HAS_ETH0_EXT_RX_CLK) 528 ETH0_EXT_RX_CLK = CLOCK_IP_HAS_ETH0_EXT_RX_CLK, 529 #endif 530 #if defined(CLOCK_IP_HAS_ETH0_EXT_TX_CLK) 531 ETH0_EXT_TX_CLK = CLOCK_IP_HAS_ETH0_EXT_TX_CLK, 532 #endif 533 #if defined(CLOCK_IP_HAS_ETH1_EXT_RX_CLK) 534 ETH1_EXT_RX_CLK = CLOCK_IP_HAS_ETH1_EXT_RX_CLK, 535 #endif 536 #if defined(CLOCK_IP_HAS_ETH1_EXT_TX_CLK) 537 ETH1_EXT_TX_CLK = CLOCK_IP_HAS_ETH1_EXT_TX_CLK, 538 #endif 539 #if defined(CLOCK_IP_HAS_LFAST0_EXT_REF_CLK) 540 LFAST0_EXT_REF_CLK = CLOCK_IP_HAS_LFAST0_EXT_REF_CLK, 541 #endif 542 #if defined(CLOCK_IP_HAS_LFAST1_EXT_REF_CLK) 543 LFAST1_EXT_REF_CLK = CLOCK_IP_HAS_LFAST1_EXT_REF_CLK, 544 #endif 545 #if defined(CLOCK_IP_HAS_FTM_0_EXT_REF_CLK) 546 FTM_0_EXT_REF_CLK = CLOCK_IP_HAS_FTM_0_EXT_REF_CLK, 547 #endif 548 #if defined(CLOCK_IP_HAS_FTM_1_EXT_REF_CLK) 549 FTM_1_EXT_REF_CLK = CLOCK_IP_HAS_FTM_1_EXT_REF_CLK, 550 #endif 551 #if defined(CLOCK_IP_HAS_GMAC_0_EXT_REF_CLK) 552 GMAC_0_EXT_REF_CLK = CLOCK_IP_HAS_GMAC_0_EXT_REF_CLK, 553 #endif 554 #if defined(CLOCK_IP_HAS_GMAC_0_EXT_RX_CLK) 555 GMAC_0_EXT_RX_CLK = CLOCK_IP_HAS_GMAC_0_EXT_RX_CLK, 556 #endif 557 #if defined(CLOCK_IP_HAS_GMAC_0_EXT_TX_CLK) 558 GMAC_0_EXT_TX_CLK = CLOCK_IP_HAS_GMAC_0_EXT_TX_CLK, 559 #endif 560 #if defined(CLOCK_IP_HAS_GMAC_0_SGMII_REF_CLK) 561 GMAC_0_SGMII_REF_CLK = CLOCK_IP_HAS_GMAC_0_SGMII_REF_CLK, 562 #endif 563 #if defined(CLOCK_IP_HAS_GMAC_0_SGMII_RX_CLK) 564 GMAC_0_SGMII_RX_CLK = CLOCK_IP_HAS_GMAC_0_SGMII_RX_CLK, 565 #endif 566 #if defined(CLOCK_IP_HAS_GMAC_0_SGMII_TX_CLK) 567 GMAC_0_SGMII_TX_CLK = CLOCK_IP_HAS_GMAC_0_SGMII_TX_CLK, 568 #endif 569 #if defined(CLOCK_IP_HAS_GMAC_1_EXT_REF_CLK) 570 GMAC_1_EXT_REF_CLK = CLOCK_IP_HAS_GMAC_1_EXT_REF_CLK, 571 #endif 572 #if defined(CLOCK_IP_HAS_GMAC_1_EXT_RX_CLK) 573 GMAC_1_EXT_RX_CLK = CLOCK_IP_HAS_GMAC_1_EXT_RX_CLK, 574 #endif 575 #if defined(CLOCK_IP_HAS_GMAC_1_EXT_TX_CLK) 576 GMAC_1_EXT_TX_CLK = CLOCK_IP_HAS_GMAC_1_EXT_TX_CLK, 577 #endif 578 #if defined(CLOCK_IP_HAS_GMAC_EXT_TS_CLK) 579 GMAC_EXT_TS_CLK = CLOCK_IP_HAS_GMAC_EXT_TS_CLK, 580 #endif 581 #if defined(CLOCK_IP_HAS_GMAC_0_EXT_TS_CLK) 582 GMAC_0_EXT_TS_CLK = CLOCK_IP_HAS_GMAC_0_EXT_TS_CLK, 583 #endif 584 #if defined(CLOCK_IP_HAS_GMAC_1_EXT_TS_CLK) 585 GMAC_1_EXT_TS_CLK = CLOCK_IP_HAS_GMAC_1_EXT_TS_CLK, 586 #endif 587 #if defined(CLOCK_IP_HAS_GMAC_1_INT_REF_CLK) 588 GMAC_1_INT_REF_CLK = CLOCK_IP_HAS_GMAC_1_INT_REF_CLK, 589 #endif 590 #if defined(CLOCK_IP_HAS_PFE_MAC_0_EXT_REF_CLK) 591 PFE_MAC_0_EXT_REF_CLK = CLOCK_IP_HAS_PFE_MAC_0_EXT_REF_CLK, 592 #endif 593 #if defined(CLOCK_IP_HAS_PFE_MAC_0_EXT_RX_CLK) 594 PFE_MAC_0_EXT_RX_CLK = CLOCK_IP_HAS_PFE_MAC_0_EXT_RX_CLK, 595 #endif 596 #if defined(CLOCK_IP_HAS_PFE_MAC_0_EXT_TX_CLK) 597 PFE_MAC_0_EXT_TX_CLK = CLOCK_IP_HAS_PFE_MAC_0_EXT_TX_CLK, 598 #endif 599 #if defined(CLOCK_IP_HAS_PFE_MAC_1_EXT_REF_CLK) 600 PFE_MAC_1_EXT_REF_CLK = CLOCK_IP_HAS_PFE_MAC_1_EXT_REF_CLK, 601 #endif 602 #if defined(CLOCK_IP_HAS_PFE_MAC_1_EXT_RX_CLK) 603 PFE_MAC_1_EXT_RX_CLK = CLOCK_IP_HAS_PFE_MAC_1_EXT_RX_CLK, 604 #endif 605 #if defined(CLOCK_IP_HAS_PFE_MAC_1_EXT_TX_CLK) 606 PFE_MAC_1_EXT_TX_CLK = CLOCK_IP_HAS_PFE_MAC_1_EXT_TX_CLK, 607 #endif 608 #if defined(CLOCK_IP_HAS_PFE_MAC_2_EXT_REF_CLK) 609 PFE_MAC_2_EXT_REF_CLK = CLOCK_IP_HAS_PFE_MAC_2_EXT_REF_CLK, 610 #endif 611 #if defined(CLOCK_IP_HAS_PFE_MAC_2_EXT_RX_CLK) 612 PFE_MAC_2_EXT_RX_CLK = CLOCK_IP_HAS_PFE_MAC_2_EXT_RX_CLK, 613 #endif 614 #if defined(CLOCK_IP_HAS_PFE_MAC_2_EXT_TX_CLK) 615 PFE_MAC_2_EXT_TX_CLK = CLOCK_IP_HAS_PFE_MAC_2_EXT_TX_CLK, 616 #endif 617 #if defined(CLOCK_IP_HAS_TCLK0_REF_CLK) 618 TCLK0_REF_CLK = CLOCK_IP_HAS_TCLK0_REF_CLK, 619 #endif 620 #if defined(CLOCK_IP_HAS_TCLK1_REF_CLK) 621 TCLK1_REF_CLK = CLOCK_IP_HAS_TCLK1_REF_CLK, 622 #endif 623 #if defined(CLOCK_IP_HAS_TCLK2_REF_CLK) 624 TCLK2_REF_CLK = CLOCK_IP_HAS_TCLK2_REF_CLK, 625 #endif 626 #if defined(CLOCK_IP_HAS_TEST_CLK) 627 TEST_CLK = CLOCK_IP_HAS_TEST_CLK, 628 #endif 629 #if defined(CLOCK_IP_HAS_TPR_CLK) 630 TPR_CLK = CLOCK_IP_HAS_TPR_CLK, 631 #endif 632 #if defined(CLOCK_IP_HAS_RTC_CLKIN) 633 RTC_CLKIN = CLOCK_IP_HAS_RTC_CLKIN, 634 #endif 635 #if defined(CLOCK_IP_HAS_A53_CORE_CLK) 636 A53_CORE_CLK = CLOCK_IP_HAS_A53_CORE_CLK, 637 #endif 638 #if defined(CLOCK_IP_HAS_A53_CORE_DIV2_CLK) 639 A53_CORE_DIV2_CLK = CLOCK_IP_HAS_A53_CORE_DIV2_CLK, 640 #endif 641 #if defined(CLOCK_IP_HAS_A53_CORE_DIV4_CLK) 642 A53_CORE_DIV4_CLK = CLOCK_IP_HAS_A53_CORE_DIV4_CLK, 643 #endif 644 #if defined(CLOCK_IP_HAS_A53_CORE_DIV10_CLK) 645 A53_CORE_DIV10_CLK = CLOCK_IP_HAS_A53_CORE_DIV10_CLK, 646 #endif 647 #if defined(CLOCK_IP_HAS_AIPS_PLAT_CLK) 648 AIPS_PLAT_CLK = CLOCK_IP_HAS_AIPS_PLAT_CLK, 649 #endif 650 #if defined(CLOCK_IP_HAS_AIPS_SLOW_CLK) 651 AIPS_SLOW_CLK = CLOCK_IP_HAS_AIPS_SLOW_CLK, 652 #endif 653 #if defined(CLOCK_IP_HAS_ACCEL3_CLK) 654 ACCEL3_CLK = CLOCK_IP_HAS_ACCEL3_CLK, 655 #endif 656 #if defined(CLOCK_IP_HAS_ACCEL3_DIV3_CLK) 657 ACCEL3_DIV3_CLK = CLOCK_IP_HAS_ACCEL3_DIV3_CLK, 658 #endif 659 #if defined(CLOCK_IP_HAS_ACCEL4_CLK) 660 ACCEL4_CLK = CLOCK_IP_HAS_ACCEL4_CLK, 661 #endif 662 #if defined(CLOCK_IP_HAS_CLKOUT_RUN_CLK) 663 CLKOUT_RUN_CLK = CLOCK_IP_HAS_CLKOUT_RUN_CLK, 664 #endif 665 #if defined(CLOCK_IP_HAS_DCM_CLK) 666 DCM_CLK = CLOCK_IP_HAS_DCM_CLK, 667 #endif 668 #if defined(CLOCK_IP_HAS_DDR_CLK) 669 DDR_CLK = CLOCK_IP_HAS_DDR_CLK, 670 #endif 671 #if defined(CLOCK_IP_HAS_DDR0_CLK) 672 DDR0_CLK = CLOCK_IP_HAS_DDR0_CLK, 673 #endif 674 #if defined(CLOCK_IP_HAS_DMACRC0_CLK) 675 DMACRC0_CLK = CLOCK_IP_HAS_DMACRC0_CLK, 676 #endif 677 #if defined(CLOCK_IP_HAS_DMACRC1_CLK) 678 DMACRC1_CLK = CLOCK_IP_HAS_DMACRC1_CLK, 679 #endif 680 #if defined(CLOCK_IP_HAS_DMACRC4_CLK) 681 DMACRC4_CLK = CLOCK_IP_HAS_DMACRC4_CLK, 682 #endif 683 #if defined(CLOCK_IP_HAS_DMACRC5_CLK) 684 DMACRC5_CLK = CLOCK_IP_HAS_DMACRC5_CLK, 685 #endif 686 #if defined(CLOCK_IP_HAS_GMAC_REF_DIV_CLK) 687 GMAC_REF_DIV_CLK = CLOCK_IP_HAS_GMAC_REF_DIV_CLK, 688 #endif 689 #if defined(CLOCK_IP_HAS_GMAC0_REF_DIV_CLK) 690 GMAC0_REF_DIV_CLK = CLOCK_IP_HAS_GMAC0_REF_DIV_CLK, 691 #endif 692 #if defined(CLOCK_IP_HAS_GMAC0_REF_CLK) 693 GMAC0_REF_CLK = CLOCK_IP_HAS_GMAC0_REF_CLK, 694 #endif 695 #if defined(CLOCK_IP_HAS_GMAC1_REF_DIV_CLK) 696 GMAC1_REF_DIV_CLK = CLOCK_IP_HAS_GMAC1_REF_DIV_CLK, 697 #endif 698 #if defined(CLOCK_IP_HAS_GMAC1_REF_CLK) 699 GMAC1_REF_CLK = CLOCK_IP_HAS_GMAC1_REF_CLK, 700 #endif 701 #if defined(CLOCK_IP_HAS_GMAC1_INT_CLK) 702 GMAC1_INT_CLK = CLOCK_IP_HAS_GMAC1_INT_CLK, 703 #endif 704 #if defined(CLOCK_IP_HAS_AURORA_TRACE_TEST_CLK) 705 AURORA_TRACE_TEST_CLK = CLOCK_IP_HAS_AURORA_TRACE_TEST_CLK, 706 #endif 707 #if defined(CLOCK_IP_HAS_HSE_CLK) 708 HSE_CLK = CLOCK_IP_HAS_HSE_CLK, 709 #endif 710 #if defined(CLOCK_IP_HAS_LBIST_CLK) 711 LBIST_CLK = CLOCK_IP_HAS_LBIST_CLK, 712 #endif 713 #if defined(CLOCK_IP_HAS_PFE_PE_CLK) 714 PFE_PE_CLK = CLOCK_IP_HAS_PFE_PE_CLK, 715 #endif 716 #if defined(CLOCK_IP_HAS_PFE_SYS_CLK) 717 PFE_SYS_CLK = CLOCK_IP_HAS_PFE_SYS_CLK, 718 #endif 719 #if defined(CLOCK_IP_HAS_PER_CLK) 720 PER_CLK = CLOCK_IP_HAS_PER_CLK, 721 #endif 722 #if defined(CLOCK_IP_HAS_PFEMAC0_REF_DIV_CLK) 723 PFEMAC0_REF_DIV_CLK = CLOCK_IP_HAS_PFEMAC0_REF_DIV_CLK, 724 #endif 725 #if defined(CLOCK_IP_HAS_PFEMAC1_REF_DIV_CLK) 726 PFEMAC1_REF_DIV_CLK = CLOCK_IP_HAS_PFEMAC1_REF_DIV_CLK, 727 #endif 728 #if defined(CLOCK_IP_HAS_PFEMAC2_REF_DIV_CLK) 729 PFEMAC2_REF_DIV_CLK = CLOCK_IP_HAS_PFEMAC2_REF_DIV_CLK, 730 #endif 731 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK) 732 QSPI_MEM_CLK = CLOCK_IP_HAS_QSPI_MEM_CLK, 733 #endif 734 #if defined(CLOCK_IP_HAS_SCS_CLK) 735 SCS_CLK = CLOCK_IP_HAS_SCS_CLK, 736 #endif 737 #if defined(CLOCK_IP_HAS_XBAR_2X_CLK) 738 XBAR_2X_CLK = CLOCK_IP_HAS_XBAR_2X_CLK, 739 #endif 740 #if defined(CLOCK_IP_HAS_XBAR_CLK) 741 XBAR_CLK = CLOCK_IP_HAS_XBAR_CLK, 742 #endif 743 #if defined(CLOCK_IP_HAS_XBAR_DIV2_CLK) 744 XBAR_DIV2_CLK = CLOCK_IP_HAS_XBAR_DIV2_CLK, 745 #endif 746 #if defined(CLOCK_IP_HAS_XBAR_DIV3_CLK) 747 XBAR_DIV3_CLK = CLOCK_IP_HAS_XBAR_DIV3_CLK, 748 #endif 749 #if defined(CLOCK_IP_HAS_XBAR_DIV4_CLK) 750 XBAR_DIV4_CLK = CLOCK_IP_HAS_XBAR_DIV4_CLK, 751 #endif 752 #if defined(CLOCK_IP_HAS_XBAR_DIV6_CLK) 753 XBAR_DIV6_CLK = CLOCK_IP_HAS_XBAR_DIV6_CLK, 754 #endif 755 #if defined(CLOCK_IP_HAS_XMII_CLK_125MHZ) 756 XMII_CLK_125MHZ = CLOCK_IP_HAS_XMII_CLK_125MHZ, 757 #endif 758 #if defined(CLOCK_IP_HAS_XMII_CLK_2M5HZ) 759 XMII_CLK_2M5HZ = CLOCK_IP_HAS_XMII_CLK_2M5HZ, 760 #endif 761 #if defined(CLOCK_IP_HAS_XMII_CLK_25MHZ) 762 XMII_CLK_25MHZ = CLOCK_IP_HAS_XMII_CLK_25MHZ, 763 #endif 764 #if defined(CLOCK_IP_HAS_XMII_CLK_50MHZ) 765 XMII_CLK_50MHZ = CLOCK_IP_HAS_XMII_CLK_50MHZ, 766 #endif 767 #if defined(CLOCK_IP_HAS_XOSC_CLK) 768 XOSC_CLK = CLOCK_IP_HAS_XOSC_CLK, 769 #endif 770 #if defined(CLOCK_IP_HAS_SERDES_REF_CLK) 771 SERDES_REF_CLK = CLOCK_IP_HAS_SERDES_REF_CLK, 772 #endif 773 #if defined(CLOCK_IP_HAS_SERDES0_REF_CLK) 774 SERDES0_REF_CLK = CLOCK_IP_HAS_SERDES0_REF_CLK, 775 #endif 776 #if defined(CLOCK_IP_HAS_SERDES1_REF_CLK) 777 SERDES1_REF_CLK = CLOCK_IP_HAS_SERDES1_REF_CLK, 778 #endif 779 #if defined(CLOCK_IP_HAS_SCS_RUN_CLK) 780 SCS_RUN_CLK = CLOCK_IP_HAS_SCS_RUN_CLK, 781 #endif 782 #if defined(CLOCK_IP_HAS_SCS_VLPR_CLK) 783 SCS_VLPR_CLK = CLOCK_IP_HAS_SCS_VLPR_CLK, 784 #endif 785 #if defined(CLOCK_IP_HAS_SCS_HSRUN_CLK) 786 SCS_HSRUN_CLK = CLOCK_IP_HAS_SCS_HSRUN_CLK, 787 #endif 788 #if defined(CLOCK_IP_HAS_CORE_CLK) 789 CORE_CLK = CLOCK_IP_HAS_CORE_CLK, 790 #endif 791 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 792 CM7_CORE_CLK = CLOCK_IP_HAS_CM7_CORE_CLK, 793 #endif 794 #if defined(CLOCK_IP_HAS_CORE_RUN_CLK) 795 CORE_RUN_CLK = CLOCK_IP_HAS_CORE_RUN_CLK, 796 #endif 797 #if defined(CLOCK_IP_HAS_CORE_VLPR_CLK) 798 CORE_VLPR_CLK = CLOCK_IP_HAS_CORE_VLPR_CLK, 799 #endif 800 #if defined(CLOCK_IP_HAS_CORE_HSRUN_CLK) 801 CORE_HSRUN_CLK = CLOCK_IP_HAS_CORE_HSRUN_CLK, 802 #endif 803 #if defined(CLOCK_IP_HAS_BUS_CLK) 804 BUS_CLK = CLOCK_IP_HAS_BUS_CLK, 805 #endif 806 #if defined(CLOCK_IP_HAS_BUS_RUN_CLK) 807 BUS_RUN_CLK = CLOCK_IP_HAS_BUS_RUN_CLK, 808 #endif 809 #if defined(CLOCK_IP_HAS_BUS_VLPR_CLK) 810 BUS_VLPR_CLK = CLOCK_IP_HAS_BUS_VLPR_CLK, 811 #endif 812 #if defined(CLOCK_IP_HAS_BUS_HSRUN_CLK) 813 BUS_HSRUN_CLK = CLOCK_IP_HAS_BUS_HSRUN_CLK, 814 #endif 815 #if defined(CLOCK_IP_HAS_SLOW_CLK) 816 SLOW_CLK = CLOCK_IP_HAS_SLOW_CLK, 817 #endif 818 #if defined(CLOCK_IP_HAS_SLOW_RUN_CLK) 819 SLOW_RUN_CLK = CLOCK_IP_HAS_SLOW_RUN_CLK, 820 #endif 821 #if defined(CLOCK_IP_HAS_SLOW_VLPR_CLK) 822 SLOW_VLPR_CLK = CLOCK_IP_HAS_SLOW_VLPR_CLK, 823 #endif 824 #if defined(CLOCK_IP_HAS_SLOW_HSRUN_CLK) 825 SLOW_HSRUN_CLK = CLOCK_IP_HAS_SLOW_HSRUN_CLK, 826 #endif 827 #if defined(CLOCK_IP_HAS_LPO_CLK) 828 LPO_CLK = CLOCK_IP_HAS_LPO_CLK, 829 #endif 830 #if defined(CLOCK_IP_HAS_SCG_CLKOUT_CLK) 831 SCG_CLKOUT_CLK = CLOCK_IP_HAS_SCG_CLKOUT_CLK, 832 #endif 833 #if defined(CLOCK_IP_HAS_FTM0_EXT_CLK) 834 FTM0_EXT_CLK = CLOCK_IP_HAS_FTM0_EXT_CLK, 835 #endif 836 #if defined(CLOCK_IP_HAS_FTM1_EXT_CLK) 837 FTM1_EXT_CLK = CLOCK_IP_HAS_FTM1_EXT_CLK, 838 #endif 839 #if defined(CLOCK_IP_HAS_FTM2_EXT_CLK) 840 FTM2_EXT_CLK = CLOCK_IP_HAS_FTM2_EXT_CLK, 841 #endif 842 #if defined(CLOCK_IP_HAS_FTM3_EXT_CLK) 843 FTM3_EXT_CLK = CLOCK_IP_HAS_FTM3_EXT_CLK, 844 #endif 845 #if defined(CLOCK_IP_HAS_FTM4_EXT_CLK) 846 FTM4_EXT_CLK = CLOCK_IP_HAS_FTM4_EXT_CLK, 847 #endif 848 #if defined(CLOCK_IP_HAS_FTM5_EXT_CLK) 849 FTM5_EXT_CLK = CLOCK_IP_HAS_FTM5_EXT_CLK, 850 #endif 851 #if defined(CLOCK_IP_HAS_FTM6_EXT_CLK) 852 FTM6_EXT_CLK = CLOCK_IP_HAS_FTM6_EXT_CLK, 853 #endif 854 #if defined(CLOCK_IP_HAS_FTM7_EXT_CLK) 855 FTM7_EXT_CLK = CLOCK_IP_HAS_FTM7_EXT_CLK, 856 #endif 857 #if defined(CLOCK_IP_HAS_Px_CLKOUT_SRC_CLK) 858 Px_CLKOUT_SRC_CLK = CLOCK_IP_HAS_Px_CLKOUT_SRC_CLK, 859 #endif 860 #if defined(CLOCK_IP_HAS_Px_PSI5_S_UTIL_CLK) 861 Px_PSI5_S_UTIL_CLK = CLOCK_IP_HAS_Px_PSI5_S_UTIL_CLK, 862 #endif 863 #if defined(CLOCK_IP_HAS_SHIFT_LBIST_CLK) 864 SHIFT_LBIST_CLK = CLOCK_IP_HAS_SHIFT_LBIST_CLK, 865 #endif 866 #if defined(CLOCK_IP_HAS_P0_SYS_CLK) 867 P0_SYS_CLK = CLOCK_IP_HAS_P0_SYS_CLK, 868 #endif 869 #if defined(CLOCK_IP_HAS_P1_SYS_CLK) 870 P1_SYS_CLK = CLOCK_IP_HAS_P1_SYS_CLK, 871 #endif 872 #if defined(CLOCK_IP_HAS_P1_SYS_DIV2_CLK) 873 P1_SYS_DIV2_CLK = CLOCK_IP_HAS_P1_SYS_DIV2_CLK, 874 #endif 875 #if defined(CLOCK_IP_HAS_P1_SYS_DIV4_CLK) 876 P1_SYS_DIV4_CLK = CLOCK_IP_HAS_P1_SYS_DIV4_CLK, 877 #endif 878 #if defined(CLOCK_IP_HAS_P2_SYS_CLK) 879 P2_SYS_CLK = CLOCK_IP_HAS_P2_SYS_CLK, 880 #endif 881 #if defined(CLOCK_IP_HAS_CORE_M33_CLK) 882 CORE_M33_CLK = CLOCK_IP_HAS_CORE_M33_CLK, 883 #endif 884 #if defined(CLOCK_IP_HAS_P2_SYS_DIV2_CLK) 885 P2_SYS_DIV2_CLK = CLOCK_IP_HAS_P2_SYS_DIV2_CLK, 886 #endif 887 #if defined(CLOCK_IP_HAS_P2_SYS_DIV4_CLK) 888 P2_SYS_DIV4_CLK = CLOCK_IP_HAS_P2_SYS_DIV4_CLK, 889 #endif 890 #if defined(CLOCK_IP_HAS_P3_SYS_CLK) 891 P3_SYS_CLK = CLOCK_IP_HAS_P3_SYS_CLK, 892 #endif 893 #if defined(CLOCK_IP_HAS_CE_SYS_DIV2_CLK) 894 CE_SYS_DIV2_CLK = CLOCK_IP_HAS_CE_SYS_DIV2_CLK, 895 #endif 896 #if defined(CLOCK_IP_HAS_CE_SYS_DIV4_CLK) 897 CE_SYS_DIV4_CLK = CLOCK_IP_HAS_CE_SYS_DIV4_CLK, 898 #endif 899 #if defined(CLOCK_IP_HAS_P3_SYS_DIV2_NOC_CLK) 900 P3_SYS_DIV2_NOC_CLK = CLOCK_IP_HAS_P3_SYS_DIV2_NOC_CLK, 901 #endif 902 #if defined(CLOCK_IP_HAS_P3_SYS_DIV4_CLK) 903 P3_SYS_DIV4_CLK = CLOCK_IP_HAS_P3_SYS_DIV4_CLK, 904 #endif 905 #if defined(CLOCK_IP_HAS_P4_SYS_CLK) 906 P4_SYS_CLK = CLOCK_IP_HAS_P4_SYS_CLK, 907 #endif 908 #if defined(CLOCK_IP_HAS_P4_SYS_DIV2_CLK) 909 P4_SYS_DIV2_CLK = CLOCK_IP_HAS_P4_SYS_DIV2_CLK, 910 #endif 911 #if defined(CLOCK_IP_HAS_HSE_SYS_DIV2_CLK) 912 HSE_SYS_DIV2_CLK = CLOCK_IP_HAS_HSE_SYS_DIV2_CLK, 913 #endif 914 #if defined(CLOCK_IP_HAS_P5_SYS_CLK) 915 P5_SYS_CLK = CLOCK_IP_HAS_P5_SYS_CLK, 916 #endif 917 #if defined(CLOCK_IP_HAS_P5_SYS_DIV2_CLK) 918 P5_SYS_DIV2_CLK = CLOCK_IP_HAS_P5_SYS_DIV2_CLK, 919 #endif 920 #if defined(CLOCK_IP_HAS_P5_SYS_DIV4_CLK) 921 P5_SYS_DIV4_CLK = CLOCK_IP_HAS_P5_SYS_DIV4_CLK, 922 #endif 923 #if defined(CLOCK_IP_HAS_P2_MATH_CLK) 924 P2_MATH_CLK = CLOCK_IP_HAS_P2_MATH_CLK, 925 #endif 926 #if defined(CLOCK_IP_HAS_P2_MATH_DIV3_CLK) 927 P2_MATH_DIV3_CLK = CLOCK_IP_HAS_P2_MATH_DIV3_CLK, 928 #endif 929 #if defined(CLOCK_IP_HAS_RTU0_CORE_CLK) 930 RTU0_CORE_CLK = CLOCK_IP_HAS_RTU0_CORE_CLK, 931 #endif 932 #if defined(CLOCK_IP_HAS_RTU0_CORE_DIV2_CLK) 933 RTU0_CORE_DIV2_CLK = CLOCK_IP_HAS_RTU0_CORE_DIV2_CLK, 934 #endif 935 #if defined(CLOCK_IP_HAS_RTU1_CORE_CLK) 936 RTU1_CORE_CLK = CLOCK_IP_HAS_RTU1_CORE_CLK, 937 #endif 938 #if defined(CLOCK_IP_HAS_RTU1_CORE_DIV2_CLK) 939 RTU1_CORE_DIV2_CLK = CLOCK_IP_HAS_RTU1_CORE_DIV2_CLK, 940 #endif 941 #if defined(CLOCK_IP_HAS_P0_PSI5_S_UTIL_CLK) 942 P0_PSI5_S_UTIL_CLK = CLOCK_IP_HAS_P0_PSI5_S_UTIL_CLK, 943 #endif 944 #if defined(CLOCK_IP_HAS_P4_PSI5_S_UTIL_CLK) 945 P4_PSI5_S_UTIL_CLK = CLOCK_IP_HAS_P4_PSI5_S_UTIL_CLK, 946 #endif 947 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 948 SYSTEM_DRUN_CLK = CLOCK_IP_HAS_SYSTEM_DRUN_CLK, 949 #endif 950 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 951 SYSTEM_DIV2_CLK = CLOCK_IP_HAS_SYSTEM_DIV2_CLK, 952 #endif 953 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) 954 SYSTEM_DIV4_MON1_CLK = CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK, 955 #endif 956 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK) 957 SYSTEM_DIV4_MON2_CLK = CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK, 958 #endif 959 #if defined(CLOCK_IP_HAS_SYS_CLK) 960 SYS_CLK = CLOCK_IP_HAS_SYS_CLK, 961 #endif 962 #if defined(CLOCK_IP_HAS_SYS_DIV2_CLK) 963 SYS_DIV2_CLK = CLOCK_IP_HAS_SYS_DIV2_CLK, 964 #endif 965 #if defined(CLOCK_IP_HAS_SYS_DIV4_CLK) 966 SYS_DIV4_CLK = CLOCK_IP_HAS_SYS_DIV4_CLK, 967 #endif 968 #if defined(CLOCK_IP_HAS_SYS_DIV8_CLK) 969 SYS_DIV8_CLK = CLOCK_IP_HAS_SYS_DIV8_CLK, 970 #endif 971 #if defined(CLOCK_IP_HAS_RT_DAPB_CLK) 972 RT_DAPB_CLK = CLOCK_IP_HAS_RT_DAPB_CLK, 973 #endif 974 #if defined(CLOCK_IP_HAS_ACCEL_CLK) 975 ACCEL_CLK = CLOCK_IP_HAS_ACCEL_CLK, 976 #endif 977 #if defined(CLOCK_IP_HAS_ACCEL_DIV3_CLK) 978 ACCEL_DIV3_CLK = CLOCK_IP_HAS_ACCEL_DIV3_CLK, 979 #endif 980 #if defined(CLOCK_IP_HAS_ACCEL_DIV4_CLK) 981 ACCEL_DIV4_CLK = CLOCK_IP_HAS_ACCEL_DIV4_CLK, 982 #endif 983 #if defined(CLOCK_IP_HAS_ACCEL_XBAR_CLK) 984 ACCEL_XBAR_CLK = CLOCK_IP_HAS_ACCEL_XBAR_CLK, 985 #endif 986 #if defined(CLOCK_IP_HAS_ACCEL_XBAR_DIV2_CLK) 987 ACCEL_XBAR_DIV2_CLK = CLOCK_IP_HAS_ACCEL_XBAR_DIV2_CLK, 988 #endif 989 #if defined(CLOCK_IP_HAS_ACCEL_XBAR_DIV4_CLK) 990 ACCEL_XBAR_DIV4_CLK = CLOCK_IP_HAS_ACCEL_XBAR_DIV4_CLK, 991 #endif 992 #if defined(CLOCK_IP_HAS_ACCEL_XBAR_DIV8_CLK) 993 ACCEL_XBAR_DIV8_CLK = CLOCK_IP_HAS_ACCEL_XBAR_DIV8_CLK, 994 #endif 995 #if defined(CLOCK_IP_HAS_AP_DAPB_CLK) 996 AP_DAPB_CLK = CLOCK_IP_HAS_AP_DAPB_CLK, 997 #endif 998 THE_LAST_PRODUCER_CLK = CLOCK_IP_FEATURE_PRODUCERS_NO, /* Number of producers clocks */ 999 #if defined(CLOCK_IP_HAS_ACCEL4_LAX0_CLK) 1000 ACCEL4_LAX0_CLK = CLOCK_IP_HAS_ACCEL4_LAX0_CLK, 1001 #endif 1002 #if defined(CLOCK_IP_HAS_ACCEL4_LAX1_CLK) 1003 ACCEL4_LAX1_CLK = CLOCK_IP_HAS_ACCEL4_LAX1_CLK, 1004 #endif 1005 #if defined(CLOCK_IP_HAS_ADC0_CLK) 1006 ADC0_CLK = CLOCK_IP_HAS_ADC0_CLK, 1007 #endif 1008 #if defined(CLOCK_IP_HAS_ADC1_CLK) 1009 ADC1_CLK = CLOCK_IP_HAS_ADC1_CLK, 1010 #endif 1011 #if defined(CLOCK_IP_HAS_ADC2_CLK) 1012 ADC2_CLK = CLOCK_IP_HAS_ADC2_CLK, 1013 #endif 1014 #if defined(CLOCK_IP_HAS_ADC3_CLK) 1015 ADC3_CLK = CLOCK_IP_HAS_ADC3_CLK, 1016 #endif 1017 #if defined(CLOCK_IP_HAS_ADC4_CLK) 1018 ADC4_CLK = CLOCK_IP_HAS_ADC4_CLK, 1019 #endif 1020 #if defined(CLOCK_IP_HAS_ADC5_CLK) 1021 ADC5_CLK = CLOCK_IP_HAS_ADC5_CLK, 1022 #endif 1023 #if defined(CLOCK_IP_HAS_ADC6_CLK) 1024 ADC6_CLK = CLOCK_IP_HAS_ADC6_CLK, 1025 #endif 1026 #if defined(CLOCK_IP_HAS_ADCBIST_CLK) 1027 ADCBIST_CLK = CLOCK_IP_HAS_ADCBIST_CLK, 1028 #endif 1029 #if defined(CLOCK_IP_HAS_BCTU0_CLK) 1030 BCTU0_CLK = CLOCK_IP_HAS_BCTU0_CLK, 1031 #endif 1032 #if defined(CLOCK_IP_HAS_BCTU1_CLK) 1033 BCTU1_CLK = CLOCK_IP_HAS_BCTU1_CLK, 1034 #endif 1035 #if defined(CLOCK_IP_HAS_CE_SYS_DIV2_MON_CLK) 1036 CE_SYS_DIV2_MON_CLK = CLOCK_IP_HAS_CE_SYS_DIV2_MON_CLK, 1037 #endif 1038 #if defined(CLOCK_IP_HAS_CE_EDMA_CLK) 1039 CE_EDMA_CLK = CLOCK_IP_HAS_CE_EDMA_CLK, 1040 #endif 1041 #if defined(CLOCK_IP_HAS_CE_PIT0_CLK) 1042 CE_PIT0_CLK = CLOCK_IP_HAS_CE_PIT0_CLK, 1043 #endif 1044 #if defined(CLOCK_IP_HAS_CE_PIT1_CLK) 1045 CE_PIT1_CLK = CLOCK_IP_HAS_CE_PIT1_CLK, 1046 #endif 1047 #if defined(CLOCK_IP_HAS_CE_PIT2_CLK) 1048 CE_PIT2_CLK = CLOCK_IP_HAS_CE_PIT2_CLK, 1049 #endif 1050 #if defined(CLOCK_IP_HAS_CE_PIT3_CLK) 1051 CE_PIT3_CLK = CLOCK_IP_HAS_CE_PIT3_CLK, 1052 #endif 1053 #if defined(CLOCK_IP_HAS_CE_PIT4_CLK) 1054 CE_PIT4_CLK = CLOCK_IP_HAS_CE_PIT4_CLK, 1055 #endif 1056 #if defined(CLOCK_IP_HAS_CE_PIT5_CLK) 1057 CE_PIT5_CLK = CLOCK_IP_HAS_CE_PIT5_CLK, 1058 #endif 1059 #if defined(CLOCK_IP_HAS_CLKOUT_STANDBY_CLK) 1060 CLKOUT_STANDBY_CLK = CLOCK_IP_HAS_CLKOUT_STANDBY_CLK, 1061 #endif 1062 #if defined(CLOCK_IP_HAS_CLKOUT0_CLK) 1063 CLKOUT0_CLK = CLOCK_IP_HAS_CLKOUT0_CLK, 1064 #endif 1065 #if defined(CLOCK_IP_HAS_CLKOUT1_CLK) 1066 CLKOUT1_CLK = CLOCK_IP_HAS_CLKOUT1_CLK, 1067 #endif 1068 #if defined(CLOCK_IP_HAS_CLKOUT2_CLK) 1069 CLKOUT2_CLK = CLOCK_IP_HAS_CLKOUT2_CLK, 1070 #endif 1071 #if defined(CLOCK_IP_HAS_CLKOUT3_CLK) 1072 CLKOUT3_CLK = CLOCK_IP_HAS_CLKOUT3_CLK, 1073 #endif 1074 #if defined(CLOCK_IP_HAS_CLKOUT4_CLK) 1075 CLKOUT4_CLK = CLOCK_IP_HAS_CLKOUT4_CLK, 1076 #endif 1077 #if defined(CLOCK_IP_HAS_CLKOUT5_CLK) 1078 CLKOUT5_CLK = CLOCK_IP_HAS_CLKOUT5_CLK, 1079 #endif 1080 #if defined(CLOCK_IP_HAS_CMP0_CLK) 1081 CMP0_CLK = CLOCK_IP_HAS_CMP0_CLK, 1082 #endif 1083 #if defined(CLOCK_IP_HAS_CMP1_CLK) 1084 CMP1_CLK = CLOCK_IP_HAS_CMP1_CLK, 1085 #endif 1086 #if defined(CLOCK_IP_HAS_CMP2_CLK) 1087 CMP2_CLK = CLOCK_IP_HAS_CMP2_CLK, 1088 #endif 1089 #if defined(CLOCK_IP_HAS_CMU0_CLK) 1090 CMU0_CLK = CLOCK_IP_HAS_CMU0_CLK, 1091 #endif 1092 #if defined(CLOCK_IP_HAS_CMU1_CLK) 1093 CMU1_CLK = CLOCK_IP_HAS_CMU1_CLK, 1094 #endif 1095 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK) 1096 COOLFLUX_D_RAM0_CLK = CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK, 1097 #endif 1098 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK) 1099 COOLFLUX_D_RAM1_CLK = CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK, 1100 #endif 1101 #if defined(CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK) 1102 COOLFLUX_DSP16L_CLK = CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK, 1103 #endif 1104 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK) 1105 COOLFLUX_I_RAM0_CLK = CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK, 1106 #endif 1107 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK) 1108 COOLFLUX_I_RAM1_CLK = CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK, 1109 #endif 1110 #if defined(CLOCK_IP_HAS_CORE_A53_CLUSTER_0_CLK) 1111 CORE_A53_CLUSTER_0_CLK = CLOCK_IP_HAS_CORE_A53_CLUSTER_0_CLK, 1112 #endif 1113 #if defined(CLOCK_IP_HAS_CORE_A53_CLUSTER_1_CLK) 1114 CORE_A53_CLUSTER_1_CLK = CLOCK_IP_HAS_CORE_A53_CLUSTER_1_CLK, 1115 #endif 1116 #if defined(CLOCK_IP_HAS_CORE_M7_0_CLK) 1117 CORE_M7_0_CLK = CLOCK_IP_HAS_CORE_M7_0_CLK, 1118 #endif 1119 #if defined(CLOCK_IP_HAS_CORE_M7_1_CLK) 1120 CORE_M7_1_CLK = CLOCK_IP_HAS_CORE_M7_1_CLK, 1121 #endif 1122 #if defined(CLOCK_IP_HAS_CORE_M7_2_CLK) 1123 CORE_M7_2_CLK = CLOCK_IP_HAS_CORE_M7_2_CLK, 1124 #endif 1125 #if defined(CLOCK_IP_HAS_CORE_M7_3_CLK) 1126 CORE_M7_3_CLK = CLOCK_IP_HAS_CORE_M7_3_CLK, 1127 #endif 1128 #if defined(CLOCK_IP_HAS_CRC0_CLK) 1129 CRC0_CLK = CLOCK_IP_HAS_CRC0_CLK, 1130 #endif 1131 #if defined(CLOCK_IP_HAS_CTU0_CLK) 1132 CTU0_CLK = CLOCK_IP_HAS_CTU0_CLK, 1133 #endif 1134 #if defined(CLOCK_IP_HAS_CTU1_CLK) 1135 CTU1_CLK = CLOCK_IP_HAS_CTU1_CLK, 1136 #endif 1137 #if defined(CLOCK_IP_HAS_DAPB_CLK) 1138 DAPB_CLK = CLOCK_IP_HAS_DAPB_CLK, 1139 #endif 1140 #if defined(CLOCK_IP_HAS_DCM0_CLK) 1141 DCM0_CLK = CLOCK_IP_HAS_DCM0_CLK, 1142 #endif 1143 #if defined(CLOCK_IP_HAS_DMA_CRC0_CLK) 1144 DMA_CRC0_CLK = CLOCK_IP_HAS_DMA_CRC0_CLK, 1145 #endif 1146 #if defined(CLOCK_IP_HAS_DMA_CRC1_CLK) 1147 DMA_CRC1_CLK = CLOCK_IP_HAS_DMA_CRC1_CLK, 1148 #endif 1149 #if defined(CLOCK_IP_HAS_DMA0_CLK) 1150 DMA0_CLK = CLOCK_IP_HAS_DMA0_CLK, 1151 #endif 1152 #if defined(CLOCK_IP_HAS_DMA1_CLK) 1153 DMA1_CLK = CLOCK_IP_HAS_DMA1_CLK, 1154 #endif 1155 #if defined(CLOCK_IP_HAS_DMAMUX0_CLK) 1156 DMAMUX0_CLK = CLOCK_IP_HAS_DMAMUX0_CLK, 1157 #endif 1158 #if defined(CLOCK_IP_HAS_DMAMUX1_CLK) 1159 DMAMUX1_CLK = CLOCK_IP_HAS_DMAMUX1_CLK, 1160 #endif 1161 #if defined(CLOCK_IP_HAS_DMAMUX2_CLK) 1162 DMAMUX2_CLK = CLOCK_IP_HAS_DMAMUX2_CLK, 1163 #endif 1164 #if defined(CLOCK_IP_HAS_DMAMUX3_CLK) 1165 DMAMUX3_CLK = CLOCK_IP_HAS_DMAMUX3_CLK, 1166 #endif 1167 #if defined(CLOCK_IP_HAS_DMAMUX4_CLK) 1168 DMAMUX4_CLK = CLOCK_IP_HAS_DMAMUX4_CLK, 1169 #endif 1170 #if defined(CLOCK_IP_HAS_DMAMUX5_CLK) 1171 DMAMUX5_CLK = CLOCK_IP_HAS_DMAMUX5_CLK, 1172 #endif 1173 #if defined(CLOCK_IP_HAS_DSPI_MSC_CLK) 1174 DSPI_MSC_CLK = CLOCK_IP_HAS_DSPI_MSC_CLK, 1175 #endif 1176 #if defined(CLOCK_IP_HAS_EDMA_CLK) 1177 EDMA_CLK = CLOCK_IP_HAS_EDMA_CLK, 1178 #endif 1179 #if defined(CLOCK_IP_HAS_EDMA0_CLK) 1180 EDMA0_CLK = CLOCK_IP_HAS_EDMA0_CLK, 1181 #endif 1182 #if defined(CLOCK_IP_HAS_EDMA0_TCD0_CLK) 1183 EDMA0_TCD0_CLK = CLOCK_IP_HAS_EDMA0_TCD0_CLK, 1184 #endif 1185 #if defined(CLOCK_IP_HAS_EDMA0_TCD1_CLK) 1186 EDMA0_TCD1_CLK = CLOCK_IP_HAS_EDMA0_TCD1_CLK, 1187 #endif 1188 #if defined(CLOCK_IP_HAS_EDMA0_TCD2_CLK) 1189 EDMA0_TCD2_CLK = CLOCK_IP_HAS_EDMA0_TCD2_CLK, 1190 #endif 1191 #if defined(CLOCK_IP_HAS_EDMA0_TCD3_CLK) 1192 EDMA0_TCD3_CLK = CLOCK_IP_HAS_EDMA0_TCD3_CLK, 1193 #endif 1194 #if defined(CLOCK_IP_HAS_EDMA0_TCD4_CLK) 1195 EDMA0_TCD4_CLK = CLOCK_IP_HAS_EDMA0_TCD4_CLK, 1196 #endif 1197 #if defined(CLOCK_IP_HAS_EDMA0_TCD5_CLK) 1198 EDMA0_TCD5_CLK = CLOCK_IP_HAS_EDMA0_TCD5_CLK, 1199 #endif 1200 #if defined(CLOCK_IP_HAS_EDMA0_TCD6_CLK) 1201 EDMA0_TCD6_CLK = CLOCK_IP_HAS_EDMA0_TCD6_CLK, 1202 #endif 1203 #if defined(CLOCK_IP_HAS_EDMA0_TCD7_CLK) 1204 EDMA0_TCD7_CLK = CLOCK_IP_HAS_EDMA0_TCD7_CLK, 1205 #endif 1206 #if defined(CLOCK_IP_HAS_EDMA0_TCD8_CLK) 1207 EDMA0_TCD8_CLK = CLOCK_IP_HAS_EDMA0_TCD8_CLK, 1208 #endif 1209 #if defined(CLOCK_IP_HAS_EDMA0_TCD9_CLK) 1210 EDMA0_TCD9_CLK = CLOCK_IP_HAS_EDMA0_TCD9_CLK, 1211 #endif 1212 #if defined(CLOCK_IP_HAS_EDMA0_TCD10_CLK) 1213 EDMA0_TCD10_CLK = CLOCK_IP_HAS_EDMA0_TCD10_CLK, 1214 #endif 1215 #if defined(CLOCK_IP_HAS_EDMA0_TCD11_CLK) 1216 EDMA0_TCD11_CLK = CLOCK_IP_HAS_EDMA0_TCD11_CLK, 1217 #endif 1218 #if defined(CLOCK_IP_HAS_EDMA0_TCD12_CLK) 1219 EDMA0_TCD12_CLK = CLOCK_IP_HAS_EDMA0_TCD12_CLK, 1220 #endif 1221 #if defined(CLOCK_IP_HAS_EDMA0_TCD13_CLK) 1222 EDMA0_TCD13_CLK = CLOCK_IP_HAS_EDMA0_TCD13_CLK, 1223 #endif 1224 #if defined(CLOCK_IP_HAS_EDMA0_TCD14_CLK) 1225 EDMA0_TCD14_CLK = CLOCK_IP_HAS_EDMA0_TCD14_CLK, 1226 #endif 1227 #if defined(CLOCK_IP_HAS_EDMA0_TCD15_CLK) 1228 EDMA0_TCD15_CLK = CLOCK_IP_HAS_EDMA0_TCD15_CLK, 1229 #endif 1230 #if defined(CLOCK_IP_HAS_EDMA0_TCD16_CLK) 1231 EDMA0_TCD16_CLK = CLOCK_IP_HAS_EDMA0_TCD16_CLK, 1232 #endif 1233 #if defined(CLOCK_IP_HAS_EDMA0_TCD17_CLK) 1234 EDMA0_TCD17_CLK = CLOCK_IP_HAS_EDMA0_TCD17_CLK, 1235 #endif 1236 #if defined(CLOCK_IP_HAS_EDMA0_TCD18_CLK) 1237 EDMA0_TCD18_CLK = CLOCK_IP_HAS_EDMA0_TCD18_CLK, 1238 #endif 1239 #if defined(CLOCK_IP_HAS_EDMA0_TCD19_CLK) 1240 EDMA0_TCD19_CLK = CLOCK_IP_HAS_EDMA0_TCD19_CLK, 1241 #endif 1242 #if defined(CLOCK_IP_HAS_EDMA0_TCD20_CLK) 1243 EDMA0_TCD20_CLK = CLOCK_IP_HAS_EDMA0_TCD20_CLK, 1244 #endif 1245 #if defined(CLOCK_IP_HAS_EDMA0_TCD21_CLK) 1246 EDMA0_TCD21_CLK = CLOCK_IP_HAS_EDMA0_TCD21_CLK, 1247 #endif 1248 #if defined(CLOCK_IP_HAS_EDMA0_TCD22_CLK) 1249 EDMA0_TCD22_CLK = CLOCK_IP_HAS_EDMA0_TCD22_CLK, 1250 #endif 1251 #if defined(CLOCK_IP_HAS_EDMA0_TCD23_CLK) 1252 EDMA0_TCD23_CLK = CLOCK_IP_HAS_EDMA0_TCD23_CLK, 1253 #endif 1254 #if defined(CLOCK_IP_HAS_EDMA0_TCD24_CLK) 1255 EDMA0_TCD24_CLK = CLOCK_IP_HAS_EDMA0_TCD24_CLK, 1256 #endif 1257 #if defined(CLOCK_IP_HAS_EDMA0_TCD25_CLK) 1258 EDMA0_TCD25_CLK = CLOCK_IP_HAS_EDMA0_TCD25_CLK, 1259 #endif 1260 #if defined(CLOCK_IP_HAS_EDMA0_TCD26_CLK) 1261 EDMA0_TCD26_CLK = CLOCK_IP_HAS_EDMA0_TCD26_CLK, 1262 #endif 1263 #if defined(CLOCK_IP_HAS_EDMA0_TCD27_CLK) 1264 EDMA0_TCD27_CLK = CLOCK_IP_HAS_EDMA0_TCD27_CLK, 1265 #endif 1266 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 1267 EDMA0_TCD28_CLK = CLOCK_IP_HAS_EDMA0_TCD28_CLK, 1268 #endif 1269 #if defined(CLOCK_IP_HAS_EDMA0_TCD29_CLK) 1270 EDMA0_TCD29_CLK = CLOCK_IP_HAS_EDMA0_TCD29_CLK, 1271 #endif 1272 #if defined(CLOCK_IP_HAS_EDMA0_TCD30_CLK) 1273 EDMA0_TCD30_CLK = CLOCK_IP_HAS_EDMA0_TCD30_CLK, 1274 #endif 1275 #if defined(CLOCK_IP_HAS_EDMA0_TCD31_CLK) 1276 EDMA0_TCD31_CLK = CLOCK_IP_HAS_EDMA0_TCD31_CLK, 1277 #endif 1278 #if defined(CLOCK_IP_HAS_EDMA1_CLK) 1279 EDMA1_CLK = CLOCK_IP_HAS_EDMA1_CLK, 1280 #endif 1281 #if defined(CLOCK_IP_HAS_EDMA1_TCD0_CLK) 1282 EDMA1_TCD0_CLK = CLOCK_IP_HAS_EDMA1_TCD0_CLK, 1283 #endif 1284 #if defined(CLOCK_IP_HAS_EDMA1_TCD1_CLK) 1285 EDMA1_TCD1_CLK = CLOCK_IP_HAS_EDMA1_TCD1_CLK, 1286 #endif 1287 #if defined(CLOCK_IP_HAS_EDMA1_TCD2_CLK) 1288 EDMA1_TCD2_CLK = CLOCK_IP_HAS_EDMA1_TCD2_CLK, 1289 #endif 1290 #if defined(CLOCK_IP_HAS_EDMA1_TCD3_CLK) 1291 EDMA1_TCD3_CLK = CLOCK_IP_HAS_EDMA1_TCD3_CLK, 1292 #endif 1293 #if defined(CLOCK_IP_HAS_EDMA1_TCD4_CLK) 1294 EDMA1_TCD4_CLK = CLOCK_IP_HAS_EDMA1_TCD4_CLK, 1295 #endif 1296 #if defined(CLOCK_IP_HAS_EDMA1_TCD5_CLK) 1297 EDMA1_TCD5_CLK = CLOCK_IP_HAS_EDMA1_TCD5_CLK, 1298 #endif 1299 #if defined(CLOCK_IP_HAS_EDMA1_TCD6_CLK) 1300 EDMA1_TCD6_CLK = CLOCK_IP_HAS_EDMA1_TCD6_CLK, 1301 #endif 1302 #if defined(CLOCK_IP_HAS_EDMA1_TCD7_CLK) 1303 EDMA1_TCD7_CLK = CLOCK_IP_HAS_EDMA1_TCD7_CLK, 1304 #endif 1305 #if defined(CLOCK_IP_HAS_EDMA1_TCD8_CLK) 1306 EDMA1_TCD8_CLK = CLOCK_IP_HAS_EDMA1_TCD8_CLK, 1307 #endif 1308 #if defined(CLOCK_IP_HAS_EDMA1_TCD9_CLK) 1309 EDMA1_TCD9_CLK = CLOCK_IP_HAS_EDMA1_TCD9_CLK, 1310 #endif 1311 #if defined(CLOCK_IP_HAS_EDMA1_TCD10_CLK) 1312 EDMA1_TCD10_CLK = CLOCK_IP_HAS_EDMA1_TCD10_CLK, 1313 #endif 1314 #if defined(CLOCK_IP_HAS_EDMA1_TCD11_CLK) 1315 EDMA1_TCD11_CLK = CLOCK_IP_HAS_EDMA1_TCD11_CLK, 1316 #endif 1317 #if defined(CLOCK_IP_HAS_EDMA1_TCD12_CLK) 1318 EDMA1_TCD12_CLK = CLOCK_IP_HAS_EDMA1_TCD12_CLK, 1319 #endif 1320 #if defined(CLOCK_IP_HAS_EDMA1_TCD13_CLK) 1321 EDMA1_TCD13_CLK = CLOCK_IP_HAS_EDMA1_TCD13_CLK, 1322 #endif 1323 #if defined(CLOCK_IP_HAS_EDMA1_TCD14_CLK) 1324 EDMA1_TCD14_CLK = CLOCK_IP_HAS_EDMA1_TCD14_CLK, 1325 #endif 1326 #if defined(CLOCK_IP_HAS_EDMA1_TCD15_CLK) 1327 EDMA1_TCD15_CLK = CLOCK_IP_HAS_EDMA1_TCD15_CLK, 1328 #endif 1329 #if defined(CLOCK_IP_HAS_EDMA1_TCD16_CLK) 1330 EDMA1_TCD16_CLK = CLOCK_IP_HAS_EDMA1_TCD16_CLK, 1331 #endif 1332 #if defined(CLOCK_IP_HAS_EDMA1_TCD17_CLK) 1333 EDMA1_TCD17_CLK = CLOCK_IP_HAS_EDMA1_TCD17_CLK, 1334 #endif 1335 #if defined(CLOCK_IP_HAS_EDMA1_TCD18_CLK) 1336 EDMA1_TCD18_CLK = CLOCK_IP_HAS_EDMA1_TCD18_CLK, 1337 #endif 1338 #if defined(CLOCK_IP_HAS_EDMA1_TCD19_CLK) 1339 EDMA1_TCD19_CLK = CLOCK_IP_HAS_EDMA1_TCD19_CLK, 1340 #endif 1341 #if defined(CLOCK_IP_HAS_EDMA1_TCD20_CLK) 1342 EDMA1_TCD20_CLK = CLOCK_IP_HAS_EDMA1_TCD20_CLK, 1343 #endif 1344 #if defined(CLOCK_IP_HAS_EDMA1_TCD21_CLK) 1345 EDMA1_TCD21_CLK = CLOCK_IP_HAS_EDMA1_TCD21_CLK, 1346 #endif 1347 #if defined(CLOCK_IP_HAS_EDMA1_TCD22_CLK) 1348 EDMA1_TCD22_CLK = CLOCK_IP_HAS_EDMA1_TCD22_CLK, 1349 #endif 1350 #if defined(CLOCK_IP_HAS_EDMA1_TCD23_CLK) 1351 EDMA1_TCD23_CLK = CLOCK_IP_HAS_EDMA1_TCD23_CLK, 1352 #endif 1353 #if defined(CLOCK_IP_HAS_EDMA1_TCD24_CLK) 1354 EDMA1_TCD24_CLK = CLOCK_IP_HAS_EDMA1_TCD24_CLK, 1355 #endif 1356 #if defined(CLOCK_IP_HAS_EDMA1_TCD25_CLK) 1357 EDMA1_TCD25_CLK = CLOCK_IP_HAS_EDMA1_TCD25_CLK, 1358 #endif 1359 #if defined(CLOCK_IP_HAS_EDMA1_TCD26_CLK) 1360 EDMA1_TCD26_CLK = CLOCK_IP_HAS_EDMA1_TCD26_CLK, 1361 #endif 1362 #if defined(CLOCK_IP_HAS_EDMA1_TCD27_CLK) 1363 EDMA1_TCD27_CLK = CLOCK_IP_HAS_EDMA1_TCD27_CLK, 1364 #endif 1365 #if defined(CLOCK_IP_HAS_EDMA1_TCD28_CLK) 1366 EDMA1_TCD28_CLK = CLOCK_IP_HAS_EDMA1_TCD28_CLK, 1367 #endif 1368 #if defined(CLOCK_IP_HAS_EDMA1_TCD29_CLK) 1369 EDMA1_TCD29_CLK = CLOCK_IP_HAS_EDMA1_TCD29_CLK, 1370 #endif 1371 #if defined(CLOCK_IP_HAS_EDMA1_TCD30_CLK) 1372 EDMA1_TCD30_CLK = CLOCK_IP_HAS_EDMA1_TCD30_CLK, 1373 #endif 1374 #if defined(CLOCK_IP_HAS_EDMA1_TCD31_CLK) 1375 EDMA1_TCD31_CLK = CLOCK_IP_HAS_EDMA1_TCD31_CLK, 1376 #endif 1377 #if defined(CLOCK_IP_HAS_EDMA3_CLK) 1378 EDMA3_CLK = CLOCK_IP_HAS_EDMA3_CLK, 1379 #endif 1380 #if defined(CLOCK_IP_HAS_EDMA4_CLK) 1381 EDMA4_CLK = CLOCK_IP_HAS_EDMA4_CLK, 1382 #endif 1383 #if defined(CLOCK_IP_HAS_EDMA5_CLK) 1384 EDMA5_CLK = CLOCK_IP_HAS_EDMA5_CLK, 1385 #endif 1386 #if defined(CLOCK_IP_HAS_EFLEX_PWM0_CLK) 1387 EFLEX_PWM0_CLK = CLOCK_IP_HAS_EFLEX_PWM0_CLK, 1388 #endif 1389 #if defined(CLOCK_IP_HAS_EFLEX_PWM1_CLK) 1390 EFLEX_PWM1_CLK = CLOCK_IP_HAS_EFLEX_PWM1_CLK, 1391 #endif 1392 #if defined(CLOCK_IP_HAS_FDMA0_CLK) 1393 FDMA0_CLK = CLOCK_IP_HAS_FDMA0_CLK, 1394 #endif 1395 #if defined(CLOCK_IP_HAS_ENET_CLK) 1396 ENET_CLK = CLOCK_IP_HAS_ENET_CLK, 1397 #endif 1398 #if defined(CLOCK_IP_HAS_EIM_CLK) 1399 EIM_CLK = CLOCK_IP_HAS_EIM_CLK, 1400 #endif 1401 #if defined(CLOCK_IP_HAS_EIM0_CLK) 1402 EIM0_CLK = CLOCK_IP_HAS_EIM0_CLK, 1403 #endif 1404 #if defined(CLOCK_IP_HAS_EIM1_CLK) 1405 EIM1_CLK = CLOCK_IP_HAS_EIM1_CLK, 1406 #endif 1407 #if defined(CLOCK_IP_HAS_EIM2_CLK) 1408 EIM2_CLK = CLOCK_IP_HAS_EIM2_CLK, 1409 #endif 1410 #if defined(CLOCK_IP_HAS_EIM3_CLK) 1411 EIM3_CLK = CLOCK_IP_HAS_EIM3_CLK, 1412 #endif 1413 #if defined(CLOCK_IP_HAS_EIM_BBE32DSP_CLK) 1414 EIM_BBE32DSP_CLK = CLOCK_IP_HAS_EIM_BBE32DSP_CLK, 1415 #endif 1416 #if defined(CLOCK_IP_HAS_EIM_LAX0_CLK) 1417 EIM_LAX0_CLK = CLOCK_IP_HAS_EIM_LAX0_CLK, 1418 #endif 1419 #if defined(CLOCK_IP_HAS_EIM_LAX1_CLK) 1420 EIM_LAX1_CLK = CLOCK_IP_HAS_EIM_LAX1_CLK, 1421 #endif 1422 #if defined(CLOCK_IP_HAS_EIM_PER1_CLK) 1423 EIM_PER1_CLK = CLOCK_IP_HAS_EIM_PER1_CLK, 1424 #endif 1425 #if defined(CLOCK_IP_HAS_ENET0_CLK) 1426 ENET0_CLK = CLOCK_IP_HAS_ENET0_CLK, 1427 #endif 1428 #if defined(CLOCK_IP_HAS_ENET1_CLK) 1429 ENET1_CLK = CLOCK_IP_HAS_ENET1_CLK, 1430 #endif 1431 #if defined(CLOCK_IP_HAS_EMAC_RX_CLK) 1432 EMAC_RX_CLK = CLOCK_IP_HAS_EMAC_RX_CLK, 1433 #endif 1434 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK) 1435 EMAC_TS_CLK = CLOCK_IP_HAS_EMAC_TS_CLK, 1436 #endif 1437 #if defined(CLOCK_IP_HAS_EMAC_TX_CLK) 1438 EMAC_TX_CLK = CLOCK_IP_HAS_EMAC_TX_CLK, 1439 #endif 1440 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK) 1441 EMAC_TX_RMII_CLK = CLOCK_IP_HAS_EMAC_TX_RMII_CLK, 1442 #endif 1443 #if defined(CLOCK_IP_HAS_EMAC0_RX_CLK) 1444 EMAC0_RX_CLK = CLOCK_IP_HAS_EMAC0_RX_CLK, 1445 #endif 1446 #if defined(CLOCK_IP_HAS_EMAC0_TS_CLK) 1447 EMAC0_TS_CLK = CLOCK_IP_HAS_EMAC0_TS_CLK, 1448 #endif 1449 #if defined(CLOCK_IP_HAS_EMAC0_TX_CLK) 1450 EMAC0_TX_CLK = CLOCK_IP_HAS_EMAC0_TX_CLK, 1451 #endif 1452 #if defined(CLOCK_IP_HAS_EMIOS0_CLK) 1453 EMIOS0_CLK = CLOCK_IP_HAS_EMIOS0_CLK, 1454 #endif 1455 #if defined(CLOCK_IP_HAS_EMIOS1_CLK) 1456 EMIOS1_CLK = CLOCK_IP_HAS_EMIOS1_CLK, 1457 #endif 1458 #if defined(CLOCK_IP_HAS_EMIOS2_CLK) 1459 EMIOS2_CLK = CLOCK_IP_HAS_EMIOS2_CLK, 1460 #endif 1461 #if defined(CLOCK_IP_HAS_ERM0_CLK) 1462 ERM0_CLK = CLOCK_IP_HAS_ERM0_CLK, 1463 #endif 1464 #if defined(CLOCK_IP_HAS_ERM1_CLK) 1465 ERM1_CLK = CLOCK_IP_HAS_ERM1_CLK, 1466 #endif 1467 #if defined(CLOCK_IP_HAS_ERM_CPU0_CLK) 1468 ERM_CPU0_CLK = CLOCK_IP_HAS_ERM_CPU0_CLK, 1469 #endif 1470 #if defined(CLOCK_IP_HAS_ERM_CPU1_CLK) 1471 ERM_CPU1_CLK = CLOCK_IP_HAS_ERM_CPU1_CLK, 1472 #endif 1473 #if defined(CLOCK_IP_HAS_ERM_CPU2_CLK) 1474 ERM_CPU2_CLK = CLOCK_IP_HAS_ERM_CPU2_CLK, 1475 #endif 1476 #if defined(CLOCK_IP_HAS_ERM_EDMA0_CLK) 1477 ERM_EDMA0_CLK = CLOCK_IP_HAS_ERM_EDMA0_CLK, 1478 #endif 1479 #if defined(CLOCK_IP_HAS_ERM_EDMA1_CLK) 1480 ERM_EDMA1_CLK = CLOCK_IP_HAS_ERM_EDMA1_CLK, 1481 #endif 1482 #if defined(CLOCK_IP_HAS_ERM_LAX0_CLK) 1483 ERM_LAX0_CLK = CLOCK_IP_HAS_ERM_LAX0_CLK, 1484 #endif 1485 #if defined(CLOCK_IP_HAS_ERM_LAX1_CLK) 1486 ERM_LAX1_CLK = CLOCK_IP_HAS_ERM_LAX1_CLK, 1487 #endif 1488 #if defined(CLOCK_IP_HAS_ERM_PER_CLK) 1489 ERM_PER_CLK = CLOCK_IP_HAS_ERM_PER_CLK, 1490 #endif 1491 #if defined(CLOCK_IP_HAS_ERM_PER1_CLK) 1492 ERM_PER1_CLK = CLOCK_IP_HAS_ERM_PER1_CLK, 1493 #endif 1494 #if defined(CLOCK_IP_HAS_ERM_CLK) 1495 ERM_CLK = CLOCK_IP_HAS_ERM_CLK, 1496 #endif 1497 #if defined(CLOCK_IP_HAS_EWM0_CLK) 1498 EWM0_CLK = CLOCK_IP_HAS_EWM0_CLK, 1499 #endif 1500 #if defined(CLOCK_IP_HAS_FIRC_MON1_CLK) 1501 FIRC_MON1_CLK = CLOCK_IP_HAS_FIRC_MON1_CLK, 1502 #endif 1503 #if defined(CLOCK_IP_HAS_FIRC_MON2_CLK) 1504 FIRC_MON2_CLK = CLOCK_IP_HAS_FIRC_MON2_CLK, 1505 #endif 1506 #if defined(CLOCK_IP_HAS_FLASH0_CLK) 1507 FLASH0_CLK = CLOCK_IP_HAS_FLASH0_CLK, 1508 #endif 1509 #if defined(CLOCK_IP_HAS_CAN_PE_CLK) 1510 CAN_PE_CLK = CLOCK_IP_HAS_CAN_PE_CLK, 1511 #endif 1512 #if defined(CLOCK_IP_HAS_FLEXCAN_CLK) 1513 FLEXCAN_CLK = CLOCK_IP_HAS_FLEXCAN_CLK, 1514 #endif 1515 #if defined(CLOCK_IP_HAS_FLEXCAN0_CLK) 1516 FLEXCAN0_CLK = CLOCK_IP_HAS_FLEXCAN0_CLK, 1517 #endif 1518 #if defined(CLOCK_IP_HAS_FLEXCAN1_CLK) 1519 FLEXCAN1_CLK = CLOCK_IP_HAS_FLEXCAN1_CLK, 1520 #endif 1521 #if defined(CLOCK_IP_HAS_FLEXCAN2_CLK) 1522 FLEXCAN2_CLK = CLOCK_IP_HAS_FLEXCAN2_CLK, 1523 #endif 1524 #if defined(CLOCK_IP_HAS_FLEXCAN3_CLK) 1525 FLEXCAN3_CLK = CLOCK_IP_HAS_FLEXCAN3_CLK, 1526 #endif 1527 #if defined(CLOCK_IP_HAS_FLEXCAN4_CLK) 1528 FLEXCAN4_CLK = CLOCK_IP_HAS_FLEXCAN4_CLK, 1529 #endif 1530 #if defined(CLOCK_IP_HAS_FLEXCAN5_CLK) 1531 FLEXCAN5_CLK = CLOCK_IP_HAS_FLEXCAN5_CLK, 1532 #endif 1533 #if defined(CLOCK_IP_HAS_FLEXCAN6_CLK) 1534 FLEXCAN6_CLK = CLOCK_IP_HAS_FLEXCAN6_CLK, 1535 #endif 1536 #if defined(CLOCK_IP_HAS_FLEXCAN7_CLK) 1537 FLEXCAN7_CLK = CLOCK_IP_HAS_FLEXCAN7_CLK, 1538 #endif 1539 #if defined(CLOCK_IP_HAS_FLEXCAN8_CLK) 1540 FLEXCAN8_CLK = CLOCK_IP_HAS_FLEXCAN8_CLK, 1541 #endif 1542 #if defined(CLOCK_IP_HAS_FLEXCAN9_CLK) 1543 FLEXCAN9_CLK = CLOCK_IP_HAS_FLEXCAN9_CLK, 1544 #endif 1545 #if defined(CLOCK_IP_HAS_FLEXCAN10_CLK) 1546 FLEXCAN10_CLK = CLOCK_IP_HAS_FLEXCAN10_CLK, 1547 #endif 1548 #if defined(CLOCK_IP_HAS_FLEXCAN11_CLK) 1549 FLEXCAN11_CLK = CLOCK_IP_HAS_FLEXCAN11_CLK, 1550 #endif 1551 #if defined(CLOCK_IP_HAS_FLEXCAN12_CLK) 1552 FLEXCAN12_CLK = CLOCK_IP_HAS_FLEXCAN12_CLK, 1553 #endif 1554 #if defined(CLOCK_IP_HAS_FLEXCAN13_CLK) 1555 FLEXCAN13_CLK = CLOCK_IP_HAS_FLEXCAN13_CLK, 1556 #endif 1557 #if defined(CLOCK_IP_HAS_FLEXCAN14_CLK) 1558 FLEXCAN14_CLK = CLOCK_IP_HAS_FLEXCAN14_CLK, 1559 #endif 1560 #if defined(CLOCK_IP_HAS_FLEXCAN15_CLK) 1561 FLEXCAN15_CLK = CLOCK_IP_HAS_FLEXCAN15_CLK, 1562 #endif 1563 #if defined(CLOCK_IP_HAS_FLEXCAN16_CLK) 1564 FLEXCAN16_CLK = CLOCK_IP_HAS_FLEXCAN16_CLK, 1565 #endif 1566 #if defined(CLOCK_IP_HAS_FLEXCAN17_CLK) 1567 FLEXCAN17_CLK = CLOCK_IP_HAS_FLEXCAN17_CLK, 1568 #endif 1569 #if defined(CLOCK_IP_HAS_FLEXCAN18_CLK) 1570 FLEXCAN18_CLK = CLOCK_IP_HAS_FLEXCAN18_CLK, 1571 #endif 1572 #if defined(CLOCK_IP_HAS_FLEXCAN19_CLK) 1573 FLEXCAN19_CLK = CLOCK_IP_HAS_FLEXCAN19_CLK, 1574 #endif 1575 #if defined(CLOCK_IP_HAS_FLEXCAN20_CLK) 1576 FLEXCAN20_CLK = CLOCK_IP_HAS_FLEXCAN20_CLK, 1577 #endif 1578 #if defined(CLOCK_IP_HAS_FLEXCAN21_CLK) 1579 FLEXCAN21_CLK = CLOCK_IP_HAS_FLEXCAN21_CLK, 1580 #endif 1581 #if defined(CLOCK_IP_HAS_FLEXCAN22_CLK) 1582 FLEXCAN22_CLK = CLOCK_IP_HAS_FLEXCAN22_CLK, 1583 #endif 1584 #if defined(CLOCK_IP_HAS_FLEXCAN23_CLK) 1585 FLEXCAN23_CLK = CLOCK_IP_HAS_FLEXCAN23_CLK, 1586 #endif 1587 #if defined(CLOCK_IP_HAS_FLEXCANA_CLK) 1588 FLEXCANA_CLK = CLOCK_IP_HAS_FLEXCANA_CLK, 1589 #endif 1590 #if defined(CLOCK_IP_HAS_FLEXCANB_CLK) 1591 FLEXCANB_CLK = CLOCK_IP_HAS_FLEXCANB_CLK, 1592 #endif 1593 #if defined(CLOCK_IP_HAS_FlexIO_CLK) 1594 FlexIO_CLK = CLOCK_IP_HAS_FlexIO_CLK, 1595 #endif 1596 #if defined(CLOCK_IP_HAS_FlexIO0_CLK) 1597 FlexIO0_CLK = CLOCK_IP_HAS_FlexIO0_CLK, 1598 #endif 1599 #if defined(CLOCK_IP_HAS_FLEXIO0_CLK) 1600 FLEXIO0_CLK = CLOCK_IP_HAS_FLEXIO0_CLK, 1601 #endif 1602 #if defined(CLOCK_IP_HAS_FLEXRAY_CLK) 1603 FLEXRAY_CLK = CLOCK_IP_HAS_FLEXRAY_CLK, 1604 #endif 1605 #if defined(CLOCK_IP_HAS_FLEXTIMERA_CLK) 1606 FLEXTIMERA_CLK = CLOCK_IP_HAS_FLEXTIMERA_CLK, 1607 #endif 1608 #if defined(CLOCK_IP_HAS_FLEXTIMERB_CLK) 1609 FLEXTIMERB_CLK = CLOCK_IP_HAS_FLEXTIMERB_CLK, 1610 #endif 1611 #if defined(CLOCK_IP_HAS_FRAY0_CLK) 1612 FRAY0_CLK = CLOCK_IP_HAS_FRAY0_CLK, 1613 #endif 1614 #if defined(CLOCK_IP_HAS_FRAY1_CLK) 1615 FRAY1_CLK = CLOCK_IP_HAS_FRAY1_CLK, 1616 #endif 1617 #if defined(CLOCK_IP_HAS_FTFC_CLK) 1618 FTFC_CLK = CLOCK_IP_HAS_FTFC_CLK, 1619 #endif 1620 #if defined(CLOCK_IP_HAS_FTFM_CLK) 1621 FTFM_CLK = CLOCK_IP_HAS_FTFM_CLK, 1622 #endif 1623 #if defined(CLOCK_IP_HAS_FTIMER0_CLK) 1624 FTIMER0_CLK = CLOCK_IP_HAS_FTIMER0_CLK, 1625 #endif 1626 #if defined(CLOCK_IP_HAS_FTIMER1_CLK) 1627 FTIMER1_CLK = CLOCK_IP_HAS_FTIMER1_CLK, 1628 #endif 1629 #if defined(CLOCK_IP_HAS_FTM0_CLK) 1630 FTM0_CLK = CLOCK_IP_HAS_FTM0_CLK, 1631 #endif 1632 #if defined(CLOCK_IP_HAS_FTM1_CLK) 1633 FTM1_CLK = CLOCK_IP_HAS_FTM1_CLK, 1634 #endif 1635 #if defined(CLOCK_IP_HAS_FTM2_CLK) 1636 FTM2_CLK = CLOCK_IP_HAS_FTM2_CLK, 1637 #endif 1638 #if defined(CLOCK_IP_HAS_FTM3_CLK) 1639 FTM3_CLK = CLOCK_IP_HAS_FTM3_CLK, 1640 #endif 1641 #if defined(CLOCK_IP_HAS_FTM4_CLK) 1642 FTM4_CLK = CLOCK_IP_HAS_FTM4_CLK, 1643 #endif 1644 #if defined(CLOCK_IP_HAS_FTM5_CLK) 1645 FTM5_CLK = CLOCK_IP_HAS_FTM5_CLK, 1646 #endif 1647 #if defined(CLOCK_IP_HAS_FTM6_CLK) 1648 FTM6_CLK = CLOCK_IP_HAS_FTM6_CLK, 1649 #endif 1650 #if defined(CLOCK_IP_HAS_FTM7_CLK) 1651 FTM7_CLK = CLOCK_IP_HAS_FTM7_CLK, 1652 #endif 1653 #if defined(CLOCK_IP_HAS_GLB_LBIST_CLK) 1654 GLB_LBIST_CLK = CLOCK_IP_HAS_GLB_LBIST_CLK, 1655 #endif 1656 #if defined(CLOCK_IP_HAS_GMAC0_CLK) 1657 GMAC0_CLK = CLOCK_IP_HAS_GMAC0_CLK, 1658 #endif 1659 #if defined(CLOCK_IP_HAS_GMAC_TS_CLK) 1660 GMAC_TS_CLK = CLOCK_IP_HAS_GMAC_TS_CLK, 1661 #endif 1662 #if defined(CLOCK_IP_HAS_GMAC0_RX_CLK) 1663 GMAC0_RX_CLK = CLOCK_IP_HAS_GMAC0_RX_CLK, 1664 #endif 1665 #if defined(CLOCK_IP_HAS_GMAC0_TX_CLK) 1666 GMAC0_TX_CLK = CLOCK_IP_HAS_GMAC0_TX_CLK, 1667 #endif 1668 #if defined(CLOCK_IP_HAS_GMAC0_TS_CLK) 1669 GMAC0_TS_CLK = CLOCK_IP_HAS_GMAC0_TS_CLK, 1670 #endif 1671 #if defined(CLOCK_IP_HAS_GMAC0_TX_RMII_CLK) 1672 GMAC0_TX_RMII_CLK = CLOCK_IP_HAS_GMAC0_TX_RMII_CLK, 1673 #endif 1674 #if defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK) 1675 GMAC0_MII_RX_CLK = CLOCK_IP_HAS_GMAC0_MII_RX_CLK, 1676 #endif 1677 #if defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK) 1678 GMAC0_MII_RMII_TX_CLK = CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK, 1679 #endif 1680 #if defined(CLOCK_IP_HAS_GMAC1_MII_RX_CLK) 1681 GMAC1_MII_RX_CLK = CLOCK_IP_HAS_GMAC1_MII_RX_CLK, 1682 #endif 1683 #if defined(CLOCK_IP_HAS_GMAC1_RX_CLK) 1684 GMAC1_RX_CLK = CLOCK_IP_HAS_GMAC1_RX_CLK, 1685 #endif 1686 #if defined(CLOCK_IP_HAS_GMAC1_TX_CLK) 1687 GMAC1_TX_CLK = CLOCK_IP_HAS_GMAC1_TX_CLK, 1688 #endif 1689 #if defined(CLOCK_IP_HAS_GMAC1_TS_CLK) 1690 GMAC1_TS_CLK = CLOCK_IP_HAS_GMAC1_TS_CLK, 1691 #endif 1692 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK) 1693 GMAC1_RMII_CLK = CLOCK_IP_HAS_GMAC1_RMII_CLK, 1694 #endif 1695 #if defined(CLOCK_IP_HAS_GMAC1_RMII_EXT_CLK) 1696 GMAC1_RMII_EXT_CLK = CLOCK_IP_HAS_GMAC1_RMII_EXT_CLK, 1697 #endif 1698 #if defined(CLOCK_IP_HAS_GPIO0_CLK) 1699 GPIO0_CLK = CLOCK_IP_HAS_GPIO0_CLK, 1700 #endif 1701 #if defined(CLOCK_IP_HAS_GTM_CLK) 1702 GTM_CLK = CLOCK_IP_HAS_GTM_CLK, 1703 #endif 1704 #if defined(CLOCK_IP_HAS_IDIV0_CLK) 1705 IDIV0_CLK = CLOCK_IP_HAS_IDIV0_CLK, 1706 #endif 1707 #if defined(CLOCK_IP_HAS_IDIV1_CLK) 1708 IDIV1_CLK = CLOCK_IP_HAS_IDIV1_CLK, 1709 #endif 1710 #if defined(CLOCK_IP_HAS_IDIV2_CLK) 1711 IDIV2_CLK = CLOCK_IP_HAS_IDIV2_CLK, 1712 #endif 1713 #if defined(CLOCK_IP_HAS_IDIV3_CLK) 1714 IDIV3_CLK = CLOCK_IP_HAS_IDIV3_CLK, 1715 #endif 1716 #if defined(CLOCK_IP_HAS_IDIV4_CLK) 1717 IDIV4_CLK = CLOCK_IP_HAS_IDIV4_CLK, 1718 #endif 1719 #if defined(CLOCK_IP_HAS_IGF0_CLK) 1720 IGF0_CLK = CLOCK_IP_HAS_IGF0_CLK, 1721 #endif 1722 #if defined(CLOCK_IP_HAS_IIIC0_CLK) 1723 IIIC0_CLK = CLOCK_IP_HAS_IIIC0_CLK, 1724 #endif 1725 #if defined(CLOCK_IP_HAS_IIIC1_CLK) 1726 IIIC1_CLK = CLOCK_IP_HAS_IIIC1_CLK, 1727 #endif 1728 #if defined(CLOCK_IP_HAS_IIIC2_CLK) 1729 IIIC2_CLK = CLOCK_IP_HAS_IIIC2_CLK, 1730 #endif 1731 #if defined(CLOCK_IP_HAS_IIC0_CLK) 1732 IIC0_CLK = CLOCK_IP_HAS_IIC0_CLK, 1733 #endif 1734 #if defined(CLOCK_IP_HAS_IIC1_CLK) 1735 IIC1_CLK = CLOCK_IP_HAS_IIC1_CLK, 1736 #endif 1737 #if defined(CLOCK_IP_HAS_IIC2_CLK) 1738 IIC2_CLK = CLOCK_IP_HAS_IIC2_CLK, 1739 #endif 1740 #if defined(CLOCK_IP_HAS_IIC3_CLK) 1741 IIC3_CLK = CLOCK_IP_HAS_IIC3_CLK, 1742 #endif 1743 #if defined(CLOCK_IP_HAS_IIC4_CLK) 1744 IIC4_CLK = CLOCK_IP_HAS_IIC4_CLK, 1745 #endif 1746 #if defined(CLOCK_IP_HAS_INTM_CLK) 1747 INTM_CLK = CLOCK_IP_HAS_INTM_CLK, 1748 #endif 1749 #if defined(CLOCK_IP_HAS_ISO_CLK) 1750 ISO_CLK = CLOCK_IP_HAS_ISO_CLK, 1751 #endif 1752 #if defined(CLOCK_IP_HAS_LBIST0_CLK) 1753 LBIST0_CLK = CLOCK_IP_HAS_LBIST0_CLK, 1754 #endif 1755 #if defined(CLOCK_IP_HAS_LBIST1_CLK) 1756 LBIST1_CLK = CLOCK_IP_HAS_LBIST1_CLK, 1757 #endif 1758 #if defined(CLOCK_IP_HAS_LBIST2_CLK) 1759 LBIST2_CLK = CLOCK_IP_HAS_LBIST2_CLK, 1760 #endif 1761 #if defined(CLOCK_IP_HAS_LBIST3_CLK) 1762 LBIST3_CLK = CLOCK_IP_HAS_LBIST3_CLK, 1763 #endif 1764 #if defined(CLOCK_IP_HAS_LBIST4_CLK) 1765 LBIST4_CLK = CLOCK_IP_HAS_LBIST4_CLK, 1766 #endif 1767 #if defined(CLOCK_IP_HAS_LBIST5_CLK) 1768 LBIST5_CLK = CLOCK_IP_HAS_LBIST5_CLK, 1769 #endif 1770 #if defined(CLOCK_IP_HAS_LBIST6_CLK) 1771 LBIST6_CLK = CLOCK_IP_HAS_LBIST6_CLK, 1772 #endif 1773 #if defined(CLOCK_IP_HAS_LBIST7_CLK) 1774 LBIST7_CLK = CLOCK_IP_HAS_LBIST7_CLK, 1775 #endif 1776 #if defined(CLOCK_IP_HAS_LCU0_CLK) 1777 LCU0_CLK = CLOCK_IP_HAS_LCU0_CLK, 1778 #endif 1779 #if defined(CLOCK_IP_HAS_LCU1_CLK) 1780 LCU1_CLK = CLOCK_IP_HAS_LCU1_CLK, 1781 #endif 1782 #if defined(CLOCK_IP_HAS_LIN_BAUD_CLK) 1783 LIN_BAUD_CLK = CLOCK_IP_HAS_LIN_BAUD_CLK, 1784 #endif 1785 #if defined(CLOCK_IP_HAS_LINFLEXD_CLK) 1786 LINFLEXD_CLK = CLOCK_IP_HAS_LINFLEXD_CLK, 1787 #endif 1788 #if defined(CLOCK_IP_HAS_LIN0_CLK) 1789 LIN0_CLK = CLOCK_IP_HAS_LIN0_CLK, 1790 #endif 1791 #if defined(CLOCK_IP_HAS_LIN1_CLK) 1792 LIN1_CLK = CLOCK_IP_HAS_LIN1_CLK, 1793 #endif 1794 #if defined(CLOCK_IP_HAS_LIN2_CLK) 1795 LIN2_CLK = CLOCK_IP_HAS_LIN2_CLK, 1796 #endif 1797 #if defined(CLOCK_IP_HAS_LIN3_CLK) 1798 LIN3_CLK = CLOCK_IP_HAS_LIN3_CLK, 1799 #endif 1800 #if defined(CLOCK_IP_HAS_LIN4_CLK) 1801 LIN4_CLK = CLOCK_IP_HAS_LIN4_CLK, 1802 #endif 1803 #if defined(CLOCK_IP_HAS_LIN5_CLK) 1804 LIN5_CLK = CLOCK_IP_HAS_LIN5_CLK, 1805 #endif 1806 #if defined(CLOCK_IP_HAS_LIN6_CLK) 1807 LIN6_CLK = CLOCK_IP_HAS_LIN6_CLK, 1808 #endif 1809 #if defined(CLOCK_IP_HAS_LIN7_CLK) 1810 LIN7_CLK = CLOCK_IP_HAS_LIN7_CLK, 1811 #endif 1812 #if defined(CLOCK_IP_HAS_LIN8_CLK) 1813 LIN8_CLK = CLOCK_IP_HAS_LIN8_CLK, 1814 #endif 1815 #if defined(CLOCK_IP_HAS_LIN9_CLK) 1816 LIN9_CLK = CLOCK_IP_HAS_LIN9_CLK, 1817 #endif 1818 #if defined(CLOCK_IP_HAS_LIN10_CLK) 1819 LIN10_CLK = CLOCK_IP_HAS_LIN10_CLK, 1820 #endif 1821 #if defined(CLOCK_IP_HAS_LIN11_CLK) 1822 LIN11_CLK = CLOCK_IP_HAS_LIN11_CLK, 1823 #endif 1824 #if defined(CLOCK_IP_HAS_LFAST_REF_CLK) 1825 LFAST_REF_CLK = CLOCK_IP_HAS_LFAST_REF_CLK, 1826 #endif 1827 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK) 1828 LFAST_REF_EXT_CLK = CLOCK_IP_HAS_LFAST_REF_EXT_CLK, 1829 #endif 1830 #if defined(CLOCK_IP_HAS_LPI2C0_CLK) 1831 LPI2C0_CLK = CLOCK_IP_HAS_LPI2C0_CLK, 1832 #endif 1833 #if defined(CLOCK_IP_HAS_LPI2C1_CLK) 1834 LPI2C1_CLK = CLOCK_IP_HAS_LPI2C1_CLK, 1835 #endif 1836 #if defined(CLOCK_IP_HAS_LPIT0_CLK) 1837 LPIT0_CLK = CLOCK_IP_HAS_LPIT0_CLK, 1838 #endif 1839 #if defined(CLOCK_IP_HAS_LPSPI_CLK) 1840 LPSPI_CLK = CLOCK_IP_HAS_LPSPI_CLK, 1841 #endif 1842 #if defined(CLOCK_IP_HAS_LPSPI0_CLK) 1843 LPSPI0_CLK = CLOCK_IP_HAS_LPSPI0_CLK, 1844 #endif 1845 #if defined(CLOCK_IP_HAS_LPSPI1_CLK) 1846 LPSPI1_CLK = CLOCK_IP_HAS_LPSPI1_CLK, 1847 #endif 1848 #if defined(CLOCK_IP_HAS_LPSPI2_CLK) 1849 LPSPI2_CLK = CLOCK_IP_HAS_LPSPI2_CLK, 1850 #endif 1851 #if defined(CLOCK_IP_HAS_LPSPI3_CLK) 1852 LPSPI3_CLK = CLOCK_IP_HAS_LPSPI3_CLK, 1853 #endif 1854 #if defined(CLOCK_IP_HAS_LPSPI4_CLK) 1855 LPSPI4_CLK = CLOCK_IP_HAS_LPSPI4_CLK, 1856 #endif 1857 #if defined(CLOCK_IP_HAS_LPSPI5_CLK) 1858 LPSPI5_CLK = CLOCK_IP_HAS_LPSPI5_CLK, 1859 #endif 1860 #if defined(CLOCK_IP_HAS_LPTMR0_CLK) 1861 LPTMR0_CLK = CLOCK_IP_HAS_LPTMR0_CLK, 1862 #endif 1863 #if defined(CLOCK_IP_HAS_LPUART0_CLK) 1864 LPUART0_CLK = CLOCK_IP_HAS_LPUART0_CLK, 1865 #endif 1866 #if defined(CLOCK_IP_HAS_LPUART1_CLK) 1867 LPUART1_CLK = CLOCK_IP_HAS_LPUART1_CLK, 1868 #endif 1869 #if defined(CLOCK_IP_HAS_LPUART2_CLK) 1870 LPUART2_CLK = CLOCK_IP_HAS_LPUART2_CLK, 1871 #endif 1872 #if defined(CLOCK_IP_HAS_LPUART3_CLK) 1873 LPUART3_CLK = CLOCK_IP_HAS_LPUART3_CLK, 1874 #endif 1875 #if defined(CLOCK_IP_HAS_LPUART4_CLK) 1876 LPUART4_CLK = CLOCK_IP_HAS_LPUART4_CLK, 1877 #endif 1878 #if defined(CLOCK_IP_HAS_LPUART5_CLK) 1879 LPUART5_CLK = CLOCK_IP_HAS_LPUART5_CLK, 1880 #endif 1881 #if defined(CLOCK_IP_HAS_LPUART6_CLK) 1882 LPUART6_CLK = CLOCK_IP_HAS_LPUART6_CLK, 1883 #endif 1884 #if defined(CLOCK_IP_HAS_LPUART7_CLK) 1885 LPUART7_CLK = CLOCK_IP_HAS_LPUART7_CLK, 1886 #endif 1887 #if defined(CLOCK_IP_HAS_LPUART8_CLK) 1888 LPUART8_CLK = CLOCK_IP_HAS_LPUART8_CLK, 1889 #endif 1890 #if defined(CLOCK_IP_HAS_LPUART9_CLK) 1891 LPUART9_CLK = CLOCK_IP_HAS_LPUART9_CLK, 1892 #endif 1893 #if defined(CLOCK_IP_HAS_LPUART10_CLK) 1894 LPUART10_CLK = CLOCK_IP_HAS_LPUART10_CLK, 1895 #endif 1896 #if defined(CLOCK_IP_HAS_LPUART11_CLK) 1897 LPUART11_CLK = CLOCK_IP_HAS_LPUART11_CLK, 1898 #endif 1899 #if defined(CLOCK_IP_HAS_LPUART12_CLK) 1900 LPUART12_CLK = CLOCK_IP_HAS_LPUART12_CLK, 1901 #endif 1902 #if defined(CLOCK_IP_HAS_LPUART13_CLK) 1903 LPUART13_CLK = CLOCK_IP_HAS_LPUART13_CLK, 1904 #endif 1905 #if defined(CLOCK_IP_HAS_LPUART14_CLK) 1906 LPUART14_CLK = CLOCK_IP_HAS_LPUART14_CLK, 1907 #endif 1908 #if defined(CLOCK_IP_HAS_LPUART15_CLK) 1909 LPUART15_CLK = CLOCK_IP_HAS_LPUART15_CLK, 1910 #endif 1911 #if defined(CLOCK_IP_HAS_LPUART_MSC_CLK) 1912 LPUART_MSC_CLK = CLOCK_IP_HAS_LPUART_MSC_CLK, 1913 #endif 1914 #if defined(CLOCK_IP_HAS_LVDS_CLK) 1915 LVDS_CLK = CLOCK_IP_HAS_LVDS_CLK, 1916 #endif 1917 #if defined(CLOCK_IP_HAS_MCSS_CLK) 1918 MCSS_CLK = CLOCK_IP_HAS_MCSS_CLK, 1919 #endif 1920 #if defined(CLOCK_IP_HAS_MPU0_CLK) 1921 MPU0_CLK = CLOCK_IP_HAS_MPU0_CLK, 1922 #endif 1923 #if defined(CLOCK_IP_HAS_MSCM_CLK) 1924 MSCM_CLK = CLOCK_IP_HAS_MSCM_CLK, 1925 #endif 1926 #if defined(CLOCK_IP_HAS_MSCM0_CLK) 1927 MSCM0_CLK = CLOCK_IP_HAS_MSCM0_CLK, 1928 #endif 1929 #if defined(CLOCK_IP_HAS_MUA_CLK) 1930 MUA_CLK = CLOCK_IP_HAS_MUA_CLK, 1931 #endif 1932 #if defined(CLOCK_IP_HAS_MUB_CLK) 1933 MUB_CLK = CLOCK_IP_HAS_MUB_CLK, 1934 #endif 1935 #if defined(CLOCK_IP_HAS_MU2A_CLK) 1936 MU2A_CLK = CLOCK_IP_HAS_MU2A_CLK, 1937 #endif 1938 #if defined(CLOCK_IP_HAS_MU2B_CLK) 1939 MU2B_CLK = CLOCK_IP_HAS_MU2B_CLK, 1940 #endif 1941 #if defined(CLOCK_IP_HAS_MU3A_CLK) 1942 MU3A_CLK = CLOCK_IP_HAS_MU3A_CLK, 1943 #endif 1944 #if defined(CLOCK_IP_HAS_MU3B_CLK) 1945 MU3B_CLK = CLOCK_IP_HAS_MU3B_CLK, 1946 #endif 1947 #if defined(CLOCK_IP_HAS_MU4A_CLK) 1948 MU4A_CLK = CLOCK_IP_HAS_MU4A_CLK, 1949 #endif 1950 #if defined(CLOCK_IP_HAS_MU4B_CLK) 1951 MU4B_CLK = CLOCK_IP_HAS_MU4B_CLK, 1952 #endif 1953 #if defined(CLOCK_IP_HAS_OCOTP_CLK) 1954 OCOTP_CLK = CLOCK_IP_HAS_OCOTP_CLK, 1955 #endif 1956 #if defined(CLOCK_IP_HAS_PDB0_CLK) 1957 PDB0_CLK = CLOCK_IP_HAS_PDB0_CLK, 1958 #endif 1959 #if defined(CLOCK_IP_HAS_PDB1_CLK) 1960 PDB1_CLK = CLOCK_IP_HAS_PDB1_CLK, 1961 #endif 1962 #if defined(CLOCK_IP_HAS_PFEMAC0_RX_CLK) 1963 PFEMAC0_RX_CLK = CLOCK_IP_HAS_PFEMAC0_RX_CLK, 1964 #endif 1965 #if defined(CLOCK_IP_HAS_PFEMAC0_TX_DIV_CLK) 1966 PFEMAC0_TX_DIV_CLK = CLOCK_IP_HAS_PFEMAC0_TX_DIV_CLK, 1967 #endif 1968 #if defined(CLOCK_IP_HAS_PFEMAC1_TX_DIV_CLK) 1969 PFEMAC1_TX_DIV_CLK = CLOCK_IP_HAS_PFEMAC1_TX_DIV_CLK, 1970 #endif 1971 #if defined(CLOCK_IP_HAS_PFEMAC2_TX_DIV_CLK) 1972 PFEMAC2_TX_DIV_CLK = CLOCK_IP_HAS_PFEMAC2_TX_DIV_CLK, 1973 #endif 1974 #if defined(CLOCK_IP_HAS_PFEMAC0_TX_CLK) 1975 PFEMAC0_TX_CLK = CLOCK_IP_HAS_PFEMAC0_TX_CLK, 1976 #endif 1977 #if defined(CLOCK_IP_HAS_PFEMAC1_RX_CLK) 1978 PFEMAC1_RX_CLK = CLOCK_IP_HAS_PFEMAC1_RX_CLK, 1979 #endif 1980 #if defined(CLOCK_IP_HAS_PFEMAC1_TX_CLK) 1981 PFEMAC1_TX_CLK = CLOCK_IP_HAS_PFEMAC1_TX_CLK, 1982 #endif 1983 #if defined(CLOCK_IP_HAS_PFEMAC2_RX_CLK) 1984 PFEMAC2_RX_CLK = CLOCK_IP_HAS_PFEMAC2_RX_CLK, 1985 #endif 1986 #if defined(CLOCK_IP_HAS_PFEMAC2_TX_CLK) 1987 PFEMAC2_TX_CLK = CLOCK_IP_HAS_PFEMAC2_TX_CLK, 1988 #endif 1989 #if defined(CLOCK_IP_HAS_PIT0_CLK) 1990 PIT0_CLK = CLOCK_IP_HAS_PIT0_CLK, 1991 #endif 1992 #if defined(CLOCK_IP_HAS_PIT1_CLK) 1993 PIT1_CLK = CLOCK_IP_HAS_PIT1_CLK, 1994 #endif 1995 #if defined(CLOCK_IP_HAS_PIT2_CLK) 1996 PIT2_CLK = CLOCK_IP_HAS_PIT2_CLK, 1997 #endif 1998 #if defined(CLOCK_IP_HAS_PIT3_CLK) 1999 PIT3_CLK = CLOCK_IP_HAS_PIT3_CLK, 2000 #endif 2001 #if defined(CLOCK_IP_HAS_PIT4_CLK) 2002 PIT4_CLK = CLOCK_IP_HAS_PIT4_CLK, 2003 #endif 2004 #if defined(CLOCK_IP_HAS_PIT5_CLK) 2005 PIT5_CLK = CLOCK_IP_HAS_PIT5_CLK, 2006 #endif 2007 #if defined(CLOCK_IP_HAS_PORTA_CLK) 2008 PORTA_CLK = CLOCK_IP_HAS_PORTA_CLK, 2009 #endif 2010 #if defined(CLOCK_IP_HAS_PORTB_CLK) 2011 PORTB_CLK = CLOCK_IP_HAS_PORTB_CLK, 2012 #endif 2013 #if defined(CLOCK_IP_HAS_PORTC_CLK) 2014 PORTC_CLK = CLOCK_IP_HAS_PORTC_CLK, 2015 #endif 2016 #if defined(CLOCK_IP_HAS_PORTD_CLK) 2017 PORTD_CLK = CLOCK_IP_HAS_PORTD_CLK, 2018 #endif 2019 #if defined(CLOCK_IP_HAS_PORTE_CLK) 2020 PORTE_CLK = CLOCK_IP_HAS_PORTE_CLK, 2021 #endif 2022 #if defined(CLOCK_IP_HAS_PSI5_0_CLK) 2023 PSI5_0_CLK = CLOCK_IP_HAS_PSI5_0_CLK, 2024 #endif 2025 #if defined(CLOCK_IP_HAS_PSI5_1_CLK) 2026 PSI5_1_CLK = CLOCK_IP_HAS_PSI5_1_CLK, 2027 #endif 2028 #if defined(CLOCK_IP_HAS_PSI5S_0_CLK) 2029 PSI5S_0_CLK = CLOCK_IP_HAS_PSI5S_0_CLK, 2030 #endif 2031 #if defined(CLOCK_IP_HAS_PSI5S_1_CLK) 2032 PSI5S_1_CLK = CLOCK_IP_HAS_PSI5S_1_CLK, 2033 #endif 2034 #if defined(CLOCK_IP_HAS_QSPI_CLK) 2035 QSPI_CLK = CLOCK_IP_HAS_QSPI_CLK, 2036 #endif 2037 #if defined(CLOCK_IP_HAS_QSPI_SFIF_CLK_HYP_PREMUX_CLK) 2038 QSPI_SFIF_CLK_HYP_PREMUX_CLK = CLOCK_IP_HAS_QSPI_SFIF_CLK_HYP_PREMUX_CLK, 2039 #endif 2040 #if defined(CLOCK_IP_HAS_QSPI_SFIF_CLK) 2041 QSPI_SFIF_CLK = CLOCK_IP_HAS_QSPI_SFIF_CLK, 2042 #endif 2043 #if defined(CLOCK_IP_HAS_QSPI_2xSFIF_CLK) 2044 QSPI_2xSFIF_CLK = CLOCK_IP_HAS_QSPI_2xSFIF_CLK, 2045 #endif 2046 #if defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK) 2047 QSPI_2XSFIF_CLK = CLOCK_IP_HAS_QSPI_2XSFIF_CLK, 2048 #endif 2049 #if defined(CLOCK_IP_HAS_QSPI_2X_CLK) 2050 QSPI_2X_CLK = CLOCK_IP_HAS_QSPI_2X_CLK, 2051 #endif 2052 #if defined(CLOCK_IP_HAS_QSPI_1X_CLK) 2053 QSPI_1X_CLK = CLOCK_IP_HAS_QSPI_1X_CLK, 2054 #endif 2055 #if defined(CLOCK_IP_HAS_QSPI_SFCK_CLK) 2056 QSPI_SFCK_CLK = CLOCK_IP_HAS_QSPI_SFCK_CLK, 2057 #endif 2058 #if defined(CLOCK_IP_HAS_QSPI0_CLK) 2059 QSPI0_CLK = CLOCK_IP_HAS_QSPI0_CLK, 2060 #endif 2061 #if defined(CLOCK_IP_HAS_QSPI0_RAM_CLK) 2062 QSPI0_RAM_CLK = CLOCK_IP_HAS_QSPI0_RAM_CLK, 2063 #endif 2064 #if defined(CLOCK_IP_HAS_QSPI0_SFCK_CLK) 2065 QSPI0_SFCK_CLK = CLOCK_IP_HAS_QSPI0_SFCK_CLK, 2066 #endif 2067 #if defined(CLOCK_IP_HAS_QSPI0_TX_MEM_CLK) 2068 QSPI0_TX_MEM_CLK = CLOCK_IP_HAS_QSPI0_TX_MEM_CLK, 2069 #endif 2070 #if defined(CLOCK_IP_HAS_QSPI1_CLK) 2071 QSPI1_CLK = CLOCK_IP_HAS_QSPI1_CLK, 2072 #endif 2073 #if defined(CLOCK_IP_HAS_P0_CLKOUT_SRC_CLK) 2074 P0_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P0_CLKOUT_SRC_CLK, 2075 #endif 2076 #if defined(CLOCK_IP_HAS_P0_CTU_PER_CLK) 2077 P0_CTU_PER_CLK = CLOCK_IP_HAS_P0_CTU_PER_CLK, 2078 #endif 2079 #if defined(CLOCK_IP_HAS_P0_DSPI_CLK) 2080 P0_DSPI_CLK = CLOCK_IP_HAS_P0_DSPI_CLK, 2081 #endif 2082 #if defined(CLOCK_IP_HAS_P0_DSPI_MSC_CLK) 2083 P0_DSPI_MSC_CLK = CLOCK_IP_HAS_P0_DSPI_MSC_CLK, 2084 #endif 2085 #if defined(CLOCK_IP_HAS_P0_EMIOS_LCU_CLK) 2086 P0_EMIOS_LCU_CLK = CLOCK_IP_HAS_P0_EMIOS_LCU_CLK, 2087 #endif 2088 #if defined(CLOCK_IP_HAS_P0_FR_PE_CLK) 2089 P0_FR_PE_CLK = CLOCK_IP_HAS_P0_FR_PE_CLK, 2090 #endif 2091 #if defined(CLOCK_IP_HAS_P0_GTM_CLK) 2092 P0_GTM_CLK = CLOCK_IP_HAS_P0_GTM_CLK, 2093 #endif 2094 #if defined(CLOCK_IP_HAS_P0_GTM_NOC_CLK) 2095 P0_GTM_NOC_CLK = CLOCK_IP_HAS_P0_GTM_NOC_CLK, 2096 #endif 2097 #if defined(CLOCK_IP_HAS_P0_GTM_TS_CLK) 2098 P0_GTM_TS_CLK = CLOCK_IP_HAS_P0_GTM_TS_CLK, 2099 #endif 2100 #if defined(CLOCK_IP_HAS_P0_LIN_BAUD_CLK) 2101 P0_LIN_BAUD_CLK = CLOCK_IP_HAS_P0_LIN_BAUD_CLK, 2102 #endif 2103 #if defined(CLOCK_IP_HAS_P0_LIN_CLK) 2104 P0_LIN_CLK = CLOCK_IP_HAS_P0_LIN_CLK, 2105 #endif 2106 #if defined(CLOCK_IP_HAS_P0_NANO_CLK) 2107 P0_NANO_CLK = CLOCK_IP_HAS_P0_NANO_CLK, 2108 #endif 2109 #if defined(CLOCK_IP_HAS_P0_PSI5_125K_CLK) 2110 P0_PSI5_125K_CLK = CLOCK_IP_HAS_P0_PSI5_125K_CLK, 2111 #endif 2112 #if defined(CLOCK_IP_HAS_P0_PSI5_189K_CLK) 2113 P0_PSI5_189K_CLK = CLOCK_IP_HAS_P0_PSI5_189K_CLK, 2114 #endif 2115 #if defined(CLOCK_IP_HAS_P0_PSI5_1US_CLK) 2116 P0_PSI5_1US_CLK = CLOCK_IP_HAS_P0_PSI5_1US_CLK, 2117 #endif 2118 #if defined(CLOCK_IP_HAS_P0_PSI5_S_BAUD_CLK) 2119 P0_PSI5_S_BAUD_CLK = CLOCK_IP_HAS_P0_PSI5_S_BAUD_CLK, 2120 #endif 2121 #if defined(CLOCK_IP_HAS_P0_PSI5_S_CORE_CLK) 2122 P0_PSI5_S_CORE_CLK = CLOCK_IP_HAS_P0_PSI5_S_CORE_CLK, 2123 #endif 2124 #if defined(CLOCK_IP_HAS_P0_PSI5_S_TRIG0_CLK) 2125 P0_PSI5_S_TRIG0_CLK = CLOCK_IP_HAS_P0_PSI5_S_TRIG0_CLK, 2126 #endif 2127 #if defined(CLOCK_IP_HAS_P0_PSI5_S_TRIG1_CLK) 2128 P0_PSI5_S_TRIG1_CLK = CLOCK_IP_HAS_P0_PSI5_S_TRIG1_CLK, 2129 #endif 2130 #if defined(CLOCK_IP_HAS_P0_PSI5_S_TRIG2_CLK) 2131 P0_PSI5_S_TRIG2_CLK = CLOCK_IP_HAS_P0_PSI5_S_TRIG2_CLK, 2132 #endif 2133 #if defined(CLOCK_IP_HAS_P0_PSI5_S_TRIG3_CLK) 2134 P0_PSI5_S_TRIG3_CLK = CLOCK_IP_HAS_P0_PSI5_S_TRIG3_CLK, 2135 #endif 2136 #if defined(CLOCK_IP_HAS_P0_PSI5_S_UART_CLK) 2137 P0_PSI5_S_UART_CLK = CLOCK_IP_HAS_P0_PSI5_S_UART_CLK, 2138 #endif 2139 #if defined(CLOCK_IP_HAS_P0_PSI5_S_WDOG0_CLK) 2140 P0_PSI5_S_WDOG0_CLK = CLOCK_IP_HAS_P0_PSI5_S_WDOG0_CLK, 2141 #endif 2142 #if defined(CLOCK_IP_HAS_P0_PSI5_S_WDOG1_CLK) 2143 P0_PSI5_S_WDOG1_CLK = CLOCK_IP_HAS_P0_PSI5_S_WDOG1_CLK, 2144 #endif 2145 #if defined(CLOCK_IP_HAS_P0_PSI5_S_WDOG2_CLK) 2146 P0_PSI5_S_WDOG2_CLK = CLOCK_IP_HAS_P0_PSI5_S_WDOG2_CLK, 2147 #endif 2148 #if defined(CLOCK_IP_HAS_P0_PSI5_S_WDOG3_CLK) 2149 P0_PSI5_S_WDOG3_CLK = CLOCK_IP_HAS_P0_PSI5_S_WDOG3_CLK, 2150 #endif 2151 #if defined(CLOCK_IP_HAS_P0_REG_INTF_2X_CLK) 2152 P0_REG_INTF_2X_CLK = CLOCK_IP_HAS_P0_REG_INTF_2X_CLK, 2153 #endif 2154 #if defined(CLOCK_IP_HAS_P0_REG_INTF_CLK) 2155 P0_REG_INTF_CLK = CLOCK_IP_HAS_P0_REG_INTF_CLK, 2156 #endif 2157 #if defined(CLOCK_IP_HAS_P1_CLKOUT_SRC_CLK) 2158 P1_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P1_CLKOUT_SRC_CLK, 2159 #endif 2160 #if defined(CLOCK_IP_HAS_P1_DSPI_CLK) 2161 P1_DSPI_CLK = CLOCK_IP_HAS_P1_DSPI_CLK, 2162 #endif 2163 #if defined(CLOCK_IP_HAS_P1_DSPI60_CLK) 2164 P1_DSPI60_CLK = CLOCK_IP_HAS_P1_DSPI60_CLK, 2165 #endif 2166 #if defined(CLOCK_IP_HAS_P1_LFAST0_REF_CLK) 2167 P1_LFAST0_REF_CLK = CLOCK_IP_HAS_P1_LFAST0_REF_CLK, 2168 #endif 2169 #if defined(CLOCK_IP_HAS_P1_LFAST1_REF_CLK) 2170 P1_LFAST1_REF_CLK = CLOCK_IP_HAS_P1_LFAST1_REF_CLK, 2171 #endif 2172 #if defined(CLOCK_IP_HAS_P1_LFAST_DFT_CLK) 2173 P1_LFAST_DFT_CLK = CLOCK_IP_HAS_P1_LFAST_DFT_CLK, 2174 #endif 2175 #if defined(CLOCK_IP_HAS_P1_NETC_AXI_CLK) 2176 P1_NETC_AXI_CLK = CLOCK_IP_HAS_P1_NETC_AXI_CLK, 2177 #endif 2178 #if defined(CLOCK_IP_HAS_P1_LIN_BAUD_CLK) 2179 P1_LIN_BAUD_CLK = CLOCK_IP_HAS_P1_LIN_BAUD_CLK, 2180 #endif 2181 #if defined(CLOCK_IP_HAS_P1_LIN_CLK) 2182 P1_LIN_CLK = CLOCK_IP_HAS_P1_LIN_CLK, 2183 #endif 2184 #if defined(CLOCK_IP_HAS_ETH_TS_CLK) 2185 ETH_TS_CLK = CLOCK_IP_HAS_ETH_TS_CLK, 2186 #endif 2187 #if defined(CLOCK_IP_HAS_ETH_TS_DIV4_CLK) 2188 ETH_TS_DIV4_CLK = CLOCK_IP_HAS_ETH_TS_DIV4_CLK, 2189 #endif 2190 #if defined(CLOCK_IP_HAS_ETH0_REF_RMII_CLK) 2191 ETH0_REF_RMII_CLK = CLOCK_IP_HAS_ETH0_REF_RMII_CLK, 2192 #endif 2193 #if defined(CLOCK_IP_HAS_ETH0_RX_MII_CLK) 2194 ETH0_RX_MII_CLK = CLOCK_IP_HAS_ETH0_RX_MII_CLK, 2195 #endif 2196 #if defined(CLOCK_IP_HAS_ETH0_RX_RGMII_CLK) 2197 ETH0_RX_RGMII_CLK = CLOCK_IP_HAS_ETH0_RX_RGMII_CLK, 2198 #endif 2199 #if defined(CLOCK_IP_HAS_ETH0_TX_MII_CLK) 2200 ETH0_TX_MII_CLK = CLOCK_IP_HAS_ETH0_TX_MII_CLK, 2201 #endif 2202 #if defined(CLOCK_IP_HAS_ETH0_TX_RGMII_CLK) 2203 ETH0_TX_RGMII_CLK = CLOCK_IP_HAS_ETH0_TX_RGMII_CLK, 2204 #endif 2205 #if defined(CLOCK_IP_HAS_ETH0_TX_RGMII_LPBK_CLK) 2206 ETH0_TX_RGMII_LPBK_CLK = CLOCK_IP_HAS_ETH0_TX_RGMII_LPBK_CLK, 2207 #endif 2208 #if defined(CLOCK_IP_HAS_ETH0_PS_TX_CLK) 2209 ETH0_PS_TX_CLK = CLOCK_IP_HAS_ETH0_PS_TX_CLK, 2210 #endif 2211 #if defined(CLOCK_IP_HAS_ETH1_REF_RMII_CLK) 2212 ETH1_REF_RMII_CLK = CLOCK_IP_HAS_ETH1_REF_RMII_CLK, 2213 #endif 2214 #if defined(CLOCK_IP_HAS_ETH1_RX_MII_CLK) 2215 ETH1_RX_MII_CLK = CLOCK_IP_HAS_ETH1_RX_MII_CLK, 2216 #endif 2217 #if defined(CLOCK_IP_HAS_ETH1_RX_RGMII_CLK) 2218 ETH1_RX_RGMII_CLK = CLOCK_IP_HAS_ETH1_RX_RGMII_CLK, 2219 #endif 2220 #if defined(CLOCK_IP_HAS_ETH1_TX_MII_CLK) 2221 ETH1_TX_MII_CLK = CLOCK_IP_HAS_ETH1_TX_MII_CLK, 2222 #endif 2223 #if defined(CLOCK_IP_HAS_ETH1_TX_RGMII_CLK) 2224 ETH1_TX_RGMII_CLK = CLOCK_IP_HAS_ETH1_TX_RGMII_CLK, 2225 #endif 2226 #if defined(CLOCK_IP_HAS_ETH1_TX_RGMII_LPBK_CLK) 2227 ETH1_TX_RGMII_LPBK_CLK = CLOCK_IP_HAS_ETH1_TX_RGMII_LPBK_CLK, 2228 #endif 2229 #if defined(CLOCK_IP_HAS_ETH1_PS_TX_CLK) 2230 ETH1_PS_TX_CLK = CLOCK_IP_HAS_ETH1_PS_TX_CLK, 2231 #endif 2232 #if defined(CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK) 2233 ETPU_AB_REGISTERS_CLK = CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK, 2234 #endif 2235 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK) 2236 ETPU_CODE_RAM1_CLK = CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK, 2237 #endif 2238 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK) 2239 ETPU_CODE_RAM2_CLK = CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK, 2240 #endif 2241 #if defined(CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK) 2242 ETPU_RAM_MIRROR_CLK = CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK, 2243 #endif 2244 #if defined(CLOCK_IP_HAS_ETPU_RAM_SDM_CLK) 2245 ETPU_RAM_SDM_CLK = CLOCK_IP_HAS_ETPU_RAM_SDM_CLK, 2246 #endif 2247 #if defined(CLOCK_IP_HAS_P1_REG_INTF_CLK) 2248 P1_REG_INTF_CLK = CLOCK_IP_HAS_P1_REG_INTF_CLK, 2249 #endif 2250 #if defined(CLOCK_IP_HAS_P2_DBG_ATB_CLK) 2251 P2_DBG_ATB_CLK = CLOCK_IP_HAS_P2_DBG_ATB_CLK, 2252 #endif 2253 #if defined(CLOCK_IP_HAS_P2_REG_INTF_CLK) 2254 P2_REG_INTF_CLK = CLOCK_IP_HAS_P2_REG_INTF_CLK, 2255 #endif 2256 #if defined(CLOCK_IP_HAS_P3_AES_CLK) 2257 P3_AES_CLK = CLOCK_IP_HAS_P3_AES_CLK, 2258 #endif 2259 #if defined(CLOCK_IP_HAS_P3_CAN_PE_CLK) 2260 P3_CAN_PE_CLK = CLOCK_IP_HAS_P3_CAN_PE_CLK, 2261 #endif 2262 #if defined(CLOCK_IP_HAS_P3_CLKOUT_SRC_CLK) 2263 P3_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P3_CLKOUT_SRC_CLK, 2264 #endif 2265 #if defined(CLOCK_IP_HAS_P3_DBG_TS_CLK) 2266 P3_DBG_TS_CLK = CLOCK_IP_HAS_P3_DBG_TS_CLK, 2267 #endif 2268 #if defined(CLOCK_IP_HAS_P3_REG_INTF_CLK) 2269 P3_REG_INTF_CLK = CLOCK_IP_HAS_P3_REG_INTF_CLK, 2270 #endif 2271 #if defined(CLOCK_IP_HAS_P3_SYS_MON1_CLK) 2272 P3_SYS_MON1_CLK = CLOCK_IP_HAS_P3_SYS_MON1_CLK, 2273 #endif 2274 #if defined(CLOCK_IP_HAS_P3_SYS_MON2_CLK) 2275 P3_SYS_MON2_CLK = CLOCK_IP_HAS_P3_SYS_MON2_CLK, 2276 #endif 2277 #if defined(CLOCK_IP_HAS_P3_SYS_MON3_CLK) 2278 P3_SYS_MON3_CLK = CLOCK_IP_HAS_P3_SYS_MON3_CLK, 2279 #endif 2280 #if defined(CLOCK_IP_HAS_P4_CLKOUT_SRC_CLK) 2281 P4_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P4_CLKOUT_SRC_CLK, 2282 #endif 2283 #if defined(CLOCK_IP_HAS_P4_DSPI_CLK) 2284 P4_DSPI_CLK = CLOCK_IP_HAS_P4_DSPI_CLK, 2285 #endif 2286 #if defined(CLOCK_IP_HAS_P4_DSPI60_CLK) 2287 P4_DSPI60_CLK = CLOCK_IP_HAS_P4_DSPI60_CLK, 2288 #endif 2289 #if defined(CLOCK_IP_HAS_P4_EMIOS_LCU_CLK) 2290 P4_EMIOS_LCU_CLK = CLOCK_IP_HAS_P4_EMIOS_LCU_CLK, 2291 #endif 2292 #if defined(CLOCK_IP_HAS_P4_LIN_BAUD_CLK) 2293 P4_LIN_BAUD_CLK = CLOCK_IP_HAS_P4_LIN_BAUD_CLK, 2294 #endif 2295 #if defined(CLOCK_IP_HAS_P4_LIN_CLK) 2296 P4_LIN_CLK = CLOCK_IP_HAS_P4_LIN_CLK, 2297 #endif 2298 #if defined(CLOCK_IP_HAS_P4_PSI5_125K_CLK) 2299 P4_PSI5_125K_CLK = CLOCK_IP_HAS_P4_PSI5_125K_CLK, 2300 #endif 2301 #if defined(CLOCK_IP_HAS_P4_PSI5_189K_CLK) 2302 P4_PSI5_189K_CLK = CLOCK_IP_HAS_P4_PSI5_189K_CLK, 2303 #endif 2304 #if defined(CLOCK_IP_HAS_P4_PSI5_1US_CLK) 2305 P4_PSI5_1US_CLK = CLOCK_IP_HAS_P4_PSI5_1US_CLK, 2306 #endif 2307 #if defined(CLOCK_IP_HAS_P4_PSI5_S_BAUD_CLK) 2308 P4_PSI5_S_BAUD_CLK = CLOCK_IP_HAS_P4_PSI5_S_BAUD_CLK, 2309 #endif 2310 #if defined(CLOCK_IP_HAS_P4_PSI5_S_CORE_CLK) 2311 P4_PSI5_S_CORE_CLK = CLOCK_IP_HAS_P4_PSI5_S_CORE_CLK, 2312 #endif 2313 #if defined(CLOCK_IP_HAS_P4_PSI5_S_TRIG0_CLK) 2314 P4_PSI5_S_TRIG0_CLK = CLOCK_IP_HAS_P4_PSI5_S_TRIG0_CLK, 2315 #endif 2316 #if defined(CLOCK_IP_HAS_P4_PSI5_S_TRIG1_CLK) 2317 P4_PSI5_S_TRIG1_CLK = CLOCK_IP_HAS_P4_PSI5_S_TRIG1_CLK, 2318 #endif 2319 #if defined(CLOCK_IP_HAS_P4_PSI5_S_TRIG2_CLK) 2320 P4_PSI5_S_TRIG2_CLK = CLOCK_IP_HAS_P4_PSI5_S_TRIG2_CLK, 2321 #endif 2322 #if defined(CLOCK_IP_HAS_P4_PSI5_S_TRIG3_CLK) 2323 P4_PSI5_S_TRIG3_CLK = CLOCK_IP_HAS_P4_PSI5_S_TRIG3_CLK, 2324 #endif 2325 #if defined(CLOCK_IP_HAS_P4_PSI5_S_UART_CLK) 2326 P4_PSI5_S_UART_CLK = CLOCK_IP_HAS_P4_PSI5_S_UART_CLK, 2327 #endif 2328 #if defined(CLOCK_IP_HAS_P4_PSI5_S_WDOG0_CLK) 2329 P4_PSI5_S_WDOG0_CLK = CLOCK_IP_HAS_P4_PSI5_S_WDOG0_CLK, 2330 #endif 2331 #if defined(CLOCK_IP_HAS_P4_PSI5_S_WDOG1_CLK) 2332 P4_PSI5_S_WDOG1_CLK = CLOCK_IP_HAS_P4_PSI5_S_WDOG1_CLK, 2333 #endif 2334 #if defined(CLOCK_IP_HAS_P4_PSI5_S_WDOG2_CLK) 2335 P4_PSI5_S_WDOG2_CLK = CLOCK_IP_HAS_P4_PSI5_S_WDOG2_CLK, 2336 #endif 2337 #if defined(CLOCK_IP_HAS_P4_PSI5_S_WDOG3_CLK) 2338 P4_PSI5_S_WDOG3_CLK = CLOCK_IP_HAS_P4_PSI5_S_WDOG3_CLK, 2339 #endif 2340 #if defined(CLOCK_IP_HAS_P4_QSPI0_2X_CLK) 2341 P4_QSPI0_2X_CLK = CLOCK_IP_HAS_P4_QSPI0_2X_CLK, 2342 #endif 2343 #if defined(CLOCK_IP_HAS_P4_QSPI0_1X_CLK) 2344 P4_QSPI0_1X_CLK = CLOCK_IP_HAS_P4_QSPI0_1X_CLK, 2345 #endif 2346 #if defined(CLOCK_IP_HAS_P4_QSPI1_2X_CLK) 2347 P4_QSPI1_2X_CLK = CLOCK_IP_HAS_P4_QSPI1_2X_CLK, 2348 #endif 2349 #if defined(CLOCK_IP_HAS_P4_QSPI1_1X_CLK) 2350 P4_QSPI1_1X_CLK = CLOCK_IP_HAS_P4_QSPI1_1X_CLK, 2351 #endif 2352 #if defined(CLOCK_IP_HAS_P4_REG_INTF_2X_CLK) 2353 P4_REG_INTF_2X_CLK = CLOCK_IP_HAS_P4_REG_INTF_2X_CLK, 2354 #endif 2355 #if defined(CLOCK_IP_HAS_P4_REG_INTF_CLK) 2356 P4_REG_INTF_CLK = CLOCK_IP_HAS_P4_REG_INTF_CLK, 2357 #endif 2358 #if defined(CLOCK_IP_HAS_P4_SDHC_CLK) 2359 P4_SDHC_CLK = CLOCK_IP_HAS_P4_SDHC_CLK, 2360 #endif 2361 #if defined(CLOCK_IP_HAS_P4_SDHC_IP_CLK) 2362 P4_SDHC_IP_CLK = CLOCK_IP_HAS_P4_SDHC_IP_CLK, 2363 #endif 2364 #if defined(CLOCK_IP_HAS_P4_SDHC_IP_DIV2_CLK) 2365 P4_SDHC_IP_DIV2_CLK = CLOCK_IP_HAS_P4_SDHC_IP_DIV2_CLK, 2366 #endif 2367 #if defined(CLOCK_IP_HAS_P5_AE_CLK) 2368 P5_AE_CLK = CLOCK_IP_HAS_P5_AE_CLK, 2369 #endif 2370 #if defined(CLOCK_IP_HAS_P5_CANXL_PE_CLK) 2371 P5_CANXL_PE_CLK = CLOCK_IP_HAS_P5_CANXL_PE_CLK, 2372 #endif 2373 #if defined(CLOCK_IP_HAS_P5_CANXL_CHI_CLK) 2374 P5_CANXL_CHI_CLK = CLOCK_IP_HAS_P5_CANXL_CHI_CLK, 2375 #endif 2376 #if defined(CLOCK_IP_HAS_P5_CLKOUT_SRC_CLK) 2377 P5_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P5_CLKOUT_SRC_CLK, 2378 #endif 2379 #if defined(CLOCK_IP_HAS_P5_DSPI_CLK) 2380 P5_DSPI_CLK = CLOCK_IP_HAS_P5_DSPI_CLK, 2381 #endif 2382 #if defined(CLOCK_IP_HAS_P5_DIPORT_CLK) 2383 P5_DIPORT_CLK = CLOCK_IP_HAS_P5_DIPORT_CLK, 2384 #endif 2385 #if defined(CLOCK_IP_HAS_P5_LIN_BAUD_CLK) 2386 P5_LIN_BAUD_CLK = CLOCK_IP_HAS_P5_LIN_BAUD_CLK, 2387 #endif 2388 #if defined(CLOCK_IP_HAS_P5_LIN_CLK) 2389 P5_LIN_CLK = CLOCK_IP_HAS_P5_LIN_CLK, 2390 #endif 2391 #if defined(CLOCK_IP_HAS_P5_REG_INTF_CLK) 2392 P5_REG_INTF_CLK = CLOCK_IP_HAS_P5_REG_INTF_CLK, 2393 #endif 2394 #if defined(CLOCK_IP_HAS_P6_REG_INTF_CLK) 2395 P6_REG_INTF_CLK = CLOCK_IP_HAS_P6_REG_INTF_CLK, 2396 #endif 2397 #if defined(CLOCK_IP_HAS_RTU0_REG_INTF_CLK) 2398 RTU0_REG_INTF_CLK = CLOCK_IP_HAS_RTU0_REG_INTF_CLK, 2399 #endif 2400 #if defined(CLOCK_IP_HAS_RTU0_CORE_MON1_CLK) 2401 RTU0_CORE_MON1_CLK = CLOCK_IP_HAS_RTU0_CORE_MON1_CLK, 2402 #endif 2403 #if defined(CLOCK_IP_HAS_RTU0_CORE_MON2_CLK) 2404 RTU0_CORE_MON2_CLK = CLOCK_IP_HAS_RTU0_CORE_MON2_CLK, 2405 #endif 2406 #if defined(CLOCK_IP_HAS_RTU0_CORE_DIV2_MON1_CLK) 2407 RTU0_CORE_DIV2_MON1_CLK = CLOCK_IP_HAS_RTU0_CORE_DIV2_MON1_CLK, 2408 #endif 2409 #if defined(CLOCK_IP_HAS_RTU0_CORE_DIV2_MON2_CLK) 2410 RTU0_CORE_DIV2_MON2_CLK = CLOCK_IP_HAS_RTU0_CORE_DIV2_MON2_CLK, 2411 #endif 2412 #if defined(CLOCK_IP_HAS_RTU0_CORE_DIV2_MON3_CLK) 2413 RTU0_CORE_DIV2_MON3_CLK = CLOCK_IP_HAS_RTU0_CORE_DIV2_MON3_CLK, 2414 #endif 2415 #if defined(CLOCK_IP_HAS_RTU1_REG_INTF_CLK) 2416 RTU1_REG_INTF_CLK = CLOCK_IP_HAS_RTU1_REG_INTF_CLK, 2417 #endif 2418 #if defined(CLOCK_IP_HAS_RTU1_CORE_MON1_CLK) 2419 RTU1_CORE_MON1_CLK = CLOCK_IP_HAS_RTU1_CORE_MON1_CLK, 2420 #endif 2421 #if defined(CLOCK_IP_HAS_RTU1_CORE_MON2_CLK) 2422 RTU1_CORE_MON2_CLK = CLOCK_IP_HAS_RTU1_CORE_MON2_CLK, 2423 #endif 2424 #if defined(CLOCK_IP_HAS_RTU1_CORE_DIV2_MON1_CLK) 2425 RTU1_CORE_DIV2_MON1_CLK = CLOCK_IP_HAS_RTU1_CORE_DIV2_MON1_CLK, 2426 #endif 2427 #if defined(CLOCK_IP_HAS_RTU1_CORE_DIV2_MON2_CLK) 2428 RTU1_CORE_DIV2_MON2_CLK = CLOCK_IP_HAS_RTU1_CORE_DIV2_MON2_CLK, 2429 #endif 2430 #if defined(CLOCK_IP_HAS_RTU1_CORE_DIV2_MON3_CLK) 2431 RTU1_CORE_DIV2_MON3_CLK = CLOCK_IP_HAS_RTU1_CORE_DIV2_MON3_CLK, 2432 #endif 2433 #if defined(CLOCK_IP_HAS_RFE_PLL_CLK) 2434 RFE_PLL_CLK = CLOCK_IP_HAS_RFE_PLL_CLK, 2435 #endif 2436 #if defined(CLOCK_IP_HAS_RTC_CLK) 2437 RTC_CLK = CLOCK_IP_HAS_RTC_CLK, 2438 #endif 2439 #if defined(CLOCK_IP_HAS_RTC0_CLK) 2440 RTC0_CLK = CLOCK_IP_HAS_RTC0_CLK, 2441 #endif 2442 #if defined(CLOCK_IP_HAS_RTC_EXT_REF_CLK) 2443 RTC_EXT_REF_CLK = CLOCK_IP_HAS_RTC_EXT_REF_CLK, 2444 #endif 2445 #if defined(CLOCK_IP_HAS_RXLUT_CLK) 2446 RXLUT_CLK = CLOCK_IP_HAS_RXLUT_CLK, 2447 #endif 2448 #if defined(CLOCK_IP_HAS_SAI0_CLK) 2449 SAI0_CLK = CLOCK_IP_HAS_SAI0_CLK, 2450 #endif 2451 #if defined(CLOCK_IP_HAS_SAI1_CLK) 2452 SAI1_CLK = CLOCK_IP_HAS_SAI1_CLK, 2453 #endif 2454 #if defined(CLOCK_IP_HAS_SDHC0_CLK) 2455 SDHC0_CLK = CLOCK_IP_HAS_SDHC0_CLK, 2456 #endif 2457 #if defined(CLOCK_IP_HAS_SEMA42_CLK) 2458 SEMA42_CLK = CLOCK_IP_HAS_SEMA42_CLK, 2459 #endif 2460 #if defined(CLOCK_IP_HAS_SIPI0_CLK) 2461 SIPI0_CLK = CLOCK_IP_HAS_SIPI0_CLK, 2462 #endif 2463 #if defined(CLOCK_IP_HAS_SIPI1_CLK) 2464 SIPI1_CLK = CLOCK_IP_HAS_SIPI1_CLK, 2465 #endif 2466 #if defined(CLOCK_IP_HAS_SINC_CLK) 2467 SINC_CLK = CLOCK_IP_HAS_SINC_CLK, 2468 #endif 2469 #if defined(CLOCK_IP_HAS_SIUL0_CLK) 2470 SIUL0_CLK = CLOCK_IP_HAS_SIUL0_CLK, 2471 #endif 2472 #if defined(CLOCK_IP_HAS_SIUL1_CLK) 2473 SIUL1_CLK = CLOCK_IP_HAS_SIUL1_CLK, 2474 #endif 2475 #if defined(CLOCK_IP_HAS_SIUL2_0_CLK) 2476 SIUL2_0_CLK = CLOCK_IP_HAS_SIUL2_0_CLK, 2477 #endif 2478 #if defined(CLOCK_IP_HAS_SIUL2_1_CLK) 2479 SIUL2_1_CLK = CLOCK_IP_HAS_SIUL2_1_CLK, 2480 #endif 2481 #if defined(CLOCK_IP_HAS_SIUL2_4_CLK) 2482 SIUL2_4_CLK = CLOCK_IP_HAS_SIUL2_4_CLK, 2483 #endif 2484 #if defined(CLOCK_IP_HAS_SIUL2_5_CLK) 2485 SIUL2_5_CLK = CLOCK_IP_HAS_SIUL2_5_CLK, 2486 #endif 2487 #if defined(CLOCK_IP_HAS_SPI_CLK) 2488 SPI_CLK = CLOCK_IP_HAS_SPI_CLK, 2489 #endif 2490 #if defined(CLOCK_IP_HAS_SPI0_CLK) 2491 SPI0_CLK = CLOCK_IP_HAS_SPI0_CLK, 2492 #endif 2493 #if defined(CLOCK_IP_HAS_SPI1_CLK) 2494 SPI1_CLK = CLOCK_IP_HAS_SPI1_CLK, 2495 #endif 2496 #if defined(CLOCK_IP_HAS_SPI2_CLK) 2497 SPI2_CLK = CLOCK_IP_HAS_SPI2_CLK, 2498 #endif 2499 #if defined(CLOCK_IP_HAS_SPI3_CLK) 2500 SPI3_CLK = CLOCK_IP_HAS_SPI3_CLK, 2501 #endif 2502 #if defined(CLOCK_IP_HAS_SPI4_CLK) 2503 SPI4_CLK = CLOCK_IP_HAS_SPI4_CLK, 2504 #endif 2505 #if defined(CLOCK_IP_HAS_SPI5_CLK) 2506 SPI5_CLK = CLOCK_IP_HAS_SPI5_CLK, 2507 #endif 2508 #if defined(CLOCK_IP_HAS_SPI6_CLK) 2509 SPI6_CLK = CLOCK_IP_HAS_SPI6_CLK, 2510 #endif 2511 #if defined(CLOCK_IP_HAS_SPI7_CLK) 2512 SPI7_CLK = CLOCK_IP_HAS_SPI7_CLK, 2513 #endif 2514 #if defined(CLOCK_IP_HAS_SPI8_CLK) 2515 SPI8_CLK = CLOCK_IP_HAS_SPI8_CLK, 2516 #endif 2517 #if defined(CLOCK_IP_HAS_SPI9_CLK) 2518 SPI9_CLK = CLOCK_IP_HAS_SPI9_CLK, 2519 #endif 2520 #if defined(CLOCK_IP_HAS_SRX0_CLK) 2521 SRX0_CLK = CLOCK_IP_HAS_SRX0_CLK, 2522 #endif 2523 #if defined(CLOCK_IP_HAS_SRX1_CLK) 2524 SRX1_CLK = CLOCK_IP_HAS_SRX1_CLK, 2525 #endif 2526 #if defined(CLOCK_IP_HAS_STCU0_CLK) 2527 STCU0_CLK = CLOCK_IP_HAS_STCU0_CLK, 2528 #endif 2529 #if defined(CLOCK_IP_HAS_STM0_CLK) 2530 STM0_CLK = CLOCK_IP_HAS_STM0_CLK, 2531 #endif 2532 #if defined(CLOCK_IP_HAS_STM1_CLK) 2533 STM1_CLK = CLOCK_IP_HAS_STM1_CLK, 2534 #endif 2535 #if defined(CLOCK_IP_HAS_STM2_CLK) 2536 STM2_CLK = CLOCK_IP_HAS_STM2_CLK, 2537 #endif 2538 #if defined(CLOCK_IP_HAS_STM3_CLK) 2539 STM3_CLK = CLOCK_IP_HAS_STM3_CLK, 2540 #endif 2541 #if defined(CLOCK_IP_HAS_STM4_CLK) 2542 STM4_CLK = CLOCK_IP_HAS_STM4_CLK, 2543 #endif 2544 #if defined(CLOCK_IP_HAS_STM5_CLK) 2545 STM5_CLK = CLOCK_IP_HAS_STM5_CLK, 2546 #endif 2547 #if defined(CLOCK_IP_HAS_STM6_CLK) 2548 STM6_CLK = CLOCK_IP_HAS_STM6_CLK, 2549 #endif 2550 #if defined(CLOCK_IP_HAS_STM7_CLK) 2551 STM7_CLK = CLOCK_IP_HAS_STM7_CLK, 2552 #endif 2553 #if defined(CLOCK_IP_HAS_STMA_CLK) 2554 STMA_CLK = CLOCK_IP_HAS_STMA_CLK, 2555 #endif 2556 #if defined(CLOCK_IP_HAS_STMB_CLK) 2557 STMB_CLK = CLOCK_IP_HAS_STMB_CLK, 2558 #endif 2559 #if defined(CLOCK_IP_HAS_STMC_CLK) 2560 STMC_CLK = CLOCK_IP_HAS_STMC_CLK, 2561 #endif 2562 #if defined(CLOCK_IP_HAS_STMD_CLK) 2563 STMD_CLK = CLOCK_IP_HAS_STMD_CLK, 2564 #endif 2565 #if defined(CLOCK_IP_HAS_SWG_CLK) 2566 SWG_CLK = CLOCK_IP_HAS_SWG_CLK, 2567 #endif 2568 #if defined(CLOCK_IP_HAS_SWG0_CLK) 2569 SWG0_CLK = CLOCK_IP_HAS_SWG0_CLK, 2570 #endif 2571 #if defined(CLOCK_IP_HAS_SWG1_CLK) 2572 SWG1_CLK = CLOCK_IP_HAS_SWG1_CLK, 2573 #endif 2574 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK) 2575 SWG_PAD_CLK = CLOCK_IP_HAS_SWG_PAD_CLK, 2576 #endif 2577 #if defined(CLOCK_IP_HAS_SWT0_CLK) 2578 SWT0_CLK = CLOCK_IP_HAS_SWT0_CLK, 2579 #endif 2580 #if defined(CLOCK_IP_HAS_SWT1_CLK) 2581 SWT1_CLK = CLOCK_IP_HAS_SWT1_CLK, 2582 #endif 2583 #if defined(CLOCK_IP_HAS_SWT2_CLK) 2584 SWT2_CLK = CLOCK_IP_HAS_SWT2_CLK, 2585 #endif 2586 #if defined(CLOCK_IP_HAS_SWT3_CLK) 2587 SWT3_CLK = CLOCK_IP_HAS_SWT3_CLK, 2588 #endif 2589 #if defined(CLOCK_IP_HAS_SWT4_CLK) 2590 SWT4_CLK = CLOCK_IP_HAS_SWT4_CLK, 2591 #endif 2592 #if defined(CLOCK_IP_HAS_SWT5_CLK) 2593 SWT5_CLK = CLOCK_IP_HAS_SWT5_CLK, 2594 #endif 2595 #if defined(CLOCK_IP_HAS_SWT6_CLK) 2596 SWT6_CLK = CLOCK_IP_HAS_SWT6_CLK, 2597 #endif 2598 #if defined(CLOCK_IP_HAS_TCM_CM7_0_CLK) 2599 TCM_CM7_0_CLK = CLOCK_IP_HAS_TCM_CM7_0_CLK, 2600 #endif 2601 #if defined(CLOCK_IP_HAS_TCM_CM7_1_CLK) 2602 TCM_CM7_1_CLK = CLOCK_IP_HAS_TCM_CM7_1_CLK, 2603 #endif 2604 #if defined(CLOCK_IP_HAS_TEMPSENSE_CLK) 2605 TEMPSENSE_CLK = CLOCK_IP_HAS_TEMPSENSE_CLK, 2606 #endif 2607 #if defined(CLOCK_IP_HAS_TIMER_CLK) 2608 TIMER_CLK = CLOCK_IP_HAS_TIMER_CLK, 2609 #endif 2610 #if defined(CLOCK_IP_HAS_ENET0_TIME_CLK) 2611 ENET0_TIME_CLK = CLOCK_IP_HAS_ENET0_TIME_CLK, 2612 #endif 2613 #if defined(CLOCK_IP_HAS_TRACE_CLK) 2614 TRACE_CLK = CLOCK_IP_HAS_TRACE_CLK, 2615 #endif 2616 #if defined(CLOCK_IP_HAS_TRGMUX0_CLK) 2617 TRGMUX0_CLK = CLOCK_IP_HAS_TRGMUX0_CLK, 2618 #endif 2619 #if defined(CLOCK_IP_HAS_TRGMUX1_CLK) 2620 TRGMUX1_CLK = CLOCK_IP_HAS_TRGMUX1_CLK, 2621 #endif 2622 #if defined(CLOCK_IP_HAS_TSENSE0_CLK) 2623 TSENSE0_CLK = CLOCK_IP_HAS_TSENSE0_CLK, 2624 #endif 2625 #if defined(CLOCK_IP_HAS_SDHC_CLK) 2626 SDHC_CLK = CLOCK_IP_HAS_SDHC_CLK, 2627 #endif 2628 #if defined(CLOCK_IP_HAS_USDHC_CLK) 2629 USDHC_CLK = CLOCK_IP_HAS_USDHC_CLK, 2630 #endif 2631 #if defined(CLOCK_IP_HAS_USDHC0_CLK) 2632 USDHC0_CLK = CLOCK_IP_HAS_USDHC0_CLK, 2633 #endif 2634 #if defined(CLOCK_IP_HAS_WKPU0_CLK) 2635 WKPU0_CLK = CLOCK_IP_HAS_WKPU0_CLK, 2636 #endif 2637 #if defined(CLOCK_IP_HAS_XBAR_DIV3_FAIL_CLK) 2638 XBAR_DIV3_FAIL_CLK = CLOCK_IP_HAS_XBAR_DIV3_FAIL_CLK, 2639 #endif 2640 #if defined(CLOCK_IP_HAS_XBAR_MIPICSI201_CLK) 2641 XBAR_MIPICSI201_CLK = CLOCK_IP_HAS_XBAR_MIPICSI201_CLK, 2642 #endif 2643 #if defined(CLOCK_IP_HAS_XBAR_MIPICSI223_CLK) 2644 XBAR_MIPICSI223_CLK = CLOCK_IP_HAS_XBAR_MIPICSI223_CLK, 2645 #endif 2646 #if defined(CLOCK_IP_HAS_BBE32EP_DSP_CLK) 2647 BBE32EP_DSP_CLK = CLOCK_IP_HAS_BBE32EP_DSP_CLK, 2648 #endif 2649 #if defined(CLOCK_IP_HAS_CAN_CHI_CLK) 2650 CAN_CHI_CLK = CLOCK_IP_HAS_CAN_CHI_CLK, 2651 #endif 2652 #if defined(CLOCK_IP_HAS_CAN_TS_CLK) 2653 CAN_TS_CLK = CLOCK_IP_HAS_CAN_TS_CLK, 2654 #endif 2655 #if defined(CLOCK_IP_HAS_CAN0_CLK) 2656 CAN0_CLK = CLOCK_IP_HAS_CAN0_CLK, 2657 #endif 2658 #if defined(CLOCK_IP_HAS_CAN1_CLK) 2659 CAN1_CLK = CLOCK_IP_HAS_CAN1_CLK, 2660 #endif 2661 #if defined(CLOCK_IP_HAS_CRC_CLK) 2662 CRC_CLK = CLOCK_IP_HAS_CRC_CLK, 2663 #endif 2664 #if defined(CLOCK_IP_HAS_CSI_CFG_CLK) 2665 CSI_CLK = CLOCK_IP_HAS_CSI_CLK, 2666 #endif 2667 #if defined(CLOCK_IP_HAS_CSI_CFG_CLK) 2668 CSI_CFG_CLK = CLOCK_IP_HAS_CSI_CFG_CLK, 2669 #endif 2670 #if defined(CLOCK_IP_HAS_CSI_IPS_CLK) 2671 CSI_IPS_CLK = CLOCK_IP_HAS_CSI_IPS_CLK, 2672 #endif 2673 #if defined(CLOCK_IP_HAS_CSI_TXCLK_CLK) 2674 CSI_TXCLK_CLK = CLOCK_IP_HAS_CSI_TXCLK_CLK, 2675 #endif 2676 #if defined(CLOCK_IP_HAS_CTE_CLK) 2677 CTE_CLK = CLOCK_IP_HAS_CTE_CLK, 2678 #endif 2679 #if defined(CLOCK_IP_HAS_CTU_CLK) 2680 CTU_CLK = CLOCK_IP_HAS_CTU_CLK, 2681 #endif 2682 #if defined(CLOCK_IP_HAS_CTU_IPS_CLK) 2683 CTU_IPS_CLK = CLOCK_IP_HAS_CTU_IPS_CLK, 2684 #endif 2685 #if defined(CLOCK_IP_HAS_DMA_CLK) 2686 DMA_CLK = CLOCK_IP_HAS_DMA_CLK, 2687 #endif 2688 #if defined(CLOCK_IP_HAS_DMA_CRC_CLK) 2689 DMA_CRC_CLK = CLOCK_IP_HAS_DMA_CRC_CLK, 2690 #endif 2691 #if defined(CLOCK_IP_HAS_DMA_TCD_CLK) 2692 DMA_TCD_CLK = CLOCK_IP_HAS_DMA_TCD_CLK, 2693 #endif 2694 #if defined(CLOCK_IP_HAS_EIM_AP1_CLK) 2695 EIM_AP1_CLK = CLOCK_IP_HAS_EIM_AP1_CLK, 2696 #endif 2697 #if defined(CLOCK_IP_HAS_EIM_CM70_CLK) 2698 EIM_CM70_CLK = CLOCK_IP_HAS_EIM_CM70_CLK, 2699 #endif 2700 #if defined(CLOCK_IP_HAS_EIM_CM71_CLK) 2701 EIM_CM71_CLK = CLOCK_IP_HAS_EIM_CM71_CLK, 2702 #endif 2703 #if defined(CLOCK_IP_HAS_EIM_DSP_CLK) 2704 EIM_DSP_CLK = CLOCK_IP_HAS_EIM_DSP_CLK, 2705 #endif 2706 #if defined(CLOCK_IP_HAS_EIM_RT0_CLK) 2707 EIM_RT0_CLK = CLOCK_IP_HAS_EIM_RT0_CLK, 2708 #endif 2709 #if defined(CLOCK_IP_HAS_EIM_RT2_CLK) 2710 EIM_RT2_CLK = CLOCK_IP_HAS_EIM_RT2_CLK, 2711 #endif 2712 #if defined(CLOCK_IP_HAS_ERM_AP1_CLK) 2713 ERM_AP1_CLK = CLOCK_IP_HAS_ERM_AP1_CLK, 2714 #endif 2715 #if defined(CLOCK_IP_HAS_ERM_RT0_CLK) 2716 ERM_RT0_CLK = CLOCK_IP_HAS_ERM_RT0_CLK, 2717 #endif 2718 #if defined(CLOCK_IP_HAS_ERM_RT1_CLK) 2719 ERM_RT1_CLK = CLOCK_IP_HAS_ERM_RT1_CLK, 2720 #endif 2721 #if defined(CLOCK_IP_HAS_ERM_RT2_CLK) 2722 ERM_RT2_CLK = CLOCK_IP_HAS_ERM_RT2_CLK, 2723 #endif 2724 #if defined(CLOCK_IP_HAS_FCCU_IPS_CLK) 2725 FCCU_IPS_CLK = CLOCK_IP_HAS_FCCU_IPS_CLK, 2726 #endif 2727 #if defined(CLOCK_IP_HAS_SYS_M7_0_CLK) 2728 SYS_M7_0_CLK = CLOCK_IP_HAS_SYS_M7_0_CLK, 2729 #endif 2730 #if defined(CLOCK_IP_HAS_SYS_M7_1_CLK) 2731 SYS_M7_1_CLK = CLOCK_IP_HAS_SYS_M7_1_CLK, 2732 #endif 2733 #if defined(CLOCK_IP_HAS_SYS_HSE_CLK) 2734 SYS_HSE_CLK = CLOCK_IP_HAS_SYS_HSE_CLK, 2735 #endif 2736 #if defined(CLOCK_IP_HAS_MC_CLK) 2737 MC_CLK = CLOCK_IP_HAS_MC_CLK, 2738 #endif 2739 #if defined(CLOCK_IP_HAS_MIPICSI2_0_CLK) 2740 MIPICSI2_0_CLK = CLOCK_IP_HAS_MIPICSI2_0_CLK, 2741 #endif 2742 #if defined(CLOCK_IP_HAS_MIPICSI2_1_CLK) 2743 MIPICSI2_1_CLK = CLOCK_IP_HAS_MIPICSI2_1_CLK, 2744 #endif 2745 #if defined(CLOCK_IP_HAS_MSCDSPI_CLK) 2746 MSCDSPI_CLK = CLOCK_IP_HAS_MSCDSPI_CLK, 2747 #endif 2748 #if defined(CLOCK_IP_HAS_MSCLIN_CLK) 2749 MSCLIN_CLK = CLOCK_IP_HAS_MSCLIN_CLK, 2750 #endif 2751 #if defined(CLOCK_IP_HAS_NOC_TRACE_CLK) 2752 NOC_TRACE_CLK = CLOCK_IP_HAS_NOC_TRACE_CLK, 2753 #endif 2754 #if defined(CLOCK_IP_HAS_NANO_CLK) 2755 NANO_CLK = CLOCK_IP_HAS_NANO_CLK, 2756 #endif 2757 #if defined(CLOCK_IP_HAS_SAR_ADC_CLK) 2758 SAR_ADC_CLK = CLOCK_IP_HAS_SAR_ADC_CLK, 2759 #endif 2760 #if defined(CLOCK_IP_HAS_SDA_AP_CLK) 2761 SDA_AP_CLK = CLOCK_IP_HAS_SDA_AP_CLK, 2762 #endif 2763 #if defined(CLOCK_IP_HAS_SDADC0_CLK) 2764 SDADC0_CLK = CLOCK_IP_HAS_SDADC0_CLK, 2765 #endif 2766 #if defined(CLOCK_IP_HAS_SDADC1_CLK) 2767 SDADC1_CLK = CLOCK_IP_HAS_SDADC1_CLK, 2768 #endif 2769 #if defined(CLOCK_IP_HAS_SDADC2_CLK) 2770 SDADC2_CLK = CLOCK_IP_HAS_SDADC2_CLK, 2771 #endif 2772 #if defined(CLOCK_IP_HAS_SDADC3_CLK) 2773 SDADC3_CLK = CLOCK_IP_HAS_SDADC3_CLK, 2774 #endif 2775 #if defined(CLOCK_IP_HAS_SEMA42_1_CLK) 2776 SEMA42_1_CLK = CLOCK_IP_HAS_SEMA42_1_CLK, 2777 #endif 2778 #if defined(CLOCK_IP_HAS_SIUL2_CLK) 2779 SIUL2_CLK = CLOCK_IP_HAS_SIUL2_CLK, 2780 #endif 2781 #if defined(CLOCK_IP_HAS_SPT_CLK) 2782 SPT_CLK = CLOCK_IP_HAS_SPT_CLK, 2783 #endif 2784 #if defined(CLOCK_IP_HAS_SRAM_CLK) 2785 SRAM_CLK = CLOCK_IP_HAS_SRAM_CLK, 2786 #endif 2787 #if defined(CLOCK_IP_HAS_STCU_CLK) 2788 STCU_CLK = CLOCK_IP_HAS_STCU_CLK, 2789 #endif 2790 #if defined(CLOCK_IP_HAS_TMU_CLK) 2791 TMU_CLK = CLOCK_IP_HAS_TMU_CLK, 2792 #endif 2793 #if defined(CLOCK_IP_HAS_WKPU_CLK) 2794 WKPU_CLK = CLOCK_IP_HAS_WKPU_CLK, 2795 #endif 2796 #if defined(CLOCK_IP_HAS_XRDC0_CLK) 2797 XRDC0_CLK = CLOCK_IP_HAS_XRDC0_CLK, 2798 #endif 2799 #if defined(CLOCK_IP_HAS_XRDC1_CLK) 2800 XRDC1_CLK = CLOCK_IP_HAS_XRDC1_CLK, 2801 #endif 2802 #if defined(CLOCK_IP_HAS_CORE_PLL_REFCLKOUT) 2803 CORE_PLL_REFCLKOUT = CLOCK_IP_HAS_CORE_PLL_REFCLKOUT, 2804 #endif 2805 #if defined(CLOCK_IP_HAS_CORE_PLL_FBCLKOUT) 2806 CORE_PLL_FBCLKOUT = CLOCK_IP_HAS_CORE_PLL_FBCLKOUT, 2807 #endif 2808 #if defined(CLOCK_IP_HAS_PERIPH_PLL_REFCLKOUT) 2809 PERIPH_PLL_REFCLKOUT = CLOCK_IP_HAS_PERIPH_PLL_REFCLKOUT, 2810 #endif 2811 #if defined(CLOCK_IP_HAS_PERIPH_PLL_FBCLKOUT) 2812 PERIPH_PLL_FBCLKOUT = CLOCK_IP_HAS_PERIPH_PLL_FBCLKOUT, 2813 #endif 2814 #if defined(CLOCK_IP_HAS_TCLK_CLK) 2815 TCLK_CLK = CLOCK_IP_HAS_TCLK_CLK, 2816 #endif 2817 #if defined(CLOCK_IP_HAS_TCK_CLK) 2818 TCK_CLK = CLOCK_IP_HAS_TCK_CLK, 2819 #endif 2820 #if defined(CLOCK_IP_HAS_AES_CLK) 2821 AES_CLK = CLOCK_IP_HAS_AES_CLK, 2822 #endif 2823 #if defined(CLOCK_IP_HAS_AES_ACCEL_CLK) 2824 AES_ACCEL_CLK = CLOCK_IP_HAS_AES_ACCEL_CLK, 2825 #endif 2826 #if defined(CLOCK_IP_HAS_AES_APP0_CLK) 2827 AES_APP0_CLK = CLOCK_IP_HAS_AES_APP0_CLK, 2828 #endif 2829 #if defined(CLOCK_IP_HAS_AES_APP1_CLK) 2830 AES_APP1_CLK = CLOCK_IP_HAS_AES_APP1_CLK, 2831 #endif 2832 #if defined(CLOCK_IP_HAS_AES_APP2_CLK) 2833 AES_APP2_CLK = CLOCK_IP_HAS_AES_APP2_CLK, 2834 #endif 2835 #if defined(CLOCK_IP_HAS_AES_APP3_CLK) 2836 AES_APP3_CLK = CLOCK_IP_HAS_AES_APP3_CLK, 2837 #endif 2838 #if defined(CLOCK_IP_HAS_AES_APP4_CLK) 2839 AES_APP4_CLK = CLOCK_IP_HAS_AES_APP4_CLK, 2840 #endif 2841 #if defined(CLOCK_IP_HAS_AES_APP5_CLK) 2842 AES_APP5_CLK = CLOCK_IP_HAS_AES_APP5_CLK, 2843 #endif 2844 #if defined(CLOCK_IP_HAS_AES_APP6_CLK) 2845 AES_APP6_CLK = CLOCK_IP_HAS_AES_APP6_CLK, 2846 #endif 2847 #if defined(CLOCK_IP_HAS_AES_APP7_CLK) 2848 AES_APP7_CLK = CLOCK_IP_HAS_AES_APP7_CLK, 2849 #endif 2850 #if defined(CLOCK_IP_HAS_DSPI_SCK_TST_CLK) 2851 DSPI_SCK_TST_CLK = CLOCK_IP_HAS_DSPI_SCK_TST_CLK, 2852 #endif 2853 RESERVED_CLK = CLOCK_IP_FEATURE_NAMES_NO, /* Invalid clock name */ 2854 } Clock_Ip_NameType; 2855 2856 /** @brief Clock ip status return codes. */ 2857 typedef enum 2858 { 2859 CLOCK_IP_SUCCESS = 0x00U, /**< Clock tree was initialized successfully. */ 2860 CLOCK_IP_ERROR = 0x01U, /**< One of the elements timeout, clock tree couldn't be initialized. */ 2861 2862 } Clock_Ip_StatusType; 2863 2864 /** @brief Clock ip pll status return codes. */ 2865 typedef enum 2866 { 2867 CLOCK_IP_PLL_LOCKED = 0x00U, /**< PLL is locked */ 2868 CLOCK_IP_PLL_UNLOCKED = 0x01U, /**< PLL is unlocked */ 2869 CLOCK_IP_PLL_STATUS_UNDEFINED = 0x02U, /**< PLL Status is unknown */ 2870 2871 } Clock_Ip_PllStatusType; 2872 2873 /** @brief Clock ip report error types. */ 2874 typedef enum 2875 { 2876 CLOCK_IP_CMU_ERROR = 0U, /**< @brief Cmu Fccu notification. */ 2877 CLOCK_IP_REPORT_TIMEOUT_ERROR = 1U, /**< @brief Report Timeout Error. */ 2878 CLOCK_IP_REPORT_FXOSC_CONFIGURATION_ERROR = 2U, /**< @brief Report Fxosc Configuration Error. */ 2879 CLOCK_IP_REPORT_CLOCK_MUX_SWITCH_ERROR = 3U, /**< @brief Report Clock Mux Switch Error. */ 2880 CLOCK_IP_RAM_MEMORY_CONFIG_ENTRY = 4U, /**< @brief Ram config entry point. */ 2881 CLOCK_IP_RAM_MEMORY_CONFIG_EXIT = 5U, /**< @brief Ram config exit point. */ 2882 CLOCK_IP_FLASH_MEMORY_CONFIG_ENTRY = 6U, /**< @brief Flash config entry point. */ 2883 CLOCK_IP_FLASH_MEMORY_CONFIG_EXIT = 7U, /**< @brief Flash config exit point. */ 2884 CLOCK_IP_ACTIVE = 8U, /**< @brief Report Clock Active. */ 2885 CLOCK_IP_INACTIVE = 9U, /**< @brief Report Clock Inactive. */ 2886 CLOCK_IP_REPORT_WRITE_PROTECTION_ERROR = 10U, /**< @brief Report Write Protection Error. */ 2887 } Clock_Ip_NotificationType; 2888 2889 /** @brief Clock ip trigger divider type. */ 2890 typedef enum 2891 { 2892 IMMEDIATE_DIVIDER_UPDATE, /**< @brief Immediate divider update. */ 2893 COMMON_TRIGGER_DIVIDER_UPDATE, /**< @brief Common trigger divider update. */ 2894 2895 } Clock_Ip_TriggerDividerType; 2896 2897 /*================================================================================================== 2898 * STRUCTURES AND OTHER TYPEDEFS 2899 ==================================================================================================*/ 2900 /*! 2901 * @brief Clock notifications callback type. 2902 * Implements ClockNotificationsCallbackType_Class 2903 */ 2904 typedef void (*Clock_Ip_NotificationsCallbackType)(Clock_Ip_NotificationType Error, Clock_Ip_NameType ClockName); 2905 2906 /*! 2907 * @brief Register value structure. 2908 * Implements Clock_Ip_RegisterValueType_Class 2909 */ 2910 typedef struct 2911 { 2912 uint32* RegisterAddr; /**< Register address. */ 2913 uint32 RegisterData; /**< Register value. */ 2914 2915 } Clock_Ip_RegisterValueType; 2916 2917 /*! 2918 * @brief Register index structure. 2919 * Implements Clock_Ip_RegisterIndexType_Class 2920 */ 2921 typedef struct 2922 { 2923 uint16 StartIndex; /**< Start index in register array. */ 2924 uint16 EndIndex; /**< End index in register array. */ 2925 2926 } Clock_Ip_RegisterIndexType; 2927 2928 2929 2930 /*! 2931 * @brief Clock Source IRCOSC configuration structure. 2932 * Implements Clock_Ip_IrcoscConfigType_Class 2933 */ 2934 typedef struct 2935 { 2936 Clock_Ip_NameType Name; /**< Clock name associated to ircosc */ 2937 uint16 Enable; /**< Enable ircosc. */ 2938 2939 uint8 Regulator; /**< Enable regulator. */ 2940 uint8 Range; /**< Ircosc range. */ 2941 uint8 LowPowerModeEnable; /**< Ircosc enable in VLP mode */ 2942 uint8 StopModeEnable; /**< Ircosc enable in STOP mode */ 2943 2944 } Clock_Ip_IrcoscConfigType; 2945 2946 /*! 2947 * @brief CGM Clock Source XOSC configuration structure. 2948 * Implements Clock_Ip_XoscConfigType_Class 2949 */ 2950 typedef struct 2951 { 2952 Clock_Ip_NameType Name; /**< Clock name associated to xosc */ 2953 2954 uint32 Freq; /**< External oscillator frequency. */ 2955 2956 uint16 Enable; /**< Enable xosc. */ 2957 2958 uint16 StartupDelay; /**< Startup stabilization time. */ 2959 uint8 BypassOption; /**< XOSC bypass option */ 2960 uint8 CompEn; /**< Comparator enable */ 2961 uint8 TransConductance; /**< Crystal overdrive protection */ 2962 2963 uint8 Gain; /**< Gain value */ 2964 uint8 Monitor; /**< Monitor type */ 2965 uint8 AutoLevelController; /**< Automatic level controller */ 2966 2967 } Clock_Ip_XoscConfigType; 2968 2969 /*! 2970 * @brief CGM Clock Source PLLDIG configuration structure. 2971 * Implements Clock_Ip_PllConfigType_Class 2972 */ 2973 typedef struct 2974 { 2975 Clock_Ip_NameType Name; /**< Clock name associated to pll */ 2976 2977 uint16 Enable; /**< Enable pll. */ 2978 2979 Clock_Ip_NameType InputReference; /**< Input reference. */ 2980 2981 uint8 Bypass; /**< Bypass pll. */ 2982 2983 uint8 Predivider; /**< Input clock predivider. */ 2984 uint16 Multiplier; /**< Clock multiplier. */ 2985 uint8 Postdivider; /**< Clock postidivder.*/ 2986 2987 uint16 NumeratorFracLoopDiv; /**< Numerator of fractional loop division factor (MFN) */ 2988 uint8 MulFactorDiv; /**< Multiplication factor divider (MFD) */ 2989 2990 uint8 FrequencyModulationBypass; /**< Enable/disable modulation */ 2991 uint8 ModulationType; /**< Modulation type */ 2992 uint16 ModulationPeriod; /**< Stepsize - modulation period */ 2993 uint16 IncrementStep; /**< Stepno - step no */ 2994 2995 uint8 SigmaDelta; /**< Sigma Delta Modulation Enable */ 2996 2997 uint8 DitherControl; /**< Dither control enable */ 2998 uint8 DitherControlValue; /**< Dither control value */ 2999 3000 uint8 Monitor; /**< Monitor type */ 3001 3002 uint16 Dividers[3U]; /**< Dividers values */ 3003 3004 } Clock_Ip_PllConfigType; 3005 3006 /*! 3007 * @brief Clock selector configuration structure. 3008 * Implements Clock_Ip_SelectorConfigType_Class 3009 */ 3010 typedef struct 3011 { 3012 Clock_Ip_NameType Name; /**< Clock name associated to selector */ 3013 Clock_Ip_NameType Value; /**< Name of the selected input source */ 3014 3015 } Clock_Ip_SelectorConfigType; 3016 3017 /*! 3018 * @brief Clock divider configuration structure. 3019 * Implements Clock_Ip_DividerConfigType_Class 3020 */ 3021 typedef struct 3022 { 3023 Clock_Ip_NameType Name; /**< Clock name associated to divider. */ 3024 uint32 Value; /**< Divider value - if value is zero then divider is disabled. */ 3025 uint8 Options[1U]; /**< Option divider value - this value depend hardware information. */ 3026 } Clock_Ip_DividerConfigType; 3027 3028 /*! 3029 * @brief Clock divider trigger configuration structure. 3030 * Implements Clock_Ip_DividerTriggerConfigType_Class 3031 */ 3032 typedef struct 3033 { 3034 Clock_Ip_NameType Name; /**< Clock name associated to divider for which trigger is configured. */ 3035 Clock_Ip_TriggerDividerType TriggerType; /**< Trigger value - if value is zero then divider is updated immediately, divider is not triggered. */ 3036 Clock_Ip_NameType Source; /**< Clock name of the common input source of all dividers from the same group that support a common update */ 3037 3038 } Clock_Ip_DividerTriggerConfigType; 3039 3040 3041 3042 /*! 3043 * @brief Clock fractional divider configuration structure. 3044 * Implements Clock_Ip_FracDivConfigType_Class 3045 */ 3046 typedef struct 3047 { 3048 Clock_Ip_NameType Name; /**< Clock name associated to fractional divider. */ 3049 uint8 Enable; /**< Enable control for port n */ 3050 uint32 Value[2U]; /**< Fractional dividers */ 3051 3052 } Clock_Ip_FracDivConfigType; 3053 3054 /*! 3055 * @brief Clock external clock configuration structure. 3056 * Implements Clock_Ip_ExtClkConfigType_Class 3057 */ 3058 typedef struct 3059 { 3060 Clock_Ip_NameType Name; /**< Clock name of the external clock. */ 3061 uint32 Value; /**< Enable value - if value is zero then clock is gated, otherwise is enabled in different modes. */ 3062 3063 } Clock_Ip_ExtClkConfigType; 3064 3065 /*! 3066 * @brief Clock Source PCFS configuration structure. 3067 * Implements Clock_Ip_PcfsConfigType_Class 3068 */ 3069 typedef struct 3070 { 3071 Clock_Ip_NameType Name; /**< Clock source from which ramp-down and to which ramp-up are processed. */ 3072 uint32 MaxAllowableIDDchange; /**< Maximum variation of current per time (mA/microsec) - max allowable IDD change is determined by the user's power supply design. */ 3073 uint32 StepDuration; /**< Step duration of each PCFS step */ 3074 Clock_Ip_NameType SelectorName; /**< Name of the selector that supports PCFS and name is one the inputs that can be selected */ 3075 uint32 ClockSourceFrequency; /**< Frequency of the clock source from which ramp-down and to which ramp-up are processed. */ 3076 3077 } Clock_Ip_PcfsConfigType; 3078 3079 /*! 3080 * @brief Clock gate clock configuration structure. 3081 * Implements Clock_Ip_GateConfigType_Class 3082 */ 3083 typedef struct 3084 { 3085 Clock_Ip_NameType Name; /**< Clock name associated to clock gate. */ 3086 uint16 Enable; /**< Enable or disable clock */ 3087 3088 } Clock_Ip_GateConfigType; 3089 3090 /*! 3091 * @brief Clock cmu configuration structure. 3092 * Implements Clock_Ip_CmuConfigType_Class 3093 */ 3094 typedef struct 3095 { 3096 Clock_Ip_NameType Name; /**< Clock name associated to clock monitor. */ 3097 uint8 Enable; /**< Enable/disable clock monitor */ 3098 uint32 Interrupt; /**< Enable/disable interrupt */ 3099 uint32 MonitoredClockFrequency; /**< Frequency of the clock source from which ramp-down and to which ramp-up are processed. */ 3100 Clock_Ip_RegisterIndexType Indexes; /**< Register index if register value optimization is enabled. */ 3101 } Clock_Ip_CmuConfigType; 3102 3103 /*! 3104 * @brief Configured frequency structure. 3105 * Implements Clock_Ip_ConfiguredFrequencyType_Class 3106 */ 3107 typedef struct 3108 { 3109 Clock_Ip_NameType Name; /**< Clock name of the configured frequency value */ 3110 uint32 ConfiguredFrequencyValue; /**< Configured frequency value */ 3111 } Clock_Ip_ConfiguredFrequencyType; 3112 3113 /*! 3114 * @brief Clock configuration structure. 3115 * Implements Clock_Ip_ClockConfigType_Class 3116 */ 3117 typedef struct 3118 { 3119 uint32 ClkConfigId; /**< The ID for Clock configuration */ 3120 3121 const Clock_Ip_RegisterValueType (*RegValues)[]; /**< Pointer to register values array */ 3122 3123 uint8 IrcoscsCount; /**< IRCOSCs count */ 3124 uint8 XoscsCount; /**< XOSCs count */ 3125 uint8 PllsCount; /**< PLLs count */ 3126 uint8 SelectorsCount; /**< Selectors count */ 3127 uint8 DividersCount; /**< Dividers count */ 3128 uint8 DividerTriggersCount; /**< Divider triggers count */ 3129 uint8 FracDivsCount; /**< Fractional dividers count */ 3130 uint8 ExtClksCount; /**< External clocks count */ 3131 uint8 GatesCount; /**< Clock gates count */ 3132 uint8 PcfsCount; /**< Clock pcfs count */ 3133 uint8 CmusCount; /**< Clock cmus count */ 3134 uint8 ConfigureFrequenciesCount; /**< Configured frequencies count */ 3135 3136 const Clock_Ip_IrcoscConfigType (*Ircoscs)[]; /**< IRCOSCs */ 3137 const Clock_Ip_XoscConfigType (*Xoscs)[]; /**< XOSCs */ 3138 const Clock_Ip_PllConfigType (*Plls)[]; /**< PLLs */ 3139 const Clock_Ip_SelectorConfigType (*Selectors)[]; /**< Selectors */ 3140 const Clock_Ip_DividerConfigType (*Dividers)[]; /**< Dividers */ 3141 const Clock_Ip_DividerTriggerConfigType (*DividerTriggers)[]; /**< Divider triggers */ 3142 const Clock_Ip_FracDivConfigType (*FracDivs)[]; /**< Fractional dividers */ 3143 const Clock_Ip_ExtClkConfigType (*ExtClks)[]; /**< External clocks */ 3144 const Clock_Ip_GateConfigType (*Gates)[]; /**< Clock gates */ 3145 const Clock_Ip_PcfsConfigType (*Pcfs)[]; /**< Progressive clock switching */ 3146 const Clock_Ip_CmuConfigType (*Cmus)[]; /**< Clock cmus */ 3147 const Clock_Ip_ConfiguredFrequencyType (*ConfiguredFrequencies)[]; /**< Configured frequency values */ 3148 3149 } Clock_Ip_ClockConfigType; 3150 3151 /*================================================================================================== 3152 * GLOBAL VARIABLE DECLARATIONS 3153 ==================================================================================================*/ 3154 3155 /*================================================================================================== 3156 * FUNCTION PROTOTYPES 3157 ==================================================================================================*/ 3158 3159 /*================================================================================================== 3160 CONFIGURATION STRUCTURE 3161 ==================================================================================================*/ 3162 3163 3164 #if defined(__cplusplus) 3165 } 3166 #endif /* __cplusplus*/ 3167 3168 /*! @}*/ 3169 3170 #endif /* CLOCK_IP_TYPES_H */ 3171 3172 3173
