1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : SYSINFO
10 // Version        : 1
11 // Bus type       : apb
12 // =============================================================================
13 #ifndef _HARDWARE_REGS_SYSINFO_H
14 #define _HARDWARE_REGS_SYSINFO_H
15 // =============================================================================
16 // Register    : SYSINFO_CHIP_ID
17 // Description : JEDEC JEP-106 compliant chip identifier.
18 #define SYSINFO_CHIP_ID_OFFSET _u(0x00000000)
19 #define SYSINFO_CHIP_ID_BITS   _u(0xffffffff)
20 #define SYSINFO_CHIP_ID_RESET  _u(0x00000001)
21 // -----------------------------------------------------------------------------
22 // Field       : SYSINFO_CHIP_ID_REVISION
23 #define SYSINFO_CHIP_ID_REVISION_RESET  "-"
24 #define SYSINFO_CHIP_ID_REVISION_BITS   _u(0xf0000000)
25 #define SYSINFO_CHIP_ID_REVISION_MSB    _u(31)
26 #define SYSINFO_CHIP_ID_REVISION_LSB    _u(28)
27 #define SYSINFO_CHIP_ID_REVISION_ACCESS "RO"
28 // -----------------------------------------------------------------------------
29 // Field       : SYSINFO_CHIP_ID_PART
30 #define SYSINFO_CHIP_ID_PART_RESET  "-"
31 #define SYSINFO_CHIP_ID_PART_BITS   _u(0x0ffff000)
32 #define SYSINFO_CHIP_ID_PART_MSB    _u(27)
33 #define SYSINFO_CHIP_ID_PART_LSB    _u(12)
34 #define SYSINFO_CHIP_ID_PART_ACCESS "RO"
35 // -----------------------------------------------------------------------------
36 // Field       : SYSINFO_CHIP_ID_MANUFACTURER
37 #define SYSINFO_CHIP_ID_MANUFACTURER_RESET  "-"
38 #define SYSINFO_CHIP_ID_MANUFACTURER_BITS   _u(0x00000ffe)
39 #define SYSINFO_CHIP_ID_MANUFACTURER_MSB    _u(11)
40 #define SYSINFO_CHIP_ID_MANUFACTURER_LSB    _u(1)
41 #define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO"
42 // -----------------------------------------------------------------------------
43 // Field       : SYSINFO_CHIP_ID_STOP_BIT
44 #define SYSINFO_CHIP_ID_STOP_BIT_RESET  _u(0x1)
45 #define SYSINFO_CHIP_ID_STOP_BIT_BITS   _u(0x00000001)
46 #define SYSINFO_CHIP_ID_STOP_BIT_MSB    _u(0)
47 #define SYSINFO_CHIP_ID_STOP_BIT_LSB    _u(0)
48 #define SYSINFO_CHIP_ID_STOP_BIT_ACCESS "RO"
49 // =============================================================================
50 // Register    : SYSINFO_PACKAGE_SEL
51 #define SYSINFO_PACKAGE_SEL_OFFSET _u(0x00000004)
52 #define SYSINFO_PACKAGE_SEL_BITS   _u(0x00000001)
53 #define SYSINFO_PACKAGE_SEL_RESET  _u(0x00000000)
54 #define SYSINFO_PACKAGE_SEL_MSB    _u(0)
55 #define SYSINFO_PACKAGE_SEL_LSB    _u(0)
56 #define SYSINFO_PACKAGE_SEL_ACCESS "RO"
57 // =============================================================================
58 // Register    : SYSINFO_PLATFORM
59 // Description : Platform register. Allows software to know what environment it
60 //               is running in during pre-production development. Post-
61 //               production, the PLATFORM is always ASIC, non-SIM.
62 #define SYSINFO_PLATFORM_OFFSET _u(0x00000008)
63 #define SYSINFO_PLATFORM_BITS   _u(0x0000001f)
64 #define SYSINFO_PLATFORM_RESET  _u(0x00000000)
65 // -----------------------------------------------------------------------------
66 // Field       : SYSINFO_PLATFORM_GATESIM
67 #define SYSINFO_PLATFORM_GATESIM_RESET  "-"
68 #define SYSINFO_PLATFORM_GATESIM_BITS   _u(0x00000010)
69 #define SYSINFO_PLATFORM_GATESIM_MSB    _u(4)
70 #define SYSINFO_PLATFORM_GATESIM_LSB    _u(4)
71 #define SYSINFO_PLATFORM_GATESIM_ACCESS "RO"
72 // -----------------------------------------------------------------------------
73 // Field       : SYSINFO_PLATFORM_BATCHSIM
74 #define SYSINFO_PLATFORM_BATCHSIM_RESET  "-"
75 #define SYSINFO_PLATFORM_BATCHSIM_BITS   _u(0x00000008)
76 #define SYSINFO_PLATFORM_BATCHSIM_MSB    _u(3)
77 #define SYSINFO_PLATFORM_BATCHSIM_LSB    _u(3)
78 #define SYSINFO_PLATFORM_BATCHSIM_ACCESS "RO"
79 // -----------------------------------------------------------------------------
80 // Field       : SYSINFO_PLATFORM_HDLSIM
81 #define SYSINFO_PLATFORM_HDLSIM_RESET  "-"
82 #define SYSINFO_PLATFORM_HDLSIM_BITS   _u(0x00000004)
83 #define SYSINFO_PLATFORM_HDLSIM_MSB    _u(2)
84 #define SYSINFO_PLATFORM_HDLSIM_LSB    _u(2)
85 #define SYSINFO_PLATFORM_HDLSIM_ACCESS "RO"
86 // -----------------------------------------------------------------------------
87 // Field       : SYSINFO_PLATFORM_ASIC
88 #define SYSINFO_PLATFORM_ASIC_RESET  "-"
89 #define SYSINFO_PLATFORM_ASIC_BITS   _u(0x00000002)
90 #define SYSINFO_PLATFORM_ASIC_MSB    _u(1)
91 #define SYSINFO_PLATFORM_ASIC_LSB    _u(1)
92 #define SYSINFO_PLATFORM_ASIC_ACCESS "RO"
93 // -----------------------------------------------------------------------------
94 // Field       : SYSINFO_PLATFORM_FPGA
95 #define SYSINFO_PLATFORM_FPGA_RESET  "-"
96 #define SYSINFO_PLATFORM_FPGA_BITS   _u(0x00000001)
97 #define SYSINFO_PLATFORM_FPGA_MSB    _u(0)
98 #define SYSINFO_PLATFORM_FPGA_LSB    _u(0)
99 #define SYSINFO_PLATFORM_FPGA_ACCESS "RO"
100 // =============================================================================
101 // Register    : SYSINFO_GITREF_RP2350
102 // Description : Git hash of the chip source. Used to identify chip version.
103 #define SYSINFO_GITREF_RP2350_OFFSET _u(0x00000014)
104 #define SYSINFO_GITREF_RP2350_BITS   _u(0xffffffff)
105 #define SYSINFO_GITREF_RP2350_RESET  "-"
106 #define SYSINFO_GITREF_RP2350_MSB    _u(31)
107 #define SYSINFO_GITREF_RP2350_LSB    _u(0)
108 #define SYSINFO_GITREF_RP2350_ACCESS "RO"
109 // =============================================================================
110 #endif // _HARDWARE_REGS_SYSINFO_H
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