1 /* 2 * Copyright (c) 2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef __NI_TOWER_LIB_H__ 9 #define __NI_TOWER_LIB_H__ 10 11 #include "ni_tower_rse_drv.h" 12 13 #include <stdint.h> 14 15 #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof((arr)[0])) 16 17 /* 18 * Platform specific apu region initialization macro wrapper. This macros 19 * returns 'struct ni_tower_apu_reg_cfg_info' definition by providing 20 * the base and end address of APU region and the associated access permission. 21 */ 22 #define INIT_APU_REGION(base, end, perm) \ 23 { \ 24 .base_addr = base, \ 25 .end_addr = end, \ 26 .background = NI_T_FOREGROUND, \ 27 .permissions = { perm, 0, 0, 0 }, \ 28 .entity_ids = { 0, 0, 0, 0 }, \ 29 .id_valid = NI_T_ID_VALID_NONE, \ 30 .region_enable = NI_T_REGION_ENABLE, \ 31 .lock = NI_T_LOCK \ 32 } 33 34 /* 35 * Platform specific apu region initialization macro wrapper with APU ID 36 * Filtering. This macro returns 'struct ni_tower_apu_reg_cfg_info' definition 37 * by providing the base and end address of APU region and the associated 38 * access permission for all four enitities. 39 */ 40 #define INIT_APU_REGION_WITH_ALL_ID_FILTER(base, end, mcp_perm, scp_perm, \ 41 rse_perm, dap_perm) \ 42 { \ 43 .base_addr = base, \ 44 .end_addr = end, \ 45 .background = NI_T_FOREGROUND, \ 46 .permissions = { mcp_perm, scp_perm, rse_perm, dap_perm }, \ 47 .entity_ids = { SYSCTRL_MCP_APU_ID, SYSCTRL_SCP_APU_ID, \ 48 SYSCTRL_RSE_APU_ID, SYSCTRL_DAP_APU_ID }, \ 49 .id_valid = NI_T_ID_VALID_ALL, \ 50 .region_enable = NI_T_REGION_ENABLE, \ 51 .lock = NI_T_LOCK \ 52 } 53 54 /* 55 * Platform specific apu region initialization macro wrapper without locking 56 * the region. This macros returns 'struct ni_tower_apu_reg_cfg_info' 57 * definition by providing the base and end address of APU region and the 58 * associated access permission. 59 */ 60 #define INIT_APU_REGION_UNLOCKED(base, end, perm) \ 61 { \ 62 .base_addr = base, \ 63 .end_addr = end, \ 64 .background = NI_T_FOREGROUND, \ 65 .permissions = { perm, 0, 0, 0 }, \ 66 .entity_ids = { 0, 0, 0, 0 }, \ 67 .id_valid = NI_T_ID_VALID_NONE, \ 68 .region_enable = NI_T_REGION_ENABLE, \ 69 .lock = NI_T_UNLOCK \ 70 } 71 72 /* Interface ID of xSNI components - completer interfaces */ 73 enum sysctrl_xSNI_ids { 74 /* Request from AP */ 75 SYSCTRL_APP_ASNI_ID = 0x0, 76 /* Request from LCP */ 77 SYSCTRL_LCP_ASNI_ID, 78 /* Request from MCP ATU */ 79 SYSCTRL_MCP_ASNI_ID, 80 /* Request from RSE ATU */ 81 SYSCTRL_RSE_MAIN_ASNI_ID, 82 /* Request from RSE and SCP targeting LCP address space */ 83 SYSCTRL_RSE_SCP_ASNI_ID, 84 /* Request from SCP ATU */ 85 SYSCTRL_SCP_ASNI_ID 86 }; 87 88 /* Interface ID of xMNI components - requester interfaces */ 89 enum sysctrl_xMNI_ids { 90 /* Targets AP address space */ 91 SYSCTRL_APP_AMNI_ID = 0x0, 92 /* Targets memory map shared between AP and MCP */ 93 SYSCTRL_APP_MCP_AMNI_ID, 94 /* Targets memory map shared between AP and SCP */ 95 SYSCTRL_APP_SCP_AMNI_ID, 96 /* Targets LCP address space */ 97 SYSCTRL_LCP_AMNI_ID, 98 /* Targets memory map shared between LCP and SCP */ 99 SYSCTRL_LCP_SCP_AMNI_ID, 100 /* Targets Shared SRAM between RSE, SCP and MCP */ 101 SYSCTRL_RSM_AMNI_ID, 102 /* Targets MCP address space */ 103 SYSCTRL_RSE_MCP_AMNI_ID, 104 /* Targets SCP address space */ 105 SYSCTRL_RSE_SCP_AMNI_ID, 106 /* Targets CMN GPV registers */ 107 SYSCTRL_CMN_PMNI_ID, 108 /* Targets Shared RAM between RSE/SCP/MCP */ 109 SYSCTRL_RSM_PMNI_ID, 110 /* Targets SYSCTRL SMMU registers */ 111 SYSCTRL_TCU_PMNI_ID, 112 /* Targets the System Control NI-Tower registers (default target) */ 113 SYSCTRL_CONFIG_SPACE_ID = 0xF 114 }; 115 116 /* APU IDs of the initiator for filter access */ 117 enum sysctrl_apu_filter_ids { 118 SYSCTRL_MCP_APU_ID = 0x3C, 119 SYSCTRL_SCP_APU_ID = 0x3D, 120 SYSCTRL_RSE_APU_ID = 0x3E, 121 SYSCTRL_DAP_APU_ID = 0x3F, 122 }; 123 124 /* Interface ID of Peripheral xMNI components */ 125 enum periph_xMNI_ids { 126 /* Targets ARSM SRAM */ 127 PERIPH_RAM_AMNI_ID = 0x0, 128 /* Targets Secure SRAM Error record block for the shared ARSM SRAM */ 129 PERIPH_ECCREG_PMNI_ID, 130 /* Targets AP Generic Timer Control Frame */ 131 PERIPH_GTIMERCTRL_PMNI_ID, 132 /* Targets AP Non-secure WatchDog */ 133 PERIPH_NSGENWDOG_PMNI_ID, 134 /* Targets AP Non-secure Generic Timer Control Base Frame */ 135 PERIPH_NSGTIMER_PMNI_ID, 136 /* Targets AP Non-secure UART */ 137 PERIPH_NSUART0_PMNI_ID, 138 /* Targets AP Non-secure UART for RMM debug */ 139 PERIPH_NSUART1_PMNI_ID, 140 /* Targets AP root WatchDog */ 141 PERIPH_ROOTGENWDOG_PMNI_ID, 142 /* Targets AP Secure WatchDog */ 143 PERIPH_SECGENWDOG_PMNI_ID, 144 /* Targets AP Secure Generic Timer Control Base Frame */ 145 PERIPH_SECGTIMER_PMNI_ID, 146 /* Targets AP Secure UART */ 147 PERIPH_SECUART_PMNI_ID 148 }; 149 150 /** 151 * \brief Programs System Control block NI-Tower PSAM and APU for AON domain 152 * 153 * \param[in] chip_id Current Chip ID 154 * 155 * \return Returns -1 if there is an error, else 0. 156 */ 157 int32_t program_sysctrl_ni_tower_aon(uint32_t chip_id); 158 159 /** 160 * \brief Programs System Control block NI-Tower PSAM and APU for SYSTOP domain 161 * 162 * \return Returns -1 if there is an error, else 0. 163 */ 164 int32_t program_sysctrl_ni_tower_systop(void); 165 166 /** 167 * \brief Program NI-Tower peripheral block APU 168 * 169 * \return Returns -1 if there is an error, else 0. 170 */ 171 int32_t program_periph_ni_tower(void); 172 173 /** 174 * \brief Program NI-Tower peripheral block APU to lock ram region after 175 * limiting the region as read only. 176 * 177 * \return Returns -1 if there is an error, else 0. 178 */ 179 int32_t program_periph_ni_tower_post_ap_bl1_load(void); 180 181 #endif /* __NI_TOWER_LIB_H__ */ 182
