1 /*! 2 \file gd32l23x_syscfg.h 3 \brief definitions for the SYSCFG 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_SYSCFG_H 36 #define GD32L23X_SYSCFG_H 37 38 #include "gd32l23x.h" 39 40 /* SYSCFG definitions */ 41 #define SYSCFG SYSCFG_BASE 42 43 /* registers definitions */ 44 #define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */ 45 #define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */ 46 #define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */ 47 #define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */ 48 #define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */ 49 #define SYSCFG_CPU_IRQ_LAT REG32(SYSCFG + 0x100U) /*!< IRQ latency register */ 50 51 /* SYSCFG_CFG0 bits definitions */ 52 #define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap config */ 53 #define SYSCFG_CFG0_PA11_PA12_RMP BIT(4) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins) */ 54 #define SYSCFG_CFG0_BOOT0_PD3_RMP BIT(6) /*!< BOOT0 and PD3 remapping bit */ 55 #define SYSCFG_CFG0_PB6_HCCE BIT(16) /*!< PB6 pin high current capability enable */ 56 #define SYSCFG_CFG0_PB7_HCCE BIT(17) /*!< PB7 pin high current capability enable */ 57 #define SYSCFG_CFG0_PB8_HCCE BIT(18) /*!< PB8 pin high current capability enable */ 58 #define SYSCFG_CFG0_PB9_HCCE BIT(19) /*!< PB9 pin high current capability enable */ 59 60 /* SYSCFG_EXTISS0 bits definitions */ 61 #define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */ 62 #define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */ 63 #define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */ 64 #define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */ 65 66 /* SYSCFG_EXTISS1 bits definitions */ 67 #define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */ 68 #define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */ 69 #define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */ 70 #define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */ 71 72 /* SYSCFG_EXTISS2 bits definitions */ 73 #define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */ 74 #define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */ 75 #define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */ 76 #define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */ 77 78 /* SYSCFG_EXTISS3 bits definitions */ 79 #define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */ 80 #define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */ 81 #define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */ 82 #define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */ 83 84 /* SYSCFG_VREF_CS bits definitions */ 85 #define SYSCFG_VREFEN BIT(0) /*!< VREF enable */ 86 #define SYSCFG_HIPM BIT(1) /*!< High impedance mode */ 87 #define SYSCFG_VREFRDY BIT(3) /*!< VREF ready */ 88 89 /* SYSCFG_VREF_CALIB bits definitions */ 90 #define SYSCFG_VREF_CALIB_VREFCAL BITS(0,5) /*!< VREF calibration value */ 91 92 /* SYSCFG_CPU_IRQ_LAT bits definitions */ 93 #define SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY BITS(0,7) /*!< IRQ_LATENCY specifies the minimum number of cycles between an interrupt */ 94 95 /* constants definitions */ 96 /* boot mode definitions */ 97 #define SYSCFG_BOOTMODE_FLASH ((uint8_t)0x00U) /*!< boot from main flash */ 98 #define SYSCFG_BOOTMODE_SYSTEM ((uint8_t)0x01U) /*!< boot from system flash memory */ 99 #define SYSCFG_BOOTMODE_SRAM ((uint8_t)0x03U) /*!< boot from embedded SRAM */ 100 101 /* DMA remap definitions */ 102 #define SYSCFG_PA11_PA12_REMAP SYSCFG_CFG0_PA11_PA12_RMP /*!< PA11 PA12 remap */ 103 #define SYSCFG_BOOT0_PD3_REMAP SYSCFG_CFG0_BOOT0_PD3_RMP /*!< BOOT0 PD3 remap */ 104 105 /* pin high current capability definitions */ 106 #define SYSCFG_PB6_HIGH_CURRENT SYSCFG_CFG0_PB6_HCCE /*!< PB6 pin high current capability */ 107 #define SYSCFG_PB7_HIGH_CURRENT SYSCFG_CFG0_PB7_HCCE /*!< PB7 pin high current capability */ 108 #define SYSCFG_PB8_HIGH_CURRENT SYSCFG_CFG0_PB8_HCCE /*!< PB7 pin high current capability */ 109 #define SYSCFG_PB9_HIGH_CURRENT SYSCFG_CFG0_PB9_HCCE /*!< PB9 pin high current capability */ 110 111 /* EXTI source select definition */ 112 #define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */ 113 #define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */ 114 #define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */ 115 #define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */ 116 117 /* EXTI source select mask bits definition */ 118 #define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ 119 120 /* EXTI source select jumping step definition */ 121 #define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */ 122 123 /* EXTI source select moving step definition */ 124 #define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ 125 126 /* EXTI source port definitions */ 127 #define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ 128 #define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */ 129 #define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */ 130 #define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */ 131 #define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */ 132 133 /* EXTI source pin definitions */ 134 #define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */ 135 #define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */ 136 #define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */ 137 #define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */ 138 #define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */ 139 #define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */ 140 #define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */ 141 #define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */ 142 #define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */ 143 #define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */ 144 #define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */ 145 #define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */ 146 #define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */ 147 #define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */ 148 #define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */ 149 #define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ 150 151 /* SYSCFG_CPU_IRQ_LAT register IRQ_LATENCY value */ 152 #define IRQ_LATENCY(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to IRQ_LATENCY bits field */ 153 154 /* function declarations */ 155 /* initialization functions */ 156 /* reset the SYSCFG registers */ 157 void syscfg_deinit(void); 158 159 /* configure the GPIO pin as EXTI Line */ 160 void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); 161 162 /* enable remap pin function for small packages */ 163 void syscfg_pin_remap_enable(uint32_t remap_pin); 164 /* disable remap pin function for small packages */ 165 void syscfg_pin_remap_disable(uint32_t remap_pin); 166 167 /* enable PBx(x=6,7,8,9) high current capability */ 168 void syscfg_high_current_enable(uint32_t syscfg_gpio); 169 /* disable PBx(x=6,7,8,9) high current capability */ 170 void syscfg_high_current_disable(uint32_t syscfg_gpio); 171 172 /* set the IRQ_LATENCY value */ 173 void irq_latency_set(uint8_t irq_latency); 174 /* get the boot mode */ 175 uint8_t syscfg_bootmode_get(void); 176 177 #endif /* gd32l23x_SYSCFG_H */ 178
