1 /****************************************************************************** 2 * Filename: hw_sys0_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_SYS0_H__ 34 #define __HW_SYS0_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // SYS0 component 40 // 41 //***************************************************************************** 42 // Description Register 43 #define SYS0_O_DESC 0x00000000U 44 45 // Mutable section Unlock 46 #define SYS0_O_MUNLOCK 0x0000000CU 47 48 // ATEST Configuration 49 #define SYS0_O_ATESTCFG 0x00000100U 50 51 // TSENSE Configuration 52 #define SYS0_O_TSENSCFG 0x00000108U 53 54 // LPCMP configuration 55 #define SYS0_O_LPCMPCFG 0x0000010CU 56 57 // Device ID 58 #define SYS0_O_DEVICEID 0x000003FCU 59 60 // Part ID 61 #define SYS0_O_PARTID 0x000007F8U 62 63 // Internal. Only to be used through TI provided API. 64 #define SYS0_O_TMUTE0 0x00000800U 65 66 // Internal. Only to be used through TI provided API. 67 #define SYS0_O_TMUTE1 0x00000804U 68 69 // TMUTE2 trim Register 70 #define SYS0_O_TMUTE2 0x00000808U 71 72 // Internal. Only to be used through TI provided API. 73 #define SYS0_O_TMUTE3 0x0000080CU 74 75 // TMUTE4 trim Register 76 #define SYS0_O_TMUTE4 0x00000810U 77 78 // Internal. Only to be used through TI provided API. 79 #define SYS0_O_TMUTE5 0x00000814U 80 81 //***************************************************************************** 82 // 83 // Register: SYS0_O_DESC 84 // 85 //***************************************************************************** 86 // Field: [31:16] MODID 87 // 88 // Module Identifier is used to uniquely identify this IP 89 #define SYS0_DESC_MODID_W 16U 90 #define SYS0_DESC_MODID_M 0xFFFF0000U 91 #define SYS0_DESC_MODID_S 16U 92 93 // Field: [15:12] STDIPOFF 94 // 95 // Standard IP MMR block offset. Standard IP MMRs are the set from aggregated 96 // IRQ registers till DTB. 97 // 98 // 0: Standard IP MMRs do not exist 99 // 100 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 101 // address) 102 #define SYS0_DESC_STDIPOFF_W 4U 103 #define SYS0_DESC_STDIPOFF_M 0x0000F000U 104 #define SYS0_DESC_STDIPOFF_S 12U 105 106 // Field: [11:8] INSTIDX 107 // 108 // IP Instance ID number. If multiple instances of IP exist in the device, this 109 // field can identify the instance number (0-15). 110 #define SYS0_DESC_INSTIDX_W 4U 111 #define SYS0_DESC_INSTIDX_M 0x00000F00U 112 #define SYS0_DESC_INSTIDX_S 8U 113 114 // Field: [7:4] MAJREV 115 // 116 // Major revision of IP (0-15). 117 #define SYS0_DESC_MAJREV_W 4U 118 #define SYS0_DESC_MAJREV_M 0x000000F0U 119 #define SYS0_DESC_MAJREV_S 4U 120 121 // Field: [3:0] MINREV 122 // 123 // Minor revision of IP (0-15). 124 #define SYS0_DESC_MINREV_W 4U 125 #define SYS0_DESC_MINREV_M 0x0000000FU 126 #define SYS0_DESC_MINREV_S 0U 127 128 //***************************************************************************** 129 // 130 // Register: SYS0_O_MUNLOCK 131 // 132 //***************************************************************************** 133 // Field: [31:0] KEY 134 // 135 // Write the unlock key 0xC5AF_6927 to temporarily unlock registers in mutable 136 // section. The lock is set automatically if no write accesses, to the mutable 137 // section, are detected for consecutive 32 CLKULL (24MHz) clock cycles. 138 // Writing any value other that the unlock key will immediately lock the 139 // mutable register space for write access. 140 // ENUMs: 141 // UNLOCK Unlock registers in the mutable section 142 // LOCK Lock registers in the mutable section 143 #define SYS0_MUNLOCK_KEY_W 32U 144 #define SYS0_MUNLOCK_KEY_M 0xFFFFFFFFU 145 #define SYS0_MUNLOCK_KEY_S 0U 146 #define SYS0_MUNLOCK_KEY_UNLOCK 0xC5AF6927U 147 #define SYS0_MUNLOCK_KEY_LOCK 0x00000000U 148 149 //***************************************************************************** 150 // 151 // Register: SYS0_O_ATESTCFG 152 // 153 //***************************************************************************** 154 // Field: [31:24] KEY 155 // 156 // Key must be written with value 0x5A for successful write to ATESTCFG and to 157 // unlock register state. 158 // Write with any value other than 0x5A to KEY will be ignored and register 159 // content is not updated. 160 // It is recommended to write this register with incorrect KEY to lock back 161 // register state after necessary ATESTCFG updates are done. 162 // Read value of KEY is 0x0. 163 #define SYS0_ATESTCFG_KEY_W 8U 164 #define SYS0_ATESTCFG_KEY_M 0xFF000000U 165 #define SYS0_ATESTCFG_KEY_S 24U 166 167 // Field: [8] VSEL 168 // 169 // Selects supply for ATEST switches. 170 // ENUMs: 171 // VDDA Selects VDDA 172 // VDDBST Selects VDDBOOST 173 #define SYS0_ATESTCFG_VSEL 0x00000100U 174 #define SYS0_ATESTCFG_VSEL_M 0x00000100U 175 #define SYS0_ATESTCFG_VSEL_S 8U 176 #define SYS0_ATESTCFG_VSEL_VDDA 0x00000100U 177 #define SYS0_ATESTCFG_VSEL_VDDBST 0x00000000U 178 179 // Field: [7] VA2VA1 180 // 181 // Enables isolation switch between VA_ATEST_A1 and VA_PAD_A1. 182 // ENUMs: 183 // CLOSE Switch is closed 184 // OPEN Switch is open 185 #define SYS0_ATESTCFG_VA2VA1 0x00000080U 186 #define SYS0_ATESTCFG_VA2VA1_M 0x00000080U 187 #define SYS0_ATESTCFG_VA2VA1_S 7U 188 #define SYS0_ATESTCFG_VA2VA1_CLOSE 0x00000080U 189 #define SYS0_ATESTCFG_VA2VA1_OPEN 0x00000000U 190 191 // Field: [6] VA2VA0 192 // 193 // Enables isolation switch between VA_ATEST_A0 and VA_PAD_A0. 194 // ENUMs: 195 // CLOSE Switch is closed 196 // OPEN Switch is open 197 #define SYS0_ATESTCFG_VA2VA0 0x00000040U 198 #define SYS0_ATESTCFG_VA2VA0_M 0x00000040U 199 #define SYS0_ATESTCFG_VA2VA0_S 6U 200 #define SYS0_ATESTCFG_VA2VA0_CLOSE 0x00000040U 201 #define SYS0_ATESTCFG_VA2VA0_OPEN 0x00000000U 202 203 // Field: [5] VR2VA1 204 // 205 // Enables isolation switch between VR_ATEST_A1 and VA_ATEST_A1. 206 // ENUMs: 207 // CLOSE Switch is closed 208 // OPEN Switch is open 209 #define SYS0_ATESTCFG_VR2VA1 0x00000020U 210 #define SYS0_ATESTCFG_VR2VA1_M 0x00000020U 211 #define SYS0_ATESTCFG_VR2VA1_S 5U 212 #define SYS0_ATESTCFG_VR2VA1_CLOSE 0x00000020U 213 #define SYS0_ATESTCFG_VR2VA1_OPEN 0x00000000U 214 215 // Field: [4] VR2VA0 216 // 217 // Enables isolation switch between VR_ATEST_A0 and VA_ATEST_A0. 218 // ENUMs: 219 // CLOSE Switch is closed 220 // OPEN Switch is open 221 #define SYS0_ATESTCFG_VR2VA0 0x00000010U 222 #define SYS0_ATESTCFG_VR2VA0_M 0x00000010U 223 #define SYS0_ATESTCFG_VR2VA0_S 4U 224 #define SYS0_ATESTCFG_VR2VA0_CLOSE 0x00000010U 225 #define SYS0_ATESTCFG_VR2VA0_OPEN 0x00000000U 226 227 // Field: [3] SHTVA1 228 // 229 // Shorts VA_ATEST_A1 to ground. 230 // ENUMs: 231 // CLOSE Switch is closed 232 // OPEN Switch is open 233 #define SYS0_ATESTCFG_SHTVA1 0x00000008U 234 #define SYS0_ATESTCFG_SHTVA1_M 0x00000008U 235 #define SYS0_ATESTCFG_SHTVA1_S 3U 236 #define SYS0_ATESTCFG_SHTVA1_CLOSE 0x00000008U 237 #define SYS0_ATESTCFG_SHTVA1_OPEN 0x00000000U 238 239 // Field: [2] SHTVA0 240 // 241 // Shorts VA_ATEST_A0 to ground. 242 // ENUMs: 243 // CLOSE Switch is closed 244 // OPEN Switch is open 245 #define SYS0_ATESTCFG_SHTVA0 0x00000004U 246 #define SYS0_ATESTCFG_SHTVA0_M 0x00000004U 247 #define SYS0_ATESTCFG_SHTVA0_S 2U 248 #define SYS0_ATESTCFG_SHTVA0_CLOSE 0x00000004U 249 #define SYS0_ATESTCFG_SHTVA0_OPEN 0x00000000U 250 251 // Field: [1] SHTVR1 252 // 253 // Shorts VR_ATEST_A1 to ground. 254 // ENUMs: 255 // CLOSE Switch is closed 256 // OPEN Switch is open 257 #define SYS0_ATESTCFG_SHTVR1 0x00000002U 258 #define SYS0_ATESTCFG_SHTVR1_M 0x00000002U 259 #define SYS0_ATESTCFG_SHTVR1_S 1U 260 #define SYS0_ATESTCFG_SHTVR1_CLOSE 0x00000002U 261 #define SYS0_ATESTCFG_SHTVR1_OPEN 0x00000000U 262 263 // Field: [0] SHTVR0 264 // 265 // Shorts VR_ATEST_A0 to ground. 266 // ENUMs: 267 // CLOSE Switch is closed 268 // OPEN Switch is open 269 #define SYS0_ATESTCFG_SHTVR0 0x00000001U 270 #define SYS0_ATESTCFG_SHTVR0_M 0x00000001U 271 #define SYS0_ATESTCFG_SHTVR0_S 0U 272 #define SYS0_ATESTCFG_SHTVR0_CLOSE 0x00000001U 273 #define SYS0_ATESTCFG_SHTVR0_OPEN 0x00000000U 274 275 //***************************************************************************** 276 // 277 // Register: SYS0_O_TSENSCFG 278 // 279 //***************************************************************************** 280 // Field: [11:8] SPARE 281 // 282 // Spare bits 283 #define SYS0_TSENSCFG_SPARE_W 4U 284 #define SYS0_TSENSCFG_SPARE_M 0x00000F00U 285 #define SYS0_TSENSCFG_SPARE_S 8U 286 287 // Field: [1:0] SEL 288 // 289 // Used to enable and configure temperature sensor module. Setting the value to 290 // 0x3 will disable the temperature sensor. 291 // ENUMs: 292 // GND 20uA current is injected on VR_ATEST_A0 and ground 293 // measured on VR_ATEST_A1 294 // VALUE 20uA current is injected on VR_ATEST_A0 and 295 // voltage measured on VR_ATEST_A1 296 // DISABLE Temperature sensor is disabled 297 #define SYS0_TSENSCFG_SEL_W 2U 298 #define SYS0_TSENSCFG_SEL_M 0x00000003U 299 #define SYS0_TSENSCFG_SEL_S 0U 300 #define SYS0_TSENSCFG_SEL_GND 0x00000002U 301 #define SYS0_TSENSCFG_SEL_VALUE 0x00000001U 302 #define SYS0_TSENSCFG_SEL_DISABLE 0x00000000U 303 304 //***************************************************************************** 305 // 306 // Register: SYS0_O_LPCMPCFG 307 // 308 //***************************************************************************** 309 // Field: [30] HYSPOL 310 // 311 // Spare bit for LPCOMP 312 #define SYS0_LPCMPCFG_HYSPOL 0x40000000U 313 #define SYS0_LPCMPCFG_HYSPOL_M 0x40000000U 314 #define SYS0_LPCMPCFG_HYSPOL_S 30U 315 316 // Field: [29:28] ATESTMUX 317 // 318 // Used to configure ATEST mux in comparator module and provides chosen output 319 // on VA_ATEST_A0. 320 // Note: This bit field is write-protected using global lock indicator on 321 // production device. 322 // ENUMs: 323 // IBIASOUT Selects bias current output 324 // COMP_VIN_NEG Selects voltage divider output 325 // COMPOUT Selects comparator output 326 // OFF ATEST mux is off 327 #define SYS0_LPCMPCFG_ATESTMUX_W 2U 328 #define SYS0_LPCMPCFG_ATESTMUX_M 0x30000000U 329 #define SYS0_LPCMPCFG_ATESTMUX_S 28U 330 #define SYS0_LPCMPCFG_ATESTMUX_IBIASOUT 0x30000000U 331 #define SYS0_LPCMPCFG_ATESTMUX_COMP_VIN_NEG 0x20000000U 332 #define SYS0_LPCMPCFG_ATESTMUX_COMPOUT 0x10000000U 333 #define SYS0_LPCMPCFG_ATESTMUX_OFF 0x00000000U 334 335 // Field: [24] EVTIFG 336 // 337 // Event flag 338 // 339 // The event flag is set when the comparator output transition is qualified 340 // based on the edge polarity configuration in EDGCFG. 341 // ENUMs: 342 // SET 343 // CLR Clear 344 #define SYS0_LPCMPCFG_EVTIFG 0x01000000U 345 #define SYS0_LPCMPCFG_EVTIFG_M 0x01000000U 346 #define SYS0_LPCMPCFG_EVTIFG_S 24U 347 #define SYS0_LPCMPCFG_EVTIFG_SET 0x01000000U 348 #define SYS0_LPCMPCFG_EVTIFG_CLR 0x00000000U 349 350 // Field: [21] COUTEN 351 // 352 // Enables LPCOMP output on device pin. 353 // ENUMs: 354 // EN Enabled 355 // DIS Disabled 356 #define SYS0_LPCMPCFG_COUTEN 0x00200000U 357 #define SYS0_LPCMPCFG_COUTEN_M 0x00200000U 358 #define SYS0_LPCMPCFG_COUTEN_S 21U 359 #define SYS0_LPCMPCFG_COUTEN_EN 0x00200000U 360 #define SYS0_LPCMPCFG_COUTEN_DIS 0x00000000U 361 362 // Field: [20] COUT 363 // 364 // LPCOMP output status. This bit captures the value LPCOMP raw output. 365 // ENUMs: 366 // HIGH Output is high 367 // LOW Output is low 368 #define SYS0_LPCMPCFG_COUT 0x00100000U 369 #define SYS0_LPCMPCFG_COUT_M 0x00100000U 370 #define SYS0_LPCMPCFG_COUT_S 20U 371 #define SYS0_LPCMPCFG_COUT_HIGH 0x00100000U 372 #define SYS0_LPCMPCFG_COUT_LOW 0x00000000U 373 374 // Field: [18] WUENSB 375 // 376 // Enables lpcmpcfg output to wake device from standby. 377 // ENUMs: 378 // EN Enable 379 // DIS Disable 380 #define SYS0_LPCMPCFG_WUENSB 0x00040000U 381 #define SYS0_LPCMPCFG_WUENSB_M 0x00040000U 382 #define SYS0_LPCMPCFG_WUENSB_S 18U 383 #define SYS0_LPCMPCFG_WUENSB_EN 0x00040000U 384 #define SYS0_LPCMPCFG_WUENSB_DIS 0x00000000U 385 386 // Field: [17] EVTEN 387 // 388 // Enables event generation. Comparator module will produce event on ULL event 389 // fabric when EVTIFG is set. 390 // ENUMs: 391 // EN Enable 392 // DIS Disable 393 #define SYS0_LPCMPCFG_EVTEN 0x00020000U 394 #define SYS0_LPCMPCFG_EVTEN_M 0x00020000U 395 #define SYS0_LPCMPCFG_EVTEN_S 17U 396 #define SYS0_LPCMPCFG_EVTEN_EN 0x00020000U 397 #define SYS0_LPCMPCFG_EVTEN_DIS 0x00000000U 398 399 // Field: [16] EDGCFG 400 // 401 // Selects positive edge or negative edge detection on comparator output to set 402 // the event flag 403 // ENUMs: 404 // FALL Fall edge detection 405 // RISE Rise edge detection 406 #define SYS0_LPCMPCFG_EDGCFG 0x00010000U 407 #define SYS0_LPCMPCFG_EDGCFG_M 0x00010000U 408 #define SYS0_LPCMPCFG_EDGCFG_S 16U 409 #define SYS0_LPCMPCFG_EDGCFG_FALL 0x00010000U 410 #define SYS0_LPCMPCFG_EDGCFG_RISE 0x00000000U 411 412 // Field: [14:12] NSEL 413 // 414 // Negative input selection. Setting values 0x5-0x7 will open all the switches. 415 // ENUMs: 416 // VDDD Selects VDDD 417 // VDDA Selects VDDA 418 // VA_PAD_A3 Selects VA_PAD_A3 419 // VA_PAD_A2 Selects VA_PAD_A2 420 // OPEN All switches are open 421 #define SYS0_LPCMPCFG_NSEL_W 3U 422 #define SYS0_LPCMPCFG_NSEL_M 0x00007000U 423 #define SYS0_LPCMPCFG_NSEL_S 12U 424 #define SYS0_LPCMPCFG_NSEL_VDDD 0x00004000U 425 #define SYS0_LPCMPCFG_NSEL_VDDA 0x00003000U 426 #define SYS0_LPCMPCFG_NSEL_VA_PAD_A3 0x00002000U 427 #define SYS0_LPCMPCFG_NSEL_VA_PAD_A2 0x00001000U 428 #define SYS0_LPCMPCFG_NSEL_OPEN 0x00000000U 429 430 // Field: [11:8] PSEL 431 // 432 // Positive input selection. Setting values 0x9-0xF will open all the switches. 433 // ENUMs: 434 // VDDA Selects VDDA 435 // VA_ATEST_A1 Selects VA_ATEST_A1 436 // VA_ATEST_A0 Selects VA_ATEST_A0 437 // VR_ATEST_A1 Selects VR_ATEST_A1 438 // VR_ATEST_A0 Selects VR_ATEST_A0 439 // VA_PAD_A3 Selects VA_PAD_A3 440 // VA_PAD_A2 Selects VA_PAD_A2 441 // VA_PAD_A1 Selects VA_PAD_A1 442 // OPEN All switches are open 443 #define SYS0_LPCMPCFG_PSEL_W 4U 444 #define SYS0_LPCMPCFG_PSEL_M 0x00000F00U 445 #define SYS0_LPCMPCFG_PSEL_S 8U 446 #define SYS0_LPCMPCFG_PSEL_VDDA 0x00000800U 447 #define SYS0_LPCMPCFG_PSEL_VA_ATEST_A1 0x00000700U 448 #define SYS0_LPCMPCFG_PSEL_VA_ATEST_A0 0x00000600U 449 #define SYS0_LPCMPCFG_PSEL_VR_ATEST_A1 0x00000500U 450 #define SYS0_LPCMPCFG_PSEL_VR_ATEST_A0 0x00000400U 451 #define SYS0_LPCMPCFG_PSEL_VA_PAD_A3 0x00000300U 452 #define SYS0_LPCMPCFG_PSEL_VA_PAD_A2 0x00000200U 453 #define SYS0_LPCMPCFG_PSEL_VA_PAD_A1 0x00000100U 454 #define SYS0_LPCMPCFG_PSEL_OPEN 0x00000000U 455 456 // Field: [7:5] HYSSEL 457 // 458 // Used to enable and select hysteresis level 459 // 460 // Hysteresis is disabled when HYSSEL = 0 and enabled for other values of 461 // HYSSEL from 1 to 7. Refer to device specific datasheet for individual 462 // hysteresis values. 463 // ENUMs: 464 // VAL7 Hysteresis value: TBD 465 // VAL6 Hysteresis value: TBD 466 // VAL5 Hysteresis value: TBD 467 // VAL4 Hysteresis value: TBD 468 // VAL3 Hysteresis value: TBD 469 // VAL2 Hysteresis value: TBD 470 // VAL1 Hysteresis value: TBD 471 // VAL0 Hysteresis is disabled 472 #define SYS0_LPCMPCFG_HYSSEL_W 3U 473 #define SYS0_LPCMPCFG_HYSSEL_M 0x000000E0U 474 #define SYS0_LPCMPCFG_HYSSEL_S 5U 475 #define SYS0_LPCMPCFG_HYSSEL_VAL7 0x000000E0U 476 #define SYS0_LPCMPCFG_HYSSEL_VAL6 0x000000C0U 477 #define SYS0_LPCMPCFG_HYSSEL_VAL5 0x000000A0U 478 #define SYS0_LPCMPCFG_HYSSEL_VAL4 0x00000080U 479 #define SYS0_LPCMPCFG_HYSSEL_VAL3 0x00000060U 480 #define SYS0_LPCMPCFG_HYSSEL_VAL2 0x00000040U 481 #define SYS0_LPCMPCFG_HYSSEL_VAL1 0x00000020U 482 #define SYS0_LPCMPCFG_HYSSEL_VAL0 0x00000000U 483 484 // Field: [4] DIVPATH 485 // 486 // Used to select the path on which voltage divider is applied 487 // ENUMs: 488 // PSIDE Divider is applied on P-side 489 // NSIDE Divider is applied on N-side 490 #define SYS0_LPCMPCFG_DIVPATH 0x00000010U 491 #define SYS0_LPCMPCFG_DIVPATH_M 0x00000010U 492 #define SYS0_LPCMPCFG_DIVPATH_S 4U 493 #define SYS0_LPCMPCFG_DIVPATH_PSIDE 0x00000010U 494 #define SYS0_LPCMPCFG_DIVPATH_NSIDE 0x00000000U 495 496 // Field: [3:1] DIV 497 // 498 // Used to configure reference divider. Setting values 0x5-0x7 will set the 499 // divide value to 1. 500 // ENUMs: 501 // VAL4 Divide value is 1/4 502 // VAL3 Divide value is 1/3 503 // VAL2 Divide value is 1/2 504 // VAL1 Divide value is 3/4 505 // VAL0 Divide value is 1 506 #define SYS0_LPCMPCFG_DIV_W 3U 507 #define SYS0_LPCMPCFG_DIV_M 0x0000000EU 508 #define SYS0_LPCMPCFG_DIV_S 1U 509 #define SYS0_LPCMPCFG_DIV_VAL4 0x00000008U 510 #define SYS0_LPCMPCFG_DIV_VAL3 0x00000006U 511 #define SYS0_LPCMPCFG_DIV_VAL2 0x00000004U 512 #define SYS0_LPCMPCFG_DIV_VAL1 0x00000002U 513 #define SYS0_LPCMPCFG_DIV_VAL0 0x00000000U 514 515 // Field: [0] EN 516 // 517 // Used to enable comparator module. 518 // ENUMs: 519 // EN Enable 520 // DIS Disable 521 #define SYS0_LPCMPCFG_EN 0x00000001U 522 #define SYS0_LPCMPCFG_EN_M 0x00000001U 523 #define SYS0_LPCMPCFG_EN_S 0U 524 #define SYS0_LPCMPCFG_EN_EN 0x00000001U 525 #define SYS0_LPCMPCFG_EN_DIS 0x00000000U 526 527 //***************************************************************************** 528 // 529 // Register: SYS0_O_DEVICEID 530 // 531 //***************************************************************************** 532 // Field: [31:28] VERSION 533 // 534 // Monotonic increasing value indicating new hardware revision. A newer 535 // hardware revision shall never have a lower version than an older revision of 536 // hardware. 537 #define SYS0_DEVICEID_VERSION_W 4U 538 #define SYS0_DEVICEID_VERSION_M 0xF0000000U 539 #define SYS0_DEVICEID_VERSION_S 28U 540 541 // Field: [27:12] DEVICE 542 // 543 // Value generated by RAMP for the SOC. This value uniquely identifies the die 544 // from any other TI device. 545 #define SYS0_DEVICEID_DEVICE_W 16U 546 #define SYS0_DEVICEID_DEVICE_M 0x0FFFF000U 547 #define SYS0_DEVICEID_DEVICE_S 12U 548 549 // Field: [11:1] MANFACTURER 550 // 551 // JEP 106 assigned manufacturer ID. This field identifies the device as a 552 // Texas Instruments device. 553 #define SYS0_DEVICEID_MANFACTURER_W 11U 554 #define SYS0_DEVICEID_MANFACTURER_M 0x00000FFEU 555 #define SYS0_DEVICEID_MANFACTURER_S 1U 556 557 // Field: [0] ALWAYSONE 558 // 559 // Value 1 in this bit field means that a 32-bit scan register exists. 560 #define SYS0_DEVICEID_ALWAYSONE 0x00000001U 561 #define SYS0_DEVICEID_ALWAYSONE_M 0x00000001U 562 #define SYS0_DEVICEID_ALWAYSONE_S 0U 563 564 //***************************************************************************** 565 // 566 // Register: SYS0_O_PARTID 567 // 568 //***************************************************************************** 569 // Field: [31] START 570 // 571 // Start bit 572 // ENUMs: 573 // SET 574 // CLR Clear 575 #define SYS0_PARTID_START 0x80000000U 576 #define SYS0_PARTID_START_M 0x80000000U 577 #define SYS0_PARTID_START_S 31U 578 #define SYS0_PARTID_START_SET 0x80000000U 579 #define SYS0_PARTID_START_CLR 0x00000000U 580 581 // Field: [30:28] MAJORREV 582 // 583 // Monotonic increasing value indicating a new revision of the SKU significant 584 // enough that users of the device may have to revise PCB or software design 585 #define SYS0_PARTID_MAJORREV_W 3U 586 #define SYS0_PARTID_MAJORREV_M 0x70000000U 587 #define SYS0_PARTID_MAJORREV_S 28U 588 589 // Field: [27:24] MINORREV 590 // 591 // Monotonic increasing value indicating a new revision of the SKU that 592 // preserves compatibility with lesser MINORREV values 593 #define SYS0_PARTID_MINORREV_W 4U 594 #define SYS0_PARTID_MINORREV_M 0x0F000000U 595 #define SYS0_PARTID_MINORREV_S 24U 596 597 // Field: [23:16] VARIANT 598 // 599 // Bit pattern uniquely identifying a variant of a part 600 #define SYS0_PARTID_VARIANT_W 8U 601 #define SYS0_PARTID_VARIANT_M 0x00FF0000U 602 #define SYS0_PARTID_VARIANT_S 16U 603 604 // Field: [15:0] PART 605 // 606 // Bit pattern uniquely identifying a part 607 #define SYS0_PARTID_PART_W 16U 608 #define SYS0_PARTID_PART_M 0x0000FFFFU 609 #define SYS0_PARTID_PART_S 0U 610 611 //***************************************************************************** 612 // 613 // Register: SYS0_O_TMUTE0 614 // 615 //***************************************************************************** 616 // Field: [31:0] CDACL 617 // 618 // Internal. Only to be used through TI provided API. 619 #define SYS0_TMUTE0_CDACL_W 32U 620 #define SYS0_TMUTE0_CDACL_M 0xFFFFFFFFU 621 #define SYS0_TMUTE0_CDACL_S 0U 622 623 //***************************************************************************** 624 // 625 // Register: SYS0_O_TMUTE1 626 // 627 //***************************************************************************** 628 // Field: [31:0] CDACM 629 // 630 // Internal. Only to be used through TI provided API. 631 #define SYS0_TMUTE1_CDACM_W 32U 632 #define SYS0_TMUTE1_CDACM_M 0xFFFFFFFFU 633 #define SYS0_TMUTE1_CDACM_S 0U 634 635 //***************************************************************************** 636 // 637 // Register: SYS0_O_TMUTE2 638 // 639 //***************************************************************************** 640 // Field: [30:26] IBTRIM 641 // 642 // LPCOMP: Bias current trim, 250nA to be terminated across I2V, 1M ohm 643 // setting. Resulting target trim voltage 250mV. 644 #define SYS0_TMUTE2_IBTRIM_W 5U 645 #define SYS0_TMUTE2_IBTRIM_M 0x7C000000U 646 #define SYS0_TMUTE2_IBTRIM_S 26U 647 648 // Field: [25:23] TRIM 649 // 650 // ADC REFBUF trim bits. 651 #define SYS0_TMUTE2_TRIM_W 3U 652 #define SYS0_TMUTE2_TRIM_M 0x03800000U 653 #define SYS0_TMUTE2_TRIM_S 23U 654 655 // Field: [22:16] LATCH 656 // 657 // SOC ADC: Latch trim bits. These bits are used in the analog IP. 658 #define SYS0_TMUTE2_LATCH_W 7U 659 #define SYS0_TMUTE2_LATCH_M 0x007F0000U 660 #define SYS0_TMUTE2_LATCH_S 16U 661 662 // Field: [15:4] OFFSET 663 // 664 // SOCADC: Offset trim bits. These bits are used in DTC. 665 #define SYS0_TMUTE2_OFFSET_W 12U 666 #define SYS0_TMUTE2_OFFSET_M 0x0000FFF0U 667 #define SYS0_TMUTE2_OFFSET_S 4U 668 669 // Field: [3:2] RES 670 // 671 // SOCADC: Resistor trim bits. These bits are used in the analog IP. 672 #define SYS0_TMUTE2_RES_W 2U 673 #define SYS0_TMUTE2_RES_M 0x0000000CU 674 #define SYS0_TMUTE2_RES_S 2U 675 676 // Field: [1:0] CDACU 677 // 678 // SOCADC: Upper 2 bits of CDAC trim. These bits are used in DTC. 679 #define SYS0_TMUTE2_CDACU_W 2U 680 #define SYS0_TMUTE2_CDACU_M 0x00000003U 681 #define SYS0_TMUTE2_CDACU_S 0U 682 683 //***************************************************************************** 684 // 685 // Register: SYS0_O_TMUTE3 686 // 687 //***************************************************************************** 688 // Field: [31:26] BATC1 689 // 690 // Internal. Only to be used through TI provided API. 691 #define SYS0_TMUTE3_BATC1_W 6U 692 #define SYS0_TMUTE3_BATC1_M 0xFC000000U 693 #define SYS0_TMUTE3_BATC1_S 26U 694 695 // Field: [25:19] BATC0 696 // 697 // Internal. Only to be used through TI provided API. 698 #define SYS0_TMUTE3_BATC0_W 7U 699 #define SYS0_TMUTE3_BATC0_M 0x03F80000U 700 #define SYS0_TMUTE3_BATC0_S 19U 701 702 // Field: [18:14] TEMPC2 703 // 704 // Internal. Only to be used through TI provided API. 705 #define SYS0_TMUTE3_TEMPC2_W 5U 706 #define SYS0_TMUTE3_TEMPC2_M 0x0007C000U 707 #define SYS0_TMUTE3_TEMPC2_S 14U 708 709 // Field: [13:8] TEMPC1 710 // 711 // Internal. Only to be used through TI provided API. 712 #define SYS0_TMUTE3_TEMPC1_W 6U 713 #define SYS0_TMUTE3_TEMPC1_M 0x00003F00U 714 #define SYS0_TMUTE3_TEMPC1_S 8U 715 716 // Field: [7:0] TEMPC0 717 // 718 // Internal. Only to be used through TI provided API. 719 #define SYS0_TMUTE3_TEMPC0_W 8U 720 #define SYS0_TMUTE3_TEMPC0_M 0x000000FFU 721 #define SYS0_TMUTE3_TEMPC0_S 0U 722 723 //***************************************************************************** 724 // 725 // Register: SYS0_O_TMUTE4 726 // 727 //***************************************************************************** 728 // Field: [31:28] RECHCOMPREFLVL 729 // 730 // Internal. Only to be used through TI provided API. 731 #define SYS0_TMUTE4_RECHCOMPREFLVL_W 4U 732 #define SYS0_TMUTE4_RECHCOMPREFLVL_M 0xF0000000U 733 #define SYS0_TMUTE4_RECHCOMPREFLVL_S 28U 734 735 // Field: [27:26] IOSTRCFG2 736 // 737 // Internal. Only to be used through TI provided API. 738 #define SYS0_TMUTE4_IOSTRCFG2_W 2U 739 #define SYS0_TMUTE4_IOSTRCFG2_M 0x0C000000U 740 #define SYS0_TMUTE4_IOSTRCFG2_S 26U 741 742 // Field: [25:22] IOSTRCFG1 743 // 744 // Internal. Only to be used through TI provided API. 745 #define SYS0_TMUTE4_IOSTRCFG1_W 4U 746 #define SYS0_TMUTE4_IOSTRCFG1_M 0x03C00000U 747 #define SYS0_TMUTE4_IOSTRCFG1_S 22U 748 749 // Field: [21:19] MAX 750 // 751 // Internal. Only to be used through TI provided API. 752 #define SYS0_TMUTE4_MAX_W 3U 753 #define SYS0_TMUTE4_MAX_M 0x00380000U 754 #define SYS0_TMUTE4_MAX_S 19U 755 756 // Field: [18:16] MED 757 // 758 // Internal. Only to be used through TI provided API. 759 #define SYS0_TMUTE4_MED_W 3U 760 #define SYS0_TMUTE4_MED_M 0x00070000U 761 #define SYS0_TMUTE4_MED_S 16U 762 763 // Field: [15:13] MIN 764 // 765 // Internal. Only to be used through TI provided API. 766 #define SYS0_TMUTE4_MIN_W 3U 767 #define SYS0_TMUTE4_MIN_M 0x0000E000U 768 #define SYS0_TMUTE4_MIN_S 13U 769 770 // Field: [12:11] DCDCLOAD 771 // 772 // Internal. Only to be used through TI provided API. 773 #define SYS0_TMUTE4_DCDCLOAD_W 2U 774 #define SYS0_TMUTE4_DCDCLOAD_M 0x00001800U 775 #define SYS0_TMUTE4_DCDCLOAD_S 11U 776 777 // Field: [10:8] IPEAK 778 // 779 // DCDC: Set inductor peak current 780 // Min = 0x0 781 // Max = 0x7 782 // DCDC load support increases from 0x0 to 0x7 783 #define SYS0_TMUTE4_IPEAK_W 3U 784 #define SYS0_TMUTE4_IPEAK_M 0x00000700U 785 #define SYS0_TMUTE4_IPEAK_S 8U 786 787 // Field: [7:6] DTIME 788 // 789 // Internal. Only to be used through TI provided API. 790 #define SYS0_TMUTE4_DTIME_W 2U 791 #define SYS0_TMUTE4_DTIME_M 0x000000C0U 792 #define SYS0_TMUTE4_DTIME_S 6U 793 794 // Field: [5:3] LENSEL 795 // 796 // Internal. Only to be used through TI provided API. 797 #define SYS0_TMUTE4_LENSEL_W 3U 798 #define SYS0_TMUTE4_LENSEL_M 0x00000038U 799 #define SYS0_TMUTE4_LENSEL_S 3U 800 801 // Field: [2:0] HENSEL 802 // 803 // Internal. Only to be used through TI provided API. 804 #define SYS0_TMUTE4_HENSEL_W 3U 805 #define SYS0_TMUTE4_HENSEL_M 0x00000007U 806 #define SYS0_TMUTE4_HENSEL_S 0U 807 808 //***************************************************************************** 809 // 810 // Register: SYS0_O_TMUTE5 811 // 812 //***************************************************************************** 813 // Field: [12:10] DCDCDRVDS 814 // 815 // Internal. Only to be used through TI provided API. 816 #define SYS0_TMUTE5_DCDCDRVDS_W 3U 817 #define SYS0_TMUTE5_DCDCDRVDS_M 0x00001C00U 818 #define SYS0_TMUTE5_DCDCDRVDS_S 10U 819 820 // Field: [9:5] GLDOISCLR 821 // 822 // Internal. Only to be used through TI provided API. 823 #define SYS0_TMUTE5_GLDOISCLR_W 5U 824 #define SYS0_TMUTE5_GLDOISCLR_M 0x000003E0U 825 #define SYS0_TMUTE5_GLDOISCLR_S 5U 826 827 // Field: [4:0] GLDOISSET 828 // 829 // Internal. Only to be used through TI provided API. 830 #define SYS0_TMUTE5_GLDOISSET_W 5U 831 #define SYS0_TMUTE5_GLDOISSET_M 0x0000001FU 832 #define SYS0_TMUTE5_GLDOISSET_S 0U 833 834 835 #endif // __SYS0__ 836
